From nobody Sun Jul 26 13:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1781279499; cv=none; d=zohomail.com; s=zohoarc; b=aWOYXRDMht5kf0aT1yT807OnjlKArFY7eWOL+XtmwzHnOPxYuO4nTV+jdFHEn6aFx8KNmcSbyEMmYk3NyW+mkItLJ5kCuZuKkqfyrHMXZfJ8TK4ihQWd6IYbaWwIZSdpLlsxY54GswmDLhbVHFC5ABa5oBsZARi60RwXyJ9/keU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781279499; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m4IDSyjWcAzO6Xi7rKP9aTp7TUacMkhUAjZNmS+VHtQ=; b=FVk6xeMu6G9EfjCqjcEDP/dF6r0ZBzQakiU3Ud4ACcExi7wleTiQmZhaQcpSsWXHbq/wuhYTAfvZe/RSCf/Tp56NQpo532145DXc1KddBr9nr/tIdyHkk/8o5x46lV4Ma2rp91qQHohtkr7yFCpDmNChP8iVRkcW4RGP5jUoPPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781279499603462.8236063728252; Fri, 12 Jun 2026 08:51:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wY49m-00016N-6Z; Fri, 12 Jun 2026 11:50:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wY49l-00016E-2L for qemu-devel@nongnu.org; Fri, 12 Jun 2026 11:50:53 -0400 Received: from tor.source.kernel.org ([172.105.4.254]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wY49i-00087T-Gd for qemu-devel@nongnu.org; Fri, 12 Jun 2026 11:50:52 -0400 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 969AC60008; Fri, 12 Jun 2026 15:50:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C3AFB1F000E9; Fri, 12 Jun 2026 15:50:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781279449; bh=m4IDSyjWcAzO6Xi7rKP9aTp7TUacMkhUAjZNmS+VHtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=J6LVtuxCkZjs38hy9uChhIfA9qolsVCdbJvrXys5kD5TSEzpwM/oOx3frAAmVM94E NNtBVkLNhIZZB6OtVqmZ903ifq+g/b22k64aa5WZWxWVxGxOKvP2zodDiG8zeU8dxd OXRUBcZLvg36fAR+VW2yiGjy7D9slm6tGB7t9UZyQaJqB0FRF6VzFH1DOjbwUZk6Eq uTTiK5enUzendJe4D+Nmk53vjikVfjdjQOQ6ZlVcSJsKqmrvLqQNu6IWubQ23PzXCm dqaxZoQiJxfuGAT5I7kY5fMj8xugAbcOGHz0kKhkVABYfljSQUTBbGc0YqR/594rHM wKNng3BACp0rg== From: Helge Deller To: Stefan Hajnoczi , qemu-devel@nongnu.org Cc: Helge Deller , Pierrick Bouvier , Laurent Vivier , Max Filippov , Dominique Martinet Subject: [PULL 1/4] linux-user: add preadv2/preadv2 Date: Fri, 12 Jun 2026 17:50:40 +0200 Message-ID: <20260612155043.3552-2-deller@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260612155043.3552-1-deller@kernel.org> References: <20260612155043.3552-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=172.105.4.254; envelope-from=deller@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1781279501941158500 Content-Type: text/plain; charset="utf-8" From: Dominique Martinet Some programs apparently use these, like the python test suite. The flags argument (rwf_t) is an int, with values shared on all arches and does not need translating. This was tested manually with the following python script: ``` import os fd =3D os.open('test', os.O_RDWR|os.O_CREAT) os.pwritev(fd, [b'test', b'ok'], 0, os.RWF_HIPRI) buf =3D [bytearray(3), bytearray(10)] os.preadv(fd, buf, 0, os.RWF_HIPRI) print(buf[0]) print(buf[1]) ``` Signed-off-by: Dominique Martinet Reviewed-by: Helge Deller Signed-off-by: Helge Deller --- linux-user/syscall.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 37ede95510..fbe357b7e0 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -741,6 +741,11 @@ safe_syscall5(ssize_t, preadv, int, fd, const struct i= ovec *, iov, int, iovcnt, unsigned long, pos_l, unsigned long, pos_h) safe_syscall5(ssize_t, pwritev, int, fd, const struct iovec *, iov, int, i= ovcnt, unsigned long, pos_l, unsigned long, pos_h) +safe_syscall6(ssize_t, preadv2, int, fd, const struct iovec *, iov, int, i= ovcnt, + unsigned long, pos_l, unsigned long, pos_h, __kernel_rwf_t, = flags) +safe_syscall6(ssize_t, pwritev2, int, fd, const struct iovec *, iov, + int, iovcnt, unsigned long, pos_l, unsigned long, pos_h, + __kernel_rwf_t, flags) safe_syscall3(int, connect, int, fd, const struct sockaddr *, addr, socklen_t, addrlen) safe_syscall6(ssize_t, sendto, int, fd, const void *, buf, size_t, len, @@ -11907,6 +11912,39 @@ static abi_long do_syscall1(CPUArchState *cpu_env,= int num, abi_long arg1, } } return ret; +#endif +#if defined(TARGET_NR_preadv2) + case TARGET_NR_preadv2: + { + struct iovec *vec =3D lock_iovec(VERIFY_WRITE, arg2, arg3, 0); + if (vec !=3D NULL) { + unsigned long low, high; + + target_to_host_low_high(arg4, arg5, &low, &high); + ret =3D get_errno(safe_preadv2(arg1, vec, arg3, low, high,= arg6)); + unlock_iovec(vec, arg2, arg3, 1); + } else { + ret =3D -host_to_target_errno(errno); + } + } + return ret; +#endif +#if defined(TARGET_NR_pwritev2) + case TARGET_NR_pwritev2: + { + struct iovec *vec =3D lock_iovec(VERIFY_READ, arg2, arg3, 1); + if (vec !=3D NULL) { + unsigned long low, high; + + target_to_host_low_high(arg4, arg5, &low, &high); + ret =3D get_errno(safe_pwritev2(arg1, vec, arg3, low, high, + arg6)); + unlock_iovec(vec, arg2, arg3, 0); + } else { + ret =3D -host_to_target_errno(errno); + } + } + return ret; #endif case TARGET_NR_getsid: return get_errno(getsid(arg1)); --=20 2.54.0 From nobody Sun Jul 26 13:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 12 Jun 2026 11:50:53 -0400 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 9CD436008A; Fri, 12 Jun 2026 15:50:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C94241F000E9; Fri, 12 Jun 2026 15:50:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781279451; bh=0eEpzlx9/ON/Uwph3+LU5JGk/Iqo/Yt7aIelhbODELY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hshoN7AQXfvjGIj+2PMM5AGC8Y+YqW8ClgD4HuZlx5qartK3ZsY6lIGT5jU4fimyl FHGqdEiU0ZcjX8oEbh3E9qsvVAwhP+VUcUoZ768X9TpvHGMdIuWWn5RbAygcWBEfri hGqu445Skv5gWeCVb9VDZxf+hyTAOQDxJkrJwOR+0SPnjvFa2ahldduEmwnimgRFE8 EmHe1Cr3HhiT1yv3LbN2SyyFxGMJwJUtaPjcOrJuMspZje6TsTgin5E/9p29BFpJZx bITdChDu+4j2OI3RyqCZuUecxNOWf1L+cdENZY8+ekPe2j0URhlB0OlPnPD78pL5QJ C0/wCAJbLueJQ== From: Helge Deller To: Stefan Hajnoczi , qemu-devel@nongnu.org Cc: Helge Deller , Pierrick Bouvier , Laurent Vivier , Max Filippov , Richard Henderson Subject: [PULL 2/4] linux-user: Implement /proc/cpuinfo for ppc cpus Date: Fri, 12 Jun 2026 17:50:41 +0200 Message-ID: <20260612155043.3552-3-deller@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260612155043.3552-1-deller@kernel.org> References: <20260612155043.3552-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2600:3c04:e001:324:0:1991:8:25; envelope-from=deller@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1781279507676158500 Content-Type: text/plain; charset="utf-8" From: Helge Deller Mimic the entries for /proc/cpuinfo to what can be seen on two debian porterboxes (ppc64 and ppc64le), which are running via KVM/QEMU. The "timebase" value in /proc/cpuinfo is used by glibc on power, but only if the __kernel_get_tbfreq vdso call isn't implemented. So switch cpu_ppc_load_tbl() for linux-user to get_clock(), as suggested by Richard, = and report timebase =3D 1GHz in /proc/cpuinfo, which will make the vdso implementation simple too. v4: change timebase to 1GHz and use get_clock() v3: drop another colon, indenting fixes v2: drop colon, add clock output, refine pvr calculation Reviewed-by: Richard Henderson Signed-off-by: Helge Deller --- linux-user/ppc/cpu_loop.c | 2 +- linux-user/ppc/target_proc.h | 91 +++++++++++++++++++++++++++++++++++- 2 files changed, 91 insertions(+), 2 deletions(-) diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 1f9ee20bd0..7c53e25a93 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -26,7 +26,7 @@ =20 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) { - return cpu_get_host_ticks(); + return get_clock(); } =20 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) diff --git a/linux-user/ppc/target_proc.h b/linux-user/ppc/target_proc.h index 43fe29ca72..0a48fd65e9 100644 --- a/linux-user/ppc/target_proc.h +++ b/linux-user/ppc/target_proc.h @@ -1 +1,90 @@ -/* No target-specific /proc support */ +/* + * ppc specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef PPC_TARGET_PROC_H +#define PPC_TARGET_PROC_H + +#include + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + struct timespec res; + double freq_mhz; + int i, num_cpus; + unsigned int maj, min, pvr; + + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(env_cpu(cpu_env)); + DeviceClass *dc =3D DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); + + pvr =3D pcc->pvr; + + /* Taken from Linux kernel: */ + /* If we are a Freescale core do a simple check so + * we don't have to keep adding cases in the future */ + if (PVR_VER(pvr) & 0x8000) { + switch (PVR_VER(pvr)) { + case 0x8000: /* 7441/7450/7451, Voyager */ + case 0x8001: /* 7445/7455, Apollo 6 */ + case 0x8002: /* 7447/7457, Apollo 7 */ + case 0x8003: /* 7447A, Apollo 7 PM */ + case 0x8004: /* 7448, Apollo 8 */ + case 0x800c: /* 7410, Nitro */ + maj =3D ((pvr >> 8) & 0xF); + min =3D PVR_MIN(pvr); + break; + default: /* e500/book-e */ + maj =3D PVR_MAJ(pvr); + min =3D PVR_MIN(pvr); + break; + } + } else { + switch (PVR_VER(pvr)) { + case 0x1008: /* 740P/750P ?? */ + maj =3D ((pvr >> 8) & 0xFF) - 1; + min =3D pvr & 0xFF; + break; + case 0x004e: /* POWER9 bits 12-15 give chip type */ + case 0x0080: /* POWER10 bit 12 gives SMT8/4 */ + maj =3D (pvr >> 8) & 0x0F; + min =3D pvr & 0xFF; + break; + default: + maj =3D (pvr >> 8) & 0xFF; + min =3D pvr & 0xFF; + break; + } + } + + if (clock_getres(CLOCK_REALTIME, &res) =3D=3D -1) { + res.tv_nsec =3D 1; + } + freq_mhz =3D 1000.0 / res.tv_nsec; + + num_cpus =3D sysconf(_SC_NPROCESSORS_ONLN); + for (i =3D 0; i < num_cpus; i++) { + dprintf(fd, "processor\t: %d\n", i); + dprintf(fd, "cpu\t\t: %s%s\n", + dc->desc, + pcc->insns_flags & PPC_ALTIVEC ? ", altivec supported"= :""); + dprintf(fd, "clock\t\t: %.3fMHz\n", freq_mhz); + dprintf(fd, "revision\t: %d.%d (pvr %04x %04x)\n\n", + maj, min, PVR_VER(pvr), PVR_REV(pvr)); + } + + dprintf(fd, "timebase\t: 1000000000\n"); + dprintf(fd, "platform\t: pSeries\n"); + dprintf(fd, "model\t\t: IBM pSeries (QEMU user v" QEMU_VERSION ")\n"); + dprintf(fd, "machine\t\t: CHRP IBM pSeries\n"); + + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* PPC_TARGET_PROC_H */ --=20 2.54.0 From nobody Sun Jul 26 13:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1781279521; cv=none; d=zohomail.com; s=zohoarc; b=eNPhqHk+5VFojZljt8HSba/PRpF/4lrKUhLskQB0yO6zrF1AK1bwVU2D2y5s1tM/EPvdNT4zrHKrO0n1mIWArTeTArthqLNYAuLMaFLhR49IIsPvfCOo93lC5SAZ0kEfFFWdrgJysFk+8NTa3GBWSw7XOgmZNiiZmwcAno01zCc= ARC-Message-Signature: i=1; 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Fri, 12 Jun 2026 11:51:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wY49o-00017H-Af for qemu-devel@nongnu.org; Fri, 12 Jun 2026 11:50:56 -0400 Received: from sea.source.kernel.org ([172.234.252.31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wY49m-0008Ck-Ec for qemu-devel@nongnu.org; Fri, 12 Jun 2026 11:50:56 -0400 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 90DDF44328; Fri, 12 Jun 2026 15:50:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0D191F000E9; Fri, 12 Jun 2026 15:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781279453; bh=ka4VbvNFDIvk3wX9UUytgcfG8jW4A6Dg6ZEgYbgSxww=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VPLnw73iJaxTG1csdQVcEzPl7Wlz2vraQxd/Lu1TZLLxrc7qHqx3S9KmdDehGPVg5 bxz4gfwcuq+c3Xkab914LRJfQZcBfSv5x3O8O126rvJcNCcS9C2X35Eew0DTtMtcze hSk/o5Rwu35zoBUOfB2d0fU6XuYw9kOoan9Uto5dn12KIQrnLk1DP+i1eQcg3GQnUp JBOWrsOQUOPSVsXQzofmIaR71OhFQFy6cIpl3laIN64fAvPMrSugL0+ZK+lXOGFpm/ k/wqP4l5BcXHKWK5Qic1EjCPuJOsirz/ASLIbccQcYaEX/FB7H/1nDCYOnr8gGlH2j YnKLtWCiByTeg== From: Helge Deller To: Stefan Hajnoczi , qemu-devel@nongnu.org Cc: Helge Deller , Pierrick Bouvier , Laurent Vivier , Max Filippov , Matt Turner , Richard Henderson Subject: [PULL 3/4] target/xtensa: add cpu_set_fcr/fsr helpers to sync fp_status Date: Fri, 12 Jun 2026 17:50:42 +0200 Message-ID: <20260612155043.3552-4-deller@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260612155043.3552-1-deller@kernel.org> References: <20260612155043.3552-1-deller@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=172.234.252.31; envelope-from=deller@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1781279523825158500 From: Matt Turner Factor FCR=E2=86=92fp_status and FSR=E2=86=92fp_status synchronisation out = of the wur_fpu{2k,}_fcr/wur_fpu_fsr helpers into cpu_set_fcr(), cpu_set_fsr(), and cpu_get_fsr(). Signal delivery code needs to restore the FP rounding mode and exception flags without duplicating the flag-mapping tables. cpu_set_fcr() applies the union mask 0xfffff07f (superset of the wur_fpu_fcr mask 0x0000007f and the wur_fpu2k_fcr mask 0xfffff07f) so that FCR bits valid only on fpu2k configs are preserved while MBZ bits 7-11 are always cleared. Signed-off-by: Matt Turner Reviewed-by: Richard Henderson Signed-off-by: Helge Deller --- target/xtensa/cpu.h | 4 +++ target/xtensa/fpu_helper.c | 71 +++++++++++++++++++++----------------- 2 files changed, 44 insertions(+), 31 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 75cfeee6e3..442e98bd1b 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -642,6 +642,10 @@ static inline void xtensa_select_static_vectors(CPUXte= nsaState *env, } void xtensa_runstall(CPUXtensaState *env, bool runstall); =20 +uint32_t cpu_get_fsr(CPUXtensaState *env); +void cpu_set_fcr(CPUXtensaState *env, uint32_t v); +void cpu_set_fsr(CPUXtensaState *env, uint32_t v); + #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_ALL (~(uint64_t)0) =20 diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 5358060c50..2e51cabe3f 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -64,46 +64,39 @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use= _first) &env->fp_status); } =20 -void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) +uint32_t cpu_get_fsr(CPUXtensaState *env) { - static const int rounding_mode[] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down, - }; + uint32_t flags =3D 0; + int fef =3D get_float_exception_flags(&env->fp_status); + unsigned i; =20 - env->uregs[FCR] =3D v & 0xfffff07f; - set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); + for (i =3D 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { + if (fef & xtensa_fp_flag_map[i].softfloat_fp_flag) { + flags |=3D xtensa_fp_flag_map[i].xtensa_fp_flag; + } + } + return flags << XTENSA_FSR_FLAGS_SHIFT; } =20 -void HELPER(wur_fpu_fcr)(CPUXtensaState *env, uint32_t v) +void cpu_set_fcr(CPUXtensaState *env, uint32_t v) { - static const int rounding_mode[] =3D { + static const FloatRoundMode rounding_mode[] =3D { float_round_nearest_even, float_round_to_zero, float_round_up, float_round_down, }; =20 - if (v & 0xfffff000) { - qemu_log_mask(LOG_GUEST_ERROR, - "MBZ field of FCR is written non-zero: %08x\n", v); - } - env->uregs[FCR] =3D v & 0x0000007f; + env->uregs[FCR] =3D v & 0xfffff07f; set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); } =20 -void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_t v) +void cpu_set_fsr(CPUXtensaState *env, uint32_t v) { uint32_t flags =3D v >> XTENSA_FSR_FLAGS_SHIFT; int fef =3D 0; unsigned i; =20 - if (v & 0xfffff000) { - qemu_log_mask(LOG_GUEST_ERROR, - "MBZ field of FSR is written non-zero: %08x\n", v); - } env->uregs[FSR] =3D v & 0x00000f80; for (i =3D 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { if (flags & xtensa_fp_flag_map[i].xtensa_fp_flag) { @@ -113,19 +106,35 @@ void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_= t v) set_float_exception_flags(fef, &env->fp_status); } =20 -uint32_t HELPER(rur_fpu_fsr)(CPUXtensaState *env) +void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) { - uint32_t flags =3D 0; - int fef =3D get_float_exception_flags(&env->fp_status); - unsigned i; + cpu_set_fcr(env, v); +} =20 - for (i =3D 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) { - if (fef & xtensa_fp_flag_map[i].softfloat_fp_flag) { - flags |=3D xtensa_fp_flag_map[i].xtensa_fp_flag; - } +void HELPER(wur_fpu_fcr)(CPUXtensaState *env, uint32_t v) +{ + if (v & 0xfffff000) { + qemu_log_mask(LOG_GUEST_ERROR, + "MBZ field of FCR is written non-zero: %08x\n", v); } - env->uregs[FSR] =3D flags << XTENSA_FSR_FLAGS_SHIFT; - return flags << XTENSA_FSR_FLAGS_SHIFT; + cpu_set_fcr(env, v & 0x0000007f); +} + +void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_t v) +{ + if (v & 0xfffff000) { + qemu_log_mask(LOG_GUEST_ERROR, + "MBZ field of FSR is written non-zero: %08x\n", v); + } + cpu_set_fsr(env, v); +} + +uint32_t HELPER(rur_fpu_fsr)(CPUXtensaState *env) +{ + uint32_t fsr =3D cpu_get_fsr(env); + + env->uregs[FSR] =3D fsr; + return fsr; } =20 float64 HELPER(abs_d)(float64 v) --=20 2.54.0 From nobody Sun Jul 26 13:25:58 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 12 Jun 2026 15:50:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E14B61F000E9; Fri, 12 Jun 2026 15:50:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781279455; bh=cCWxnWBTELIri7mBIrY3nW5i67rK3zVx7spuTib8SAk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HNqovlGo/yD7eLzbzFHTkCnHNDKBAijHpg5taJl1lOKjGfAgNtpiTEz4/B7nsWSoP qk6t5o1rp1+TEc1gsAjisr/AbvoUuZ+oBNO91JLwfRy2DoFNA/9qfotK5266fpupxD +uY7wHw/v5OsF8kRgUmUHdcxVokIlU2PG6BmknBB4eKxCnXJFGCDsGlPsaY8tE39hm yISPKg8LYvvHs8PDguooSEHRdALRSOgl9VY9acFLOdfBwiB6WN0PImS4y0IzHqWkm/ AniNiKFz0n03oE42pHPe+oZSJsOtCZxx7uyQ2ZaPxgpCIxKyFi+1Hq+f2g9JqztQLD lmX5DaxkBcd8Q== From: Helge Deller To: Stefan Hajnoczi , qemu-devel@nongnu.org Cc: Helge Deller , Pierrick Bouvier , Laurent Vivier , Max Filippov , Matt Turner , Richard Henderson Subject: [PULL 4/4] linux-user/xtensa: save/restore FP registers across signal delivery Date: Fri, 12 Jun 2026 17:50:43 +0200 Message-ID: <20260612155043.3552-5-deller@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260612155043.3552-1-deller@kernel.org> References: <20260612155043.3552-1-deller@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2600:3c04:e001:324:0:1991:8:25; envelope-from=deller@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1781279482048158500 Content-Type: text/plain; charset="utf-8" From: Matt Turner Add support for saving and restoring f0-f15 across signal delivery. The target_xtensa_xtregs_fp struct carries 32-bit f-regs for cores with XTENSA_OPTION_FP_COPROCESSOR; target_xtensa_xtregs_dfp carries 64-bit f-regs for cores with XTENSA_OPTION_DFP_COPROCESSOR. Lock the xtregs region via lock_user before reading on sigreturn, since sc_xtregs is a user-space pointer that may lie outside the locked sigframe. Signed-off-by: Matt Turner Reviewed-by: Richard Henderson Signed-off-by: Helge Deller --- linux-user/xtensa/signal.c | 96 ++++++++++++++++++++++++++++++++++---- 1 file changed, 88 insertions(+), 8 deletions(-) diff --git a/linux-user/xtensa/signal.c b/linux-user/xtensa/signal.c index ef8b0c3a27..e3f9da322b 100644 --- a/linux-user/xtensa/signal.c +++ b/linux-user/xtensa/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "target/xtensa/cpu.h" =20 struct target_sigcontext { abi_ulong sc_pc; @@ -43,10 +44,25 @@ struct target_ucontext { target_sigset_t tuc_sigmask; }; =20 +struct target_xtensa_xtregs_fp { + uint32_t f[16]; + uint32_t fcr; + uint32_t fsr; +}; + +struct target_xtensa_xtregs_dfp { + uint64_t f[16]; + uint32_t fcr; + uint32_t fsr; +}; + struct target_rt_sigframe { target_siginfo_t info; struct target_ucontext uc; - /* TODO: xtregs */ + union { + struct target_xtensa_xtregs_fp fp; + struct target_xtensa_xtregs_dfp dfp; + } xtregs; uint8_t retcode[6]; abi_ulong window[4]; }; @@ -107,6 +123,7 @@ static int flush_window_regs(CPUXtensaState *env) } =20 static int setup_sigcontext(struct target_rt_sigframe *frame, + abi_ulong frame_addr, CPUXtensaState *env) { struct target_sigcontext *sc =3D &frame->uc.tuc_mcontext; @@ -123,8 +140,25 @@ static int setup_sigcontext(struct target_rt_sigframe = *frame, for (i =3D 0; i < 16; ++i) { __put_user(env->regs[i], sc->sc_a + i); } - __put_user(0, &sc->sc_xtregs); - /* TODO: xtregs */ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR))= { + for (i =3D 0; i < 16; ++i) { + __put_user(env->fregs[i].f64, &frame->xtregs.dfp.f[i]); + } + __put_user(env->uregs[FCR], &frame->xtregs.dfp.fcr); + __put_user(cpu_get_fsr(env), &frame->xtregs.dfp.fsr); + __put_user(frame_addr + offsetof(struct target_rt_sigframe, xtregs= ), + &sc->sc_xtregs); + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCE= SSOR)) { + for (i =3D 0; i < 16; ++i) { + __put_user(env->fregs[i].f32[FP_F32_LOW], &frame->xtregs.fp.f[= i]); + } + __put_user(env->uregs[FCR], &frame->xtregs.fp.fcr); + __put_user(cpu_get_fsr(env), &frame->xtregs.fp.fsr); + __put_user(frame_addr + offsetof(struct target_rt_sigframe, xtregs= ), + &sc->sc_xtregs); + } else { + __put_user(0, &sc->sc_xtregs); + } return 1; } =20 @@ -190,7 +224,7 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, __put_user(0, &frame->uc.tuc_flags); __put_user(0, &frame->uc.tuc_link); target_save_altstack(&frame->uc.tuc_stack, env); - if (!setup_sigcontext(frame, env)) { + if (!setup_sigcontext(frame, frame_addr, env)) { unlock_user_struct(frame, frame_addr, 0); goto give_sigsegv; } @@ -243,8 +277,8 @@ give_sigsegv: force_sigsegv(sig); } =20 -static void restore_sigcontext(CPUXtensaState *env, - struct target_rt_sigframe *frame) +static int restore_sigcontext(CPUXtensaState *env, + struct target_rt_sigframe *frame) { struct target_sigcontext *sc =3D &frame->uc.tuc_mcontext; uint32_t ps; @@ -266,7 +300,51 @@ static void restore_sigcontext(CPUXtensaState *env, for (i =3D 0; i < 16; ++i) { __get_user(env->regs[i], sc->sc_a + i); } - /* TODO: xtregs */ + { + abi_ulong xtregs_addr; + + __get_user(xtregs_addr, &sc->sc_xtregs); + if (xtregs_addr) { + if (xtensa_option_enabled(env->config, + XTENSA_OPTION_DFP_COPROCESSOR)) { + struct target_xtensa_xtregs_dfp *xtregs; + uint32_t fcr, fsr; + + xtregs =3D lock_user(VERIFY_READ, xtregs_addr, + sizeof(*xtregs), 1); + if (!xtregs) { + return 0; + } + for (i =3D 0; i < 16; ++i) { + __get_user(env->fregs[i].f64, &xtregs->f[i]); + } + __get_user(fcr, &xtregs->fcr); + __get_user(fsr, &xtregs->fsr); + unlock_user(xtregs, xtregs_addr, 0); + cpu_set_fcr(env, fcr); + cpu_set_fsr(env, fsr); + } else if (xtensa_option_enabled(env->config, + XTENSA_OPTION_FP_COPROCESSOR)= ) { + struct target_xtensa_xtregs_fp *xtregs; + uint32_t fcr, fsr; + + xtregs =3D lock_user(VERIFY_READ, xtregs_addr, + sizeof(*xtregs), 1); + if (!xtregs) { + return 0; + } + for (i =3D 0; i < 16; ++i) { + __get_user(env->fregs[i].f32[FP_F32_LOW], &xtregs->f[i= ]); + } + __get_user(fcr, &xtregs->fcr); + __get_user(fsr, &xtregs->fsr); + unlock_user(xtregs, xtregs_addr, 0); + cpu_set_fcr(env, fcr); + cpu_set_fsr(env, fsr); + } + } + } + return 1; } =20 long do_rt_sigreturn(CPUXtensaState *env) @@ -282,7 +360,9 @@ long do_rt_sigreturn(CPUXtensaState *env) target_to_host_sigset(&set, &frame->uc.tuc_sigmask); set_sigmask(&set); =20 - restore_sigcontext(env, frame); + if (!restore_sigcontext(env, frame)) { + goto badframe; + } target_restore_altstack(&frame->uc.tuc_stack, env); =20 unlock_user_struct(frame, frame_addr, 0); --=20 2.54.0