From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=mihalicyn.com ARC-Seal: i=1; a=rsa-sha256; t=1781176989; cv=none; d=zohomail.com; s=zohoarc; b=mmdlshYO/3vDXPMU8av7Ub8tSliY95WQ4sTOnb1fyyXgm2h480lAzIhpmve8u2SGBFnl5LkKJctwhYGRyrACuxfFWsnB+guKLGJIEEaBXngZ6IOEpGji8KxbcUuThAU1hEGC18ZKlzSRWDdHauUC71BBt1ZCWE54nz16hhNC2TM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781176989; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JXW8+TkkbO/zdqSD0tRYgROfejMENktX+Aqzp4oymc4=; b=BSgm0Ydc1DlBXRPUcmfc920DLVm45BpOEDyW6x5qfMO7cd6AnFrzgMyOHUv+R7grDop5De9UjIZQsbKccmMoyShIhXyqt2AnNOOWJF02yafCWRv+Mo2QVgj8gM/I5v4Z2BJeTv1GqGk29xKOoAmsA35fTfxvNKjSbZ7Dbudo0nw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781176989630177.6735235739119; Thu, 11 Jun 2026 04:23:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXdUw-0001Gz-0K; Thu, 11 Jun 2026 07:22:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXdUu-0001Fj-22 for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:22:56 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wXdUr-00015y-AW for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:22:55 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-45ef1198766so514130f8f.0 for ; Thu, 11 Jun 2026 04:22:52 -0700 (PDT) Received: from alex-laptop.lan (p200300cf570ffe006c26edf58ff062dc.dip0.t-ipconnect.de. [2003:cf:570f:fe00:6c26:edf5:8ff0:62dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35fb24sm86375554f8f.34.2026.06.11.04.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 04:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mihalicyn.com; s=mihalicyn; t=1781176972; x=1781781772; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JXW8+TkkbO/zdqSD0tRYgROfejMENktX+Aqzp4oymc4=; b=cg99FJDvRhm+JIfkkZ4ZICDWLbcOHG4UgH1nOiTbbsqfWJRXf9+PNdnA/Z2cuFw6tC Hy/JYN5jv3h41ZsJCaNwvh/dDsIhsn7mKvva2XvFpnJn8y18i/5PqMXvme8jIWTdnUog 7UfOCIRDb7PTbnHpw51Q6K/KHjcxuCzAGpspY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781176972; x=1781781772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=JXW8+TkkbO/zdqSD0tRYgROfejMENktX+Aqzp4oymc4=; b=JH0Y9Xooj59TeNBXyRz+X0pGHHxIRRKJwsw91jYlAW+E1swhEEJiY9ECVZruXT1qjX iQIYycrtnzO67k9KazmSG00iHnVTP2WuHW/BxIJGobROIg6GoZYwdo+/IAeZDrPi5KFW 3Bdvc22Q07lrTbZUFklfib9v6scnfztLlhYUzXuuOPRUt5EQ9agEdXyhAi5O7s7XOo0z 9M+pEpq2pTJcud/aO+UpNtpo3+ZDrGS3Ic9htLQqwP6HFflB5UuBQIgzP9NwSa1O0YX+ 5iCv5BYcKpgn3/eb1OOHKrr7wWuvftCk9MHl4zZgYuhFtHNYFIUiVMdg/J9+xWk3VSiu lVDA== X-Gm-Message-State: AOJu0Yxt8VYqBNx4GheBfFDabH9Q4JnuQeVKumQzu/k8IME2eM4osJal QbK2UdlJqBFAjDZUpMXmXjrWKH1zkIPlFCm6/P8pEgeVsvJYlQt2xRKdB4TG7pCE41eUsYhBWhO 7zHLSw3Q= X-Gm-Gg: Acq92OGwUr9v3k/bsCxGgvaxuet5jOcFKFiXjZTlTDRrKi0hBEBcSLOprHCb1F8etD/ k3eNgIkdfdyGVaiNSY3uTi4V86loJwWUErP+l+cUb8Q1JmjN+nBQYiFOuCV4vZeewd3YMta9GR8 n8zQ7cW2RtQh9eOKpnMI1dQoIUTeZQA85l4YtLeFfRGw8+dL28+PblojiLpQOxrSqtleRLfdHNp FyFax4aamsdT85CO3nnI5ojDxNyp/vusS3lvfPRWmDODXtTlbjwmS7h0+33ejNzPCLjdTu5oYoY I69L5FR08WCDo2JkRLz3mPEdW0nj2EmzgdzRH9YTK5CbsEtwtOzssulLzUEfZZiumesnOxk6jvE DIfnmjoS/782/KcRw0wenhxSDhqykA6gqku4IYJLphDKLbuOCwKBJtm9e1Si3qY4TT/S5Z347Yf 9Vlcay2/PZ0hSIY0H64VH5xTdsS3IjHfmb9/EjcA8EqvaqfR1z11bmYFQcjonyj90tPXYm+yah7 AXe7m03PxNDDSeRnfk/nA3q+zlp+nKd4N777QbaFU24 X-Received: by 2002:a05:6000:1862:b0:45e:daa9:f34c with SMTP id ffacd0b85a97d-46067c35ea9mr3157241f8f.26.1781176971754; Thu, 11 Jun 2026 04:22:51 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn Subject: [PATCH v9 1/8] tests/functional/migration: add VM launch/configure hooks Date: Thu, 11 Jun 2026 13:22:42 +0200 Message-ID: <20260611112249.165012-2-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alexander@mihalicyn.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781176992102158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn Introduce configure_machine, launch_source_vm and assert_dest_vm methods to allow child classes to override some pieces of source/dest VMs creation, start and check logic. Reviewed-by: Peter Xu Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- tests/functional/migration.py | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/tests/functional/migration.py b/tests/functional/migration.py index 3b7674af3b6..4344e03be41 100644 --- a/tests/functional/migration.py +++ b/tests/functional/migration.py @@ -40,19 +40,36 @@ def assert_migration(self, src_vm, dst_vm): self.assertEqual(dst_vm.cmd('query-status')['status'], 'running') self.assertEqual(src_vm.cmd('query-status')['status'],'postmigrate= ') =20 + # Can be overridden by subclasses to configure both source/dest VMs. + def configure_machine(self, vm): + vm.add_args('-nodefaults') + + # Can be overridden by subclasses to prepare the source VM before + # migration, e.g. by running some workload inside the source VM + # to see if it continues to run properly after migration. + def launch_source_vm(self, vm): + vm.launch() + + # Can be overridden by subclasses to check the destination VM after + # migration, e.g. by checking if the workload is still running after + # migration. + def assert_dest_vm(self, vm): + pass + def migrate_vms(self, dst_uri, src_uri, dst_vm, src_vm): dst_vm.qmp('migrate-incoming', uri=3Ddst_uri) src_vm.qmp('migrate', uri=3Dsrc_uri) self.assert_migration(src_vm, dst_vm) + self.assert_dest_vm(dst_vm) =20 def migrate(self, dst_uri, src_uri=3DNone): dst_vm =3D self.get_vm('-incoming', 'defer', name=3D"dst-qemu") - dst_vm.add_args('-nodefaults') + self.configure_machine(dst_vm) dst_vm.launch() =20 src_vm =3D self.get_vm(name=3D"src-qemu") - src_vm.add_args('-nodefaults') - src_vm.launch() + self.configure_machine(src_vm) + self.launch_source_vm(src_vm) =20 if src_uri is None: src_uri =3D dst_uri --=20 2.47.3 From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=mihalicyn.com ARC-Seal: i=1; a=rsa-sha256; t=1781177039; cv=none; d=zohomail.com; s=zohoarc; b=fg9KS8t2udJJEU3+428i9AEsQNtgjYBwE2MF6rljbLPb5GxKAOabD9ihbMndLwq2UwSGZTsKuHozrf2qaL9xZ2zRZSIH9FVbhXtPfcFPsD8c5RbGUaukZXO8H2u65c1XxFAfRAgK3M4+Fy22VwGV+MSZtbT0hZ0vZNKJnLB1ge4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781177039; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hODBLZgziF4WAMHARmIfmORQBJLlpHseX0kKtGNE47E=; b=RYM3RUaICW+BGgYOSs5h0oaoQJx0FtcP6tU3zsevVOaRUcDx9FeI0VCnCvUIHGdkMW/LgcDSnJtVftWeq6wa5Iz1Hpka0VCC/WoELxCXXtpTxqptQ7drNntR6iXmMdvNpaQxEOcReAlOsIfJ2/AanG4qW79Z2Rqs08vfEi2Uepk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781177039532392.42080313588986; Thu, 11 Jun 2026 04:23:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXdUy-0001Ni-B0; Thu, 11 Jun 2026 07:23:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXdUu-0001G1-VA for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:22:56 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wXdUs-000165-Jd for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:22:56 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-490b7866869so84769585e9.2 for ; Thu, 11 Jun 2026 04:22:54 -0700 (PDT) Received: from alex-laptop.lan (p200300cf570ffe006c26edf58ff062dc.dip0.t-ipconnect.de. [2003:cf:570f:fe00:6c26:edf5:8ff0:62dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35fb24sm86375554f8f.34.2026.06.11.04.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 04:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mihalicyn.com; s=mihalicyn; t=1781176973; x=1781781773; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hODBLZgziF4WAMHARmIfmORQBJLlpHseX0kKtGNE47E=; b=JIKjl6ZUF8DiGIWHsRaZ2rUVLLoJtIfMRr2ZCThCjosNppocdRe2avk7012TSRaujU QaCXH3IRZMepLi/zn2+McJ+nF1bZ8LZ3jo9gNONklSmyHFO0FElp9X/GrmoKKyH3xq16 T1jFLghOa8At2D1SNCz1g1QjjsycVr16tEB/4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781176973; x=1781781773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=hODBLZgziF4WAMHARmIfmORQBJLlpHseX0kKtGNE47E=; b=TaJ3VxKhc47Zf/lxEE1pTkBXX1aSYoMUxQ/9IXPX7YwKfA4HCz3R9rgv5QReXtFpO1 6cp1+8jN6X6Slc1RAiE43P2E67LwnhY0g8UjudRH+WwILdheJUWoamY7gpSr12fZoW/m 5bDJ/ek+7eTPVEmUUctjhbRorOBDXw/8zJouu85PnCV6vkIhfWrIXfJk+XcvC5rIDx7l Hh/PBCx8mkIVchqwvUcw8iJQA9C+FBA8I7ZFZI8IjgFcfGruIzixDQAmt0KCEITDNMhz OBcPNcrMi1Pp1O31DLUWq43YM37T+qP9pIO+5ZiYN+QirUAKZnOoXwHhOP/ML82MCQWY TbpQ== X-Gm-Message-State: AOJu0Yx0BszNgXZBeasQFJwSzrOseuizpTm+Uvpg3t60rpc0Z9LRPfsX xdRNsF4tcmZrASq6RLoeacRiiIby4p8E7/QNC5T542Oq04m+seBM2PTdw9ZZuoeWOau/JqkfvDx 7PDb4jdo= X-Gm-Gg: Acq92OE848TVYh41BC5Ldlr8J8cWaK/7WMQe+aFlVzhzjAMSTZf5tKJGujLBGE7ZB+x aGm1pTxBp77NTwK7Y44tW+0XORcJLg0BvWuU2ccbcnAsdYS76l6fRDMmEQ43JEzuq28xUieft9P LvzHhgXyHlBk75/wbsRUf8QzX9LKxUkRt04aO47k8rtKqa+9WcVfayTC5K/nQJg3Q2yWocAKLqI 95wUtuzjf5WSPprlihJL/PGZ8WjR1AYX5hPLYV8ossBah2IRLOt6nV8xoMfAH69h53YlW5zW1I6 ikm+PsAOpqOfpDE5eX//KEVdjYxdOOaRljCSFq3faN/u2SoadRjz5w79NnrbMOMKpU2K9vHYZSH 4r52OxPlQYf+Ue+7AbESi9pDMexNX5x1X84sLncfLqIGsKZrhVSkvFIcld6/ZVMMNJcQyNK9ADW o9GaZ9YQmzxhZdf6SLmFizt8czNlzEHExUkE5GM6foCo53fjB3ReGVyf7tp+BzWGWLDP5pLHrgJ 18B99ZjlsKy4rFpsKVyE58dyy9qrP9f9Q== X-Received: by 2002:a05:600c:3b20:b0:490:b58b:a8cb with SMTP id 5b1f17b1804b1-490e5639d43mr30127665e9.26.1781176973027; Thu, 11 Jun 2026 04:22:53 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn , Klaus Jensen Subject: [PATCH v9 2/8] hw/nvme: add migration blockers for non-supported cases Date: Thu, 11 Jun 2026 13:22:43 +0200 Message-ID: <20260611112249.165012-3-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alexander@mihalicyn.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781177041741158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn Let's block migration for cases we don't support: - SR-IOV - CMB - PMR - SPDM No functional changes here, because NVMe migration is not supported at all as of this commit. Reviewed-by: Klaus Jensen Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- v9: - check-patch trivial fixes --- hw/nvme/ctrl.c | 211 +++++++++++++++++++++++++++++++++++++++++++ hw/nvme/nvme.h | 3 + include/block/nvme.h | 12 +++ 3 files changed, 226 insertions(+) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 815f39173c8..7510a9e0296 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -209,6 +209,7 @@ #include "hw/pci/msix.h" #include "hw/pci/pcie_sriov.h" #include "system/spdm-socket.h" +#include "migration/blocker.h" #include "migration/vmstate.h" =20 #include "nvme.h" @@ -252,6 +253,7 @@ static const bool nvme_feature_support[NVME_FID_MAX] = =3D { [NVME_COMMAND_SET_PROFILE] =3D true, [NVME_FDP_MODE] =3D true, [NVME_FDP_EVENTS] =3D true, + /* if you add something here, please update nvme_set_migration_blocker= s() */ }; =20 static const uint32_t nvme_feature_cap[NVME_FID_MAX] =3D { @@ -4603,6 +4605,7 @@ static uint16_t nvme_io_mgmt_send(NvmeCtrl *n, NvmeRe= quest *req) return 0; case NVME_IOMS_MO_RUH_UPDATE: return nvme_io_mgmt_send_ruh_update(n, req); + /* if you add something here, please update nvme_set_migration_blocker= s() */ default: return NVME_INVALID_FIELD | NVME_DNR; }; @@ -7522,6 +7525,10 @@ static uint16_t nvme_security_receive(NvmeCtrl *n, N= vmeRequest *req) =20 static uint16_t nvme_directive_send(NvmeCtrl *n, NvmeRequest *req) { + /* + * When adding a new dtype handling here, + * please also update nvme_set_migration_blockers(). + */ return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -9233,6 +9240,204 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *= pci_dev) } } =20 +#define BLOCKER_FEATURES_MAX_LEN 256 + +static inline void nvme_add_blocker_feature(char *blocker_features, + const char *feature) +{ + if (strlen(blocker_features) > 0) { + g_strlcat(blocker_features, ", ", BLOCKER_FEATURES_MAX_LEN); + } + g_strlcat(blocker_features, feature, BLOCKER_FEATURES_MAX_LEN); +} + +static bool nvme_set_migration_blockers(NvmeCtrl *n, PCIDevice *pci_dev, + Error **errp) +{ + uint64_t unsupported_cap, cap =3D ldq_le_p(&n->bar.cap); + char blocker_features[BLOCKER_FEATURES_MAX_LEN] =3D ""; + bool adm_cmd_security_checked =3D false; + bool cmd_io_mgmt_checked =3D false; + bool cmd_zone_checked =3D false; + + /* + * Idea of this function is simple, we iterate over all Command Sets a= nd + * for each supported command we provide a special handling logic to + * determine if we should block migration or not. + * + * For instance, we have NVME_ADM_CMD_NS_ATTACHMENT and it is always + * available to the guest, but if there is only 1 namespace, then it is + * safe to allow migration, but if there are more, then we need to blo= ck + * migration because we don't handle this in migration code yet. + */ + for (int opcode =3D 0; opcode < ARRAY_SIZE(n->cse.acs); opcode++) { + /* Is command supported? */ + if (!n->cse.acs[opcode]) { + continue; + } + + switch (opcode) { + case NVME_ADM_CMD_DELETE_SQ: + case NVME_ADM_CMD_CREATE_SQ: + case NVME_ADM_CMD_GET_LOG_PAGE: + case NVME_ADM_CMD_DELETE_CQ: + case NVME_ADM_CMD_CREATE_CQ: + case NVME_ADM_CMD_IDENTIFY: + case NVME_ADM_CMD_ABORT: + case NVME_ADM_CMD_SET_FEATURES: + case NVME_ADM_CMD_GET_FEATURES: + case NVME_ADM_CMD_ASYNC_EV_REQ: + case NVME_ADM_CMD_DBBUF_CONFIG: + case NVME_ADM_CMD_FORMAT_NVM: + case NVME_ADM_CMD_DIRECTIVE_SEND: + case NVME_ADM_CMD_DIRECTIVE_RECV: + break; + case NVME_ADM_CMD_NS_ATTACHMENT: + int namespaces_num =3D 0; + for (int i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { + NvmeNamespace *ns =3D nvme_subsys_ns(n->subsys, i); + if (!ns) { + continue; + } + + namespaces_num++; + } + + if (namespaces_num > 1) { + nvme_add_blocker_feature(blocker_features, + "Namespace Attachment"); + } + + break; + case NVME_ADM_CMD_VIRT_MNGMT: + if (n->params.sriov_max_vfs) { + nvme_add_blocker_feature(blocker_features, "SR-IOV"); + } + + break; + case NVME_ADM_CMD_SECURITY_SEND: + case NVME_ADM_CMD_SECURITY_RECV: + if (adm_cmd_security_checked) { + break; + } + + if (pci_dev->spdm_port) { + nvme_add_blocker_feature(blocker_features, "SPDM"); + } + + adm_cmd_security_checked =3D true; + + break; + default: + g_assert_not_reached(); + } + } + + for (int opcode =3D 0; opcode < ARRAY_SIZE(n->cse.iocs.nvm); opcode++)= { + if (!n->cse.iocs.nvm[opcode]) { + continue; + } + + switch (opcode) { + case NVME_CMD_FLUSH: + case NVME_CMD_WRITE: + case NVME_CMD_READ: + case NVME_CMD_COMPARE: + case NVME_CMD_WRITE_ZEROES: + case NVME_CMD_DSM: + case NVME_CMD_VERIFY: + case NVME_CMD_COPY: + break; + case NVME_CMD_IO_MGMT_RECV: + case NVME_CMD_IO_MGMT_SEND: + if (cmd_io_mgmt_checked) { + break; + } + + /* check for NVME_IOMS_MO_RUH_UPDATE */ + if (n->subsys->params.fdp.enabled) { + nvme_add_blocker_feature(blocker_features, "FDP"); + } + + cmd_io_mgmt_checked =3D true; + + break; + default: + g_assert_not_reached(); + } + } + + for (int opcode =3D 0; opcode < ARRAY_SIZE(n->cse.iocs.zoned); opcode+= +) { + /* + * If command isn't supported or we have the same command + * in n->cse.iocs.nvm, then we can skip it here. + */ + if (!n->cse.iocs.zoned[opcode] || n->cse.iocs.nvm[opcode]) { + continue; + } + + switch (opcode) { + case NVME_CMD_ZONE_APPEND: + case NVME_CMD_ZONE_MGMT_SEND: + case NVME_CMD_ZONE_MGMT_RECV: + if (cmd_zone_checked) { + break; + } + + for (int i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { + NvmeNamespace *ns =3D nvme_subsys_ns(n->subsys, i); + if (!ns) { + continue; + } + + if (ns->params.zoned) { + nvme_add_blocker_feature(blocker_features, + "Zoned Namespace"); + break; + } + } + + cmd_zone_checked =3D true; + + break; + default: + g_assert_not_reached(); + } + } + + /* + * Try our best to explicitly detect all not supported caps, + * to let users know what features cause migration to be blocked, + * but in case we miss handling here, everything else will be + * covered by unsupported_cap check. + */ + if (NVME_CAP_CMBS(cap)) { + nvme_add_blocker_feature(blocker_features, "CMB"); + cap &=3D ~((uint64_t)CAP_CMBS_MASK << CAP_CMBS_SHIFT); + } + + if (NVME_CAP_PMRS(cap)) { + nvme_add_blocker_feature(blocker_features, "PMR"); + cap &=3D ~((uint64_t)CAP_PMRS_MASK << CAP_PMRS_SHIFT); + } + + unsupported_cap =3D cap & ~NVME_MIGRATION_SUPPORTED_CAP_BITS; + if (unsupported_cap) { + nvme_add_blocker_feature(blocker_features, "unknown capability"); + } + + assert(n->migration_blocker =3D=3D NULL); + if (strlen(blocker_features) > 0) { + error_setg(&n->migration_blocker, + "Migration is not supported for %s", blocker_features); + if (migrate_add_blocker(&n->migration_blocker, errp) < 0) { + return false; + } + } + + return true; +} + static int nvme_init_subsys(NvmeCtrl *n, Error **errp) { int cntlid; @@ -9338,6 +9543,10 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 n->subsys->namespaces[ns->params.nsid] =3D ns; } + + if (!nvme_set_migration_blockers(n, pci_dev, errp)) { + return; + } } =20 static void nvme_exit(PCIDevice *pci_dev) @@ -9390,6 +9599,8 @@ static void nvme_exit(PCIDevice *pci_dev) } =20 memory_region_del_subregion(&n->bar0, &n->iomem); + + migrate_del_blocker(&n->migration_blocker); } =20 static const Property nvme_props[] =3D { diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 5ef3ebee29e..05aee24a15c 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -668,6 +668,9 @@ typedef struct NvmeCtrl { =20 /* Socket mapping to SPDM over NVMe Security In/Out commands */ int spdm_socket; + + /* Migration-related stuff */ + Error *migration_blocker; } NvmeCtrl; =20 typedef enum NvmeResetType { diff --git a/include/block/nvme.h b/include/block/nvme.h index e4e7be51205..17a7c7818d7 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -141,6 +141,18 @@ enum NvmeCapMask { #define NVME_CAP_SET_CMBS(cap, val) \ ((cap) |=3D (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT) =20 +#define NVME_MIGRATION_SUPPORTED_CAP_BITS ( \ + ((uint64_t)CAP_MQES_MASK << CAP_MQES_SHIFT) \ + | ((uint64_t)CAP_CQR_MASK << CAP_CQR_SHIFT) \ + | ((uint64_t)CAP_AMS_MASK << CAP_AMS_SHIFT) \ + | ((uint64_t)CAP_TO_MASK << CAP_TO_SHIFT) \ + | ((uint64_t)CAP_DSTRD_MASK << CAP_DSTRD_SHIFT) \ + | ((uint64_t)CAP_NSSRS_MASK << CAP_NSSRS_SHIFT) \ + | ((uint64_t)CAP_CSS_MASK << CAP_CSS_SHIFT) \ + | ((uint64_t)CAP_MPSMIN_MASK << CAP_MPSMIN_SHIFT) \ + | ((uint64_t)CAP_MPSMAX_MASK << CAP_MPSMAX_SHIFT) \ +) + enum NvmeCapCss { NVME_CAP_CSS_NCSS =3D 1 << 0, NVME_CAP_CSS_IOCSS =3D 1 << 6, --=20 2.47.3 From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2003:cf:570f:fe00:6c26:edf5:8ff0:62dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35fb24sm86375554f8f.34.2026.06.11.04.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 04:22:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mihalicyn.com; s=mihalicyn; t=1781176974; x=1781781774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hMXs98sZvrlyIMbqRYGDBzRG9ME97KoeTLg2sAOwlRo=; b=inBQHQsYR+5b3FIweE60IVJwuLjyRxSSPj5UHkfiJ/hm0pAXt4QmevcfNhFvZawNdf NgDZ5dgn/7xGcZvoI7CqYknk5/Uvcj0wW82pjXjebFDsAbhdJoRcxZLSDm+QrwyYSO1Y 4KAhNFGcf7Lq1oNQ9hM+hETWhsppqd5l3uZ9c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781176974; x=1781781774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=hMXs98sZvrlyIMbqRYGDBzRG9ME97KoeTLg2sAOwlRo=; b=goAZ67Z/DYekhYJOOjCwC3le4iIbGxBHWtHpXRmxHyExxhdk094HcuoY1H5Knu/BjI nasGv5/XxQ3soaWM0zG7FfrDVzgsX3Hic2f1zRwGI1dQOK6Bz8Cz1xJ0RcyYAwTLj57h Przx9LO0vj6b99jXP6LX5TBqtPAH0NWnS3CzXnM+02oiZM65gyn6I1UHYipPRc7IVFvn 3j8xCzidR/oxfLqY1FcGpyKxgz7EyrWpv0/ujOCBOfoXeDR0YHZvmXDCusNv827XBm0o mrX5bdtwVPltOjkwZFWr8t6Z5auIiwtFJ+r7nEmPm2a21ftrkznKpKhzqZoRVfs0wecq 54Yg== X-Gm-Message-State: AOJu0YwijPG/Y7dHy123ryxt12bx5jo7vsl4KKtDWpZx7ywKWDNEOuKe yZ9izeDJWYrvZO6mf82CjMRBG9RdmEBOe3ZigLhnfLEFrga3HC2SZZTAkVkd2Vy26/yJ6wEU64G rlqH5kII= X-Gm-Gg: Acq92OE3plpSpPwDWhDTTDUUL6W7jHli6e1pLW2Eg71n+DvtHoJ9zrtCKmmv/nl4SF6 rzjPWA1vcUZrQpyyVj2FlNvrRMLf9v1t7CXoRi78v+ejf9Hir3u7S+DWQGK9RrvfDgv1+88OpJu 36IIe/W5ArSBdSgtfVcOmgAAchdtWYuz194IUt1RExPOM3/nn4sCYiDsTDs/FYi03N1rRM2G2C1 FCY+fFgrDHeHVDGjtbhrt90260Jg2Z0jQ+IGupEaW2MHW6bCji+/NDO+qAEKHF4Dyq+NraGAoJf iqXj3bF4yOy/tVHkGOcC6k4a7asf3BXrOOXt6wY9RS56+B7/Cv+PDOHrDjge0ERh1LGC96wJPVQ PGrNualrj4vncURfQxqBOhN+2/MsA25Y/dhuu1hAUGH5TubMZEPmo/TTue4qXOLyTaDJInKqteN zIG9dWLloFhffyfTrjgoaI2ollx4sCBaCMUB9zeaXHKpnctFxOIoeBfjz+35qLVv+O7yVRCloR8 h3H9a+k9E7BMeu1N0wijPpfmBuoRSWrJA== X-Received: by 2002:a05:600d:8489:10b0:490:bfda:7d7e with SMTP id 5b1f17b1804b1-490e55cc58amr20300485e9.3.1781176974177; Thu, 11 Jun 2026 04:22:54 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn , Klaus Jensen Subject: [PATCH v9 3/8] hw/nvme: split nvme_init_sq/nvme_init_cq into helpers Date: Thu, 11 Jun 2026 13:22:44 +0200 Message-ID: <20260611112249.165012-4-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alexander@mihalicyn.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781177053560158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn We will make a benefit from this split in later patches. Reviewed-by: Klaus Jensen Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- hw/nvme/ctrl.c | 59 +++++++++++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 22 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 7510a9e0296..26bb4b52d4d 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -4856,18 +4856,14 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeReques= t *req) return NVME_SUCCESS; } =20 -static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr, - uint16_t sqid, uint16_t cqid, uint16_t size) +static void __nvme_init_sq(NvmeSQueue *sq) { + NvmeCtrl *n =3D sq->ctrl; + uint16_t sqid =3D sq->sqid; + uint16_t cqid =3D sq->cqid; int i; NvmeCQueue *cq; =20 - sq->ctrl =3D n; - sq->dma_addr =3D dma_addr; - sq->sqid =3D sqid; - sq->size =3D size; - sq->cqid =3D cqid; - sq->head =3D sq->tail =3D 0; sq->io_req =3D g_new0(NvmeRequest, sq->size); =20 QTAILQ_INIT(&sq->req_list); @@ -4897,6 +4893,18 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n= , uint64_t dma_addr, n->sq[sqid] =3D sq; } =20 +static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr, + uint16_t sqid, uint16_t cqid, uint16_t size) +{ + sq->ctrl =3D n; + sq->dma_addr =3D dma_addr; + sq->sqid =3D sqid; + sq->size =3D size; + sq->cqid =3D cqid; + sq->head =3D sq->tail =3D 0; + __nvme_init_sq(sq); +} + static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req) { NvmeSQueue *sq; @@ -5557,25 +5565,16 @@ static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeReques= t *req) return NVME_SUCCESS; } =20 -static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr, - uint16_t cqid, uint16_t vector, uint16_t size, - uint16_t irq_enabled) +static void __nvme_init_cq(NvmeCQueue *cq) { + NvmeCtrl *n =3D cq->ctrl; PCIDevice *pci =3D PCI_DEVICE(n); + uint16_t cqid =3D cq->cqid; =20 - if (msix_present(pci) && irq_enabled) { - msix_vector_use(pci, vector); + if (msix_present(pci) && cq->irq_enabled) { + msix_vector_use(pci, cq->vector); } =20 - cq->ctrl =3D n; - cq->cqid =3D cqid; - cq->size =3D size; - cq->dma_addr =3D dma_addr; - cq->phase =3D 1; - cq->irq_enabled =3D irq_enabled; - cq->vector =3D vector; - cq->head =3D cq->tail =3D 0; - QTAILQ_INIT(&cq->req_list); QTAILQ_INIT(&cq->sq_list); if (n->dbbuf_enabled) { cq->db_addr =3D n->dbbuf_dbs + (cqid << 3) + (1 << 2); @@ -5592,6 +5591,22 @@ static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n= , uint64_t dma_addr, &DEVICE(cq->ctrl)->mem_reentrancy_guard); } =20 +static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr, + uint16_t cqid, uint16_t vector, uint16_t size, + uint16_t irq_enabled) +{ + cq->ctrl =3D n; + cq->cqid =3D cqid; + cq->size =3D size; + cq->dma_addr =3D dma_addr; + cq->phase =3D 1; + cq->irq_enabled =3D irq_enabled; + cq->vector =3D vector; + cq->head =3D cq->tail =3D 0; + QTAILQ_INIT(&cq->req_list); + __nvme_init_cq(cq); +} + static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req) { NvmeCQueue *cq; --=20 2.47.3 From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2003:cf:570f:fe00:6c26:edf5:8ff0:62dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35fb24sm86375554f8f.34.2026.06.11.04.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 04:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mihalicyn.com; s=mihalicyn; t=1781176975; x=1781781775; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=srlFZliq3fb8dZ8MUjWEZdk1nX+hqV3YhWF/DVUMbMs=; b=NgkDMS0TOuzSzvoTsqm4YZG+jt0mq5tmrSoTm6z6xd8qpELZuuSwX/LkxGCWPAgtaV DvySGC/zbG4f4k4cX44Spdny/F8bnf7IvmZ26LtdtEZVS+qk1kbdyYB5cS5qRPMbjB84 mbwmJ/47+OKp4E3l2SIbWrKf1EPdsUDLzzHpU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781176975; x=1781781775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=srlFZliq3fb8dZ8MUjWEZdk1nX+hqV3YhWF/DVUMbMs=; b=f1E8ImCxNYuljHDj9NvAmffsOzk4Igqimo8b1xiu9wYopPE0K1Fn8EuaaHiPeMIsn3 oUZScGJ5sOoE3rTXr8Z/kI52H3oNFYk8xt4P+NPNa0GYHn4rZYlkTwR8ABVYeH17J5o0 B1/cftmVMd7hPSY7ONgHpGAMgQFGhAVg1U8fn4jzQWD5Zx01/QGHPWfbcGaKg6QeVara 7QHEEBmVkkK66yFW4FxHKDD/s2qDJLO4Ld6nQIWFsLJK9V0es7PeiqFZs4TmSjOKRnap v7h4D9Idgeh/eknvAktE5nDrDiRqwkVCMf7L4MEybinqnkSzfYTZTcHQ/WKC7PPyiab5 yO0A== X-Gm-Message-State: AOJu0YxMAsebiCXZoDSlhVZfOcoRy5aDWKdUj8C0lLBCW6fKsryP1HH+ VM04mQfsIBtElBLtXEEmV7rvxUORRsYPwGnJ9pDJf0kceBw+iVzPIMtM4ez4CkrZVzLKJBkKHAr 4UkM/qDo= X-Gm-Gg: Acq92OH+u2clJFU0qYxEzbhZP3h73gcdMn2cYaJ53RWhf2YeMUSttmAO3WH7eCnHAl2 s41a7ydk0BGO55PygBL5IDCv2n4QuZKNIRmEdZ3/iSSuTqQjTsusAPTgBAxBwvzdoAvwb4SKK0x hjRkWfVDFNVYSqX5vyBKogeZXG8FwanEP2EyElWOpguRWcCwbHwjazHC0FRqVAdoVwXmJ8dLUka /AhgVzdkrFbcNBqcbsSkW8OjYJcpOmqNN/Umqv/neK+pktIFav6cfWataRfLLzNVOGEDI0Uq05F 8WkHTg9THBUCcR75nS/JnnkTMDLfpgnJ93YbYt1hdZmwL6Otyg3kK8qlkGPZwFQzy1vDFXVKPcz w3LUvjk1HKWURgiOsvWIa3mB0bfxQ3Qkvrz3XZkkJs5tpwZX0/VxTHHvkOU3Nk+Fs1A/qwe49As SDEFhIfP/lhHarwBpuGGVbmeE26qCQyWbBRwdoiAdazHoWKbJYyR+mrQXT6o5rHbFnNwVpWTHGl xsdW62AjpyRLxAK7GulSTKepUnqyIPH8g== X-Received: by 2002:a05:6000:18a6:b0:43b:5097:6f62 with SMTP id ffacd0b85a97d-460677a92bcmr3772519f8f.36.1781176975279; Thu, 11 Jun 2026 04:22:55 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn , Klaus Jensen Subject: [PATCH v9 4/8] hw/nvme: set CQE.sq_id earlier in nvme_process_sq Date: Thu, 11 Jun 2026 13:22:45 +0200 Message-ID: <20260611112249.165012-5-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alexander@mihalicyn.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781177055550158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn Instead of filling req->cqe.sq_id in nvme_post_cqes, let's set it earlier in nvme_process_sq. This shouldn't cause any issues, because req->cqe.sq_id never changes during lifetime of req. This will help us for migration support. Reviewed-by: Klaus Jensen Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- hw/nvme/ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 26bb4b52d4d..5569e6872d6 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1522,7 +1522,6 @@ static void nvme_post_cqes(void *opaque) =20 sq =3D req->sq; req->cqe.status =3D cpu_to_le16((req->status << 1) | cq->phase); - req->cqe.sq_id =3D cpu_to_le16(sq->sqid); req->cqe.sq_head =3D cpu_to_le16(sq->head); addr =3D cq->dma_addr + (cq->tail << NVME_CQES); ret =3D pci_dma_write(PCI_DEVICE(n), addr, (void *)&req->cqe, @@ -7852,6 +7851,7 @@ static void nvme_process_sq(void *opaque) QTAILQ_REMOVE(&sq->req_list, req, entry); QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry); nvme_req_clear(req); + req->cqe.sq_id =3D cpu_to_le16(sq->sqid); req->cqe.cid =3D cmd.cid; memcpy(&req->cmd, &cmd, sizeof(NvmeCmd)); =20 --=20 2.47.3 From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=mihalicyn.com ARC-Seal: i=1; a=rsa-sha256; t=1781177019; cv=none; d=zohomail.com; s=zohoarc; b=R0wnWCJR16TlTpwZnfTiFaP/8onrJaJccnk1/WZL3YCbM4K3NHpZUiNcrSfMm+dpR2WF2bk9D+F1Lf/TycEQfhoqGEsu1dibRkNM8iHg6gGDcSXWxk1eVXBHhmE1r93U+FTpV+KMQEsUKxdVbp8GSaUppLgi5DhMveBsuMYvH/8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781177019; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4uBDjD++ufYkPG4JfE12kYu5daqsRYxf0c/eetggXvQ=; b=RBrdsUKhzYWx0OcSgjfJDQ3rdv/g5YLBw2Rc53s7b68gngsJLieL8ZcKKNYAxm+eHHCEM/7nAyvTwBUUmgRgl9Mr4D+VvMkvfxSniwjrCwd5ISoVRbeJObl5CiYT6g5Pk1NhTLHJaa2MRA6kBvJkbpWtoj4/XnLhS4mSiqv7CwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781177019539324.2666232420653; Thu, 11 Jun 2026 04:23:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXdV1-0001VC-Dn; Thu, 11 Jun 2026 07:23:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXdUy-0001Nk-6y for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:23:00 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wXdUv-00017K-TW for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:22:59 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-45eee266c6cso6417818f8f.1 for ; Thu, 11 Jun 2026 04:22:57 -0700 (PDT) Received: from alex-laptop.lan (p200300cf570ffe006c26edf58ff062dc.dip0.t-ipconnect.de. [2003:cf:570f:fe00:6c26:edf5:8ff0:62dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35fb24sm86375554f8f.34.2026.06.11.04.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 04:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mihalicyn.com; s=mihalicyn; t=1781176976; x=1781781776; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4uBDjD++ufYkPG4JfE12kYu5daqsRYxf0c/eetggXvQ=; b=L+OJ24KpLF5AGEfkMN3D5zkSbG4dEnQzx3A5oGiVdjbunpDHFoonqmt5ik1n/m3NW4 qUUDs81qrOgGalmKNd0n9kL1SdrC8HjbBmT8XlyzwwGqhvAtnfjGGiSmnLGBkWEzqP19 1MmLLc3R0OEjF0yS702APK1Nch/w1skAz3Zr8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781176976; x=1781781776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=4uBDjD++ufYkPG4JfE12kYu5daqsRYxf0c/eetggXvQ=; b=fZsxYTK32Jifz6yVNj2/AchvixOx+Ak/ea/pYBNzP584jJ3SU5xU+mkRb7q48LT7NJ EB9E4FF3GjrryHGMhGyyjt15CJFWtHTEPGAdgl2kcvWUaDajPXM/BJM+OcLa/6UUlr8z zJsoH1z2my/eIQS3ik+2c0WC0XY7nYIjkc3GJbXd+/IEc1zBHsIHQbVPUpVNWEW8Dx/S jbKz2Kq5mxSZ48GHt0MSw+nqjCLKXKk2mn3zbqQSmK1RTxZ22nnURmvCRdCUhUejE9x7 A0BDiUdjAFcEVPZrnUTBlW+Zi0Tz41YNGzoomKuIz4NZGRfFLP33TV0xAxbgEjx3U9cT dnoA== X-Gm-Message-State: AOJu0Yz9IKlzRJ46+Hij6pu6F22KMmnFjkIs7jjLTsk789szdFLUz94I lmDAwqlQXuxk1MU9KBKOOkqHR8u2fdqNUWP18j1GsqL6drnyOder1JZPxUuDaWE46430ptV1LTd g3gxQS8I= X-Gm-Gg: Acq92OFYkPdSSP1aSoj/gBXCXWWY56zb1ZxPt2/me7pi0m4Ls1rN4K7JmxXxLKrWwT9 oxEv5op7nxsH0zx/D5AcPiqKFpIvpuu20sUGiF8S2Y/IKy0wJDhL5QJ8S8xe9ZlmJ8WP4JPJBJi GVUwIDl4mCxmcyjEZmnF5/98W9CABxakRJQ0xm0MkiDXd/GcXm4pGP4l0seaeF4zgffr+c8hEpO 2IvbcP6ot7+6GaR9gUp5a78q6Cxz+5FGqf+GdFBXpqSzB2P5MLSqdAiQt3b7z1yMRPe0Awv26k8 RtgW4YVK6bERGke6Vl6KJM2CldhO8+GH2DGlEoVfPNEYweLlDn3GV+QIu5BkT1lE5q79z0rWOmG GBWa1dsyJuMhYIxs1JyWAmgB7LThc+tl/yiTpBJ9tSxR4ncU4o5+6Mj4+fJp1bPQ3U85HDs3S2q 5hZTvRe/XX3/N2UnR72ykQWGsOG9EsND5G8/40ET9cJz4YOxNCoTyZqkLllqxReRDn7H1/9psR7 orMRwjy1AY+3xyCYsnlRSDT7ZjARJazDg== X-Received: by 2002:a05:6000:4022:b0:43f:e22e:e8da with SMTP id ffacd0b85a97d-4606758d0b1mr3825025f8f.5.1781176976412; Thu, 11 Jun 2026 04:22:56 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn , Klaus Jensen Subject: [PATCH v9 5/8] hw/nvme: unmap req->sg earlier in nvme_enqueue_req_completion Date: Thu, 11 Jun 2026 13:22:46 +0200 Message-ID: <20260611112249.165012-6-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alexander@mihalicyn.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781177021609158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn Instead of unmapping req->sg in nvme_post_cqes(), we can do it earlier in nvme_enqueue_req_completion(). When req completion is enqueued we don't need to access req->sg anymore. We only care about req->sq, req->cqe and req->status. Reviewed-by: Klaus Jensen Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- hw/nvme/ctrl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 5569e6872d6..c65b43a04ca 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1536,7 +1536,6 @@ static void nvme_post_cqes(void *opaque) QTAILQ_REMOVE(&cq->req_list, req, entry); =20 nvme_inc_cq_tail(cq); - nvme_sg_unmap(&req->sg); =20 if (QTAILQ_EMPTY(&sq->req_list) && !nvme_sq_empty(sq)) { qemu_bh_schedule(sq->bh); @@ -1566,6 +1565,8 @@ static void nvme_enqueue_req_completion(NvmeCQueue *c= q, NvmeRequest *req) req->status, req->cmd.opcode); } =20 + nvme_sg_unmap(&req->sg); + QTAILQ_REMOVE(&req->sq->out_req_list, req, entry); QTAILQ_INSERT_TAIL(&cq->req_list, req, entry); =20 --=20 2.47.3 From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=mihalicyn.com ARC-Seal: i=1; a=rsa-sha256; t=1781177040; cv=none; d=zohomail.com; s=zohoarc; b=mXkc+rkHQm+loId7AA1gDcKYE/p2Z52VSeB5rSrnj1QzEhKoXk2OVmOMqwJ0/rfiU8AHgtjVLSaXaLOIhYEWipOl5FUnLjgs/S72uK5vD+EPdrgmlv1Y/vY2Pu99EMN6eRgJrzgEBhyCpK3G1NNkQHcDUbdrXmMCb8/CtexuJKE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781177040; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YKDTof7hhx4rEM/ecDz8BbuNNqta8VjPAfvh6jFaR7A=; b=aZp5eYXgO55gZiJIhfPi1teEq6fObQLUcsqW1fRHfRjAZ81m4u/REioXXtR0I1LdzKFezY+SelzkBVbSU6wrZUoELVFaxCFjHdbQHFWBdlolGIdmiUWSkTsS7YRHwz3kBKSFQ+bv5tJ8x+DPA523a7FXIcE4D+Wtx8HCZnp3Caw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781177040810939.2432062018903; Thu, 11 Jun 2026 04:24:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXdV4-0001WQ-0z; Thu, 11 Jun 2026 07:23:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXdV2-0001Vd-CZ for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:23:04 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wXdUx-000183-LE for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:23:04 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-45fd461e4a5so5479884f8f.0 for ; Thu, 11 Jun 2026 04:22:59 -0700 (PDT) Received: from alex-laptop.lan (p200300cf570ffe006c26edf58ff062dc.dip0.t-ipconnect.de. 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Thu, 11 Jun 2026 04:22:57 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn Subject: [PATCH v9 6/8] hw/nvme: add basic live migration support Date: Thu, 11 Jun 2026 13:22:47 +0200 Message-ID: <20260611112249.165012-7-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alexander@mihalicyn.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781177043455158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn It has some limitations: - only one NVMe namespace is supported - SMART counters are not preserved - CMB is not supported - PMR is not supported - SPDM is not supported - SR-IOV is not supported Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- v2: - AERs are now fully supported v6: - handle full CQ case v7: - renamed copy_cq_req_list to move_cq_req_list - validate incoming migration stream better v9: - trivial check-patch fixes --- hw/nvme/ctrl.c | 760 ++++++++++++++++++++++++++++++++++++++++++- hw/nvme/ns.c | 164 ++++++++++ hw/nvme/nvme.h | 9 + hw/nvme/trace-events | 10 + 4 files changed, 934 insertions(+), 9 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index c65b43a04ca..ced394276d3 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -210,6 +210,7 @@ #include "hw/pci/pcie_sriov.h" #include "system/spdm-socket.h" #include "migration/blocker.h" +#include "migration/qemu-file-types.h" #include "migration/vmstate.h" =20 #include "nvme.h" @@ -1520,6 +1521,18 @@ static void nvme_post_cqes(void *opaque) break; } =20 + /* + * Here we take the following fields from NvmeRequest structure + * and write cqe to the guest RAM based on them: + * - req->sq + * - req->status + * - req->cqe + * + * If you change this code and more fields from NvmeRequest are + * used, please make sure that you have handled this in: + * nvme_vmstate_request and nvme_ctrl_pre_save(). + */ + sq =3D req->sq; req->cqe.status =3D cpu_to_le16((req->status << 1) | cq->phase); req->cqe.sq_head =3D cpu_to_le16(sq->head); @@ -4905,6 +4918,25 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n= , uint64_t dma_addr, __nvme_init_sq(sq); } =20 +static void nvme_restore_sq(NvmeSQueue *sq_from) +{ + NvmeCtrl *n =3D sq_from->ctrl; + NvmeSQueue *sq =3D sq_from; + + if (sq_from->sqid =3D=3D 0) { + sq =3D &n->admin_sq; + sq->ctrl =3D n; + sq->dma_addr =3D sq_from->dma_addr; + sq->sqid =3D sq_from->sqid; + sq->size =3D sq_from->size; + sq->cqid =3D sq_from->cqid; + sq->head =3D sq_from->head; + sq->tail =3D sq_from->tail; + } + + __nvme_init_sq(sq); +} + static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req) { NvmeSQueue *sq; @@ -5607,6 +5639,39 @@ static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n= , uint64_t dma_addr, __nvme_init_cq(cq); } =20 +static void move_cq_req_list(NvmeCQueue *cq_to, NvmeCQueue *cq_from) +{ + NvmeRequest *req, *next; + + QTAILQ_FOREACH_SAFE(req, &cq_from->req_list, entry, next) { + QTAILQ_REMOVE(&cq_from->req_list, req, entry); + QTAILQ_INSERT_TAIL(&cq_to->req_list, req, entry); + } +} + +static void nvme_restore_cq(NvmeCQueue *cq_from) +{ + NvmeCtrl *n =3D cq_from->ctrl; + NvmeCQueue *cq =3D cq_from; + + if (cq_from->cqid =3D=3D 0) { + cq =3D &n->admin_cq; + cq->ctrl =3D n; + cq->cqid =3D cq_from->cqid; + cq->size =3D cq_from->size; + cq->dma_addr =3D cq_from->dma_addr; + cq->phase =3D cq_from->phase; + cq->irq_enabled =3D cq_from->irq_enabled; + cq->vector =3D cq_from->vector; + cq->head =3D cq_from->head; + cq->tail =3D cq_from->tail; + QTAILQ_INIT(&cq->req_list); + move_cq_req_list(cq, cq_from); + } + + __nvme_init_cq(cq); +} + static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req) { NvmeCQueue *cq; @@ -7297,7 +7362,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const = NvmeRequest *req) n->dbbuf_eis =3D eis_addr; n->dbbuf_enabled =3D true; =20 - for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { + for (i =3D 0; i < n->num_queues; i++) { NvmeSQueue *sq =3D n->sq[i]; NvmeCQueue *cq =3D n->cq[i]; =20 @@ -7741,7 +7806,7 @@ static int nvme_atomic_write_check(NvmeCtrl *n, NvmeC= md *cmd, /* * Walk the queues to see if there are any atomic conflicts. */ - for (i =3D 1; i < n->params.max_ioqpairs + 1; i++) { + for (i =3D 1; i < n->num_queues; i++) { NvmeSQueue *sq; NvmeRequest *req; NvmeRwCmd *req_rw; @@ -7811,6 +7876,12 @@ static void nvme_process_sq(void *opaque) NvmeCmd cmd; NvmeRequest *req; =20 + /* + * We don't want to have a race with nvme_ctrl_pre_save(). + * What implicitly protects us from this is BQL. + */ + assert(bql_locked()); + if (n->dbbuf_enabled) { nvme_update_sq_tail(sq); } @@ -7928,12 +7999,12 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetT= ype rst) nvme_ns_drain(ns); } =20 - for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { + for (i =3D 0; i < n->num_queues; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { + for (i =3D 0; i < n->num_queues; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -8603,6 +8674,8 @@ static bool nvme_check_params(NvmeCtrl *n, Error **er= rp) params->max_ioqpairs =3D params->num_queues - 1; } =20 + n->num_queues =3D params->max_ioqpairs + 1; + if (n->namespace.blkconf.blk && n->subsys) { error_setg(errp, "subsystem support is unavailable with legacy " "namespace ('drive' property)"); @@ -8776,8 +8849,8 @@ static void nvme_init_state(NvmeCtrl *n) n->conf_msix_qsize =3D n->params.msix_qsize; } =20 - n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); - n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); + n->sq =3D g_new0(NvmeSQueue *, n->num_queues); + n->cq =3D g_new0(NvmeCQueue *, n->num_queues); n->temperature =3D NVME_TEMPERATURE; n->features.temp_thresh_hi =3D NVME_TEMPERATURE_WARNING; n->starttime_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); @@ -9012,7 +9085,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) } =20 if (n->params.msix_exclusive_bar && !pci_is_vf(pci_dev)) { - bar_size =3D nvme_mbar_size(n->params.max_ioqpairs + 1, 0, NULL, N= ULL); + bar_size =3D nvme_mbar_size(n->num_queues, 0, NULL, NULL); memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nv= me", bar_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | @@ -9024,7 +9097,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) /* add one to max_ioqpairs to account for the admin queue pair */ if (!pci_is_vf(pci_dev)) { nr_vectors =3D n->params.msix_qsize; - bar_size =3D nvme_mbar_size(n->params.max_ioqpairs + 1, + bar_size =3D nvme_mbar_size(n->num_queues, nr_vectors, &msix_table_offset, &msix_pba_offset); } else { @@ -9756,9 +9829,678 @@ static uint32_t nvme_pci_read_config(PCIDevice *dev= , uint32_t address, int len) return pci_default_read_config(dev, address, len); } =20 +static const VMStateDescription nvme_vmstate_cqe =3D { + .name =3D "nvme-cqe", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(result, NvmeCqe), + VMSTATE_UINT32(dw1, NvmeCqe), + VMSTATE_UINT16(sq_head, NvmeCqe), + VMSTATE_UINT16(sq_id, NvmeCqe), + VMSTATE_UINT16(cid, NvmeCqe), + VMSTATE_UINT16(status, NvmeCqe), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_cmd_dptr_sgl =3D { + .name =3D "nvme-request-cmd-dptr-sgl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(addr, NvmeSglDescriptor), + VMSTATE_UINT32(len, NvmeSglDescriptor), + VMSTATE_UINT8_ARRAY(rsvd, NvmeSglDescriptor, 3), + VMSTATE_UINT8(type, NvmeSglDescriptor), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_cmd_dptr =3D { + .name =3D "nvme-request-cmd-dptr", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(prp1, NvmeCmdDptr), + VMSTATE_UINT64(prp2, NvmeCmdDptr), + VMSTATE_STRUCT(sgl, NvmeCmdDptr, 0, + nvme_vmstate_cmd_dptr_sgl, NvmeSglDescriptor), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_cmd =3D { + .name =3D "nvme-request-cmd", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8(opcode, NvmeCmd), + VMSTATE_UINT8(flags, NvmeCmd), + VMSTATE_UINT16(cid, NvmeCmd), + VMSTATE_UINT32(nsid, NvmeCmd), + VMSTATE_UINT64(res1, NvmeCmd), + VMSTATE_UINT64(mptr, NvmeCmd), + VMSTATE_STRUCT(dptr, NvmeCmd, 0, nvme_vmstate_cmd_dptr, NvmeCmdDpt= r), + VMSTATE_UINT32(cdw10, NvmeCmd), + VMSTATE_UINT32(cdw11, NvmeCmd), + VMSTATE_UINT32(cdw12, NvmeCmd), + VMSTATE_UINT32(cdw13, NvmeCmd), + VMSTATE_UINT32(cdw14, NvmeCmd), + VMSTATE_UINT32(cdw15, NvmeCmd), + VMSTATE_END_OF_LIST() + } +}; + +static bool nvme_req_pre_load(void *opaque, Error **errp) +{ + memset(opaque, 0x0, sizeof(NvmeRequest)); + return true; +} + +static const VMStateDescription nvme_vmstate_request =3D { + .name =3D "nvme-request", + .version_id =3D 1, + .minimum_version_id =3D 1, + .pre_load_errp =3D nvme_req_pre_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT16(status, NvmeRequest), + VMSTATE_STRUCT(cqe, NvmeRequest, 0, nvme_vmstate_cqe, NvmeCqe), + VMSTATE_STRUCT(cmd, NvmeRequest, 0, nvme_vmstate_cmd, NvmeCmd), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_bar =3D { + .name =3D "nvme-bar", + .minimum_version_id =3D 1, + .version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(cap, NvmeBar), + VMSTATE_UINT32(vs, NvmeBar), + VMSTATE_UINT32(intms, NvmeBar), + VMSTATE_UINT32(intmc, NvmeBar), + VMSTATE_UINT32(cc, NvmeBar), + VMSTATE_UINT8_ARRAY(rsvd24, NvmeBar, 4), + VMSTATE_UINT32(csts, NvmeBar), + VMSTATE_UINT32(nssr, NvmeBar), + VMSTATE_UINT32(aqa, NvmeBar), + VMSTATE_UINT64(asq, NvmeBar), + VMSTATE_UINT64(acq, NvmeBar), + VMSTATE_UINT32(cmbloc, NvmeBar), + VMSTATE_UINT32(cmbsz, NvmeBar), + VMSTATE_UINT32(bpinfo, NvmeBar), + VMSTATE_UINT32(bprsel, NvmeBar), + VMSTATE_UINT64(bpmbl, NvmeBar), + VMSTATE_UINT64(cmbmsc, NvmeBar), + VMSTATE_UINT32(cmbsts, NvmeBar), + VMSTATE_UINT8_ARRAY(rsvd92, NvmeBar, 3492), + VMSTATE_UINT32(pmrcap, NvmeBar), + VMSTATE_UINT32(pmrctl, NvmeBar), + VMSTATE_UINT32(pmrsts, NvmeBar), + VMSTATE_UINT32(pmrebs, NvmeBar), + VMSTATE_UINT32(pmrswtp, NvmeBar), + VMSTATE_UINT32(pmrmscl, NvmeBar), + VMSTATE_UINT32(pmrmscu, NvmeBar), + VMSTATE_UINT8_ARRAY(css, NvmeBar, 484), + VMSTATE_END_OF_LIST() + }, +}; + +static bool nvme_cqueue_pre_load(void *opaque, Error **errp) +{ + NvmeCQueue *cq =3D opaque; + + QTAILQ_INIT(&cq->req_list); + return true; +} + +static const VMStateDescription nvme_vmstate_cqueue =3D { + .name =3D "nvme-cq", + .version_id =3D 1, + .minimum_version_id =3D 1, + .pre_load_errp =3D nvme_cqueue_pre_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8(phase, NvmeCQueue), + VMSTATE_UINT16(cqid, NvmeCQueue), + VMSTATE_UINT16(irq_enabled, NvmeCQueue), + VMSTATE_UINT32(head, NvmeCQueue), + VMSTATE_UINT32(tail, NvmeCQueue), + VMSTATE_UINT32(vector, NvmeCQueue), + VMSTATE_UINT32(size, NvmeCQueue), + VMSTATE_UINT64(dma_addr, NvmeCQueue), + + VMSTATE_QTAILQ_V(req_list, NvmeCQueue, 1, nvme_vmstate_request, + NvmeRequest, entry), + + /* db_addr, ei_addr, etc will be recalculated */ + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_squeue =3D { + .name =3D "nvme-sq", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT16(sqid, NvmeSQueue), + VMSTATE_UINT16(cqid, NvmeSQueue), + VMSTATE_UINT32(head, NvmeSQueue), + VMSTATE_UINT32(tail, NvmeSQueue), + VMSTATE_UINT32(size, NvmeSQueue), + VMSTATE_UINT64(dma_addr, NvmeSQueue), + /* db_addr, ei_addr, etc will be recalculated */ + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_async_event_result =3D { + .name =3D "nvme-async-event-result", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8(event_type, NvmeAerResult), + VMSTATE_UINT8(event_info, NvmeAerResult), + VMSTATE_UINT8(log_page, NvmeAerResult), + VMSTATE_UINT8(resv, NvmeAerResult), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_async_event =3D { + .name =3D "nvme-async-event", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_STRUCT(result, NvmeAsyncEvent, 0, + nvme_vmstate_async_event_result, NvmeAerResult), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_hbs =3D { + .name =3D "nvme-hbs", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8(acre, NvmeHostBehaviorSupport), + VMSTATE_UINT8(etdas, NvmeHostBehaviorSupport), + VMSTATE_UINT8(lbafee, NvmeHostBehaviorSupport), + VMSTATE_UINT8(rsvd3, NvmeHostBehaviorSupport), + VMSTATE_UINT16(cdfe, NvmeHostBehaviorSupport), + VMSTATE_UINT8_ARRAY(rsvd6, NvmeHostBehaviorSupport, 506), + VMSTATE_END_OF_LIST() + } +}; + +const VMStateDescription nvme_vmstate_atomic =3D { + .name =3D "nvme-atomic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(atomic_max_write_size, NvmeAtomic), + VMSTATE_UINT64(atomic_boundary, NvmeAtomic), + VMSTATE_UINT64(atomic_nabo, NvmeAtomic), + VMSTATE_BOOL(atomic_writes, NvmeAtomic), + VMSTATE_END_OF_LIST() + } +}; + +static bool pre_save_validate_aer_req(NvmeRequest *req, Error **errp) +{ + /* + * Can't use assert() here, because we don't want + * to just crash QEMU when user requests a migration. + */ + if (!(req->cmd.opcode =3D=3D NVME_ADM_CMD_ASYNC_EV_REQ)) { + error_setg(errp, "req->cmd.opcode (%u) !=3D NVME_ADM_CMD_ASYNC_EV_= REQ", + req->cmd.opcode); + return false; + } + + if (!(req->ns =3D=3D NULL)) { + error_setg(errp, "req->ns !=3D NULL"); + return false; + } + + if (!(req->sq =3D=3D &req->sq->ctrl->admin_sq)) { + error_setg(errp, "req->sq !=3D &req->sq->ctrl->admin_sq"); + return false; + } + + if (!(req->aiocb =3D=3D NULL)) { + error_setg(errp, "req->aiocb !=3D NULL"); + return false; + } + + if (!(req->opaque =3D=3D NULL)) { + error_setg(errp, "req->opaque !=3D NULL"); + return false; + } + + if (!(req->atomic_write =3D=3D false)) { + error_setg(errp, "req->atomic_write !=3D false"); + return false; + } + + if (req->sg.flags & NVME_SG_ALLOC) { + error_setg(errp, "unexpected NVME_SG_ALLOC flag in req->sg.flags"); + return false; + } + + return true; +} + +static bool pre_save_validate_cq_req(NvmeRequest *req, Error **errp) +{ + if (!(req->ns =3D=3D NULL)) { + error_setg(errp, "req->ns !=3D NULL"); + return false; + } + + if (!(req->aiocb =3D=3D NULL)) { + error_setg(errp, "req->aiocb !=3D NULL"); + return false; + } + + if (!(req->opaque =3D=3D NULL)) { + error_setg(errp, "req->opaque !=3D NULL"); + return false; + } + + if (!(req->atomic_write =3D=3D false)) { + error_setg(errp, "req->atomic_write !=3D false"); + return false; + } + + if (req->sg.flags & NVME_SG_ALLOC) { + error_setg(errp, "unexpected NVME_SG_ALLOC flag in req->sg.flags"); + return false; + } + + return true; +} + +static bool nvme_ctrl_pre_save(void *opaque, Error **errp) +{ + NvmeCtrl *n =3D opaque; + int i; + + trace_pci_nvme_pre_save_enter(n); + + /* + * We don't want to have a race with nvme_process_sq(). + * What implicitly protects us from this is BQL. + */ + assert(bql_locked()); + + /* cancel all SQ processing BHs */ + for (i =3D 0; i < n->num_queues; i++) { + NvmeSQueue *sq =3D n->sq[i]; + + if (!sq) { + continue; + } + + qemu_bh_cancel(sq->bh); + } + + /* drain all IO */ + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { + NvmeNamespace *ns; + + ns =3D nvme_ns(n, i); + if (!ns) { + continue; + } + + trace_pci_nvme_pre_save_ns_drain(n, i); + nvme_ns_drain(ns); + } + + /* + * Now, we should take care of AERs. + * + * 1. Save all queued events (n->aer_queue). + * This is done automatically, see nvme_vmstate VMStateDescription. + * Here we only need to print them for debugging purpose. + * 2. Go over outstanding AER requests (n->aer_reqs) and check they are + * all have expected opcode (NVME_ADM_CMD_ASYNC_EV_REQ) and other f= ields. + * + * We must be really careful here, because in case of further + * QEMU NVMe changes, we may break migration without noticing it, or w= orse, + * introduce silent data corruption during migration. + */ + if (n->aer_queued) { + NvmeAsyncEvent *event; + + QTAILQ_FOREACH(event, &n->aer_queue, entry) { + trace_pci_nvme_pre_save_aer(event->result.event_type, + event->result.event_info, + event->result.log_page); + } + } + + for (i =3D 0; i < n->outstanding_aers; i++) { + NvmeRequest *req =3D n->aer_reqs[i]; + + if (!pre_save_validate_aer_req(req, errp)) { + return false; + } + } + + /* + * Make sure that all in-flight IO requests + * (except NVME_ADM_CMD_ASYNC_EV_REQ) are processed. + */ + for (i =3D 0; i < n->num_queues; i++) { + NvmeRequest *req; + NvmeSQueue *sq =3D n->sq[i]; + + if (!sq) { + continue; + } + + trace_pci_nvme_pre_save_sq_out_req_check(n, i, + sq->head, sq->tail, sq->s= ize); + + QTAILQ_FOREACH(req, &sq->out_req_list, entry) { + assert(req->cmd.opcode =3D=3D NVME_ADM_CMD_ASYNC_EV_REQ); + } + } + + /* wait when all IO requests completions are written to guest memory */ + for (i =3D 0; i < n->num_queues; i++) { + NvmeCQueue *cq =3D n->cq[i]; + + if (!cq) { + continue; + } + + qemu_bh_cancel(cq->bh); + /* this should empty cq->req_list unless CQ is full */ + nvme_post_cqes(cq); + + trace_pci_nvme_pre_save_cq_req_check(n, i, + cq->head, cq->tail, cq->size); + + if (!QTAILQ_EMPTY(&cq->req_list)) { + NvmeRequest *req; + + assert(nvme_cq_full(cq)); + + QTAILQ_FOREACH(req, &cq->req_list, entry) { + trace_pci_nvme_pre_save_cq_unposted_cqe( + n, i, nvme_cid(req), + nvme_nsid(req->ns), + le32_to_cpu(req->cqe.result), + le32_to_cpu(req->cqe.dw1), + req->status, req->cmd.opcode); + if (!pre_save_validate_cq_req(req, errp)) { + return false; + } + } + } + } + + for (uint32_t nsid =3D 0; nsid <=3D NVME_MAX_NAMESPACES; nsid++) { + NvmeNamespace *ns =3D n->namespaces[nsid]; + + if (!ns) { + continue; + } + + if (ns !=3D &n->namespace) { + error_setg(errp, + "only one NVMe namespace is supported for migration= "); + return false; + } + } + + return true; +} + +static bool nvme_ctrl_post_load(void *opaque, int version_id, Error **errp) +{ + NvmeCtrl *n =3D opaque; + int i; + + trace_pci_nvme_post_load_enter(n); + + /* restore CQs first */ + for (i =3D 0; i < n->num_queues; i++) { + NvmeCQueue *cq =3D n->cq[i]; + + if (!cq) { + continue; + } + + if (cq->cqid !=3D i) { + error_setg(errp, "inconsistent migration stream (cq->cqid !=3D= i)"); + return false; + } + + cq->ctrl =3D n; + nvme_restore_cq(cq); + trace_pci_nvme_post_load_restore_cq(n, i, cq->head, cq->tail, cq->= size); + + if (i =3D=3D 0) { + /* + * Admin CQ lives in n->admin_cq, we don't need + * memory allocated for it in get_ptrs_array_entry() anymore. + * + * nvme_restore_cq() also takes care of: + * n->cq[0] =3D &n->admin_cq; + * so n->cq[0] remains valid. + */ + g_free(cq); + } + } + + for (i =3D 0; i < n->num_queues; i++) { + NvmeSQueue *sq =3D n->sq[i]; + + if (!sq) { + continue; + } + + if (sq->sqid !=3D i) { + error_setg(errp, "inconsistent migration stream (sq->sqid !=3D= i)"); + return false; + } + + if (!n->cq[sq->cqid]) { + error_setg(errp, + "inconsistent migration stream (n->cq[sq->cqid] is = NULL)"); + return false; + } + + sq->ctrl =3D n; + nvme_restore_sq(sq); + trace_pci_nvme_post_load_restore_sq(n, i, sq->head, sq->tail, sq->= size); + + if (i =3D=3D 0) { + /* same as for CQ */ + g_free(sq); + } + } + + /* restore cq->req_list-s */ + for (i =3D 0; i < n->num_queues; i++) { + NvmeRequest *req_from, *next; + typeof_field(NvmeCQueue, req_list) req_list; + NvmeCQueue *cq =3D n->cq[i]; + + if (!cq || QTAILQ_EMPTY(&cq->req_list)) { + continue; + } + + /* + * We use nvme_vmstate_request VMStateDescription to save/restore + * NvmeRequest structures, but tricky thing here is that + * memory for each cq->req_list item is allocated separately + * during restore. It doesn't work for us. We need to take + * an existing NvmeRequest structure from SQ's req_list pool + * and fill it with data from the newly allocated one (req_from). + * Then, we can safely release allocated memory for it. + */ + + /* make a copy of cq->req_list (QTAILQ head) and clean cq->req_lis= t */ + QTAILQ_INIT(&req_list); + QTAILQ_FOREACH_SAFE(req_from, &cq->req_list, entry, next) { + QTAILQ_REMOVE(&cq->req_list, req_from, entry); + QTAILQ_INSERT_TAIL(&req_list, req_from, entry); + } + QTAILQ_INIT(&cq->req_list); + + QTAILQ_FOREACH_SAFE(req_from, &req_list, entry, next) { + uint16_t sqid =3D le16_to_cpu(req_from->cqe.sq_id); + NvmeRequest *req; + NvmeSQueue *sq; + + assert(!nvme_check_sqid(n, sqid)); + sq =3D n->sq[sqid]; + + req =3D QTAILQ_FIRST(&sq->req_list); + QTAILQ_REMOVE(&sq->req_list, req, entry); + QTAILQ_INSERT_TAIL(&cq->req_list, req, entry); + nvme_req_clear(req); + + /* copy data from the source NvmeRequest */ + req->status =3D req_from->status; + memcpy(&req->cqe, &req_from->cqe, sizeof(NvmeCqe)); + memcpy(&req->cmd, &req_from->cmd, sizeof(NvmeCmd)); + + QTAILQ_REMOVE(&req_list, req_from, entry); + g_free(req_from); + } + + qemu_bh_schedule(cq->bh); + } + + if (n->aer_queued) { + NvmeAsyncEvent *event; + + QTAILQ_FOREACH(event, &n->aer_queue, entry) { + trace_pci_nvme_post_load_aer(event->result.event_type, + event->result.event_info, + event->result.log_page); + } + } + + for (i =3D 0; i < n->outstanding_aers; i++) { + NvmeSQueue *sq =3D &n->admin_sq; + NvmeRequest *req_from =3D n->aer_reqs[i]; + NvmeRequest *req; + + /* Idea here is the same as for "restore cq->req_list-s" step */ + + /* take an NvmeRequest struct from SQ */ + req =3D QTAILQ_FIRST(&sq->req_list); + QTAILQ_REMOVE(&sq->req_list, req, entry); + QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry); + nvme_req_clear(req); + + /* copy data from the source NvmeRequest */ + req->status =3D req_from->status; + memcpy(&req->cqe, &req_from->cqe, sizeof(NvmeCqe)); + memcpy(&req->cmd, &req_from->cmd, sizeof(NvmeCmd)); + + n->aer_reqs[i] =3D req; + g_free(req_from); + } + + /* + * We need to attach namespaces (currently, only one namespace is + * supported for migration). + * This logic comes from nvme_start_ctrl(). + */ + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { + NvmeNamespace *ns =3D nvme_subsys_ns(n->subsys, i); + + if (!ns || (!ns->params.shared && ns->ctrl !=3D n)) { + continue; + } + + if (nvme_csi_supported(n, ns->csi) && !ns->params.detached) { + if (!ns->attached || ns->params.shared) { + nvme_attach_ns(n, ns); + } + } + } + + /* schedule SQ processing */ + for (i =3D 0; i < n->num_queues; i++) { + NvmeSQueue *sq =3D n->sq[i]; + + if (!sq) { + continue; + } + + qemu_bh_schedule(sq->bh); + } + + return true; +} + static const VMStateDescription nvme_vmstate =3D { .name =3D "nvme", - .unmigratable =3D 1, + .minimum_version_id =3D 1, + .version_id =3D 1, + .pre_save_errp =3D nvme_ctrl_pre_save, + .post_load_errp =3D nvme_ctrl_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj, NvmeCtrl), + VMSTATE_MSIX(parent_obj, NvmeCtrl), + VMSTATE_STRUCT(bar, NvmeCtrl, 0, nvme_vmstate_bar, NvmeBar), + + VMSTATE_BOOL(qs_created, NvmeCtrl), + VMSTATE_UINT32(page_size, NvmeCtrl), + VMSTATE_UINT16(page_bits, NvmeCtrl), + VMSTATE_UINT16(max_prp_ents, NvmeCtrl), + VMSTATE_UINT32(max_q_ents, NvmeCtrl), + VMSTATE_UINT8(outstanding_aers, NvmeCtrl), + VMSTATE_UINT32(irq_status, NvmeCtrl), + VMSTATE_INT32(cq_pending, NvmeCtrl), + + VMSTATE_UINT64(host_timestamp, NvmeCtrl), + VMSTATE_UINT64(timestamp_set_qemu_clock_ms, NvmeCtrl), + VMSTATE_UINT64(starttime_ms, NvmeCtrl), + VMSTATE_UINT16(temperature, NvmeCtrl), + VMSTATE_UINT8(smart_critical_warning, NvmeCtrl), + + VMSTATE_UINT32(conf_msix_qsize, NvmeCtrl), + VMSTATE_UINT32(conf_ioqpairs, NvmeCtrl), + VMSTATE_UINT64(dbbuf_dbs, NvmeCtrl), + VMSTATE_UINT64(dbbuf_eis, NvmeCtrl), + VMSTATE_BOOL(dbbuf_enabled, NvmeCtrl), + + VMSTATE_UINT8(aer_mask, NvmeCtrl), + VMSTATE_VARRAY_OF_POINTER_TO_STRUCT_UINT8_ALLOC( + aer_reqs, NvmeCtrl, outstanding_aers, 0, + nvme_vmstate_request, NvmeRequest), + VMSTATE_QTAILQ_V(aer_queue, NvmeCtrl, 1, nvme_vmstate_async_event, + NvmeAsyncEvent, entry), + VMSTATE_INT32(aer_queued, NvmeCtrl), + + VMSTATE_STRUCT(namespace, NvmeCtrl, 0, nvme_vmstate_ns, NvmeNamesp= ace), + + VMSTATE_VARRAY_OF_POINTER_TO_STRUCT_UINT32_ALLOC( + sq, NvmeCtrl, num_queues, 0, nvme_vmstate_squeue, NvmeSQueue), + VMSTATE_VARRAY_OF_POINTER_TO_STRUCT_UINT32_ALLOC( + cq, NvmeCtrl, num_queues, 0, nvme_vmstate_cqueue, NvmeCQueue), + + VMSTATE_UINT16(features.temp_thresh_hi, NvmeCtrl), + VMSTATE_UINT16(features.temp_thresh_low, NvmeCtrl), + VMSTATE_UINT32(features.async_config, NvmeCtrl), + VMSTATE_STRUCT(features.hbs, NvmeCtrl, 0, + nvme_vmstate_hbs, NvmeHostBehaviorSupport), + + VMSTATE_UINT32(dn, NvmeCtrl), + VMSTATE_STRUCT(atomic, NvmeCtrl, 0, nvme_vmstate_atomic, NvmeAtomi= c), + + VMSTATE_END_OF_LIST() + }, }; =20 static void nvme_class_init(ObjectClass *oc, const void *data) diff --git a/hw/nvme/ns.c b/hw/nvme/ns.c index b0106eaa5c8..4caab590977 100644 --- a/hw/nvme/ns.c +++ b/hw/nvme/ns.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "system/system.h" #include "system/block-backend.h" +#include "migration/vmstate.h" =20 #include "nvme.h" #include "trace.h" @@ -886,6 +887,168 @@ static void nvme_ns_realize(DeviceState *dev, Error *= *errp) } } =20 +static const VMStateDescription nvme_vmstate_lbaf =3D { + .name =3D "nvme_lbaf", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT16(ms, NvmeLBAF), + VMSTATE_UINT8(ds, NvmeLBAF), + VMSTATE_UINT8(rp, NvmeLBAF), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_id_ns =3D { + .name =3D "nvme_id_ns", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(nsze, NvmeIdNs), + VMSTATE_UINT64(ncap, NvmeIdNs), + VMSTATE_UINT64(nuse, NvmeIdNs), + VMSTATE_UINT8(nsfeat, NvmeIdNs), + VMSTATE_UINT8(nlbaf, NvmeIdNs), + VMSTATE_UINT8(flbas, NvmeIdNs), + VMSTATE_UINT8(mc, NvmeIdNs), + VMSTATE_UINT8(dpc, NvmeIdNs), + VMSTATE_UINT8(dps, NvmeIdNs), + VMSTATE_UINT8(nmic, NvmeIdNs), + VMSTATE_UINT8(rescap, NvmeIdNs), + VMSTATE_UINT8(fpi, NvmeIdNs), + VMSTATE_UINT8(dlfeat, NvmeIdNs), + VMSTATE_UINT16(nawun, NvmeIdNs), + VMSTATE_UINT16(nawupf, NvmeIdNs), + VMSTATE_UINT16(nacwu, NvmeIdNs), + VMSTATE_UINT16(nabsn, NvmeIdNs), + VMSTATE_UINT16(nabo, NvmeIdNs), + VMSTATE_UINT16(nabspf, NvmeIdNs), + VMSTATE_UINT16(noiob, NvmeIdNs), + VMSTATE_UINT8_ARRAY(nvmcap, NvmeIdNs, 16), + VMSTATE_UINT16(npwg, NvmeIdNs), + VMSTATE_UINT16(npwa, NvmeIdNs), + VMSTATE_UINT16(npdg, NvmeIdNs), + VMSTATE_UINT16(npda, NvmeIdNs), + VMSTATE_UINT16(nows, NvmeIdNs), + VMSTATE_UINT16(mssrl, NvmeIdNs), + VMSTATE_UINT32(mcl, NvmeIdNs), + VMSTATE_UINT8(msrc, NvmeIdNs), + VMSTATE_UINT8_ARRAY(rsvd81, NvmeIdNs, 18), + VMSTATE_UINT8(nsattr, NvmeIdNs), + VMSTATE_UINT16(nvmsetid, NvmeIdNs), + VMSTATE_UINT16(endgid, NvmeIdNs), + VMSTATE_UINT8_ARRAY(nguid, NvmeIdNs, 16), + VMSTATE_UINT64(eui64, NvmeIdNs), + VMSTATE_STRUCT_ARRAY(lbaf, NvmeIdNs, NVME_MAX_NLBAF, 1, + nvme_vmstate_lbaf, NvmeLBAF), + VMSTATE_UINT8_ARRAY(vs, NvmeIdNs, 3712), + + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_id_ns_nvm =3D { + .name =3D "nvme_id_ns_nvm", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(lbstm, NvmeIdNsNvm), + VMSTATE_UINT8(pic, NvmeIdNsNvm), + VMSTATE_UINT8_ARRAY(rsvd9, NvmeIdNsNvm, 3), + VMSTATE_UINT32_ARRAY(elbaf, NvmeIdNsNvm, NVME_MAX_NLBAF), + VMSTATE_UINT32(npdgl, NvmeIdNsNvm), + VMSTATE_UINT32(nprg, NvmeIdNsNvm), + VMSTATE_UINT32(npra, NvmeIdNsNvm), + VMSTATE_UINT32(nors, NvmeIdNsNvm), + VMSTATE_UINT32(npdal, NvmeIdNsNvm), + VMSTATE_UINT8_ARRAY(rsvd288, NvmeIdNsNvm, 3808), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription nvme_vmstate_id_ns_ind =3D { + .name =3D "nvme_id_ns_ind", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8(nsfeat, NvmeIdNsInd), + VMSTATE_UINT8(nmic, NvmeIdNsInd), + VMSTATE_UINT8(rescap, NvmeIdNsInd), + VMSTATE_UINT8(fpi, NvmeIdNsInd), + VMSTATE_UINT32(anagrpid, NvmeIdNsInd), + VMSTATE_UINT8(nsattr, NvmeIdNsInd), + VMSTATE_UINT8(rsvd9, NvmeIdNsInd), + VMSTATE_UINT16(nvmsetid, NvmeIdNsInd), + VMSTATE_UINT16(endgrpid, NvmeIdNsInd), + VMSTATE_UINT8(nstat, NvmeIdNsInd), + VMSTATE_UINT8_ARRAY(rsvd15, NvmeIdNsInd, 4081), + VMSTATE_END_OF_LIST() + } +}; + +typedef struct TmpNvmeNamespace { + NvmeNamespace *parent; + bool enable_write_cache; +} TmpNvmeNamespace; + +static bool nvme_ns_tmp_pre_save(void *opaque, Error **errp) +{ + struct TmpNvmeNamespace *tns =3D opaque; + + tns->enable_write_cache =3D blk_enable_write_cache(tns->parent->blkcon= f.blk); + + return true; +} + +static bool nvme_ns_tmp_post_load(void *opaque, int version_id, Error **er= rp) +{ + struct TmpNvmeNamespace *tns =3D opaque; + + blk_set_enable_write_cache(tns->parent->blkconf.blk, + tns->enable_write_cache); + + return true; +} + +static const VMStateDescription nvme_vmstate_ns_tmp =3D { + .name =3D "nvme_ns_tmp", + .pre_save_errp =3D nvme_ns_tmp_pre_save, + .post_load_errp =3D nvme_ns_tmp_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_BOOL(enable_write_cache, TmpNvmeNamespace), + VMSTATE_END_OF_LIST() + } +}; + +const VMStateDescription nvme_vmstate_ns =3D { + .name =3D "nvme_ns", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_WITH_TMP(NvmeNamespace, TmpNvmeNamespace, nvme_vmstate_ns_= tmp), + + VMSTATE_STRUCT(id_ns, NvmeNamespace, 0, nvme_vmstate_id_ns, NvmeId= Ns), + VMSTATE_STRUCT(id_ns_nvm, NvmeNamespace, 0, + nvme_vmstate_id_ns_nvm, NvmeIdNsNvm), + VMSTATE_STRUCT(id_ns_ind, NvmeNamespace, 0, + nvme_vmstate_id_ns_ind, NvmeIdNsInd), + VMSTATE_STRUCT(lbaf, NvmeNamespace, 0, nvme_vmstate_lbaf, NvmeLBAF= ), + VMSTATE_UINT32(nlbaf, NvmeNamespace), + VMSTATE_UINT8(csi, NvmeNamespace), + VMSTATE_UINT16(status, NvmeNamespace), + VMSTATE_UINT8(pif, NvmeNamespace), + + VMSTATE_UINT16(zns.zrwas, NvmeNamespace), + VMSTATE_UINT16(zns.zrwafg, NvmeNamespace), + VMSTATE_UINT32(zns.numzrwa, NvmeNamespace), + + VMSTATE_UINT32(features.err_rec, NvmeNamespace), + VMSTATE_STRUCT(atomic, NvmeNamespace, 0, + nvme_vmstate_atomic, NvmeAtomic), + VMSTATE_END_OF_LIST() + } +}; + static const Property nvme_ns_props[] =3D { DEFINE_BLOCK_PROPERTIES(NvmeNamespace, blkconf), DEFINE_PROP_BOOL("detached", NvmeNamespace, params.detached, false), @@ -937,6 +1100,7 @@ static void nvme_ns_class_init(ObjectClass *oc, const = void *data) dc->bus_type =3D TYPE_NVME_BUS; dc->realize =3D nvme_ns_realize; dc->unrealize =3D nvme_ns_unrealize; + dc->vmsd =3D &nvme_vmstate_ns; device_class_set_props(dc, nvme_ns_props); dc->desc =3D "Virtual NVMe namespace"; } diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h index 05aee24a15c..78a6eaa1774 100644 --- a/hw/nvme/nvme.h +++ b/hw/nvme/nvme.h @@ -444,6 +444,11 @@ typedef struct NvmeRequest { NvmeSg sg; bool atomic_write; QTAILQ_ENTRY(NvmeRequest)entry; + /* + * If you add a new field here, please make sure to update + * nvme_vmstate_request, pre_save_validate_aer_req() and + * pre_save_validate_cq_req(). + */ } NvmeRequest; =20 typedef struct NvmeBounceContext { @@ -640,6 +645,7 @@ typedef struct NvmeCtrl { =20 NvmeNamespace namespace; NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1]; + uint32_t num_queues; NvmeSQueue **sq; NvmeCQueue **cq; NvmeSQueue admin_sq; @@ -751,4 +757,7 @@ void nvme_atomic_configure_max_write_size(bool dn, uint= 16_t awun, void nvme_ns_atomic_configure_boundary(bool dn, uint16_t nabsn, uint16_t nabspf, NvmeAtomic *atomic= ); =20 +extern const VMStateDescription nvme_vmstate_atomic; +extern const VMStateDescription nvme_vmstate_ns; + #endif /* HW_NVME_NVME_H */ diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index 6be0bfa1c1f..f97a6a11f36 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -7,6 +7,16 @@ pci_nvme_dbbuf_config(uint64_t dbs_addr, uint64_t eis_addr= ) "dbs_addr=3D0x%"PRIx64 pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRI= u64"" pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %= "PRIu64"" pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t= prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" pr= p2 0x%"PRIx64" num_prps %d" +pci_nvme_pre_save_enter(void *n) "n=3D%p" +pci_nvme_pre_save_ns_drain(void *n, int i) "n=3D%p i=3D%d" +pci_nvme_pre_save_sq_out_req_check(void *n, int i, uint32_t head, uint32_t= tail, uint32_t size) "n=3D%p i=3D%d head=3D0x%"PRIx32" tail=3D0x%"PRIx32" = size=3D0x%"PRIx32"" +pci_nvme_pre_save_cq_req_check(void *n, int i, uint32_t head, uint32_t tai= l, uint32_t size) "n=3D%p i=3D%d head=3D0x%"PRIx32" tail=3D0x%"PRIx32" size= =3D0x%"PRIx32"" +pci_nvme_pre_save_cq_unposted_cqe(void *n, int i, uint16_t cid, uint32_t n= sid, uint32_t dw0, uint32_t dw1, uint16_t status, uint8_t opc) "n=3D%p i=3D= %d cid %"PRIu16" nsid %"PRIu32" dw0 0x%"PRIx32" dw1 0x%"PRIx32" status 0x%"= PRIx16" opc 0x%"PRIx8"" +pci_nvme_pre_save_aer(uint8_t typ, uint8_t info, uint8_t log_page) "type 0= x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" +pci_nvme_post_load_enter(void *n) "n=3D%p" +pci_nvme_post_load_restore_cq(void *n, int i, uint32_t head, uint32_t tail= , uint32_t size) "n=3D%p i=3D%d head=3D0x%"PRIx32" tail=3D0x%"PRIx32" size= =3D0x%"PRIx32"" +pci_nvme_post_load_restore_sq(void *n, int i, uint32_t head, uint32_t tail= , uint32_t size) "n=3D%p i=3D%d head=3D0x%"PRIx32" tail=3D0x%"PRIx32" size= =3D0x%"PRIx32"" +pci_nvme_post_load_aer(uint8_t typ, uint8_t info, uint8_t log_page) "type = 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" pci_nvme_map_sgl(uint8_t typ, uint64_t len) "type 0x%"PRIx8" len %"PRIu64"" pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode= , const char *opname) "cid %"PRIu16" nsid 0x%"PRIx32" sqid %"PRIu16" opc 0x= %"PRIx8" opname '%s'" pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char= *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'" --=20 2.47.3 From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2003:cf:570f:fe00:6c26:edf5:8ff0:62dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35fb24sm86375554f8f.34.2026.06.11.04.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 04:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mihalicyn.com; s=mihalicyn; t=1781176979; x=1781781779; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ABwUq03C/Jp8BidZ7jTz30GrehldasAncwd4fCGAeTA=; b=Uam8A5QA/q1iSG3RJoZtNokfbxzqZKohpklZhtCzT30enisq0ij/mmgeO736KS0Yk+ rD57pQpa0NIp6sna39UjRy1PT0Oh1kgXbFHTHdsK4qlDK+URvm9KRPscVr1+OlFKY5Fx A4CXsNZSCMLnLZ07MBR0ykmPi2C5BY/v31N3U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781176979; x=1781781779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ABwUq03C/Jp8BidZ7jTz30GrehldasAncwd4fCGAeTA=; b=GSmQHBCKrgc7nmIxN/taJ6vCrVfSawpMdP5iX9TRZaY9PipfKzX5exuGSRkQP4DUxK LH+daVdFtIAnTjvvj6Jby6ISGaqJzb1fcNYgBtsyqjX3JAyIWjKVtq8D5ZGlf3UqUq6C IZ9HfgyA3XnsP4PeCva8ZcKw1C2VEfq4ePR45uXDDWfmqPNyXVqpeYqcpXvkcujprfdP DUkrhu2IXwICGU//fJQT4M+FVIdpjDQr+Yrwqg0I1hXgv+BVEuLmUmGecYr5s0id3aPF swp9JBq5h4CJdbOCxgStAdCNrUzvv5BOFwHbelmcNEmSFYgIE3iz6yHeguD/JC1WVLQs rk1Q== X-Gm-Message-State: AOJu0YxhZErKkLxC80qSks8/UFhPrTCWW1dTt/cWkdA4pWSDTKV1gazL IwkPqX/wBRx71+8VKA+O6Y5tlFZ9fSbZohIK+zqBJuxw6jepy4yFRxY1u4xS0xBXLLKoZfta7U5 onpju3Fo= X-Gm-Gg: Acq92OE8UZ5N67yGpUoOap4zCI6un8ZWZGaAIraFIxbANDGI7RAcnL7/CTk0ogSbe/c NJB27ZvMQfD4KN215rVkIpL91ydTYYlrRbEqJ3V7GVkwcnhO2K8TEX3JIrEwwwC1SMN8d3kanVb mxNx3GkuBnPA/yLAfgdEhnd0ckWUxjyOLV1LSD+OdjRO42idUrkTgCRCGd3kR22cLe4j3KjdICt OiUqD/cNsbVdYdZPECNLYHSEdynC+SZXA0L5QufGCL7njsXszlhx8VIKdepPb06tA1S2SWxsbPT ASaXSKuYw94J9S7NtHftgHgoLes7+B3xSg9is9ZSHCniuo6j0ZYMxiCojrjdR1241DPW2ML6UI3 UXON+BMtlAaYK3agSIafbWzGOAmG2UvqC2h/1TGtAL8Q9DUFchCQIyyoxFwAXyBS7zuOMqxZ2Vs Ylw1/fGhAg+tf/sLlfs+CwmgZW0sptPUud/CbD4c+XQsnnWKxjmimu8UQ10Vafq/NKtzvPj+jr0 MENpztqTIvH10UDYXuW67NYvPAbjBwy/A== X-Received: by 2002:a05:6000:4601:b0:45f:f142:d55a with SMTP id ffacd0b85a97d-460674765d7mr3455684f8f.14.1781176978844; Thu, 11 Jun 2026 04:22:58 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn Subject: [PATCH v9 7/8] tests/functional/x86_64: add migration test for NVMe device Date: Thu, 11 Jun 2026 13:22:48 +0200 Message-ID: <20260611112249.165012-8-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alexander@mihalicyn.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781177067751158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn Introduce a very simple test to ensure that NVMe device migration works fine. Test plan is simple: 1. prepare VM with NVMe device 2. run workload that produces relatively heavy IO on the device 3. migrate VM 4. ensure that workload is alive and finishes without errors Test can be run as simple as: $ meson test 'func-x86_64-nvme_migration' --setup thorough -C build In the future we can extend this approach, and introduce some fio-based tests. And probably, it makes sense to make this test to apply not only to NVMe device, but also virtio-{blk,scsi}, ide, sata and other migratable devices. Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- v9: - check-patch fixes --- MAINTAINERS | 1 + tests/functional/x86_64/meson.build | 1 + .../functional/x86_64/test_nvme_migration.py | 172 ++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100755 tests/functional/x86_64/test_nvme_migration.py diff --git a/MAINTAINERS b/MAINTAINERS index 2b5b581e173..d705f5c8e0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2622,6 +2622,7 @@ S: Supported F: hw/nvme/* F: include/block/nvme.h F: tests/qtest/nvme-test.c +F: tests/functional/x86_64/test_nvme_migration.py F: docs/system/devices/nvme.rst T: git git://git.infradead.org/qemu-nvme.git nvme-next =20 diff --git a/tests/functional/x86_64/meson.build b/tests/functional/x86_64/= meson.build index 1ed10ad6c29..fd77f19d726 100644 --- a/tests/functional/x86_64/meson.build +++ b/tests/functional/x86_64/meson.build @@ -37,6 +37,7 @@ tests_x86_64_system_thorough =3D [ 'linux_initrd', 'multiprocess', 'netdev_ethtool', + 'nvme_migration', 'replay', 'reverse_debug', 'tuxrun', diff --git a/tests/functional/x86_64/test_nvme_migration.py b/tests/functio= nal/x86_64/test_nvme_migration.py new file mode 100755 index 00000000000..890f0aab6d6 --- /dev/null +++ b/tests/functional/x86_64/test_nvme_migration.py @@ -0,0 +1,172 @@ +#!/usr/bin/env python3 +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# x86_64 NVMe migration test + +from migration import MigrationTest +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern +from qemu_test import exec_command, exec_command_and_wait_for_pattern + + +class X8664NVMeMigrationTest(MigrationTest): + ASSET_KERNEL =3D Asset( + ('https://archives.fedoraproject.org/pub/archive/fedora/linux/rele= ases' + '/31/Server/x86_64/os/images/pxeboot/vmlinuz'), + 'd4738d03dbbe083ca610d0821d0a8f1488bebbdccef54ce33e3adb35fda00129') + + ASSET_INITRD =3D Asset( + ('https://archives.fedoraproject.org/pub/archive/fedora/linux/rele= ases' + '/31/Server/x86_64/os/images/pxeboot/initrd.img'), + '277cd6c7adf77c7e63d73bbb2cded8ef9e2d3a2f100000e92ff1f8396513cd8b') + + ASSET_DISKIMAGE =3D Asset( + ('https://archives.fedoraproject.org/pub/archive/fedora/linux/rele= ases' + '/31/Cloud/x86_64/images/Fedora-Cloud-Base-31-1.9.x86_64.qcow2'), + 'e3c1b309d9203604922d6e255c2c5d098a309c2d46215d8fc026954f3c5c27a0') + + DEFAULT_KERNEL_PARAMS =3D ('root=3D/dev/nvme0n1p1 console=3DttyS0 net.= ifnames=3D0 ' + 'rd.rescue quiet') + + def wait_for_console_pattern(self, success_message, vm): + wait_for_console_pattern( + self, + success_message, + failure_message=3D"Kernel panic - not syncing", + vm=3Dvm, + ) + + def exec_command_and_check(self, command, vm): + prompt =3D '# ' + exec_command_and_wait_for_pattern(self, + f"{command} && echo OK || echo FAI= L", + 'FAIL', vm=3Dvm) + # Note, that commands we send to the console are echo-ed back, + # so if we have a word "FAIL" in the command itself, we should + # expect to see it once. + wait_for_console_pattern(self, 'OK', failure_message=3D"FAIL", vm= =3Dvm) + self.wait_for_console_pattern(prompt, vm) + + def configure_machine(self, vm): + kernel_path =3D self.ASSET_KERNEL.fetch() + initrd_path =3D self.ASSET_INITRD.fetch() + diskimage_path =3D self.ASSET_DISKIMAGE.fetch() + + vm.set_console() + vm.add_args("-cpu", "max") + vm.add_args("-m", "2G") + vm.add_args("-accel", "kvm") + + vm.add_args('-drive', + f'file=3D{diskimage_path},if=3Dnone,id=3Ddrv0,sna= pshot=3Don') + vm.add_args('-device', 'nvme,bus=3Dpcie.0,' + + 'drive=3Ddrv0,id=3Dnvme-disk0,serial=3Dnvmemigtest,boo= tindex=3D1') + + vm.add_args( + "-kernel", + kernel_path, + "-initrd", + initrd_path, + "-append", + self.DEFAULT_KERNEL_PARAMS + ) + + def launch_source_vm(self, vm): + vm.launch() + + self.wait_for_console_pattern('Entering emergency mode.', vm) + prompt =3D '# ' + self.wait_for_console_pattern(prompt, vm) + + # Synchronize on NVMe driver creating the root device + exec_command_and_wait_for_pattern(self, + "while ! (dmesg -c | grep nvme0n1:) ; do sleep 1 ;= done", + "nvme0n1", vm=3Dvm) + self.wait_for_console_pattern(prompt, vm) + + # prepare system + exec_command_and_wait_for_pattern(self, 'mount /dev/nvme0n1p1 /sys= root', + prompt, vm=3Dvm) + exec_command_and_wait_for_pattern(self, 'chroot /sysroot', + prompt, vm=3Dvm) + exec_command_and_wait_for_pattern(self, 'mount -t proc proc /proc', + prompt, vm=3Dvm) + exec_command_and_wait_for_pattern(self, 'mount -t sysfs sysfs /sys= ', + prompt, vm=3Dvm) + + # Run workload before migration to check if it continues + # to run properly after migration. + # + # Workload is simple: it continuously calculates checksums of + # all files in /usr/bin to generate some I/O load on + # the NVMe disk and at the same time it drops caches to + # make sure that we have some read I/O on the disk as well. + # If there are any issues with the migration of the NVMe device, + # we should see errors in dmesg and consequently in the workload l= og. + exec_command_and_wait_for_pattern(self, + "(while [ ! -f /tmp/test_nvme_mig_workload.stop ]; do \ + rm -f /tmp/test_nvme_mig_workload.iter_finished; \ + echo 3 > /proc/sys/vm/drop_caches; \ + find /usr/bin -type f -exec cksum {} \\;; \ + touch /tmp/test_nvme_mig_workload.iter_finished; \ + done) > /dev/null 2> /tmp/test_nvme_mig_workload.errors &", + prompt, vm=3Dvm) + exec_command_and_wait_for_pattern(self, + 'echo $! > /tmp/test_nvme_mig_workload.pid', + prompt, vm=3Dvm) + + # check if process is alive and running + self.exec_command_and_check( + "kill -0 $(cat /tmp/test_nvme_mig_workload.pid)", vm) + + def assert_dest_vm(self, vm): + prompt =3D '# ' + + # check if process is alive and running after migration, + # if not - fail the test + self.exec_command_and_check( + "kill -0 $(cat /tmp/test_nvme_mig_workload.pid)", vm) + + # signal workload to stop + exec_command_and_wait_for_pattern(self, + 'touch /tmp/test_nvme_mig_workload.stop', + prompt, vm=3Dvm) + + # wait workload to finish, because we want to examine log + # to see if there are any errors + exec_command_and_wait_for_pattern(self, + "while [ ! -f /tmp/test_nvme_mig_workload.iter_finished ]; do \ + sleep 1; \ + done;", + prompt, vm=3Dvm) + + exec_command_and_wait_for_pattern(self, + 'cat /tmp/test_nvme_mig_workload.errors', + prompt, vm=3Dvm) + + # fail the test if non-empty + self.exec_command_and_check( + "[ ! -s /tmp/test_nvme_mig_workload.errors ]", vm) + + def test_migration_with_tcp_localhost(self): + self.set_machine('q35') + self.require_accelerator("kvm") + + self.migration_with_tcp_localhost() + + def test_migration_with_unix(self): + self.set_machine('q35') + self.require_accelerator("kvm") + + self.migration_with_unix() + + def test_migration_with_exec(self): + self.set_machine('q35') + self.require_accelerator("kvm") + + self.migration_with_exec() + + +if __name__ =3D=3D '__main__': + MigrationTest.main() --=20 2.47.3 From nobody Thu Jun 11 16:09:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=mihalicyn.com ARC-Seal: i=1; a=rsa-sha256; t=1781177036; cv=none; d=zohomail.com; s=zohoarc; b=nfm1G7xqLu0AJv4CSArqAHxkLZJHYRZY3pueGvQd3V9LgwyivEPd0Qnz2xiUE3J1hYEoXiArglJr+U1sUOeori5O5OBy6yDLAF+yJgInSYn4j5gLmTBlUrWhw64FDEkG37DF8cDXcY4A6n4Z6TuhaKLKrO0JdRupxZQj2DFVydI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781177036; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r0A55payGM+9uAl1mF1MVTtBvYu+YeHzGvkSWc12GNA=; b=D1vtmpvpdOA/9QLtHrJtU6erceZVUO6tBbWVOpZcZBuCNva1Wk6VovGMEw7DOi5PoTKmNLr6Oig6R55vuEBJgUbQT6Veymf/twW728jXeBKllQot26K9kzHrxNXBhHgqA+M2KX08s63WiwIEfa5/njGQzc6NjIoFoT2bs3JcXiI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781177036091322.0281340565124; Thu, 11 Jun 2026 04:23:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXdV7-0001aN-8b; Thu, 11 Jun 2026 07:23:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXdV4-0001XG-Sr for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:23:06 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wXdUz-00018v-O3 for qemu-devel@nongnu.org; Thu, 11 Jun 2026 07:23:06 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-45eeea039ebso4246200f8f.1 for ; Thu, 11 Jun 2026 04:23:01 -0700 (PDT) Received: from alex-laptop.lan (p200300cf570ffe006c26edf58ff062dc.dip0.t-ipconnect.de. [2003:cf:570f:fe00:6c26:edf5:8ff0:62dc]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4601f35fb24sm86375554f8f.34.2026.06.11.04.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 04:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mihalicyn.com; s=mihalicyn; t=1781176980; x=1781781780; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r0A55payGM+9uAl1mF1MVTtBvYu+YeHzGvkSWc12GNA=; b=VQxluwnRvggetk311Mv7otc62T07BXsC4IpspXoXigUhk5MXHr9NCUbzXbEOfgV9ck 99wV/pc4YltxQ2yckxDWHHR+oZckUvXT1ME5uXyjy7ikJ+9coSadNK5GroGoI87CJqBC Wfgl/k8tChO+KcEfmDFGa9nDcGld3S0eYV9ks= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781176980; x=1781781780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=r0A55payGM+9uAl1mF1MVTtBvYu+YeHzGvkSWc12GNA=; b=jyNN+HSyTnn/T2Rr3Y6K1cn33KEpi3R7vgbHH+inPgxIcdZzJ2CygEpI2Z73cW/jGI nM8DnV7pvN+vSV6OlENKflXmwpkFJnEIyULzK9gJxxfzngPGmwrENQxMvkpiBxKc8eT9 6fC3qmduFXO8guM36kOP9SfB9akm7G5bvepsveqC1V7gm4rjIdOz6/Q5gZW6iqrYivHq TS9WMeUyq/qHzwf+TwwT8MK4DyjBwtyc9L6023MGnkO5z6cxUsKRFUnf2pyCo9awSbgb hSWAcQcoIexD0U8S0JiHKz6vrBQC4ew/aDIwmXUxtshdRSgeLtbr4GLYyZxP1QIrflki ZInw== X-Gm-Message-State: AOJu0YwuDfNYzpOLfu5t+xLxVtMSHckrVM9JUVCYZlOvs9cEwqP8omDa BZlIYk1dk80GDH+q0U2CaxjKggvpRgDwHrVRx0vKtmS9BApzWdUDSI8uzTQMpDW4M8MreEDbNpq Mgpe1/SE= X-Gm-Gg: Acq92OGgW+PE+7VGC67nGPUHWyEOE1PSXlrJymvCzn4iKi2CU59l2hqfBysX8c/Vpa1 DI7j0AkVPJSihyDciFVShsyWJilY2ESjyAb/gMvKCosCCKXfHmwHpUE/ao9rzD2eaQIS1bTocPM U0oAp6tcYH4wRYxQFUQF619jRgQuEA8IwGjDnbGZgPWefA+T8LRNGFmHX8Z1U9CugLPx5A4aVyo V0XjPrxQnNNgIOSLamP3bzJuJHbat5t3GNgrSp2vi9w0ZmSa+4I7WFz9tyD6qcYZzVAhkm5C/74 u8CthZvS2Vx4G/zHyFdtNz+YLnzNhmqfMYVYkWzLC9o65vFNs0BO4br0vYtPfIuADHCDZrIrkIi Pw18A/YsMed/OP2PXbZVSPjRWBp/ZGMoOP+29nMuD6vKzqRGx6uOh/pxjStzv6n5MDnFMnFNC2J +M9sVCULhyF6BqpE7p4mmHEJUH3KvaeFOW/PcFOyy1Bux0YtUpR9Vp2hJA6NhNB9ZuOv89AVRZG wndxNUNrRVH6NwO2LADhIfUA3TGIHuc9A== X-Received: by 2002:a05:6000:1785:b0:43c:fc5c:a9fe with SMTP id ffacd0b85a97d-460677ae991mr4130004f8f.20.1781176979957; Thu, 11 Jun 2026 04:22:59 -0700 (PDT) From: Alexander Mikhalitsyn To: qemu-devel@nongnu.org Cc: Klaus Jensen , Stefan Hajnoczi , Jesper Devantier , qemu-block@nongnu.org, Hanna Reitz , Fam Zheng , =?UTF-8?q?St=C3=A9phane=20Graber?= , Kevin Wolf , Keith Busch , Laurent Vivier , Fabiano Rosas , Zhao Liu , Alexander Mikhalitsyn , Paolo Bonzini , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Mikhalitsyn Subject: [PATCH v9 8/8] tests/qtest/nvme-test: add migration test with full CQ Date: Thu, 11 Jun 2026 13:22:49 +0200 Message-ID: <20260611112249.165012-9-alexander@mihalicyn.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260611112249.165012-1-alexander@mihalicyn.com> References: <20260611112249.165012-1-alexander@mihalicyn.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alexander@mihalicyn.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @mihalicyn.com) X-ZM-MESSAGEID: 1781177037365158500 Content-Type: text/plain; charset="utf-8" From: Alexander Mikhalitsyn As suggested by Stefan [1], let's add a migration test to cover rare scenario when CQ is full of non-processed CQEs and migration happens. To run this test: $ meson test -C build 'qtest-x86_64/qos-test' Link: https://lore.kernel.org/qemu-devel/20260408183529.GB319710@fedora/ [1] Suggested-by: Stefan Hajnoczi Acked-by: Stefan Hajnoczi Signed-off-by: Alexander Mikhalitsyn --- v9: - check-patch fixes - added qpci_check_buggy_msi() check to skip test on ppc64 / spapr pci = bus v7: - fixed endianness bugs (and tested on s390x machine) - code style changes (don't use ptr type for physical addresses) v6: - test added --- tests/qtest/nvme-test.c | 421 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 421 insertions(+) diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c index 4aec1651e6e..7053f387fec 100644 --- a/tests/qtest/nvme-test.c +++ b/tests/qtest/nvme-test.c @@ -8,9 +8,12 @@ */ =20 #include "qemu/osdep.h" +#include +#include "qemu/bswap.h" #include "qemu/module.h" #include "qemu/units.h" #include "libqtest.h" +#include "libqtest-single.h" #include "libqos/qgraph.h" #include "libqos/pci.h" #include "block/nvme.h" @@ -142,6 +145,422 @@ static void nvmetest_pmr_reg_test(void *obj, void *da= ta, QGuestAllocator *alloc) qpci_iounmap(pdev, pmr_bar); } =20 +#define PAGE_SIZE 4096 + +typedef struct nvme_ctrl nvme_ctrl; + +typedef struct nvme_queue { + nvme_ctrl *ctrl; + uint64_t doorbell; + uint32_t size; +} nvme_queue; + +typedef struct nvme_cq { + nvme_queue common; + uint64_t phys_cqe; /* NvmeCqe* */ + uint16_t head; + uint8_t phase; +} nvme_cq; + +typedef struct nvme_sq { + nvme_queue common; + uint64_t phys_sqe; /* NvmeCmd* */ + nvme_cq *cq; + uint16_t head; + uint16_t tail; +} nvme_sq; + +struct nvme_ctrl { + QGuestAllocator *alloc; + QPCIDevice *pdev; + QPCIBar bar; + + uint32_t db_stride; + + nvme_sq admin_sq; + nvme_cq admin_cq; +}; + +#define PHYS_ADDR_OF_FIELD(T, base_phys_addr, field) \ + ((uint64_t)&((T *)(base_phys_addr))->field) + +#define PHYS_ADDR_OF(T, base_phys_addr, accessor) \ + ((uint64_t)&((T *)(base_phys_addr))accessor) + +static void nvme_init_queue_common(nvme_ctrl *ctrl, nvme_queue *q, + uint16_t db_idx, uint32_t size) +{ + q->ctrl =3D ctrl; + q->doorbell =3D (sizeof(NvmeBar) + db_idx * ctrl->db_stride); + g_test_message(" q %p db_idx %u doorbell %lx", q, db_idx, q->doorbell); + q->size =3D size; +} + +static void nvme_init_sq(nvme_ctrl *ctrl, nvme_sq *sq, uint16_t db_idx, + uint32_t size, nvme_cq *cq) +{ + nvme_init_queue_common(ctrl, &sq->common, db_idx, size); + + sq->phys_sqe =3D guest_alloc(ctrl->alloc, PAGE_SIZE); + g_assert(sq->phys_sqe); + + g_test_message("sq %p db_idx %u sqe 0x%" PRIx64, sq, db_idx, sq->phys_= sqe); + sq->cq =3D cq; + sq->head =3D 0; + sq->tail =3D 0; +} + +static void nvme_init_cq(nvme_ctrl *ctrl, nvme_cq *cq, uint16_t db_idx, + uint32_t size) +{ + nvme_init_queue_common(ctrl, &cq->common, db_idx, size); + + cq->phys_cqe =3D guest_alloc(ctrl->alloc, PAGE_SIZE); + g_assert(cq->phys_cqe); + + g_test_message("cq %p db_idx %u cqe 0x%" PRIx64, cq, db_idx, cq->phys_= cqe); + cq->head =3D 0; + cq->phase =3D 1; +} + +static int nvme_cqe_pending(nvme_cq *cq) +{ + uint16_t status =3D qtest_readw( + cq->common.ctrl->pdev->bus->qts, + PHYS_ADDR_OF(NvmeCqe, cq->phys_cqe, [cq->head].status)); + return (status & 1) =3D=3D cq->phase; +} + +static int nvme_is_cqe_success(NvmeCqe *cqe) +{ + return (le16_to_cpu(cqe->status) >> 1) =3D=3D NVME_SUCCESS; +} + +static NvmeCqe nvme_handle_cqe(nvme_sq *sq) +{ + nvme_cq *cq =3D sq->cq; + uint64_t phys_cqe =3D PHYS_ADDR_OF( + NvmeCqe, cq->phys_cqe, [cq->head]); /* NvmeCqe= * */ + NvmeCqe cqe; + uint16_t cq_next_head; + + g_assert(nvme_cqe_pending(cq)); + + qtest_memread(sq->common.ctrl->pdev->bus->qts, phys_cqe, &cqe, sizeof(= cqe)); + + cq_next_head =3D (cq->head + 1) % cq->common.size; + g_test_message("cq %p head %u -> %u", cq, cq->head, cq_next_head); + if (cq_next_head < cq->head) { + cq->phase ^=3D 1; + } + cq->head =3D cq_next_head; + + if (cqe.sq_head !=3D sq->head) { + sq->head =3D cqe.sq_head; + g_test_message("sq %p head =3D %u", sq, sq->head); + } + + qpci_io_writel(cq->common.ctrl->pdev, cq->common.ctrl->bar, + cq->common.doorbell, cq->head); + + return cqe; +} + +static NvmeCqe nvme_wait(nvme_sq *sq) +{ + int i; + bool ready =3D false; + + for (i =3D 0; i < 10; i++) { + if (nvme_cqe_pending(sq->cq)) { + ready =3D true; + break; + } + + g_usleep(1000); + } + + g_assert(ready); + + return nvme_handle_cqe(sq); +} + +static uint64_t nvme_get_next_sqe(nvme_sq *sq, uint8_t opcode, + uint16_t cid, uint64_t prp1) +{ + uint64_t phys_sqe =3D PHYS_ADDR_OF(NvmeCmd, sq->phys_sqe, [sq->tail]); + + if (((sq->tail + 1) % sq->common.size) =3D=3D sq->head) { + /* no space in SQ */ + g_test_message("%s head %d tail %d", __func__, sq->head, sq->tail); + g_assert_not_reached(); + return 0; + } + + qtest_memset(sq->common.ctrl->pdev->bus->qts, + phys_sqe, 0, sizeof(NvmeCmd)); + + #define GUEST_MEM_WRITE(fn, phys_addr, val) \ + fn(sq->common.ctrl->pdev->bus->qts, phys_addr, (val)) + + GUEST_MEM_WRITE(qtest_writeb, + PHYS_ADDR_OF_FIELD(NvmeCmd, phys_sqe, opcode), opcode); + GUEST_MEM_WRITE(qtest_writew, + PHYS_ADDR_OF_FIELD(NvmeCmd, phys_sqe, cid), cid); + GUEST_MEM_WRITE(qtest_writeq, + PHYS_ADDR_OF_FIELD(NvmeCmd, phys_sqe, dptr.prp1), prp1= ); + + #undef GUEST_MEM_WRITE + + g_test_message("sq %p next_sqe %u sqe 0x%" PRIx64, sq, sq->tail, phys_= sqe); + return phys_sqe; +} + +static void nvme_commit_sqe(nvme_sq *sq) +{ + g_test_message("sq %p commit sqe tail %u", sq, sq->tail); + sq->tail =3D (sq->tail + 1) % sq->common.size; + qpci_io_writel(sq->common.ctrl->pdev, sq->common.ctrl->bar, + sq->common.doorbell, sq->tail); +} + +static uint64_t nvme_admin_identify_ctrl(nvme_ctrl *ctrl, + uint16_t cid, bool no_wait) +{ + uint64_t phys_cmd_identify; /* NvmeCmd* */ + uint64_t phys_identify; /* NvmeIdCtrl* */ + NvmeCqe cqe; + + g_test_message("sending req cid %u no_wait %d", cid, no_wait); + + phys_identify =3D guest_alloc(ctrl->alloc, PAGE_SIZE); + g_assert(phys_identify); + + phys_cmd_identify =3D nvme_get_next_sqe(&ctrl->admin_sq, + NVME_ADM_CMD_IDENTIFY, cid, + phys_identify); + g_assert(phys_cmd_identify); + + #define GUEST_MEM_WRITE(fn, phys_addr, val) \ + fn(ctrl->pdev->bus->qts, phys_addr, (val)) + + GUEST_MEM_WRITE(qtest_writel, + PHYS_ADDR_OF_FIELD(NvmeCmd, phys_cmd_identify, nsid), = 0); + GUEST_MEM_WRITE(qtest_writel, + PHYS_ADDR_OF_FIELD(NvmeIdentify, phys_cmd_identify, cn= s), + NVME_ID_CNS_CTRL); + + #undef GUEST_MEM_WRITE + + nvme_commit_sqe(&ctrl->admin_sq); + + if (no_wait) { + return phys_identify; + } + + cqe =3D nvme_wait(&ctrl->admin_sq); + g_assert(nvme_is_cqe_success(&cqe)); + g_assert(le16_to_cpu(cqe.cid) =3D=3D cid); + + return phys_identify; +} + +static void nvme_wait_ready(nvme_ctrl *ctrl, int val) +{ + int i; + + for (i =3D 0; i < 10; i++) { + uint32_t csts =3D qpci_io_readl(ctrl->pdev, ctrl->bar, NVME_REG_CS= TS); + g_test_message("%s: csts %x", __func__, csts); + + if (NVME_CSTS_RDY(csts) =3D=3D val) { + return; + } + + g_usleep(1000); + } + + g_assert_not_reached(); +} + +static void test_migrate_setup_nvme_ctrl(nvme_ctrl *ctrl) +{ + uint64_t cap; + + /* disable controller */ + qpci_io_writel(ctrl->pdev, ctrl->bar, NVME_REG_CC, 0); + nvme_wait_ready(ctrl, 0); + + cap =3D qpci_io_readq(ctrl->pdev, ctrl->bar, NVME_REG_CAP); + ctrl->db_stride =3D 4 << NVME_CAP_DSTRD(cap); + + nvme_init_cq(ctrl, &ctrl->admin_cq, 1, 2 /* CQEs num */); + nvme_init_sq(ctrl, &ctrl->admin_sq, 0, 4 /* SQEs num */, &ctrl->admin_= cq); + + qpci_io_writel(ctrl->pdev, ctrl->bar, NVME_REG_AQA, + ((ctrl->admin_cq.common.size - 1) << AQA_ACQS_SHIFT) | + ((ctrl->admin_sq.common.size - 1) << AQA_ASQS_SHIFT) + ); + + qpci_io_writeq(ctrl->pdev, ctrl->bar, + NVME_REG_ASQ, (uint64_t)ctrl->admin_sq.phys_sqe); + qpci_io_writeq(ctrl->pdev, ctrl->bar, + NVME_REG_ACQ, (uint64_t)ctrl->admin_cq.phys_cqe); + + /* enable controller */ + { + uint32_t cc =3D 0; + NVME_SET_CC_EN(cc, 1); + qpci_io_writel(ctrl->pdev, ctrl->bar, NVME_REG_CC, cc); + } + + nvme_wait_ready(ctrl, 1); +} + +typedef struct test_migrate_req { + uint16_t cid; + bool handle_cqe; + uint64_t phys_identify; /* NvmeIdCtrl* */ +} test_migrate_req; + +static void test_migrate_send_nvme_reqs(nvme_ctrl *ctrl, test_migrate_req = *reqs, + int num) +{ + int i; + + for (i =3D 0; i < num; i++) { + reqs[i].phys_identify =3D nvme_admin_identify_ctrl(ctrl, reqs[i].c= id, + !reqs[i].handle_c= qe); + g_assert(reqs[i].phys_identify); + + if (reqs[i].handle_cqe) { + guest_free(ctrl->alloc, reqs[i].phys_identify); + } + } +} + +static void test_migrate_check_nvme(nvme_ctrl *ctrl, + test_migrate_req *reqs, int num) +{ + int i; + + for (i =3D 0; i < num; i++) { + NvmeCqe cqe; + + if (reqs[i].handle_cqe) { + continue; + } + + cqe =3D nvme_wait(&ctrl->admin_sq); + g_assert(nvme_is_cqe_success(&cqe)); + + g_assert_cmpint(le16_to_cpu(cqe.cid), =3D=3D, reqs[i].cid); + + #define GUEST_MEM_READB(phys_addr) \ + qtest_readb(ctrl->pdev->bus->qts, (phys_addr)) + + g_assert_cmpint(GUEST_MEM_READB( + PHYS_ADDR_OF_FIELD(NvmeIdCtrl, reqs[i].phys_identify, ieee[0])= ), + =3D=3D, 0x0); + g_assert_cmpint(GUEST_MEM_READB( + PHYS_ADDR_OF_FIELD(NvmeIdCtrl, reqs[i].phys_identify, ieee[1])= ), + =3D=3D, 0x54); + g_assert_cmpint(GUEST_MEM_READB( + PHYS_ADDR_OF_FIELD(NvmeIdCtrl, reqs[i].phys_identify, ieee[2])= ), + =3D=3D, 0x52); + + #undef GUEST_MEM_READB + + guest_free(ctrl->alloc, reqs[i].phys_identify); + } +} + +static void test_migrate(void *obj, void *data, QGuestAllocator *alloc) +{ + g_autofree gchar *tmpfs =3D NULL; + GError *err =3D NULL; + g_autofree gchar *mig_path =3D NULL; + g_autofree gchar *uri =3D NULL; + GString *dest_cmdline; + QTestState *to; + QDict *rsp; + QNvme *nvme =3D obj; + QPCIDevice *pdev =3D &nvme->dev; + g_autofree nvme_ctrl *ctrl =3D NULL; + test_migrate_req test_reqs[] =3D { + { 123, true }, + { 456, false }, + { 300, false }, + { 333, false } + }; + + if (qpci_check_buggy_msi(pdev)) { + return; + } + + /* create temporary dir and prepare unix socket path for migration */ + tmpfs =3D g_dir_make_tmp("nvme-test-XXXXXX", &err); + if (!tmpfs) { + g_test_message("Can't create temporary directory in %s: %s", + g_get_tmp_dir(), err->message); + g_error_free(err); + } + g_assert(tmpfs); + + mig_path =3D g_strdup_printf("%s/socket.mig", tmpfs); + uri =3D g_strdup_printf("unix:%s", mig_path); + + /* enable NVMe PCI device */ + qpci_device_enable(pdev); + + ctrl =3D g_malloc0(sizeof(*ctrl)); + ctrl->alloc =3D alloc; + ctrl->pdev =3D pdev; + ctrl->bar =3D qpci_iomap(ctrl->pdev, 0, NULL); + g_assert(pdev->bus->qts =3D=3D global_qtest); + + test_migrate_setup_nvme_ctrl(ctrl); + test_migrate_send_nvme_reqs(ctrl, test_reqs, ARRAY_SIZE(test_reqs)); + + qpci_iounmap(ctrl->pdev, ctrl->bar); + + dest_cmdline =3D g_string_new(qos_get_current_command_line()); + g_string_append_printf(dest_cmdline, " -incoming %s", uri); + + /* Create destination VM */ + to =3D qtest_init(dest_cmdline->str); + + /* Get access to PCI device from destination VM */ + nvme =3D qos_allocate_objects(to, &ctrl->alloc); + pdev =3D &nvme->dev; + ctrl->pdev =3D pdev; + ctrl->bar =3D qpci_iomap(ctrl->pdev, 0, NULL); + g_assert(pdev->bus->qts =3D=3D to); + + /* Migrate VM */ + rsp =3D qmp("{ 'execute': 'migrate', 'arguments': { 'uri': %s } }", ur= i); + g_assert(qdict_haskey(rsp, "return")); + qobject_unref(rsp); + + /* Wait when source VM is stopped */ + qmp_eventwait("STOP"); + + /* Copy guest physical memory allocator state */ + migrate_allocator(alloc, ctrl->alloc); + + /* Wait for destination VM to become alive */ + qtest_qmp_eventwait(to, "RESUME"); + + test_migrate_check_nvme(ctrl, test_reqs, ARRAY_SIZE(test_reqs)); + + qpci_iounmap(ctrl->pdev, ctrl->bar); + + qtest_quit(to); + g_unlink(mig_path); + g_rmdir(tmpfs); + g_string_free(dest_cmdline, true); +} + static void nvme_register_nodes(void) { QOSGraphEdgeOptions opts =3D { @@ -168,6 +587,8 @@ static void nvme_register_nodes(void) }); =20 qos_add_test("reg-read", "nvme", nvmetest_reg_read_test, NULL); + + qos_add_test("migrate", "nvme", test_migrate, NULL); } =20 libqos_init(nvme_register_nodes); --=20 2.47.3