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Raising fflags bits is modifying fcsr (an FP CSR). Scalar FP instructions that write integer registers (FP comparisons and FP-to-integer conversions) never call mark_fs_dirty at translation time to set mstatus.FS to dirty. However, they can raise FP exception flags via softfloat functions, which modifies fflags without any mechanism to dirty mstatus.FS. The affected helpers: - Comparisons: fle/fleq/flt/fltq/feq =E2=80=94 raise NV on NaN operands - FP-to-integer: fcvt.[w|wu|l|lu]/fcvtmod.w.d =E2=80=94 raise NX on inexact or NV on out-of-range Fix this issue by 1. Save float_exception_flags before the softfloat operation 2. Perform the operation 3. If any new exception bits are set, set fs to dirty Signed-off-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/fpu_helper.c | 157 +++++++++++++++++++++++++++++++------- 2 files changed, 130 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c98652cd62..9961815ec3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -675,6 +675,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, =20 uint8_t riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t); +void riscv_cpu_check_fflags(CPURISCVState *env, FloatExceptionFlags); =20 #ifndef CONFIG_USER_ONLY void cpu_set_exception_base(int vp_index, uint64_t address); diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index e6d1ffb1d6..db1475271b 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -50,6 +50,22 @@ void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t ha= rd) set_float_exception_flags(soft, &env->fp_status); } =20 +#ifndef CONFIG_USER_ONLY +void riscv_cpu_check_fflags(CPURISCVState *env, + FloatExceptionFlags pre_fflag) +{ + if (get_float_exception_flags(&env->fp_status) & ~pre_fflag) { + env->mstatus |=3D MSTATUS_FS; + if (env->virt_enabled) { + env->mstatus_hs |=3D MSTATUS_FS; + } + } +} +#else +void riscv_cpu_check_fflags(CPURISCVState *env, + FloatExceptionFlags pre_fflag) {} +#endif + void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) { FloatRoundMode softrm; @@ -286,59 +302,86 @@ target_ulong helper_fle_s(CPURISCVState *env, uint64_= t rs1, uint64_t rs2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); - return float32_le(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_le(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fleq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); - return float32_le_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_le_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); - return float32_lt(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_lt(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fltq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); - return float32_lt_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_lt_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); - return float32_eq_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_eq_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(env, rs1); - return float32_to_int32(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_to_int32(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(env, rs1); - return (int32_t)float32_to_uint32(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D (int32_t)float32_to_uint32(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(env, rs1); - return float32_to_int64(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_to_int64(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(env, rs1); - return float32_to_uint64(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float32_to_uint64(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1) @@ -453,52 +496,83 @@ uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t = frs1) =20 target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float64_le(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_le(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fleq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs= 2) { - return float64_le_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_le_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float64_lt(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_lt(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fltq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs= 2) { - return float64_lt_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_lt_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { - return float64_eq_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_eq_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1) { - return float64_to_int32(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_to_int32(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 uint64_t helper_fcvtmod_w_d(CPURISCVState *env, uint64_t value) { - return float64_to_int32_modulo(value, float_round_to_zero, &env->fp_st= atus); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + uint64_t ret =3D float64_to_int32_modulo(value, float_round_to_zero, + &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1) { - return (int32_t)float64_to_uint32(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D (int32_t)float64_to_uint32(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1) { - return float64_to_int64(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_to_int64(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1) { - return float64_to_uint64(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float64_to_uint64(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1) @@ -619,35 +693,50 @@ target_ulong helper_fle_h(CPURISCVState *env, uint64_= t rs1, uint64_t rs2) { float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); - return float16_le(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_le(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fleq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); - return float16_le_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_le_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); - return float16_lt(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_lt(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fltq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); - return float16_lt_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_lt_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); - return float16_eq_quiet(frs1, frs2, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_eq_quiet(frs1, frs2, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fclass_h(CPURISCVState *env, uint64_t rs1) @@ -683,25 +772,37 @@ uint64_t helper_froundnx_h(CPURISCVState *env, uint64= _t rs1) target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) { float16 frs1 =3D check_nanbox_h(env, rs1); - return float16_to_int32(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_to_int32(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_wu_h(CPURISCVState *env, uint64_t rs1) { float16 frs1 =3D check_nanbox_h(env, rs1); - return (int32_t)float16_to_uint32(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D (int32_t)float16_to_uint32(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_l_h(CPURISCVState *env, uint64_t rs1) { float16 frs1 =3D check_nanbox_h(env, rs1); - return float16_to_int64(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_to_int64(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 target_ulong helper_fcvt_lu_h(CPURISCVState *env, uint64_t rs1) { float16 frs1 =3D check_nanbox_h(env, rs1); - return float16_to_uint64(frs1, &env->fp_status); + FloatExceptionFlags pre_fflag =3D get_float_exception_flags(&env->fp_s= tatus); + target_ulong ret =3D float16_to_uint64(frs1, &env->fp_status); + riscv_cpu_check_fflags(env, pre_fflag); + return ret; } =20 uint64_t helper_fcvt_h_w(CPURISCVState *env, target_ulong rs1) --=20 2.43.7 From nobody Sun Jul 26 13:29:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1781175116; cv=none; d=zohomail.com; s=zohoarc; b=UMMU9T8EgXzh9PIyXUWK2emAjzrVTF/XZ5oZsY8zu3peJ9l4pifwhcJ6QTIJuEvbKi/TqXzZYrhoxD1zwiwBR19fHDiEmefV4YL3VgxwQwI3IYqMyKfUDlf1DL3F3/SQrsjyhZ8RUurwIVvL7BXhAElvMnjNEnaX7IIsGPVe9Wo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781175116; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Raising fflags bits is modifying fcsr (an FP CSR). When a vector FP instruction raises a floating-point exception, it modifies fflags (an FP CSR), but current implementation was not marking mstatus.FS dirty in this case. Fix the issue by snapshot fflags before the element loop and OR MSTATUS_FS into env->mstatus if any new exception bits are set afterwards. Signed-off-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 241 +++++++++++++++++++---------------- 1 file changed, 128 insertions(+), 113 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 89012fccb3..e321ca2616 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3172,34 +3172,36 @@ static void do_##NAME(void *vd, void *vs1, void *vs= 2, int i, \ *((TD *)vd + HD(i)) =3D OP(s2, s1, &env->fp_status); \ } =20 -#define GEN_VEXT_VV_ENV(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t vma =3D vext_vma(desc); \ - uint32_t i; \ - \ - VSTART_CHECK_EARLY_EXIT(env, vl); \ - \ - for (i =3D env->vstart; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - /* set masked-off elements to 1s */ \ - vext_set_elems_1s(vd, vma, i * ESZ, \ - (i + 1) * ESZ); \ - continue; \ - } \ - do_##NAME(vd, vs1, vs2, i, env); \ - } \ - env->vstart =3D 0; \ - /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, vl * ESZ, \ - total_elems * ESZ); \ +#define GEN_VEXT_VV_ENV(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t total_elems =3D \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ + uint32_t i; \ + FloatExceptionFlags pre_fflag =3D \ + get_float_exception_flags(&env->fp_status); \ + \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, vs1, vs2, i, env); \ + } \ + env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ + riscv_cpu_check_fflags(env, pre_fflag); \ } =20 RVVCALL(OPFVV2, vfadd_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_add) @@ -3219,34 +3221,36 @@ static void do_##NAME(void *vd, uint64_t s1, void *= vs2, int i, \ *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1, &env->fp_status);\ } =20 -#define GEN_VEXT_VF(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t vma =3D vext_vma(desc); \ - uint32_t i; \ - \ - VSTART_CHECK_EARLY_EXIT(env, vl); \ - \ - for (i =3D env->vstart; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - /* set masked-off elements to 1s */ \ - vext_set_elems_1s(vd, vma, i * ESZ, \ - (i + 1) * ESZ); \ - continue; \ - } \ - do_##NAME(vd, s1, vs2, i, env); \ - } \ - env->vstart =3D 0; \ - /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, vl * ESZ, \ - total_elems * ESZ); \ +#define GEN_VEXT_VF(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t total_elems =3D \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ + uint32_t i; \ + FloatExceptionFlags pre_fflag =3D \ + get_float_exception_flags(&env->fp_status); \ + \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, s1, vs2, i, env); \ + } \ + env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ + riscv_cpu_check_fflags(env, pre_fflag); \ } =20 RVVCALL(OPFVF2, vfadd_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_add) @@ -3993,35 +3997,38 @@ static void do_##NAME(void *vd, void *vs2, int i, = \ *((TD *)vd + HD(i)) =3D OP(s2, &env->fp_status); \ } =20 -#define GEN_VEXT_V_ENV(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t vma =3D vext_vma(desc); \ - uint32_t i; \ - \ - VSTART_CHECK_EARLY_EXIT(env, vl); \ - \ - if (vl =3D=3D 0) { \ - return; \ - } \ - for (i =3D env->vstart; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - /* set masked-off elements to 1s */ \ - vext_set_elems_1s(vd, vma, i * ESZ, \ - (i + 1) * ESZ); \ - continue; \ - } \ - do_##NAME(vd, vs2, i, env); \ - } \ - env->vstart =3D 0; \ - vext_set_elems_1s(vd, vta, vl * ESZ, \ - total_elems * ESZ); \ +#define GEN_VEXT_V_ENV(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t total_elems =3D \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ + uint32_t i; \ + FloatExceptionFlags pre_fflag =3D \ + get_float_exception_flags(&env->fp_status); \ + \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ + if (vl =3D=3D 0) { \ + return; \ + } \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, vs2, i, env); \ + } \ + env->vstart =3D 0; \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ + riscv_cpu_check_fflags(env, pre_fflag); \ } =20 RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt) @@ -4610,6 +4617,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ + FloatExceptionFlags pre_fflag =3D \ + get_float_exception_flags(&env->fp_status); \ \ VSTART_CHECK_EARLY_EXIT(env, vl); \ \ @@ -4636,6 +4645,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ vext_set_elem_mask(vd, i, 1); \ } \ } \ + riscv_cpu_check_fflags(env, pre_fflag); \ } =20 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h_bf16, uint16_t, H2, bfloat16_eq_quiet) @@ -4653,6 +4663,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ + FloatExceptionFlags pre_fflag =3D \ + get_float_exception_flags(&env->fp_status); \ \ VSTART_CHECK_EARLY_EXIT(env, vl); \ \ @@ -4678,6 +4690,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ vext_set_elem_mask(vd, i, 1); \ } \ } \ + riscv_cpu_check_fflags(env, pre_fflag); \ } =20 GEN_VEXT_CMP_VF(vmfeq_vf_h_bf16, uint16_t, H2, bfloat16_eq_quiet) @@ -5151,34 +5164,36 @@ GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4= , H2, DO_ADD) GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD) =20 /* Vector Single-Width Floating-Point Reduction Instructions */ -#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t esz =3D sizeof(TD); \ - uint32_t vlenb =3D simd_maxsz(desc); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t i; \ - TD s1 =3D *((TD *)vs1 + HD(0)); \ - \ - VSTART_CHECK_EARLY_EXIT(env, vl); \ - \ - for (i =3D env->vstart; i < vl; i++) { \ - TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - s1 =3D OP(s1, (TD)s2, &env->fp_status); \ - } \ - if (vl > 0) { \ - *((TD *)vd + HD(0)) =3D s1; \ - } \ - env->vstart =3D 0; \ - /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, esz, vlenb); \ +#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(TD); \ + uint32_t vlenb =3D simd_maxsz(desc); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t i; \ + FloatExceptionFlags pre_fflag =3D \ + get_float_exception_flags(&env->fp_status); \ + TD s1 =3D *((TD *)vs1 + HD(0)); \ + \ + VSTART_CHECK_EARLY_EXIT(env, vl); \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + s1 =3D OP(s1, (TD)s2, &env->fp_status); \ + } \ + if (vl > 0) { \ + *((TD *)vd + HD(0)) =3D s1; \ + } \ + env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, esz, vlenb); \ + riscv_cpu_check_fflags(env, pre_fflag); \ } =20 /* Unordered sum */ --=20 2.43.7