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a="85595451" X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="85595451" X-CSE-ConnectionGUID: xfEkZdzxTZCMTCfAcdPOJg== X-CSE-MsgGUID: zz+fC0XlRVSsLQNZ5OPqAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="246469751" From: Junjie Cao To: jic23@kernel.org Cc: fan.ni@samsung.com, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, junjie.cao@intel.com Subject: [PATCH v2 1/5] hw/cxl: introduce trace-events infrastructure Date: Thu, 11 Jun 2026 14:30:23 +0800 Message-ID: <20260611063027.1166493-2-junjie.cao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260611063027.1166493-1-junjie.cao@intel.com> References: <20260611063027.1166493-1-junjie.cao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=junjie.cao@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781160845342158501 Content-Type: text/plain; charset="utf-8" The CXL subsystem currently has no trace-events file. Create one under hw/cxl/ and register it in the top-level meson.build trace_events_subdirs list so that subsequent patches can add trace points incrementally. Signed-off-by: Junjie Cao --- hw/cxl/trace-events | 1 + hw/cxl/trace.h | 2 ++ meson.build | 1 + 3 files changed, 4 insertions(+) create mode 100644 hw/cxl/trace-events create mode 100644 hw/cxl/trace.h diff --git a/hw/cxl/trace-events b/hw/cxl/trace-events new file mode 100644 index 0000000000..23bc9b19b9 --- /dev/null +++ b/hw/cxl/trace-events @@ -0,0 +1 @@ +# See docs/devel/tracing.rst for syntax documentation. diff --git a/hw/cxl/trace.h b/hw/cxl/trace.h new file mode 100644 index 0000000000..ab87f3e98f --- /dev/null +++ b/hw/cxl/trace.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include "trace/trace-hw_cxl.h" diff --git a/meson.build b/meson.build index 19e123423b..c229199d5d 100644 --- a/meson.build +++ b/meson.build @@ -3596,6 +3596,7 @@ if have_system 'hw/audio', 'hw/block', 'hw/char', + 'hw/cxl', 'hw/display', 'hw/dma', 'hw/fsi', --=20 2.43.0 From nobody Fri Jun 26 22:03:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Jun 2026 02:53:50 -0400 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2026 23:53:46 -0700 Received: from junjie-desk-dev.bj.intel.com ([10.238.152.71]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2026 23:53:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781160828; x=1812696828; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mi/AXbKiKl5jLdXE4Q3gMAEbPnG58Ck9tvhBVlV+p+M=; b=d+edcAThzJ5GW9Dv/iihJWF6txoJUJnJTDDeEKZdaxoEtd8d2W4Qg2yj 29P9HOdMx16dQr6zAv2CEpSdh/PoG2jJV4iaTq1BT5nAMnnXey3eDv025 A6AtL4jIRuLk/eydueK6dVUZNaqn6Sy/vOGxR6h/pri09ST205bRw4U0P tngsilXvRVsUtB0PTfys6wiHnFvvO4eEMx1HivNCD7NyjmRVVmSTRI490 Z5jUSvMF6n/8odeqVH2MmYWuzl71TFLnmSJetOpwiPBbiXRmHIldcUHO+ pNR9W1U+wTH0k2gZQROUc+00+7lwJV7thwBMs00wovjLSMQFKY9abgNhG A==; X-CSE-ConnectionGUID: ep5CkZyqQVeqerI0XSAYdQ== X-CSE-MsgGUID: jUXOZIUDQm+AjXYqHj75IQ== X-IronPort-AV: E=McAfee;i="6800,10657,11813"; a="85595461" X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="85595461" X-CSE-ConnectionGUID: 4dTmxVGfTKOMcmse1DvzJw== X-CSE-MsgGUID: rVi8GgPzSq2G/zpCfTM8zA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="246469784" From: Junjie Cao To: jic23@kernel.org Cc: fan.ni@samsung.com, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, junjie.cao@intel.com Subject: [PATCH v2 2/5] hw/cxl: trace mailbox command dispatch and payload errors Date: Thu, 11 Jun 2026 14:30:24 +0800 Message-ID: <20260611063027.1166493-3-junjie.cao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260611063027.1166493-1-junjie.cao@intel.com> References: <20260611063027.1166493-1-junjie.cao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=junjie.cao@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781160869570158500 Content-Type: text/plain; charset="utf-8" Add trace events for CXL mailbox command processing: command entry, handler completion, and all payload-length validation failures. Three trace points are added: cxl_mailbox_cmd - command entry with set, cmd, name, len_in cxl_mailbox_cmd_done - handler return with ret code and len_out cxl_mailbox_payload_error - payload length mismatch (all 21 sites) To make set/cmd accessible inside individual command handlers (which do not receive them as parameters), add a current_opcode field to CXLCCI that is set before handler dispatch. This mirrors the existing cci->bg.opcode pattern used for background operations. The payload_error event covers not only the centralised entry check in cxl_process_cci_message() but also every handler-internal return of CXL_MBOX_INVALID_PAYLOAD_LENGTH, including variable-length command validators in tunnelling, DCD, firmware update, set-feature, media operations, and physical-port commands. As a minor cleanup, add a CXLCCI *cci parameter to media_operations_discovery() so it can access current_opcode. This aligns it with media_operations_sanitize() which already receives cci. Signed-off-by: Junjie Cao --- hw/cxl/cxl-mailbox-utils.c | 71 +++++++++++++++++++++++++++++++++++-- hw/cxl/trace-events | 5 +++ include/hw/cxl/cxl_device.h | 1 + 3 files changed, 75 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index d8ba7e8625..10af11dc1f 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -27,6 +27,7 @@ #include "system/hostmem.h" #include "qemu/range.h" #include "qapi/qapi-types-cxl.h" +#include "trace.h" =20 #define CXL_CAPACITY_MULTIPLIER (256 * MiB) #define CXL_DC_EVENT_LOG_SIZE 8 @@ -179,14 +180,23 @@ static CXLRetCode cmd_tunnel_management_cmd(const str= uct cxl_cmd *cmd, out =3D (void *)payload_out; =20 if (len_in < sizeof(*in)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } /* Enough room for minimum sized message - no payload */ if (in->size < sizeof(in->ccimessage)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } /* Length of input payload should be in->size + a wrapping tunnel head= er */ if (in->size !=3D len_in - offsetof(typeof(*out), ccimessage)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } if (in->ccimessage.category !=3D CXL_CCI_CAT_REQ) { @@ -299,6 +309,9 @@ static CXLRetCode cmd_events_clear_records(const struct= cxl_cmd *cmd, =20 if (len_in < sizeof(*pl) || len_in < sizeof(*pl) + sizeof(*pl->handle) * pl->nr_recs) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -361,6 +374,9 @@ static CXLRetCode cmd_events_set_interrupt_policy(const= struct cxl_cmd *cmd, CXLEventLog *log; =20 if (len_in < CXL_EVENT_INT_SETTING_MIN_LEN) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -604,6 +620,9 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, out =3D (struct cxl_fmapi_get_phys_port_state_resp_pl *)payload_out; =20 if (len_in < sizeof(*in)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } /* Check if what was requested can fit */ @@ -782,6 +801,9 @@ static CXLRetCode cmd_physical_port_control(const struc= t cxl_cmd *cmd, } QEMU_PACKED *in =3D (void *)payload_in; =20 if (len_in < sizeof(*in)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -961,6 +983,9 @@ static CXLRetCode cmd_firmware_update_transfer(const st= ruct cxl_cmd *cmd, size_t offset, length; =20 if (len < sizeof(*fw_transfer)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -1718,6 +1743,9 @@ static CXLRetCode cmd_features_set_feature(const stru= ct cxl_cmd *cmd, uint16_t count; =20 if (len_in < sizeof(*hdr)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -1748,6 +1776,9 @@ static CXLRetCode cmd_features_set_feature(const stru= ct cxl_cmd *cmd, bytes_to_copy =3D len_in - sizeof(CXLSetFeatureInHeader); =20 if (bytes_to_copy =3D=3D 0) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -1762,6 +1793,9 @@ static CXLRetCode cmd_features_set_feature(const stru= ct cxl_cmd *cmd, =20 if ((uint32_t)hdr->offset + bytes_to_copy > sizeof(ct3d->patrol_scrub_wr_attrs)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } memcpy((uint8_t *)&ct3d->patrol_scrub_wr_attrs + hdr->offset, @@ -1789,6 +1823,9 @@ static CXLRetCode cmd_features_set_feature(const stru= ct cxl_cmd *cmd, =20 if ((uint32_t)hdr->offset + bytes_to_copy > sizeof(ct3d->ecs_wr_attrs)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } memcpy((uint8_t *)&ct3d->ecs_wr_attrs + hdr->offset, @@ -2294,6 +2331,9 @@ static CXLRetCode cmd_ccls_set_lsa(const struct cxl_c= md *cmd, =20 *len_out =3D 0; if (len_in < hdr_len) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -2661,7 +2701,8 @@ static const struct media_op_supported_list_entry med= ia_op_matrix[] =3D { static CXLRetCode media_operations_discovery(uint8_t *payload_in, size_t len_in, uint8_t *payload_out, - size_t *len_out) + size_t *len_out, + CXLCCI *cci) { struct { uint8_t media_operation_class; @@ -2680,6 +2721,9 @@ static CXLRetCode media_operations_discovery(uint8_t = *payload_in, int count =3D 0; =20 if (len_in < sizeof(*media_op_in_disc_pl)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + "MEDIA_OPERATIONS", len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -2741,6 +2785,9 @@ static CXLRetCode media_operations_sanitize(CXLType3D= ev *ct3d, =20 dpa_range_list_size =3D dpa_range_count * sizeof(struct dpa_range_list= _entry); if (len_in < (sizeof(*media_op_in_sanitize_pl) + dpa_range_list_size))= { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + "MEDIA_OPERATIONS", len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -2792,6 +2839,9 @@ static CXLRetCode cmd_media_operations(const struct c= xl_cmd *cmd, uint8_t media_op_subclass =3D 0; =20 if (len_in < sizeof(*media_op_in_common_pl)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -2805,7 +2855,7 @@ static CXLRetCode cmd_media_operations(const struct c= xl_cmd *cmd, } =20 return media_operations_discovery(payload_in, len_in, payload_out, - len_out); + len_out, cci); case MEDIA_OP_CLASS_SANITIZE: switch (media_op_subclass) { case MEDIA_OP_SAN_SUBC_SANITIZE: @@ -3712,6 +3762,9 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struc= t cxl_cmd *cmd, CXLRetCode ret; =20 if (len_in < sizeof(*in)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -3723,6 +3776,9 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struc= t cxl_cmd *cmd, =20 if (len_in < sizeof(*in) + sizeof(*in->updated_entries) * in->num_entries_updat= ed) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -3883,6 +3939,9 @@ static CXLRetCode cmd_dcd_release_dyn_cap(const struc= t cxl_cmd *cmd, CXLRetCode ret; =20 if (len_in < sizeof(*in)) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -3892,6 +3951,9 @@ static CXLRetCode cmd_dcd_release_dyn_cap(const struc= t cxl_cmd *cmd, =20 if (len_in < sizeof(*in) + sizeof(*in->updated_entries) * in->num_entries_updat= ed) { + trace_cxl_mailbox_payload_error(cci->current_opcode >> 8, + cci->current_opcode & 0xff, + cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -4588,7 +4650,11 @@ int cxl_process_cci_message(CXLCCI *cci, uint8_t set= , uint8_t cmd, return CXL_MBOX_UNSUPPORTED; } =20 + cci->current_opcode =3D (set << 8) | cmd; + trace_cxl_mailbox_cmd(set, cmd, cxl_cmd->name, len_in); + if (len_in !=3D cxl_cmd->in && cxl_cmd->in !=3D ~0) { + trace_cxl_mailbox_payload_error(set, cmd, cxl_cmd->name, len_in); return CXL_MBOX_INVALID_PAYLOAD_LENGTH; } =20 @@ -4620,6 +4686,7 @@ int cxl_process_cci_message(CXLCCI *cci, uint8_t set,= uint8_t cmd, } =20 ret =3D (*h)(cxl_cmd, pl_in, len_in, pl_out, len_out, cci); + trace_cxl_mailbox_cmd_done(set, cmd, ret, *len_out); if ((cxl_cmd->effect & CXL_MBOX_BACKGROUND_OPERATION) && ret =3D=3D CXL_MBOX_BG_STARTED) { *bg_started =3D true; diff --git a/hw/cxl/trace-events b/hw/cxl/trace-events index 23bc9b19b9..609def2dec 100644 --- a/hw/cxl/trace-events +++ b/hw/cxl/trace-events @@ -1 +1,6 @@ # See docs/devel/tracing.rst for syntax documentation. + +# cxl-mailbox-utils.c +cxl_mailbox_cmd(uint8_t set, uint8_t cmd, const char *name, size_t len_in)= "set=3D0x%02x cmd=3D0x%02x [%s] len_in=3D%zu" +cxl_mailbox_cmd_done(uint8_t set, uint8_t cmd, int ret, size_t len_out) "s= et=3D0x%02x cmd=3D0x%02x ret=3D%d len_out=3D%zu" +cxl_mailbox_payload_error(uint8_t set, uint8_t cmd, const char *name, size= _t len_in) "set=3D0x%02x cmd=3D0x%02x [%s] len_in=3D%zu" diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 393f312217..3237d59ab2 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -207,6 +207,7 @@ typedef struct CXLCCI { time_t last_partxfer; } fw; =20 + uint16_t current_opcode; size_t payload_max; /* Pointer to device hosting the CCI */ DeviceState *d; --=20 2.43.0 From nobody Fri Jun 26 22:03:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1781160881; cv=none; d=zohomail.com; s=zohoarc; b=exu1HRNCBFDFiDo4Vcg4wcwDrOUwv84FwWWJfJ81bdkzUGszdpV3+xsdG+Ej925vu0PZNLCJ3bzu4dYHoG3lWKl/s31BSMsz/Wy0VGYJAncty9/gNTTV1XGh7ecsk1mkSvmt4p0h2CimZBWMKwpXDK1hNq3T2NQpiMnOw8zNi6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781160881; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: x2QIjn39R2SMUVhkwIv2Dg== X-CSE-MsgGUID: OOqGuOMxSTGhMM+vsaP1gA== X-IronPort-AV: E=McAfee;i="6800,10657,11813"; a="85595472" X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="85595472" X-CSE-ConnectionGUID: ONMn0cpuST+k+fUZDPrknw== X-CSE-MsgGUID: VgodT8ZGTN22uX4QGF7vkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="246469799" From: Junjie Cao To: jic23@kernel.org Cc: fan.ni@samsung.com, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, junjie.cao@intel.com Subject: [PATCH v2 3/5] hw/cxl: trace HDM decoder write, commit and uncommit Date: Thu, 11 Jun 2026 14:30:25 +0800 Message-ID: <20260611063027.1166493-4-junjie.cao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260611063027.1166493-1-junjie.cao@intel.com> References: <20260611063027.1166493-1-junjie.cao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=junjie.cao@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781160881587158500 Content-Type: text/plain; charset="utf-8" Add trace events for HDM decoder programming in the CXL Type-3 device model. These paths control address-decode behaviour and are among the most frequently debugged during CXL topology bring-up. Three trace points are added: cxl_hdm_decoder_write - guest write to a decoder CTRL register, with the raw value and commit flag cxl_hdm_decoder_commit - actual commit with decoded base, size, interleave ways (IW) and granularity (IG) cxl_hdm_decoder_uncommit - decoder uncommit with index Base and size are extracted using the same split-register pattern (ldl_le_p + 0xf0000000 mask) used by cxl_hdm_find_target() in cxl-host.c, producing architecturally-meaningful addresses. IW and IG are extracted from CTRL via FIELD_EX32. Signed-off-by: Junjie Cao --- hw/mem/cxl_type3.c | 19 ++++++++++++++++++- hw/mem/trace-events | 5 +++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 4739239da3..c3f7483b70 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -30,6 +30,7 @@ #include "system/numa.h" #include "hw/cxl/cxl.h" #include "hw/pci/msix.h" +#include "trace.h" =20 /* type3 device private */ enum CXL_T3_MSIX_VECTOR { @@ -419,13 +420,24 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int= which) int hdm_inc =3D R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_L= O; ComponentRegisters *cregs =3D &ct3d->cxl_cstate.crb; uint32_t *cache_mem =3D cregs->cache_mem_registers; - uint32_t ctrl; + uint32_t ctrl, low, high; + uint64_t base, size; =20 ctrl =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_in= c); /* TODO: Sanity checks that the decoder is possible */ ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0); ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); =20 + low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + which * hdm_= inc); + high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + which * hdm= _inc); + base =3D (low & 0xf0000000) | ((uint64_t)high << 32); + low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + which * hdm_= inc); + high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + which * hdm= _inc); + size =3D (low & 0xf0000000) | ((uint64_t)high << 32); + trace_cxl_hdm_decoder_commit(which, base, size, + FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, I= W), + FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, I= G)); + stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl); } =20 @@ -436,6 +448,8 @@ static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int= which) uint32_t *cache_mem =3D cregs->cache_mem_registers; uint32_t ctrl; =20 + trace_cxl_hdm_decoder_uncommit(which); + ctrl =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_in= c); =20 ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0); @@ -623,6 +637,9 @@ static void ct3d_reg_write(void *opaque, hwaddr offset,= uint64_t value, } =20 stl_le_p((uint8_t *)cache_mem + offset, value); + if (which_hdm >=3D 0) { + trace_cxl_hdm_decoder_write(which_hdm, value, should_commit); + } if (should_commit) { hdm_decoder_commit(ct3d, which_hdm); } else if (should_uncommit) { diff --git a/hw/mem/trace-events b/hw/mem/trace-events index 8b6b02b5bf..07c7315148 100644 --- a/hw/mem/trace-events +++ b/hw/mem/trace-events @@ -6,3 +6,8 @@ mhp_pc_dimm_assigned_slot(int slot) "%d" memory_device_pre_plug(const char *id, uint64_t addr) "id=3D%s addr=3D0x%"= PRIx64 memory_device_plug(const char *id, uint64_t addr) "id=3D%s addr=3D0x%"PRIx= 64 memory_device_unplug(const char *id, uint64_t addr) "id=3D%s addr=3D0x%"PR= Ix64 + +# cxl_type3.c +cxl_hdm_decoder_write(int which, uint32_t value, bool commit) "decoder=3D%= d ctrl=3D0x%08x commit=3D%d" +cxl_hdm_decoder_commit(int which, uint64_t base, uint64_t size, int iw, in= t ig) "decoder=3D%d base=3D0x%"PRIx64" size=3D0x%"PRIx64" iw=3D%d ig=3D%d" +cxl_hdm_decoder_uncommit(int which) "decoder=3D%d" --=20 2.43.0 From nobody Fri Jun 26 22:03:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 11 Jun 2026 02:53:58 -0400 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2026 23:53:57 -0700 Received: from junjie-desk-dev.bj.intel.com ([10.238.152.71]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jun 2026 23:53:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781160838; x=1812696838; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bjCmdxXe78AH05DYv6kC/9KUguuQjGAQp6spxywWFHo=; b=PevG2r9Et0pf8/SvRmC1utHbENERXsMY8SR2LOnhahrwriw4FDyrVWk2 z0iTG6oeOU1Ab5d5G41RHqz3VJJiTbz8EtCGPW7y3sNYbM8Z5TRzN9uVs hiuYz5cj13GT3VlqBNnuFi+cKWBEZMU+915XoJ1bGG0IxWBuoqx2JHGx5 +p44HeW+/rDtoSKCysGYryhviCCioFXbEPKlc0tsCPDn+N77B7QwOT77i 6ArwazhiOJMJTTTvwDnGpr30sPR245xUva00jDQ0GLgoYVCcsAaTIhs4p f/hDANnw/B3kaVnMtXKybBTMVIlzsLzFkqNk6CdX3N0NxfqabLauEQsKS A==; X-CSE-ConnectionGUID: qVB02jnTT7C7VxDsRYVNyA== X-CSE-MsgGUID: iSlN7QBLShyxR2T3MiBXTQ== X-IronPort-AV: E=McAfee;i="6800,10657,11813"; a="85595482" X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="85595482" X-CSE-ConnectionGUID: Oc6XA8rdTryoyY9ABve7LA== X-CSE-MsgGUID: NbzhNLcVQpK5YutRdt3wSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="246469819" From: Junjie Cao To: jic23@kernel.org Cc: fan.ni@samsung.com, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, junjie.cao@intel.com Subject: [PATCH v2 4/5] hw/cxl: trace event log insertion, overflow and clear Date: Thu, 11 Jun 2026 14:30:26 +0800 Message-ID: <20260611063027.1166493-5-junjie.cao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260611063027.1166493-1-junjie.cao@intel.com> References: <20260611063027.1166493-1-junjie.cao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=junjie.cao@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781160859386158500 Content-Type: text/plain; charset="utf-8" Add trace events for CXL event log activity. Event insertion, overflow, and clearing are exercised on every error injection or dynamic capacity event, but the interaction with the per-log overflow counter was previously opaque. Three trace points are added: cxl_event_insert - successful enqueue, with log type and resulting occupancy (queue depth after insert) cxl_event_overflow - overflow threshold hit, event dropped, with cumulative overflow count cxl_event_clear - bulk clear with log type and number of records removed As a minor optimisation, cache the result of cxl_event_count() in a local variable so the O(n) queue walk is performed once per insert rather than twice. Signed-off-by: Junjie Cao --- hw/cxl/cxl-events.c | 13 +++++++++++-- hw/cxl/trace-events | 5 +++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-events.c b/hw/cxl/cxl-events.c index 5356dfb5b3..685ef5dc44 100644 --- a/hw/cxl/cxl-events.c +++ b/hw/cxl/cxl-events.c @@ -13,6 +13,7 @@ #include "hw/pci/msix.h" #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_events.h" +#include "trace.h" =20 /* Artificial limit on the number of events a log can hold */ #define CXL_TEST_EVENT_OVERFLOW 8 @@ -98,6 +99,7 @@ bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventLogT= ype log_type, uint64_t time; CXLEventLog *log; CXLEvent *entry; + int occupancy; =20 if (log_type >=3D CXL_EVENT_TYPE_MAX) { return false; @@ -109,12 +111,15 @@ bool cxl_event_insert(CXLDeviceState *cxlds, CXLEvent= LogType log_type, =20 QEMU_LOCK_GUARD(&log->lock); =20 - if (cxl_event_count(log) >=3D CXL_TEST_EVENT_OVERFLOW) { + occupancy =3D cxl_event_count(log); + + if (occupancy >=3D CXL_TEST_EVENT_OVERFLOW) { if (log->overflow_err_count =3D=3D 0) { log->first_overflow_timestamp =3D time; } log->overflow_err_count++; log->last_overflow_timestamp =3D time; + trace_cxl_event_overflow(log_type, log->overflow_err_count); return false; } =20 @@ -133,8 +138,10 @@ bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventL= ogType log_type, QSIMPLEQ_INSERT_TAIL(&log->events, entry, node); cxl_event_set_status(cxlds, log_type, true); =20 + trace_cxl_event_insert(log_type, occupancy + 1); + /* Count went from 0 to 1 */ - return cxl_event_count(log) =3D=3D 1; + return occupancy =3D=3D 0; } =20 void cxl_discard_all_event_records(CXLDeviceState *cxlds) @@ -234,6 +241,8 @@ CXLRetCode cxl_event_clear_records(CXLDeviceState *cxld= s, entry =3D cxl_event_get_head(log); } =20 + trace_cxl_event_clear(log_type, nr); + return CXL_MBOX_SUCCESS; } =20 diff --git a/hw/cxl/trace-events b/hw/cxl/trace-events index 609def2dec..17f9e7059c 100644 --- a/hw/cxl/trace-events +++ b/hw/cxl/trace-events @@ -4,3 +4,8 @@ cxl_mailbox_cmd(uint8_t set, uint8_t cmd, const char *name, size_t len_in)= "set=3D0x%02x cmd=3D0x%02x [%s] len_in=3D%zu" cxl_mailbox_cmd_done(uint8_t set, uint8_t cmd, int ret, size_t len_out) "s= et=3D0x%02x cmd=3D0x%02x ret=3D%d len_out=3D%zu" cxl_mailbox_payload_error(uint8_t set, uint8_t cmd, const char *name, size= _t len_in) "set=3D0x%02x cmd=3D0x%02x [%s] len_in=3D%zu" + +# cxl-events.c +cxl_event_insert(int log_type, int occupancy) "log_type=3D%d occupancy=3D%= d" +cxl_event_overflow(int log_type, uint16_t overflow_count) "log_type=3D%d o= verflow_count=3D%u" +cxl_event_clear(int log_type, int nr_recs) "log_type=3D%d nr_recs=3D%d" --=20 2.43.0 From nobody Fri Jun 26 22:03:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="85595499" X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="85595499" X-CSE-ConnectionGUID: Yt3EXWXKSPOSxTY3+4RcFg== X-CSE-MsgGUID: XIhIlnedRmmRiXMD1Z5BfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,198,1774335600"; d="scan'208";a="246469849" From: Junjie Cao To: jic23@kernel.org Cc: fan.ni@samsung.com, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, junjie.cao@intel.com Subject: [PATCH v2 5/5] hw/cxl: trace CFMWS address-to-device routing Date: Thu, 11 Jun 2026 14:30:27 +0800 Message-ID: <20260611063027.1166493-6-junjie.cao@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260611063027.1166493-1-junjie.cao@intel.com> References: <20260611063027.1166493-1-junjie.cao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=junjie.cao@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1781160863340158500 Content-Type: text/plain; charset="utf-8" Add trace events for the CXL Fixed Memory Window address routing path. This translates a host physical address through interleave granularity calculation and up to two levels of HDM decoder lookups (host-bridge and optional switch USP). Two trace points are added: cxl_cfmws_lookup - entry to CFMWS decode with the computed root-bus interleave index cxl_cfmws_target_resolved - HDM decoder produced a port target (fires for both host-bridge and switch USP lookups) In non-passthrough topologies, a cxl_cfmws_lookup without a following cxl_cfmws_target_resolved indicates the host-bridge HDM decode failed. Passthrough-mode routing goes through pcie_find_port_first() without HDM decoding, so no target_resolved event is expected in that case. A dedicated passthrough-mode trace event is deferred pending upstream passthrough topology support. Signed-off-by: Junjie Cao --- hw/cxl/cxl-host.c | 4 ++++ hw/cxl/trace-events | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index a94b893e99..0efdfcdfa7 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -21,6 +21,7 @@ #include "hw/pci/pci_host.h" #include "hw/pci/pcie_port.h" #include "hw/pci-bridge/pci_expander_bridge.h" +#include "trace.h" =20 static void cxl_fixed_memory_window_config(CXLFixedMemoryWindowOptions *ob= ject, int index, Error **errp) @@ -169,6 +170,7 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow = *fw, hwaddr addr) PCIDevice *rp, *d; =20 rb_index =3D (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_target= s; + trace_cxl_cfmws_lookup(addr, rb_index); hb =3D PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl_host_bridge); if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) { return NULL; @@ -191,6 +193,7 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow = *fw, hwaddr addr) if (!target_found) { return NULL; } + trace_cxl_cfmws_target_resolved(addr, target); =20 rp =3D pcie_find_port_by_pn(hb->bus, target); if (!rp) { @@ -227,6 +230,7 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow = *fw, hwaddr addr) if (!target_found) { return NULL; } + trace_cxl_cfmws_target_resolved(addr, target); =20 d =3D pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target); if (!d) { diff --git a/hw/cxl/trace-events b/hw/cxl/trace-events index 17f9e7059c..0cfaa0c128 100644 --- a/hw/cxl/trace-events +++ b/hw/cxl/trace-events @@ -9,3 +9,7 @@ cxl_mailbox_payload_error(uint8_t set, uint8_t cmd, const c= har *name, size_t len cxl_event_insert(int log_type, int occupancy) "log_type=3D%d occupancy=3D%= d" cxl_event_overflow(int log_type, uint16_t overflow_count) "log_type=3D%d o= verflow_count=3D%u" cxl_event_clear(int log_type, int nr_recs) "log_type=3D%d nr_recs=3D%d" + +# cxl-host.c +cxl_cfmws_lookup(uint64_t addr, int rb_index) "addr=3D0x%"PRIx64" rb_index= =3D%d" +cxl_cfmws_target_resolved(uint64_t addr, uint8_t target) "addr=3D0x%"PRIx6= 4" target=3D0x%02x" --=20 2.43.0