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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781156196651158500 From: Brian Cain Co-authored-by: Mike Lambert Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/hexswi.h | 17 +++ target/hexagon/cpu.c | 1 + target/hexagon/hexswi.c | 270 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 target/hexagon/hexswi.h create mode 100644 target/hexagon/hexswi.c diff --git a/target/hexagon/hexswi.h b/target/hexagon/hexswi.h new file mode 100644 index 00000000000..48c1ae6e4c1 --- /dev/null +++ b/target/hexagon/hexswi.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXSWI_H +#define HEXSWI_H + + +#include "cpu.h" + +void hexagon_cpu_do_interrupt(CPUState *cpu); +void register_trap_exception(CPUHexagonState *env, int type, int imm, + uint32_t PC); + +#endif /* HEXSWI_H */ diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 27f0ef50df2..ec0ca3ee678 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -34,6 +34,7 @@ #include "sys_macros.h" #include "accel/tcg/cpu-ldst.h" #include "qemu/main-loop.h" +#include "hex_interrupts.h" #endif =20 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c new file mode 100644 index 00000000000..dbb5dec827e --- /dev/null +++ b/target/hexagon/hexswi.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_helper.h" +#include "exec/helper-proto.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "arch.h" +#include "internal.h" +#include "macros.h" +#include "sys_macros.h" +#include "tcg/tcg-op.h" +#include "hex_mmu.h" +#include "hexswi.h" +#include "hw/hexagon/hexagon_globalreg.h" + +#ifdef CONFIG_USER_ONLY +#error "This file is only used in system emulation" +#endif + +static void set_addresses(CPUHexagonState *env, uint32_t pc_offset, + uint32_t exception_index) + +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t evb =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_EVB, + env->threadId) : + cpu->boot_addr; + env->t_sreg[HEX_SREG_ELR] =3D env->gpr[HEX_REG_PC] + pc_offset; + env->gpr[HEX_REG_PC] =3D evb | (exception_index << 2); +} + +static const char *event_name[] =3D { + [HEX_EVENT_RESET] =3D "HEX_EVENT_RESET", + [HEX_EVENT_IMPRECISE] =3D "HEX_EVENT_IMPRECISE", + [HEX_EVENT_PRECISE] =3D "HEX_EVENT_PRECISE", + [HEX_EVENT_TLB_MISS_X] =3D "HEX_EVENT_TLB_MISS_X", + [HEX_EVENT_TLB_MISS_RW] =3D "HEX_EVENT_TLB_MISS_RW", + [HEX_EVENT_TRAP0] =3D "HEX_EVENT_TRAP0", + [HEX_EVENT_TRAP1] =3D "HEX_EVENT_TRAP1", + [HEX_EVENT_FPTRAP] =3D "HEX_EVENT_FPTRAP", + [HEX_EVENT_DEBUG] =3D "HEX_EVENT_DEBUG", + [HEX_EVENT_INT0] =3D "HEX_EVENT_INT0", + [HEX_EVENT_INT1] =3D "HEX_EVENT_INT1", + [HEX_EVENT_INT2] =3D "HEX_EVENT_INT2", + [HEX_EVENT_INT3] =3D "HEX_EVENT_INT3", + [HEX_EVENT_INT4] =3D "HEX_EVENT_INT4", + [HEX_EVENT_INT5] =3D "HEX_EVENT_INT5", + [HEX_EVENT_INT6] =3D "HEX_EVENT_INT6", + [HEX_EVENT_INT7] =3D "HEX_EVENT_INT7", + [HEX_EVENT_INT8] =3D "HEX_EVENT_INT8", + [HEX_EVENT_INT9] =3D "HEX_EVENT_INT9", + [HEX_EVENT_INTA] =3D "HEX_EVENT_INTA", + [HEX_EVENT_INTB] =3D "HEX_EVENT_INTB", + [HEX_EVENT_INTC] =3D "HEX_EVENT_INTC", + [HEX_EVENT_INTD] =3D "HEX_EVENT_INTD", + [HEX_EVENT_INTE] =3D "HEX_EVENT_INTE", + [HEX_EVENT_INTF] =3D "HEX_EVENT_INTF" +}; + +void hexagon_cpu_do_interrupt(CPUState *cs) + +{ + CPUHexagonState *env =3D cpu_env(cs); + uint32_t ssr; + + BQL_LOCK_GUARD(); + + qemu_log_mask(CPU_LOG_INT, + "\t%s: event 0x%02x:%s, cause 0x%" PRIx32 "(%" PRIu32 ")= \n", + __func__, (unsigned)cs->exception_index, + event_name[cs->exception_index], env->cause_code, + env->cause_code); + + env->llsc_addr =3D ~0; + + ssr =3D env->t_sreg[HEX_SREG_SSR]; + if (GET_SSR_FIELD(SSR_EX, ssr) =3D=3D 1) { + HexagonCPU *cpu =3D env_archcpu(env); + if (cpu->globalregs) { + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_DIAG, + env->cause_code, env->threadId); + } + env->cause_code =3D HEX_CAUSE_DOUBLE_EXCEPT; + cs->exception_index =3D HEX_EVENT_PRECISE; + } + + switch (cs->exception_index) { + case HEX_EVENT_TRAP0: + if (env->cause_code =3D=3D 0) { + qemu_log_mask(LOG_UNIMP, + "trap0 is unhandled, no semihosting available\n"= ); + } + + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 4, cs->exception_index); + break; + + case HEX_EVENT_TRAP1: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 4, cs->exception_index); + break; + + case HEX_EVENT_TLB_MISS_X: + switch (env->cause_code) { + case HEX_CAUSE_TLBMISSX_CAUSE_NORMAL: + case HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE: + qemu_log_mask(CPU_LOG_MMU, + "TLB miss EX exception (0x%02" PRIx32 ") caught:= " + "Cause code (0x%" PRIx32 ") " + "TID =3D 0x%" PRIx32 ", PC =3D 0x%" PRIx32 + ", BADVA =3D 0x%" PRIx32 "\n", + (uint32_t)cs->exception_index, + env->cause_code, env->threadId, + env->gpr[HEX_REG_PC], + env->t_sreg[HEX_SREG_BADVA]); + + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + break; + + default: + cpu_abort(cs, + "1:Hexagon exception %" PRId32 "/0x%02" PRIx32 ": " + "Unknown cause code %" PRIu32 "/0x%" PRIx32 "\n", + (uint32_t)cs->exception_index, + (uint32_t)cs->exception_index, + env->cause_code, + env->cause_code); + break; + } + break; + + case HEX_EVENT_TLB_MISS_RW: + switch (env->cause_code) { + case HEX_CAUSE_TLBMISSRW_CAUSE_READ: + case HEX_CAUSE_TLBMISSRW_CAUSE_WRITE: + qemu_log_mask(CPU_LOG_MMU, + "TLB miss RW exception (0x%02" PRIx32 ") caught:= " + "Cause code (0x%" PRIx32 ") " + "TID =3D 0x%" PRIx32 ", PC =3D 0x%" PRIx32 + ", BADVA =3D 0x%" PRIx32 "\n", + (uint32_t)cs->exception_index, + env->cause_code, env->threadId, + env->gpr[HEX_REG_PC], + env->t_sreg[HEX_SREG_BADVA]); + + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + /* env->sreg[HEX_SREG_BADVA] is set when the exception is rais= ed */ + break; + + default: + cpu_abort(cs, + "2:Hexagon exception %" PRId32 "/0x%02" PRIx32 ": " + "Unknown cause code %" PRIu32 "/0x%" PRIx32 "\n", + (uint32_t)cs->exception_index, + (uint32_t)cs->exception_index, + env->cause_code, + env->cause_code); + break; + } + break; + + case HEX_EVENT_FPTRAP: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + break; + + case HEX_EVENT_DEBUG: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + qemu_log_mask(LOG_UNIMP, "single-step exception is not handled\n"); + break; + + case HEX_EVENT_PRECISE: + switch (env->cause_code) { + case HEX_CAUSE_FETCH_NO_XPAGE: + case HEX_CAUSE_FETCH_NO_UPAGE: + case HEX_CAUSE_PRIV_NO_READ: + case HEX_CAUSE_PRIV_NO_UREAD: + case HEX_CAUSE_PRIV_NO_WRITE: + case HEX_CAUSE_PRIV_NO_UWRITE: + case HEX_CAUSE_MISALIGNED_LOAD: + case HEX_CAUSE_MISALIGNED_STORE: + case HEX_CAUSE_PC_NOT_ALIGNED: + qemu_log_mask(CPU_LOG_MMU, + "MMU permission exception (0x%02" PRIx32 ") caug= ht: " + "Cause code (0x%" PRIx32 ") " + "TID =3D 0x%" PRIx32 ", PC =3D 0x%" PRIx32 + ", BADVA =3D 0x%" PRIx32 "\n", + (uint32_t)cs->exception_index, + env->cause_code, env->threadId, + env->gpr[HEX_REG_PC], + env->t_sreg[HEX_SREG_BADVA]); + + + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + /* env->sreg[HEX_SREG_BADVA] is set when the exception is rais= ed */ + break; + + case HEX_CAUSE_DOUBLE_EXCEPT: + case HEX_CAUSE_PRIV_USER_NO_SINSN: + case HEX_CAUSE_PRIV_USER_NO_GINSN: + case HEX_CAUSE_INVALID_OPCODE: + case HEX_CAUSE_NO_COPROC_ENABLE: + case HEX_CAUSE_NO_COPROC2_ENABLE: + case HEX_CAUSE_UNSUPPORTED_HVX_64B: + case HEX_CAUSE_REG_WRITE_CONFLICT: + case HEX_CAUSE_VWCTRL_WINDOW_MISS: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + break; + + case HEX_CAUSE_COPROC_LDST: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + break; + + case HEX_CAUSE_STACK_LIMIT: + hexagon_ssr_set_cause(env, env->cause_code); + set_addresses(env, 0, cs->exception_index); + break; + + default: + cpu_abort(cs, + "3:Hexagon exception %" PRId32 "/0x%02" PRIx32 ": " + "Unknown cause code %" PRIu32 "/0x%" PRIx32 "\n", + (uint32_t)cs->exception_index, + (uint32_t)cs->exception_index, + env->cause_code, + env->cause_code); + break; + } + break; + + case HEX_EVENT_IMPRECISE: + qemu_log_mask(LOG_UNIMP, + "Imprecise exception: this case is not yet handled"); + break; + + default: + qemu_log_mask(LOG_UNIMP, + "Hexagon Unsupported exception 0x%02x/0x%" PRIx32 "\n", + (unsigned)cs->exception_index, env->cause_code); + break; + } + + cs->exception_index =3D HEX_EVENT_NONE; +} + +void register_trap_exception(CPUHexagonState *env, int traptype, int imm, + uint32_t PC) +{ + CPUState *cs =3D env_cpu(env); + + cs->exception_index =3D (traptype =3D=3D 0) ? HEX_EVENT_TRAP0 : HEX_EV= ENT_TRAP1; + ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index); + + env->cause_code =3D imm; + env->gpr[HEX_REG_PC] =3D PC; + cpu_loop_exit(cs); +} --=20 2.34.1