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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781156299110158500 From: Brian Cain Co-authored-by: Taylor Simpson Co-authored-by: Sid Manning Co-authored-by: Michael Lambert Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- target/hexagon/cpu.h | 2 + target/hexagon/hex_interrupts.h | 15 ++ target/hexagon/cpu.c | 4 + target/hexagon/hex_interrupts.c | 371 ++++++++++++++++++++++++++++++++ 4 files changed, 392 insertions(+) create mode 100644 target/hexagon/hex_interrupts.h create mode 100644 target/hexagon/hex_interrupts.c diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index dbdc456d732..1b225e35abc 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -197,6 +197,8 @@ struct ArchCPU { bool short_circuit; #ifndef CONFIG_USER_ONLY HexagonTLBState *tlb; + uint32_t boot_addr; + HexagonGlobalRegState *globalregs; uint32_t htid; #endif }; diff --git a/target/hexagon/hex_interrupts.h b/target/hexagon/hex_interrupt= s.h new file mode 100644 index 00000000000..6b6f5403633 --- /dev/null +++ b/target/hexagon/hex_interrupts.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEX_INTERRUPTS_H +#define HEX_INTERRUPTS_H + +bool hex_check_interrupts(CPUHexagonState *env); +void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe); +void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe); +void hex_interrupt_update(CPUHexagonState *env); + +#endif diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 73aca0a4217..eb1f7049298 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -54,6 +54,9 @@ static const Property hexagon_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY DEFINE_PROP_LINK("tlb", HexagonCPU, tlb, TYPE_HEXAGON_TLB, HexagonTLBState *), + DEFINE_PROP_UINT32("exec-start-addr", HexagonCPU, boot_addr, 0xfffffff= f), + DEFINE_PROP_LINK("global-regs", HexagonCPU, globalregs, + TYPE_HEXAGON_GLOBALREG, HexagonGlobalRegState *), DEFINE_PROP_UINT32("htid", HexagonCPU, htid, 0), #endif DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), @@ -336,6 +339,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) =20 env->t_sreg[HEX_SREG_HTID] =3D cpu->htid; env->threadId =3D cpu->htid; + env->gpr[HEX_REG_PC] =3D cpu->boot_addr; #endif env->cause_code =3D HEX_EVENT_NONE; } diff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupt= s.c new file mode 100644 index 00000000000..3534481da24 --- /dev/null +++ b/target/hexagon/hex_interrupts.c @@ -0,0 +1,371 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "cpu_helper.h" +#include "exec/cpu-interrupt.h" +#include "hex_interrupts.h" +#include "macros.h" +#include "sys_macros.h" +#include "system/cpus.h" +#include "hw/hexagon/hexagon_globalreg.h" + +static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num); + +static bool get_syscfg_gie(CPUHexagonState *env) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t syscfg =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG, + env->threadId); + return GET_SYSCFG_FIELD(SYSCFG_GIE, syscfg); +} + +static bool get_ssr_ex(CPUHexagonState *env) +{ + uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; + return GET_SSR_FIELD(SSR_EX, ssr); +} + +static bool get_ssr_ie(CPUHexagonState *env) +{ + uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; + return GET_SSR_FIELD(SSR_IE, ssr); +} + +/* Do these together so we only have to call hexagon_modify_ssr once */ +static void set_ssr_ex_cause(CPUHexagonState *env, int ex, uint32_t cause) +{ + uint32_t old, new; + + old =3D env->t_sreg[HEX_SREG_SSR]; + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_EX, ex); + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CAUSE, cause); + new =3D env->t_sreg[HEX_SREG_SSR]; + hexagon_modify_ssr(env, new, old); +} + +static bool get_iad_bit(CPUHexagonState *env, int int_num) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + uint32_t iad =3D GET_FIELD(IPENDAD_IAD, ipendad); + return extract32(iad, int_num, 1); +} + +static void set_iad_bit(CPUHexagonState *env, int int_num, int val) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + uint32_t iad =3D GET_FIELD(IPENDAD_IAD, ipendad); + iad =3D deposit32(iad, int_num, 1, val); + fSET_FIELD(ipendad, IPENDAD_IAD, iad); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); +} + +static uint32_t get_ipend(CPUHexagonState *env) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + return GET_FIELD(IPENDAD_IPEND, ipendad); +} + +static inline bool get_ipend_bit(CPUHexagonState *env, int int_num) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + return extract32(ipend, int_num, 1); +} + +static void clear_ipend(CPUHexagonState *env, uint32_t mask) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + ipend &=3D ~mask; + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); +} + +static void set_ipend(CPUHexagonState *env, uint32_t mask) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + ipend |=3D mask; + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); +} + +static void set_ipend_bit(CPUHexagonState *env, int int_num, int val) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ipendad =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD, + env->threadId); + uint32_t ipend =3D GET_FIELD(IPENDAD_IPEND, ipendad); + ipend =3D deposit32(ipend, int_num, 1, val); + fSET_FIELD(ipendad, IPENDAD_IPEND, ipend); + hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD, + ipendad, env->threadId); +} + +static bool get_imask_bit(CPUHexagonState *env, int int_num) +{ + uint32_t imask =3D env->t_sreg[HEX_SREG_IMASK]; + return extract32(imask, int_num, 1); +} + +static uint32_t get_prio(CPUHexagonState *env) +{ + uint32_t stid =3D env->t_sreg[HEX_SREG_STID]; + return extract32(stid, reg_field_info[STID_PRIO].offset, + reg_field_info[STID_PRIO].width); +} + +static void set_elr(CPUHexagonState *env, uint32_t val) +{ + env->t_sreg[HEX_SREG_ELR] =3D val; +} + +static bool get_schedcfgen(CPUHexagonState *env) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t schedcfg =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SCHEDCFG, + env->threadId); + return extract32(schedcfg, reg_field_info[SCHEDCFG_EN].offset, + reg_field_info[SCHEDCFG_EN].width); +} + +static bool is_lowest_prio(CPUHexagonState *env, int int_num) +{ + uint32_t my_prio =3D get_prio(env); + CPUState *cs; + + CPU_FOREACH(cs) { + CPUHexagonState *hex_env =3D cpu_env(cs); + if (!hex_is_qualified_for_int(hex_env, int_num)) { + continue; + } + + /* Note that lower values indicate *higher* priority */ + if (my_prio < get_prio(hex_env)) { + return false; + } + } + return true; +} + +static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num) +{ + bool syscfg_gie =3D get_syscfg_gie(env); + bool iad =3D get_iad_bit(env, int_num); + bool ssr_ie =3D get_ssr_ie(env); + bool ssr_ex =3D get_ssr_ex(env); + bool imask =3D get_imask_bit(env, int_num); + + return syscfg_gie && !iad && ssr_ie && !ssr_ex && !imask; +} + +static void clear_pending_locks(CPUHexagonState *env) +{ + g_assert(bql_locked()); + if (env->k0_lock_state =3D=3D HEX_LOCK_WAITING) { + env->k0_lock_state =3D HEX_LOCK_UNLOCKED; + } + if (env->tlb_lock_state =3D=3D HEX_LOCK_WAITING) { + env->tlb_lock_state =3D HEX_LOCK_UNLOCKED; + } +} + +static bool should_not_exec(CPUHexagonState *env) +{ + return (get_exe_mode(env) =3D=3D HEX_EXE_MODE_WAIT); +} + +static void restore_state(CPUHexagonState *env, bool int_accepted) +{ + CPUState *cs =3D env_cpu(env); + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI); + if (!int_accepted && should_not_exec(env)) { + cpu_interrupt(cs, CPU_INTERRUPT_HALT); + } +} + +static void hex_accept_int(CPUHexagonState *env, int int_num) +{ + CPUState *cs =3D env_cpu(env); + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t evb =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_EVB, + env->threadId); + const int exe_mode =3D get_exe_mode(env); + const bool in_wait_mode =3D exe_mode =3D=3D HEX_EXE_MODE_WAIT; + + set_ipend_bit(env, int_num, 0); + set_iad_bit(env, int_num, 1); + set_ssr_ex_cause(env, 1, HEX_CAUSE_INT0 | int_num); + cs->exception_index =3D HEX_EVENT_INT0 + int_num; + env->cause_code =3D HEX_EVENT_INT0 + int_num; + clear_pending_locks(env); + if (in_wait_mode) { + qemu_log_mask(CPU_LOG_INT, + "%s: thread " TARGET_FMT_ld " resuming, exiting WAIT mode\n", + __func__, env->threadId); + set_elr(env, env->wait_next_pc); + clear_wait_mode(env); + cs->halted =3D false; + } else if (env->k0_lock_state =3D=3D HEX_LOCK_WAITING) { + g_assert_not_reached(); + } else { + set_elr(env, env->gpr[HEX_REG_PC]); + } + env->gpr[HEX_REG_PC] =3D evb | (cs->exception_index << 2); + if (get_ipend(env) =3D=3D 0) { + restore_state(env, true); + } +} + + +bool hex_check_interrupts(CPUHexagonState *env) +{ + CPUState *cs =3D env_cpu(env); + bool int_handled =3D false; + bool ssr_ex =3D get_ssr_ex(env); + int max_ints =3D 32; + bool schedcfgen; + + /* Early exit if nothing pending */ + if (get_ipend(env) =3D=3D 0) { + restore_state(env, false); + return false; + } + + BQL_LOCK_GUARD(); + /* Only check priorities when schedcfgen is set */ + schedcfgen =3D get_schedcfgen(env); + for (int i =3D 0; i < max_ints; i++) { + if (!get_iad_bit(env, i) && get_ipend_bit(env, i)) { + bool syscfg_gie, iad, ssr_ie, imask; + + qemu_log_mask(CPU_LOG_INT, + "%s: thread[" TARGET_FMT_ld "] " + "pc =3D 0x" TARGET_FMT_lx + " found int %d\n", + __func__, env->threadId, + env->gpr[HEX_REG_PC], i); + if (hex_is_qualified_for_int(env, i) && + (!schedcfgen || is_lowest_prio(env, i))) { + qemu_log_mask(CPU_LOG_INT, + "%s: thread[" TARGET_FMT_ld "] int %d handle= d_\n", + __func__, env->threadId, i); + hex_accept_int(env, i); + int_handled =3D true; + break; + } + syscfg_gie =3D get_syscfg_gie(env); + iad =3D get_iad_bit(env, i); + ssr_ie =3D get_ssr_ie(env); + imask =3D get_imask_bit(env, i); + + qemu_log_mask(CPU_LOG_INT, + "%s: thread[" TARGET_FMT_ld "] " + "int %d not handled, qualified: %d, " + "schedcfg_en: %d, low prio %d\n", + __func__, env->threadId, i, + hex_is_qualified_for_int(env, i), schedcfgen, + is_lowest_prio(env, i)); + + qemu_log_mask(CPU_LOG_INT, + "%s: thread[" TARGET_FMT_ld "] " + "int %d not handled, GIE %d, iad %d, " + "SSR:IE %d, SSR:EX: %d, imask bit %d\n", + __func__, env->threadId, i, syscfg_gie, iad, ssr= _ie, + ssr_ex, imask); + } + } + + /* + * If we didn't handle the interrupt and it wasn't + * because we were in EX state, then we won't be able + * to execute the interrupt on this CPU unless something + * changes in the CPU state. Clear the interrupt_request bits + * while preserving the IPEND bits, and we can re-assert the + * interrupt_request bit(s) when we execute one of those instructions. + */ + if (!int_handled && !ssr_ex) { + restore_state(env, int_handled); + } else if (int_handled) { + assert(!cs->halted); + } + + return int_handled; +} + +void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe) +{ + if (mask =3D=3D 0) { + return; + } + + /* + * Notify all CPUs that the interrupt has happened + */ + BQL_LOCK_GUARD(); + clear_ipend(env, mask); + hex_interrupt_update(env); +} + +void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t ty= pe) +{ + g_assert(bql_locked()); + if (mask =3D=3D 0) { + return; + } + + /* + * Notify all CPUs that the interrupt has happened + */ + set_ipend(env, mask); + hex_interrupt_update(env); +} + +void hex_interrupt_update(CPUHexagonState *env) +{ + CPUState *cs; + + g_assert(bql_locked()); + if (get_ipend(env) !=3D 0) { + CPU_FOREACH(cs) { + CPUHexagonState *hex_env =3D cpu_env(cs); + const int exe_mode =3D get_exe_mode(hex_env); + if (exe_mode !=3D HEX_EXE_MODE_OFF) { + cpu_interrupt(cs, CPU_INTERRUPT_SWI); + cpu_resume(cs); + } + } + } +} --=20 2.34.1