From nobody Sun Jul 26 14:10:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781155889; cv=none; d=zohomail.com; s=zohoarc; b=VttIr6lut7+cuTFndgcYMEKWBdNGq/vYJdJEw9JBIcgkfNqpr9EEgkUyuQykYPZOuSWMOMUNP9ahEvDBLNInoFEba4QgLMnd6qoyac8zwOiHEJr1QSJJzmjoiL7sYuMlQ2gV6kw6A46H90RUc2smoiw7+tcQye86flMuQQvei1Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781155889; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dY/1s85TBUfEZ6DKxNXbQLtO9YNnO553PDpX0fAztOM=; b=etPBjD0YAfV4zQaCza2vDbCFHxWNhmYqnhgN6um8pMMWbHXV11Wb4WmPYM9Pk0WlaUPPDL/Yxq17HzmGiMly7kjeOWpgymI1vNCnkZNGUNPPe4aLEBU3PhYF7WTzxUmh3zFhLr3rltQ8BMw4FpPq5s1IYoPrmbiAkc4RDLD67Ko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781155889091604.8965165759286; Wed, 10 Jun 2026 22:31:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXXzb-0008E8-1K; Thu, 11 Jun 2026 01:30:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXXzP-00083B-Gd for qemu-devel@nongnu.org; Thu, 11 Jun 2026 01:30:05 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXXzN-00011E-Ev for qemu-devel@nongnu.org; Thu, 11 Jun 2026 01:30:03 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65B5GgZN3816384 for ; Thu, 11 Jun 2026 05:29:50 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4eqe6u1rry-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 11 Jun 2026 05:29:50 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-304dd917645so9074778eec.1 for ; Wed, 10 Jun 2026 22:29:49 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30806e8a402sm880475eec.17.2026.06.10.22.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 22:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= dY/1s85TBUfEZ6DKxNXbQLtO9YNnO553PDpX0fAztOM=; b=A4EqFZWb8OExvyGo 3nT1yARnKAFtJnftEG3pHFXqRIMLfksUSKN1Nj31GN7HDY5O4e3MxhV2NMt0S61e eQrnJNBZTb5cxJMoo0J+sMrDI/Y/XCAkalPZhka9WZLqGcEfiacw45gpNReKCfCf AWhg3c5lo7ImvcXlk+bp+QGZDCt3in56/D5svjzdliAzPzdwd0KaBx9z5Hmknyam e9QKdAGlHXIgPV82gp+3EAvpAMt305t01nkMacNEwl1/Y6APbi/IoguaVe7Kaiq+ gwd+zr/QkgS4BaabLOdqJCR0P9Z4qlHCXrZwk5FTy0bLjrw9hZdN7fZkLZwIlXNX RpCBbQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1781155789; x=1781760589; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dY/1s85TBUfEZ6DKxNXbQLtO9YNnO553PDpX0fAztOM=; b=KlnrF3XD/oMhREPeZ6Q0bv7DTeZB1V8o+7t9++vpPeTkKw6YXPuLh6R702TDm1QVKA j6vOH/kTFXs+0TkAMZe8dY8UGvbMnEx7Bw2uQ/hNqcAy1lIFC9+jpR9hc2qcz2Y+VA1u r7ywn14IHEdWJ6cMXtcQKpjYA5y4f79OOLeN3p+NBIAh/RmYXBRHl4izpp/gTopSiMRt ViItfSJA5nau9LJqnhZUNnnlk7dvPIJoSyGgbcJI2uv5kCEXBYX1EqKN8CAMzQ0j61vZ Lc1cZuBQdKFdWdDzpe+i7dKJdvWl2BvoWOSkvCGXA0cC0MUV66xEtFjwdskHeH624Y8/ M1Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781155789; x=1781760589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dY/1s85TBUfEZ6DKxNXbQLtO9YNnO553PDpX0fAztOM=; b=dyyFfBH0Fkxn1kbfb50xdZ8hwrzwMH4KWR8x6g4nHZOmr9Q17FpWa6IsBEQkFgbED/ IOuJKFixP/xOg3OAD8m7K7q8ouaTSYCYadsAukHjTUdCPLVfsgXH5DVW689USnI5B+7J IWYaCnpSNnVnjJBZg0/F2C1wTyd8i+7Z3YmZl0yTR11jmMWGlipUrLKo0Gwff9RAn2DW RhmDg3aMtYUsfivxwsutQbkr8UTEJKQ5LYIZOJLZW2n70D/x4ZHIZHLTWM6mjyPS5SDb QFFuc4qbsHdrFp5XHaXHojFYMWE3tSwDaOym7ZMlI7zBVrutx/kzAWewhwsersdVSyJ0 BzjA== X-Gm-Message-State: AOJu0Yyaz3otEwHJmsJwOXg1elwn8ak6MzDqWPagKjKvXxzRGL3LzfZ3 EKybXfmxDDwLszUaMirlnSYbs2Y+lW44506WP7mNO8S525HAAhQN0iQcrFYEqyyklX6MgP5q6JS IUA7E4Y4k7AalrSstFFEOCHFGPTw/ONZ4bIYjtQxU+0VwDfh/xd+jZB6gBUf4Lu5uTQ== X-Gm-Gg: Acq92OGRbGLDOpzvjd0DQ6UhUTcp7IgmSPpo9jlwWK2TjusDezCN+F0VconohNmwr2s v1ld+13niPODAQdI2TAaMNiyLdckrr0PdCXbUvOxUX+7GPlOvA48Hf46yYr+fVyycVSdyV071Cp GdGQZYW9GCXdXtUoZJChnPABocmoTajYGlqUpjEI90ZcIlacvv4U61HUxioridfkSWTaSW7aWqW lX8qH/7AZaqAa9UMfb0Jm0CDUsXfnI1+hu35e7QfbOGUcQ938HBYeRlhgAoA4gwGLHf5hdMNaCf 76Ga1NPrmHrEIjHBLXj/vOtG4YrFzR/WW39zVH4Z1Uxy2qeMGnjUT1uCdkDKZZ1/1UtNKF+i9hz 1IPp4+VSCiAeockE4BFd7c8Hx7B8cceVsXlwRETpG+H2R2ER2CqnQfqQ1lKVV8pN2LAPDsyJ3/H bD1Roc X-Received: by 2002:a05:7300:534f:b0:2ed:e12:376b with SMTP id 5a478bee46e88-30804bbcfe8mr1133347eec.33.1781155789293; Wed, 10 Jun 2026 22:29:49 -0700 (PDT) X-Received: by 2002:a05:7300:534f:b0:2ed:e12:376b with SMTP id 5a478bee46e88-30804bbcfe8mr1133308eec.33.1781155788779; Wed, 10 Jun 2026 22:29:48 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, matheus.bernardino@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, ltaylorsimpson@gmail.com, philmd@mailo.org, philmd@oss.qualcomm.com Subject: [PATCH v8] target/hexagon: Add implementation of cycle counters Date: Wed, 10 Jun 2026 22:28:51 -0700 Message-Id: <20260611052857.3911981-31-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260611052857.3911981-1-brian.cain@oss.qualcomm.com> References: <20260611052857.3911981-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: S6bfbCHjeR1cj4Giha9JZaItEAOrn4hV X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDA1MSBTYWx0ZWRfX6eItxGTaRvlF U1SBrRgDhzaSwLBxAuHyjVkZHnUe5uu++436qQvm/A4LS7WRbPWYRx8UbVW5ALUUVu6uYI7jOmO 8DTzYtqHGutnvU4RKRpDzetidjlSFl8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDA1MSBTYWx0ZWRfXwVyuGCuZM2w9 1ofFKgqlcs0K+4GkeGaJfd244lXfO763I181lyFW6qrveB9/JsAUSSCcmLOfAx0auTIOq0L6CQm GBXOpcvm2S2W+M3GsRraAp3jYBS+LlIaSQmtW7KLpSonpqfK5fUv5FUD3jXOTVDyY94s8g82uzJ 5/jZHET12xUrzUZnZz1VksaiPxmHa0i7IAO7H1at50+oTL3+sQ2KbRqVwuWbcWgCiHWIcvY9LVH cSs5p2YrCCGaLwX51yMcmznRK6DZVrqsW8+PzjyTKnO3T1H0DwiUIw2aDLyP2zkkWNmDvDpJCzR WGi0kr500514du3GInDngP1K1wHm1VIjb5qQv4e+5mGBiREjAz51lFvMk8r3YP2es5EBJL6nGk/ Ydm0i0dCTKm674NrY7u/09g0WmycZDiWmn13jtFTebraeZxW5Sn52iLJv+qerhs5sDkg6OMgPXD 0BA7ozaj7dYZAsvoB7Q== X-Authority-Analysis: v=2.4 cv=F5lnsKhN c=1 sm=1 tr=0 ts=6a2a47ce cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=Bw4caLd0n_0OF-yX4NUA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: S6bfbCHjeR1cj4Giha9JZaItEAOrn4hV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_01,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110051 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781155890953158500 Add cycle counting infrastructure for system emulation: - PCYCLE_ENABLED TB flag to gate cycle counting - gen_pcycle_counters() to emit cycle count increments - Real implementations replacing pcycle stubs in cpu_helper.c - hex_cycle_count TCG global for t_cycle_count - pcycle_enabled context field in DisasContext All pcycle code is guarded by #ifndef CONFIG_USER_ONLY. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/translate.h | 3 +++ target/hexagon/cpu.c | 4 ++++ target/hexagon/cpu_helper.c | 14 +++++++++++--- target/hexagon/translate.c | 26 ++++++++++++++++++++++++++ 5 files changed, 45 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2540458b370..ddf6da78c18 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -164,6 +164,7 @@ struct ArchCPU { #include "cpu_bits.h" =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) +FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 57767acf002..208cf141e7e 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -85,6 +85,9 @@ typedef struct DisasContext { TCGv new_pred_value[NUM_PREGS]; TCGv branch_taken; TCGv dczero_addr; + bool pcycle_enabled; + bool pkt_ends_tb; + uint32_t num_cycles; } DisasContext; =20 bool is_gather_store_insn(DisasContext *ctx); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a08083ea290..0773ef8fe79 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -268,6 +268,10 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState= *cs) hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } =20 +#ifndef CONFIG_USER_ONLY + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); +#endif + return (TCGTBCPUState){ .pc =3D pc, .flags =3D hex_flags }; } =20 diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index a2b486f4bb5..bb991a671e8 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -33,17 +33,25 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_e= nv, int index) =20 uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env) { - g_assert_not_reached(); + uint64_t total =3D 0; + CPUState *cs; + + g_assert(bql_locked()); + CPU_FOREACH(cs) { + CPUHexagonState *thread_env =3D cpu_env(cs); + total +=3D thread_env->t_cycle_count; + } + return total; } =20 uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env) { - g_assert_not_reached(); + return (uint32_t)(hexagon_get_sys_pcycle_count(env) >> 32); } =20 uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) { - g_assert_not_reached(); + return (uint32_t)(hexagon_get_sys_pcycle_count(env)); } =20 void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 97849ab861a..ed96d9a66b3 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -61,6 +61,9 @@ TCGv_i64 hex_store_val64[STORES_MAX]; TCGv hex_llsc_addr; TCGv hex_llsc_val; TCGv_i64 hex_llsc_val_i64; +#ifndef CONFIG_USER_ONLY +TCGv_i64 hex_cycle_count; +#endif TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; @@ -128,6 +131,15 @@ static void gen_exception_raw(int excp) gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); } =20 +#ifndef CONFIG_USER_ONLY +static void gen_pcycle_counters(DisasContext *ctx) +{ + if (ctx->pcycle_enabled) { + tcg_gen_addi_i64(hex_cycle_count, hex_cycle_count, ctx->num_cycles= ); + } +} +#endif + static void gen_exec_counters(DisasContext *ctx) { tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], @@ -136,6 +148,9 @@ static void gen_exec_counters(DisasContext *ctx) hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); +#ifndef CONFIG_USER_ONLY + gen_pcycle_counters(ctx); +#endif } =20 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -810,6 +825,8 @@ static void gen_commit_hvx(DisasContext *ctx) } } =20 +#define PCYCLES_PER_PACKET 1 + static void update_exec_counters(DisasContext *ctx) { int num_real_insns =3D 0; @@ -829,6 +846,7 @@ static void update_exec_counters(DisasContext *ctx) ctx->num_packets++; ctx->num_insns +=3D num_real_insns; ctx->num_hvx_insns +=3D num_hvx_insns; + ctx->num_cycles +=3D PCYCLES_PER_PACKET; } =20 static void gen_commit_packet(DisasContext *ctx) @@ -978,6 +996,10 @@ static void hexagon_tr_init_disas_context(DisasContext= Base *dcbase, ctx->is_tight_loop =3D FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); ctx->short_circuit =3D hex_cpu->short_circuit; ctx->hex_def =3D HEXAGON_CPU_GET_CLASS(hex_cpu)->hex_def; +#ifndef CONFIG_USER_ONLY + ctx->num_cycles =3D 0; + ctx->pcycle_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED= ); +#endif } =20 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -1121,6 +1143,10 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, llsc_val), "llsc_val"); hex_llsc_val_i64 =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); +#ifndef CONFIG_USER_ONLY + hex_cycle_count =3D tcg_global_mem_new_i64(tcg_env, + offsetof(CPUHexagonState, t_cycle_count), "t_cycle_count"); +#endif for (i =3D 0; i < STORES_MAX; i++) { snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); hex_store_addr[i] =3D tcg_global_mem_new(tcg_env, --=20 2.34.1