From nobody Sun Jul 26 14:10:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1781155795; cv=none; d=zohomail.com; s=zohoarc; b=OFeDpwanPMK21S135Mk3CalCYJo7FMHhtuocmiD39pk1L7fY2hFDF9J7raIK6kNditp+8VTFalGmBkn1LJw45ATNl8pEw94tzgaPHb+QVMbla2F5aigM6l8OJpaHbrJ7IadqRSuVsZbtVFAaLscqDDm4IHTsodWP8EnW+0BRvS8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781155795; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Vi9fcqshA75At9JeJ4JbMZRf/mNwm9Rc4amynzMh450=; b=d/eBM8LcrtsA0vmnmTaEAE02V6kBHZ6Q7M60+03eH5ZUOhYY1zs+pqN4Y15c9pqMtCvYAvfjUIssH3VFWd7EoY6RtMKlFHmLdeOuNNjWDLsj/fK/nrr/7/ir6C9XP/jNFkpJGu45W+leSeZH7kSN3sicYN6zmpV9C7QpoBZCPmI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781155795229344.26571318345157; Wed, 10 Jun 2026 22:29:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wXXyf-0007ei-GO; Thu, 11 Jun 2026 01:29:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXXyb-0007dX-DS for qemu-devel@nongnu.org; Thu, 11 Jun 2026 01:29:13 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wXXyZ-0000iM-1K for qemu-devel@nongnu.org; Thu, 11 Jun 2026 01:29:13 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65B5GQRH3817120 for ; Thu, 11 Jun 2026 05:29:07 GMT Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4eqe6usrp0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 11 Jun 2026 05:29:06 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-304ea42b025so338036eec.0 for ; Wed, 10 Jun 2026 22:29:06 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30806e8a402sm880475eec.17.2026.06.10.22.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 22:29:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Vi9fcqshA75At9JeJ4JbMZRf/mNwm9Rc4amynzMh450=; b=NB3SYBMad5vab5Ny aAqc69xM4WQZKIoUgdC6JAZ99wDJChqciIMyONothFIpLC+Fe4bzgscet5wvO29r q3J5ygwvjaMsJfIS5EgXAxy1y7DukB4++5Lh9iSQktgSRHN7HL4ka/7Bg+ByG74H LtlbVYly6HrrlowfZl7TdLEZglpUEmMg7kuNzmJC/qkctszaCnuh7gOoIUGVoYRP vl0pnndD6kO7E+w8iqLR2r1OoMldckpma77Q/RqseO3Rv/sjR6vTs8k5EVR7J8oT GgvcT1Q4A/QMmReiuYCnSxIpNUesnPATkn6TO5xhPF8IZYgwmuZSbXgJC1rYV7RY bo5+Mw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1781155746; x=1781760546; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vi9fcqshA75At9JeJ4JbMZRf/mNwm9Rc4amynzMh450=; b=dFL40jpjxMOCfNGwh5GYPoWLOCtB4125z0Ert2+enlLHtgkqIWgtRcHUuDirmEVKOz 4NZGW308tEpdfkgUHq5PE2yRosRreR/FBp9CYrTjRd6S7EEHY1aCdW8KWZlUyDfJtsRa /rK1gPXZcmf5Jd6565U/lVm3UNC16CNPiyYYvfJb18CKqj1J2y/G7hsTgdHG80ec2FDk SN1Uaxu62bnQT7MgGqlSJe/S/qBC4PeoVnKvWYnC4CbCIGnmRqKPGkQbFdeBiunPSMN3 pQW7cYW0Ky/WWHXcEjrMxOoVroJ3mZqkiI2dbLaWJ+TWdf46Xnn6AEQ1h4yBxDKVKF1T PpMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781155746; x=1781760546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Vi9fcqshA75At9JeJ4JbMZRf/mNwm9Rc4amynzMh450=; b=Gz8+ejm85ztSVdTouAZqmHvKR7O1e/XVtJnzRlnX0I1yNTgfgpenBZt+XwNpgyXUxJ F0ScoQ5YwGAy67R3JbXfa2ZiU+srEXVxXlZOf4UK8LLzS2TZmSG82L4UkdXyxJni1akS /68/Me/YLk/PSJ2rZIbVCsBeYHPCM7G0HPQTTr9WhNcY64TRwxLhUUqL7Y7LueA/tt/i F0bfS++7xtQJuKAKjvmKjn5GdQPq1DGYp9p6bO0nBAamXv8DXkUKCP43N7AH81ZZqWMD ZUPOpJIF2AKiLaSfUhjgkJZhVhxD+wvoI2SCjBQJqWPw0/T+c7MrMEUx6Oc895kU9Cgc 7m9w== X-Gm-Message-State: AOJu0YyWon3mzd80umyF8AwWFUh5Q9NIv3zZEzY/l2XQwQigFmTggbVD m+26P9WSwMenss1i3pkRESaJGMJWCeAlVFwv91DgXmf+SI7yUdVOSSO28vUg5UvCB5E1jWybsdc XGF65AzSMGYe+RT8xRjeepB2X1VtyoA+epllySIVyTjydv0TT+1X6BHnz0SoBiNYTAA== X-Gm-Gg: Acq92OH2pu/NFHHaFW3xX2N2e8fQ0VWTVtN9SzJ6fS7ZDAvbzrY4ektPcAP8EtESPMj 9IRYyw7X3TfPwfcPR3IfPBIbKs/t7xj6IHdTCWt+0kR0Vo7/iv/LO/Oygjo10is3w3dlIMnbgTD Z4UnJTMCBhw9toeQ17zFOkAF/DmKxEbjRj4bUutdUlbgs1Urd/FYpaQRpPLYe9JKlr73dy3lD3o RM/NIieDAaIC9m2l45ZlWsDQz/ctv5yrnpYjPLRnGZ0jJrwM6P7GdD3gBx1FEmsfOS4TzKo5M0t ZJMK3Hw678rH/BAj5aN8TNg35OLTHcsc5cT8b2NQaTZo5hI4BGTyenqebz7/VY44cQeo9GCMsdF A79Fv/yrL4pAg89zE7wGVZYG65pwk+iEFVez0IFJSLIItlyR+Vpecphnw4nEv0uIOhRLWTaRUEf hMpWSA X-Received: by 2002:a05:7300:7495:b0:304:70d0:4f03 with SMTP id 5a478bee46e88-30805de5ec6mr814880eec.6.1781155745773; Wed, 10 Jun 2026 22:29:05 -0700 (PDT) X-Received: by 2002:a05:7300:7495:b0:304:70d0:4f03 with SMTP id 5a478bee46e88-30805de5ec6mr814852eec.6.1781155745057; Wed, 10 Jun 2026 22:29:05 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, matheus.bernardino@oss.qualcomm.com, pierrick.bouvier@oss.qualcomm.com, ltaylorsimpson@gmail.com, philmd@mailo.org, philmd@oss.qualcomm.com, Brian Cain Subject: [PATCH v8] docs: Add hexagon sysemu docs Date: Wed, 10 Jun 2026 22:28:22 -0700 Message-Id: <20260611052857.3911981-2-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260611052857.3911981-1-brian.cain@oss.qualcomm.com> References: <20260611052857.3911981-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=FJ8rAeos c=1 sm=1 tr=0 ts=6a2a47a2 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=NEAV23lmAAAA:8 a=COk6AnOGAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=fXLLft-zuLPsu7fQao0A:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDA1MSBTYWx0ZWRfX6jsGpGFWpuJn lmN41hMpZXi1MqMa3eWTCCmnXQzu4ts0kXQV5ybU7TRnfTYNR6aMlyOod0sN0SgMb0mnSveGoWq nIxXEuwc8mNSTjYl0/E3pnBv/jv2iZY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDA1MSBTYWx0ZWRfX4EGOufZgTPJQ 0198dXMwDCKzulDPGa4poHL+pV6A1X1SoITySMPjLukXUVijlRwsugTITZnxW60sETLE0le9N/i I38MeIU1mo47TbRvWavwc0Xf1ymtcdh3hLd0VdXqJVjAnpJSAm/0i6SWP/rkD/jnM7DXvwu47tY HUgBDV9h8C27TM8ylbKdqmSO3mKg6/95zgny3IInt1SvdVAJ3ycXZnrSXcDnWW+CT9bfgrNS43R BR0XRPXaS/igQ72VPQCyt0b/EAvFd8jDhsbbv1c4fRB/PwP4wp1FP9H2gI+VSY1276MQxTTgYhg 3SE5ufF2/j6cObZs7u4MJcgbiwJxIRRDtJksdiCD9PSSqAaG0U4Bu9IPnnDSOcaW9pC2PQtMAGy hZ17DAS+hP2UCL8+P05XQ1PBpCSCWY9tU7ZDUlwL8acVUGdVJtHbUV6I4jtoLob1D9sDRZYxyis xr32ZFudwJ3ebANOV1g== X-Proofpoint-GUID: kL83WW1IKkmpAzHdhAeZTaDrfxWVxld3 X-Proofpoint-ORIG-GUID: kL83WW1IKkmpAzHdhAeZTaDrfxWVxld3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_01,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 spamscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110051 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781155797125158500 From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- MAINTAINERS | 3 + docs/devel/hexagon-sys.rst | 112 +++++++++++++++++++++++++++++++++ docs/devel/index-internals.rst | 1 + docs/system/hexagon/cdsp.rst | 12 ++++ docs/system/target-hexagon.rst | 102 ++++++++++++++++++++++++++++++ docs/system/targets.rst | 1 + 6 files changed, 231 insertions(+) create mode 100644 docs/devel/hexagon-sys.rst create mode 100644 docs/system/hexagon/cdsp.rst create mode 100644 docs/system/target-hexagon.rst diff --git a/MAINTAINERS b/MAINTAINERS index 4ff33eb630b..a2b04177be0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -259,6 +259,9 @@ F: disas/hexagon.c F: configs/targets/hexagon-linux-user/default.mak F: tests/docker/dockerfiles/debian-hexagon-cross.docker F: gdbstub/gdb-xml/hexagon*.xml +F: docs/system/target-hexagon.rst +F: docs/system/hexagon/ +F: docs/devel/hexagon-sys.rst T: git https://github.com/qualcomm/qemu.git hex-next =20 Hexagon idef-parser diff --git a/docs/devel/hexagon-sys.rst b/docs/devel/hexagon-sys.rst new file mode 100644 index 00000000000..92ebc32dce8 --- /dev/null +++ b/docs/devel/hexagon-sys.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +.. _Hexagon-System-arch: + +Hexagon System Architecture +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D + +The hexagon architecture has some unique elements which are described here. + +Interrupts +---------- +When interrupts arrive at a Hexagon DSP core, they are priority-steered to +be handled by an eligible hardware thread with the lowest priority. + +Memory +------ +Each hardware thread has an ``SSR.ASID`` field that contains its Address +Space Identifier. This value is catenated with a 32-bit virtual address - +the MMU can then resolve this extended virtual address to a physical addre= ss. + +TLBs +---- +The format of a TLB entry is shown below. + +.. note:: + The Small Core DSPs have a different TLB format which is not yet + supported. + +.. admonition:: Diagram + + .. code:: text + + 6 5 4 3 + 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + |v|g|x|A|A| | | + |a|l|P|1|0| ASID | Virtual Page | + |l|b| | | | | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + 3 2 1 0 + 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | | | | | | | | + |x|w|r|u|Cacheab| Physical Page |S| + | | | | | | | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +* ASID: the address-space identifier +* A1, A0: the behavior of these cache line attributes are not modeled by Q= EMU. +* xP: the extra-physical bit is the most significant physical address bit. +* S: the S bit and the LSBs of the physical page indicate the page size +* val: this is the 'valid' bit, when set it indicates that page matching + should consider this entry. + +.. list-table:: Page sizes + :widths: 25 25 50 + :header-rows: 1 + + * - S-bit + - Phys page LSBs + - Page size + * - 1 + - N/A + - 4kb + * - 0 + - 0b1 + - 16kb + * - 0 + - 0b10 + - 64kb + * - 0 + - 0b100 + - 256kb + * - 0 + - 0b1000 + - 1MB + * - 0 + - 0b10000 + - 4MB + * - 0 + - 0b100000 + - 16MB + +* glb: if the global bit is set, the ASID is not considered when matching + TLBs. +* Cacheab: the cacheability attributes of TLBs are not modeled, these bits + are ignored. +* RWX: read-, write-, execute-, enable bits. Indicates if user programs + are permitted to read/write/execute the given page. +* U: indicates if user programs can access this page. + +Scheduler +--------- +The Hexagon system architecture has a feature to assist the guest OS +task scheduler. The guest OS can enable this feature by setting +``SCHEDCFG.EN``. The ``BESTWAIT`` register is programmed by the guest OS +to indicate the priority of the highest priority task waiting to run on a +hardware thread. The reschedule interrupt is triggered when any hardware +thread's priority in ``STID.PRIO`` is worse than the ``BESTWAIT``. When +it is triggered, the ``BESTWAIT.PRIO`` value is reset to 0x1ff. + +HVX Coprocessor +--------------- +The Supervisor Status Register field ``SSR.XA`` binds a DSP hardware thread +to one of the eight possible HVX contexts. The guest OS is responsible for +managing this resource. + +.. seealso:: + + ``target/hexagon/README`` in the QEMU source tree for more info about = Hexagon. diff --git a/docs/devel/index-internals.rst b/docs/devel/index-internals.rst index 7a0678cbdd3..0471db80645 100644 --- a/docs/devel/index-internals.rst +++ b/docs/devel/index-internals.rst @@ -14,6 +14,7 @@ Details about QEMU's various subsystems including how to = add features to them. block-coroutine-wrapper clocks ebpf_rss + hexagon-sys migration/index multi-process reset diff --git a/docs/system/hexagon/cdsp.rst b/docs/system/hexagon/cdsp.rst new file mode 100644 index 00000000000..237529273cb --- /dev/null +++ b/docs/system/hexagon/cdsp.rst @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Compute DSP +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +A Hexagon CDSP is designed as a computation offload device for an SoC. The +``V66G_1024`` machine contains: + +* L2VIC interrupt controller +* QTimer timer device + +This machine will support any Hexagon CPU, but will default to ``v66``. diff --git a/docs/system/target-hexagon.rst b/docs/system/target-hexagon.rst new file mode 100644 index 00000000000..5f7084a6a08 --- /dev/null +++ b/docs/system/target-hexagon.rst @@ -0,0 +1,102 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +.. _Hexagon-System-emulator: + +Hexagon System emulator +----------------------- + +Use the ``qemu-system-hexagon`` executable to simulate a 32-bit Hexagon +machine. + +Hexagon Machines +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Hexagon DSPs are suited to various functions and generally appear in a +"DSP subsystem" of a larger system-on-chip (SoC). + +Hexagon DSPs are often included in a subsystem that looks like the diagram +below. Instructions are loaded into DDR before the DSP is brought out of +reset and the first instructions are fetched from DDR via the EVB/reset ve= ctor. + +In a real system, a TBU/SMMU would normally arbitrate AXI accesses but +we don't have a need to model that for QEMU. + +Hexagon DSP cores use simultaneous multithreading (SMT) with as many as 8 +hardware threads. + +.. admonition:: Diagram + + .. code:: text + + AHB (local) bus AXI (global) bus + =E2=94=82 =E2=94=82 + =E2=94=82 =E2=94=82 + =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82 =E2=94=8C=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 = =E2=94=82 + =E2=94=82 L2VIC =E2=94=9C=E2=94=80=E2=94=80=E2=94=A4 =E2=94= =82 =E2=94=82 =E2=94=82 + =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=BC=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=BA = =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=A4 + =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=96=B2=E2= =94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 Hexagon DSP = =E2=94=82 =E2=94=82 + =E2=94=82 =E2=94=82 =E2=94=82 =E2= =94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=90 + =E2=94=82 =E2=94=82 =E2=94=82 N threads =E2= =94=82 =E2=94=82 =E2=94=82 DDR =E2=94=82 + =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=A4 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 + =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=B4=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=A4 =E2=94=82 + =E2=94=82QTimer =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 + =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 + =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 + =E2=94=82 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90=E2= =94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 + =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82 =E2=94=82 =E2=94=82 HVX xM =E2=94=82=E2= =94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 + =E2=94=82QDSP6SS=E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 = =E2=94=82 =E2=94=82 =E2=94=82=E2=94=98 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 + =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 = =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=98 + =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=82 + =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 + =E2=94=82 CSR =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 + =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=98 =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 + =E2=94=82 =E2=94=82 TCM =E2=94=82 =E2=94=82 VTC= M =E2=94=82 + =E2=94=82 =E2=94=82 =E2=94=82 =E2= =94=82 + =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 + =E2=94=82 =E2=94=82 + =E2=94=82 =E2=94=82 + =E2=94=82 =E2=94=82 + =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =98 + +Components +---------- +Other than l2vic and HVX, the components below are not implemented in QEMU. + +* L2VIC: the L2 vectored interrupt controller. Supports 1024 input + interrupts, edge- or level-triggered. The core ISA has system registers + ``VID``, ``VID1`` which read through to the L2VIC device. +* QTimer: ARMSSE-based programmable timer device. Its interrupts are + wired to the L2VIC. System registers ``TIMER``, ``UTIMER`` read + through to the QTimer device. +* QDSP6SS: DSP subsystem features, accessible to the entire SoC, including + DSP NMI, watchdog, reset, etc. +* CSR: Configuration/Status Registers. +* TCM: DSP-exclusive tightly-coupled memory. This memory can be used for + DSPs when isolated from DDR and in some bootstrapping modes. +* VTCM: DSP-exclusive vector tightly-coupled memory. This memory is acces= sed + by some HVX instructions. +* HVX: the vector coprocessor supports 64 and 128-byte vector registers. + 64-byte mode is not implemented in QEMU. + + +Bootstrapping +------------- +Hexagon systems do not generally have access to a block device. So, for +QEMU the typical use case involves loading a binary or ELF file into memory +and executing from the indicated start address:: + + $ qemu-system-hexagon -kernel ./prog -append 'arg1 arg2' + +Semihosting +----------- +Hexagon supports a semihosting interface similar to other architectures'. +The ``trap0`` instruction can activate these semihosting calls so that the +guest software can access the host console and filesystem. Semihosting +is not yet implemented in QEMU hexagon. + + +Hexagon Features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +.. toctree:: + hexagon/cdsp + diff --git a/docs/system/targets.rst b/docs/system/targets.rst index 5b12858b216..5ebdd0f7fea 100644 --- a/docs/system/targets.rst +++ b/docs/system/targets.rst @@ -30,3 +30,4 @@ Contents: target-sparc64 target-i386 target-xtensa + target-hexagon --=20 2.34.1