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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781155808491158500 From: Brian Cain Also: add nop TCG overrides for break, unpause, fetchbo; add TCG override for dczeroa_nt (non-temporal variant of dczeroa). break: this hardware breakpoint instruction is used with the in-silicon debugger feature, this is not modeled. unpause: this instruction is used to resume hardware threads that are stalled by pause instructions. pause is modeled as a nop, or in RR mode as an EXCP_YIELD. This instruction is safe to ignore. Since prefetch functions are not modeled, fetchbo is safe to ignore. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/gen_tcg.h | 9 ++ target/hexagon/macros.h | 25 +++- target/hexagon/sys_macros.h | 237 ++++++++++++++++++++++++++++++++++++ target/hexagon/op_helper.c | 4 + 4 files changed, 274 insertions(+), 1 deletion(-) create mode 100644 target/hexagon/sys_macros.h diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 0159e5c2d5f..4a58ead877b 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -488,6 +488,7 @@ =20 /* dczeroa clears the 32 byte cache line at the address given */ #define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE +#define fGEN_TCG_Y2_dczeroa_nt(SHORTCODE) SHORTCODE =20 /* In linux-user mode, these are not modelled, suppress compiler warning */ #define fGEN_TCG_Y2_dcinva(SHORTCODE) \ @@ -1112,6 +1113,9 @@ RdV, tcg_constant_tl(0)); \ } while (0) =20 +#define fGEN_TCG_Y2_break(SHORTCODE) +#define fGEN_TCG_J2_unpause(SHORTCODE) + #define fGEN_TCG_J2_pause(SHORTCODE) \ do { \ uiV =3D uiV; \ @@ -1321,6 +1325,11 @@ RsV =3D RsV; \ uiV =3D uiV; \ } while (0) +#define fGEN_TCG_Y2_dcfetchbo_nt(SHORTCODE) \ + do { \ + RsV =3D RsV; \ + uiV =3D uiV; \ + } while (0) =20 #define fGEN_TCG_L2_loadw_aq(SHORTCODE) SHORTCODE #define fGEN_TCG_L4_loadd_aq(SHORTCODE) SHORTCODE diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index eebfe1e5ed9..38a43647dd9 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -631,8 +631,18 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val= , int shift) #define fCONSTLL(A) A##LL #define fECHO(A) (A) =20 -#define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0) +#ifdef CONFIG_USER_ONLY +#define fTRAP(TRAPTYPE, IMM) \ + do { \ + hexagon_raise_exception_err(env, HEX_EVENT_TRAP0, PC); \ + } while (0) +#endif + +#define fDO_TRACE(SREG) +#define fBREAK() +#define fUNPAUSE() #define fPAUSE(IMM) +#define fDCFETCH(REG) =20 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \ ((VAL) << reg_field_info[FIELD].offset) @@ -654,5 +664,18 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val= , int shift) #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM= , \ STRBITNUM) /* Nothing */ =20 +#ifdef CONFIG_USER_ONLY +/* + * This macro can only be true in guest mode. + * In user mode, the 4 VIRTINSN's can't be reached + */ +#define fTRAP1_VIRTINSN(IMM) (false) +#define fVIRTINSN_SPSWAP(IMM, REG) g_assert_not_reached() +#define fVIRTINSN_GETIE(IMM, REG) g_assert_not_reached() +#define fVIRTINSN_SETIE(IMM, REG) g_assert_not_reached() +#define fVIRTINSN_RTE(IMM, REG) g_assert_not_reached() +#endif + +#define fPREDUSE_TIMING() =20 #endif diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h new file mode 100644 index 00000000000..f497d55bb81 --- /dev/null +++ b/target/hexagon/sys_macros.h @@ -0,0 +1,237 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_SYS_MACROS_H +#define HEXAGON_SYS_MACROS_H + +/* + * Macro definitions for Hexagon system mode + */ + +#ifndef CONFIG_USER_ONLY + +#ifdef QEMU_GENERATE +#define GET_SSR_FIELD(RES, FIELD) \ + GET_FIELD(RES, FIELD, hex_t_sreg[HEX_SREG_SSR]) +#else + +#define GET_SSR_FIELD(FIELD, REGIN) \ + (uint32_t)GET_FIELD(FIELD, REGIN) +#define GET_SYSCFG_FIELD(FIELD, REGIN) \ + (uint32_t)GET_FIELD(FIELD, REGIN) +#define SET_SYSTEM_FIELD(ENV, REG, FIELD, VAL) \ + do { \ + HexagonCPU *_sf_cpu =3D env_archcpu(ENV); \ + uint32_t regval; \ + if ((REG) < HEX_SREG_GLB_START) { \ + regval =3D (ENV)->t_sreg[(REG)]; \ + } else { \ + regval =3D _sf_cpu->globalregs ? \ + hexagon_globalreg_read(_sf_cpu->globalregs, (REG), \ + (ENV)->threadId) : 0; \ + } \ + fINSERT_BITS(regval, reg_field_info[FIELD].width, \ + reg_field_info[FIELD].offset, (VAL)); \ + if ((REG) < HEX_SREG_GLB_START) { \ + (ENV)->t_sreg[(REG)] =3D regval; \ + } else if (_sf_cpu->globalregs) { \ + hexagon_globalreg_write(_sf_cpu->globalregs, (REG), regval, \ + (ENV)->threadId); \ + } \ + } while (0) +#define SET_SSR_FIELD(ENV, FIELD, VAL) \ + SET_SYSTEM_FIELD(ENV, HEX_SREG_SSR, FIELD, VAL) +#define SET_SYSCFG_FIELD(ENV, FIELD, VAL) \ + SET_SYSTEM_FIELD(ENV, HEX_SREG_SYSCFG, FIELD, VAL) + +#define CCR_FIELD_SET(ENV, FIELD) \ + (!!GET_FIELD(FIELD, (ENV)->t_sreg[HEX_SREG_CCR])) + +/* + * Direct-to-guest is not implemented yet, continuing would cause unexpect= ed + * behavior, so we abort. + */ +#define ASSERT_DIRECT_TO_GUEST_UNSET(ENV, EXCP) \ + do { \ + switch (EXCP) { \ + case HEX_EVENT_TRAP0: \ + g_assert(!CCR_FIELD_SET(ENV, CCR_GTE)); \ + break; \ + case HEX_EVENT_IMPRECISE: \ + case HEX_EVENT_PRECISE: \ + case HEX_EVENT_FPTRAP: \ + g_assert(!CCR_FIELD_SET(ENV, CCR_GEE)); \ + break; \ + default: \ + if ((EXCP) >=3D HEX_EVENT_INT0) { \ + g_assert(!CCR_FIELD_SET(ENV, CCR_GIE)); \ + } \ + break; \ + } \ + } while (0) +#endif + +#define fREAD_ELR() (env->t_sreg[HEX_SREG_ELR]) + +#define fLOAD_PHYS(NUM, SIZE, SIGN, SRC1, SRC2, DST) { \ + const uintptr_t rs =3D ((unsigned long)(unsigned)(SRC1)) & 0x7ff; \ + const uintptr_t rt =3D ((unsigned long)(unsigned)(SRC2)) << 11; \ + const uintptr_t addr =3D rs + rt; \ + cpu_physical_memory_read(addr, &DST, sizeof(uint32_t)); \ +} + +#define fPOW2_HELP_ROUNDUP(VAL) \ + ((VAL) | \ + ((VAL) >> 1) | \ + ((VAL) >> 2) | \ + ((VAL) >> 4) | \ + ((VAL) >> 8) | \ + ((VAL) >> 16)) +#define fPOW2_ROUNDUP(VAL) (fPOW2_HELP_ROUNDUP((VAL) - 1) + 1) + +#define fTRAP(TRAPTYPE, IMM) \ + register_trap_exception(env, TRAPTYPE, IMM, PC) + +#define fVIRTINSN_SPSWAP(IMM, REG) +#define fVIRTINSN_GETIE(IMM, REG) { REG =3D 0xdeafbeef; } +#define fVIRTINSN_SETIE(IMM, REG) +#define fVIRTINSN_RTE(IMM, REG) +#define fGRE_ENABLED() \ + GET_FIELD(CCR_GRE, env->t_sreg[HEX_SREG_CCR]) +#define fTRAP1_VIRTINSN(IMM) \ + (fGRE_ENABLED() && \ + (((IMM) =3D=3D 1) || ((IMM) =3D=3D 3) || ((IMM) =3D=3D 4) || ((IMM= ) =3D=3D 6))) + +/* Not modeled in qemu */ + +#define MARK_LATE_PRED_WRITE(RNUM) +#define fICINVIDX(REG) +#define fICKILL() +#define fDCKILL() +#define fL2KILL() +#define fL2UNLOCK() +#define fL2CLEAN() +#define fL2CLEANINV() +#define fL2CLEANPA(REG) +#define fL2CLEANINVPA(REG) +#define fL2CLEANINVIDX(REG) +#define fL2CLEANIDX(REG) +#define fL2INVIDX(REG) +#define fL2TAGR(INDEX, DST, DSTREG) +#define fL2UNLOCKA(VA) ((void) VA) +#define fL2TAGW(INDEX, PART2) +#define fDCCLEANIDX(REG) +#define fDCCLEANINVIDX(REG) + +/* Always succeed: */ +#define fL2LOCKA(EA, PDV, PDN) ((void) EA, PDV =3D 0xFF) +#define fCLEAR_RTE_EX() \ + do { \ + uint32_t tmp =3D env->t_sreg[HEX_SREG_SSR]; \ + fINSERT_BITS(tmp, reg_field_info[SSR_EX].width, \ + reg_field_info[SSR_EX].offset, 0); \ + log_sreg_write(env, HEX_SREG_SSR, tmp, slot); \ + } while (0) + +#define fDCINVIDX(REG) +#define fDCINVA(REG) do { REG =3D REG; } while (0) /* Nothing to do in qem= u */ + +#define fTLB_IDXMASK(INDEX) \ + ((INDEX) & (fPOW2_ROUNDUP( \ + fCAST4u(hexagon_tlb_get_num_entries(env_archcpu(env)->tlb))) - 1)) + +#define fTLB_NONPOW2WRAP(INDEX) \ + (((INDEX) >=3D hexagon_tlb_get_num_entries(env_archcpu(env)->tlb)) ? \ + ((INDEX) - hexagon_tlb_get_num_entries(env_archcpu(env)->tlb)) : \ + (INDEX)) + + +#define fTLBW(INDEX, VALUE) \ + hex_tlbw(env, (INDEX), (VALUE)) +#define fTLBW_EXTENDED(INDEX, VALUE) \ + hex_tlbw(env, (INDEX), (VALUE)) +#define fTLB_ENTRY_OVERLAP(VALUE) \ + (hex_tlb_check_overlap(env, VALUE, -1) !=3D -2) +#define fTLB_ENTRY_OVERLAP_IDX(VALUE) \ + hex_tlb_check_overlap(env, VALUE, -1) +#define fTLBR(INDEX) \ + hexagon_tlb_read(env_archcpu(env)->tlb, \ + fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX))) +#define fTLBR_EXTENDED(INDEX) \ + hexagon_tlb_read(env_archcpu(env)->tlb, \ + fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX))) +#define fTLBP(TLBHI) \ + hex_tlb_lookup(env, ((TLBHI) >> 12), ((TLBHI) << 12)) +#define iic_flush_cache(p) + +#define fIN_DEBUG_MODE(TNUM) ({ \ + HexagonCPU *_cpu =3D env_archcpu(env); \ + uint32_t _isdbst =3D _cpu->globalregs ? \ + hexagon_globalreg_read(_cpu->globalregs, \ + HEX_SREG_ISDBST, env->threadId) : 0; \ + (GET_FIELD(ISDBST_DEBUGMODE, _isdbst) \ + & (0x1 << (TNUM))) !=3D 0; }) + +#define fIN_DEBUG_MODE_NO_ISDB(TNUM) false +#define fIN_DEBUG_MODE_WARN(TNUM) false + +#ifdef QEMU_GENERATE + +/* + * Read tags back as zero for now: + * + * tag value in RD[31:10] for 32k, RD[31:9] for 16k + */ +#define fICTAGR(RS, RD, RD2) \ + do { \ + RD =3D ctx->zero; \ + } while (0) +#define fICTAGW(RS, RD) +#define fICDATAR(RS, RD) \ + do { \ + RD =3D ctx->zero; \ + } while (0) +#define fICDATAW(RS, RD) + +#define fDCTAGW(RS, RT) +/* tag: RD[23:0], state: RD[30:29] */ +#define fDCTAGR(INDEX, DST, DST_REG_NUM) \ + do { \ + DST =3D ctx->zero; \ + } while (0) +#else + +/* + * Read tags back as zero for now: + * + * tag value in RD[31:10] for 32k, RD[31:9] for 16k + */ +#define fICTAGR(RS, RD, RD2) \ + do { \ + RD =3D 0x00; \ + } while (0) +#define fICTAGW(RS, RD) +#define fICDATAR(RS, RD) \ + do { \ + RD =3D 0x00; \ + } while (0) +#define fICDATAW(RS, RD) + +#define fDCTAGW(RS, RT) +/* tag: RD[23:0], state: RD[30:29] */ +#define fDCTAGR(INDEX, DST, DST_REG_NUM) \ + do { \ + DST =3D 0; \ + } while (0) +#endif + +#else +#define ASSERT_DIRECT_TO_GUEST_UNSET(ENV, EXCP) do { } while (0) +#endif + +#define NUM_TLB_REGS(x) (hexagon_tlb_get_num_entries(env_archcpu(env)->tlb= )) + +#endif diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 368391bb846..53898db815b 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "internal.h" #include "macros.h" +#include "sys_macros.h" #include "arch.h" #include "hex_arch_types.h" #include "fma_emu.h" @@ -31,6 +32,9 @@ #include "mmvec/macros.h" #include "op_helper.h" #include "translate.h" +#ifndef CONFIG_USER_ONLY +#include "hexswi.h" +#endif =20 #define SF_BIAS 127 #define SF_MANTBITS 23 --=20 2.34.1