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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781127801861154100 Content-Type: text/plain; charset="utf-8" Add documentation for the new riscv-server-ref board. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Chao Liu --- docs/system/riscv/riscv-server-ref.rst | 62 ++++++++++++++++++++++++++ docs/system/target-riscv.rst | 1 + 2 files changed, 63 insertions(+) create mode 100644 docs/system/riscv/riscv-server-ref.rst diff --git a/docs/system/riscv/riscv-server-ref.rst b/docs/system/riscv/ris= cv-server-ref.rst new file mode 100644 index 0000000000..0573b4e07c --- /dev/null +++ b/docs/system/riscv/riscv-server-ref.rst @@ -0,0 +1,62 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +RISC-V Server Platform Reference board (``riscv-server-ref``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The RISC-V Server Platform specification `spec`_ defines a standardized +set of hardware and software capabilities that portable system software, +such as OS and hypervisors, can rely on being present in a RISC-V server +platform. This machine aims to emulate this specification, providing +an environment for firmware/OS development and testing. + +`spec`_ is version 1.0 at the introduction of this board. New spec versio= ns +might trigger a revision of the emulation itself, which will strive to alw= ays +match the latest version available. In case the emulation changes aren't +backwards compatible we'll introduce a versioning scheme, probably via +a machine property, to allow older SW to run with older spec versions. + +The main features included in the riscv-server-ref board are: + +* IOMMU platform device (riscv-iommu-sys) +* AIA +* PCIe AHCI +* PCIe NIC +* No virtio mmio bus +* No fw_cfg device +* No ACPI table +* Minimal device tree nodes + +There are multiple ways of using this reference board. The spec compliant= way +is using an EDK2 image and a TPM device. The board was tested with the TPM +device ``tpm-tis`` that uses the external ``swtpm`` emulator. More info o= n how +to use this device can be found in `tpm`_. + +To use this board coupled with the tpm-tis device, first start the ``swtpm= `` +process in a shell (the ``log`` parameter is optional): + +.. code-block:: bash + + $ mkdir /tmp/mytpm1 + $ swtpm socket --tpmstate dir=3D/tmp/mytpm1 \ + --ctrl type=3Dunixio,path=3D/tmp/mytpm1/swtpm-sock \ + --tpm2 \ + --log level=3D20 + +And then start QEMU with: + +.. code-block:: bash + + qemu-system-riscv64 -M riscv-server-ref \ + -bios fw_dynamic.bin \ + -kernel EDK2.fd \ + -drive file=3Dnvme_disk.ext2,format=3Draw,id=3Dhd0,if=3Dnone \ + -device ahci,id=3Dahci \ + -device ide-hd,drive=3Dhd0,bus=3Dahci.0 \ + -chardev socket,id=3Dchrtpm,path=3D/tmp/mytpm1/swtpm-sock \ + -tpmdev emulator,id=3Dtpm0,chardev=3Dchrtpm \ + -device tpm-tis-device,tpmdev=3Dtpm0 \ + -nographic + + +.. _spec: https://github.com/riscv-non-isa/riscv-server-platform +.. _tpm: https://qemu-project.gitlab.io/qemu/specs/tpm.html diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index afd86ca2ba..b2aeb39a8e 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -73,6 +73,7 @@ undocumented; you can get a complete list by running riscv/sifive_u riscv/virt riscv/xiangshan-kunminghu + riscv/riscv-server-ref =20 RISC-V CPU firmware ------------------- --=20 2.43.0