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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781124970349154100 Content-Type: text/plain; charset="utf-8" The debug trigger facility consists of a set of arrays: tdata1-3, cpu_breakpoint, cpu_watchpoint and itrigger_timer. All of them are static allocated with RV_MAX_TRIGGERS (2). This means that all RISC-V cpus will have 2 triggers per hart. The RISC-V Server Ref demands at least 11 triggers per hart, and several CPUs in the wild works with 4+ triggers. We need more flexibility, ergo we need to parametrize the amount of triggers and make it configurable. Before doing that we need to handle a situation faced in a previous attempt [1]. We were unable to set the tdataN array length in vmstate_debug, meaning that we would always migrate RV_MAX_TRIGGERS regardless of the actual amount of triggers in play. To fix that we need to change the tdata arrays from static to dynamic, allowing us to use VMSTATE_VARRAY_UINT32(). This also means that, in contrast with [1], we have the opportunity to turn all trigger arrays into dynamic allocation and reduce the amount of stuff being carried by CPURISCVState, or in other words, we can carry just what we're using instead of a static max value. All the forementioned trigger facility arrays are now dynamic. They are allocated during realize time in riscv_trigger_realize(), and their size is expressed by env->num_triggers. All relevant code is changed to use env->num_triggers instead of the RV_MAX_TRIGGERS to loop through each array. This will make it easier for the next patch to parametrize env->num_triggers. [1] https://lore.kernel.org/qemu-devel/94c772b0-5231-40e4-9cab-6ac39b9e4d45= @oss.qualcomm.com/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 18 ++++++++++++------ target/riscv/csr.c | 2 +- target/riscv/debug.c | 31 +++++++++++++++++++++++-------- target/riscv/machine.c | 12 +++++++++--- 4 files changed, 45 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c98652cd62..8345b9a207 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -467,12 +467,18 @@ struct CPUArchState { /* trigger module */ uint16_t mcontext; uint8_t trigger_cur; - uint64_t tdata1[RV_MAX_TRIGGERS]; - uint64_t tdata2[RV_MAX_TRIGGERS]; - uint64_t tdata3[RV_MAX_TRIGGERS]; - struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; - struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; - QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; + /* + * num_triggers is the length of tdata1, tdata2, tdata3, + * cpu_breakpoint, cpu_watchpoint and itrigger_timer + * arrays. + */ + uint32_t num_triggers; + uint64_t *tdata1; + uint64_t *tdata2; + uint64_t *tdata3; + struct CPUBreakpoint **cpu_breakpoint; + struct CPUWatchpoint **cpu_watchpoint; + QEMUTimer **itrigger_timer; int64_t last_icount; bool itrigger_enabled; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ec931a8c3d..82afad82db 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5436,7 +5436,7 @@ static RISCVException read_tdata(CPURISCVState *env, = int csrno, target_ulong *val) { /* return 0 in tdata1 to end the trigger enumeration */ - if (env->trigger_cur >=3D RV_MAX_TRIGGERS && csrno =3D=3D CSR_TDATA1) { + if (env->trigger_cur >=3D env->num_triggers && csrno =3D=3D CSR_TDATA1= ) { *val =3D 0; return RISCV_EXCP_NONE; } diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 30d39ee5cd..8b31efdbc6 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -172,7 +172,7 @@ target_ulong tselect_csr_read(CPURISCVState *env) =20 void tselect_csr_write(CPURISCVState *env, target_ulong val) { - if (val < RV_MAX_TRIGGERS) { + if (val < env->num_triggers) { env->trigger_cur =3D val; } } @@ -701,7 +701,7 @@ static bool check_itrigger_priv(CPURISCVState *env, int= index) bool riscv_itrigger_enabled(CPURISCVState *env) { int count; - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->num_triggers; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -721,7 +721,7 @@ bool riscv_itrigger_enabled(CPURISCVState *env) void helper_itrigger_match(CPURISCVState *env) { int count; - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->num_triggers; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -750,7 +750,7 @@ static void riscv_itrigger_update_count(CPURISCVState *= env) int64_t last_icount =3D env->last_icount, current_icount; current_icount =3D env->last_icount =3D icount_get_raw(); =20 - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->num_triggers; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -950,7 +950,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) int i; =20 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->num_triggers; i++) { trigger_type =3D get_trigger_type(env, i); =20 if (!trigger_common_match(env, trigger_type, i)) { @@ -996,7 +996,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) int flags; int i; =20 - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->num_triggers; i++) { trigger_type =3D get_trigger_type(env, i); =20 if (!trigger_common_match(env, trigger_type, i)) { @@ -1049,7 +1049,22 @@ void riscv_trigger_realize(CPURISCVState *env) { int i; =20 - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + /* + * Alloc env->tdata1/2/3, cpu_breakpoint, cpu_watchpoint and + * itrigger_timer dynamically. This is overkill now + * given that they could be static arrays with RV_MAX_TRIGGERS + * but we'll parametrize the trigger number later, i.e. the + * array length won't be static. + */ + env->num_triggers =3D RV_MAX_TRIGGERS; + env->tdata1 =3D g_new0(uint64_t, env->num_triggers); + env->tdata2 =3D g_new0(uint64_t, env->num_triggers); + env->tdata3 =3D g_new0(uint64_t, env->num_triggers); + env->cpu_breakpoint =3D g_new0(struct CPUBreakpoint *, env->num_trigge= rs); + env->cpu_watchpoint =3D g_new0(struct CPUWatchpoint *, env->num_trigge= rs); + env->itrigger_timer =3D g_new0(QEMUTimer *, env->num_triggers); + + for (i =3D 0; i < env->num_triggers; i++) { env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_itrigger_timer_cb, env= ); } @@ -1061,7 +1076,7 @@ void riscv_trigger_reset_hold(CPURISCVState *env) int i; =20 /* init to type 2 triggers */ - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->num_triggers; i++) { /* * type =3D TRIGGER_TYPE_AD_MATCH * dmode =3D 0 (both debug and M-mode can write tdata) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 6e70b145a5..b6b53a4840 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -247,9 +247,15 @@ static const VMStateDescription vmstate_debug =3D { .fields =3D (const VMStateField[]) { VMSTATE_UINT16(env.mcontext, RISCVCPU), VMSTATE_UINT8(env.trigger_cur, RISCVCPU), - VMSTATE_UINT64_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINT64_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINT64_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_VARRAY_UINT32(env.tdata1, RISCVCPU, + env.num_triggers, 0, + vmstate_info_uint64, uint64_t), + VMSTATE_VARRAY_UINT32(env.tdata2, RISCVCPU, + env.num_triggers, 0, + vmstate_info_uint64, uint64_t), + VMSTATE_VARRAY_UINT32(env.tdata3, RISCVCPU, + env.num_triggers, 0, + vmstate_info_uint64, uint64_t), VMSTATE_END_OF_LIST() } }; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781125009828158500 Content-Type: text/plain; charset="utf-8" All CPUs have the same amount of triggers: 2 triggers per hart, set via RV_MAX_TRIGGERS. This is not enough anymore: we'll have at least one future CPU that will demand more triggers per hart when implementing the RISC-V Server Ref Platform, requiring at least 11 triggers per hart. Parametrize the trigger amount using a new 'num_triggers' property. The default amount is kept at 2 for backwards compatibility. The new maximum is bumped to a generous 1024 triggers per hart, which hopefully will be enough for the foreseeable future. The property can be set in two ways: - a '.num_triggers' CPU definition flag, allowing CPUs to set a custom amount inside the CPU def in DEFINE_RISCV_CPU(); - a new 'num-triggers' user property. The user property has a higher priority than an existing '.num_triggers' CPU def setting. Assuming a hypothetical case where a CPU 'X' is defined with '.num_triggers =3D 8': - -cpu X,num-triggers=3D30 =3D> num_triggers set to 30 - -cpu X (...) =3D> num_triggers set to 8 For a CPU that doesn't set '.num_triggers': - -cpu rv64,num-triggers=3D30 =3D> num_triggers set to 30 - -cpu rv64 (...) =3D> num_triggers set to 2 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 11 +++++++++++ target/riscv/cpu.h | 19 ++++++++++++++++++- target/riscv/debug.c | 16 ++++++++-------- target/riscv/machine.c | 4 ++-- 4 files changed, 39 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c1b10cc7ef..eed7b0b76e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1154,6 +1154,11 @@ static void riscv_cpu_init(Object *obj) IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, "riscv.cpu.rnmi", RNMI_MAX); + + if (mcc->def->num_triggers) { + env->num_triggers =3D mcc->def->num_triggers; + } + #endif /* CONFIG_USER_ONLY */ =20 general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); @@ -2606,6 +2611,8 @@ static const Property riscv_cpu_properties[] =3D { DEFAULT_RNMI_IRQVEC), DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, DEFAULT_RNMI_EXCPVEC), + DEFINE_PROP_UINT32("num-triggers", RISCVCPU, env.num_triggers, + RV_DEFAULT_NUM_TRIGGERS), #endif =20 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), @@ -2749,6 +2756,10 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) { mcc->def->cfg.max_satp_mode =3D VM_1_10_SV32; } + + if (def->num_triggers) { + mcc->def->num_triggers =3D def->num_triggers; + } #endif } if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8345b9a207..726a79f03a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,7 +189,22 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implie= d_rules[]; #define RV_VLEN_MAX 1024 #define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 -#define RV_MAX_TRIGGERS 2 + +/* + * The Debug 1.0 spec allows a humongous amount of triggers. Section + * "Enumeration" says: "The above algorithm reads back tselect so that + * implementations which have 2^n triggers only need to implement n + * bits of tselect.". tselect can have up to XLEN bits, so the max + * theoretical RV_MAX_TRIGGERS value is 2^XLEN. + * + * Allowing 2^XLEN triggers per hart is silly so we'll set a max to a + * modest 1024 triggers, which is way more than what we see current + * hardware use (most chips uses 2-4 triggers per hart, RISC-V Server + * Ref requires at least 11). With a 1024 max per hart we'll be set + * for a long time ... hopefully. + */ +#define RV_MAX_TRIGGERS 1024 +#define RV_DEFAULT_NUM_TRIGGERS 2 =20 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) @@ -576,6 +591,8 @@ typedef struct RISCVCPUDef { RISCVCPUConfig cfg; bool bare; const RISCVCSR *custom_csrs; + /* This is just a setter for env->num_triggers. */ + uint32_t num_triggers; } RISCVCPUDef; =20 /** diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 8b31efdbc6..9578e3e913 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "cpu.h" #include "target/riscv/debug.h" #include "trace.h" @@ -1049,14 +1050,13 @@ void riscv_trigger_realize(CPURISCVState *env) { int i; =20 - /* - * Alloc env->tdata1/2/3, cpu_breakpoint, cpu_watchpoint and - * itrigger_timer dynamically. This is overkill now - * given that they could be static arrays with RV_MAX_TRIGGERS - * but we'll parametrize the trigger number later, i.e. the - * array length won't be static. - */ - env->num_triggers =3D RV_MAX_TRIGGERS; + if (env->num_triggers > RV_MAX_TRIGGERS) { + error_report( + "Invalid configuration: 'num-triggers' must be less than %= u", + RV_MAX_TRIGGERS); + exit(1); + } + env->tdata1 =3D g_new0(uint64_t, env->num_triggers); env->tdata2 =3D g_new0(uint64_t, env->num_triggers); env->tdata3 =3D g_new0(uint64_t, env->num_triggers); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b6b53a4840..ba96ceceef 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -240,8 +240,8 @@ static int debug_post_load(void *opaque, int version_id) =20 static const VMStateDescription vmstate_debug =3D { .name =3D "cpu/debug", - .version_id =3D 3, - .minimum_version_id =3D 3, + .version_id =3D 4, + .minimum_version_id =3D 4, .needed =3D debug_needed, .post_load =3D debug_post_load, .fields =3D (const VMStateField[]) { --=20 2.43.0