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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1781041226199154100 Content-Type: text/plain; charset="utf-8" All CPUs have the same amount of triggers: 2 triggers per hart, set via RV_MAX_TRIGGERS. This is not enough anymore: we'll have at least one future CPU that will demand more triggers per hart when implementing the RISC-V Server Ref Platform, requiring at least 11 triggers per hart. Parametrize the trigger amount using a new 'trigger_count' env property. The default amount is kept at 2. Set the new maximum to an educated guess of 128 triggers per hart (which is less than 2^XLEN theoretical maximum by the spec). All relevant callers (csr.c and debug.c) will now use env->trigger_count instead of RV_MAX_TRIGGERS. We're also adding two ways of setting the property: - a '.trigger_count' CPU definition flag, allowing CPUs to set a custom amount inside the CPU def in DEFINE_RISCV_CPU(); - a new 'trigger-count' user property. The user property has a higher priority than an existing '.trigger_count' CPU def setting. Assuming a hypotetical case where a CPU 'X' is defined with '.trigger_count =3D 8': - -cpu X,trigger-count=3D30 =3D> trigger_count set to 30 - -cpu X (...) =3D> trigger_count set to 8 For a CPU that doesn't set '.trigger_count': - -cpu rv64,trigger-count=3D30 =3D> trigger_count set to 30 - -cpu rv64 (...) =3D> trigger_count set to 2 Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 11 +++++++++++ target/riscv/cpu.h | 23 ++++++++++++++++++++++- target/riscv/csr.c | 2 +- target/riscv/debug.c | 16 ++++++++-------- target/riscv/machine.c | 4 ++-- target/riscv/tcg/tcg-cpu.c | 7 +++++++ 6 files changed, 51 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c1b10cc7ef..56dc9ad644 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1154,6 +1154,11 @@ static void riscv_cpu_init(Object *obj) IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, "riscv.cpu.rnmi", RNMI_MAX); + + if (mcc->def->trigger_count) { + env->trigger_count =3D mcc->def->trigger_count; + } + #endif /* CONFIG_USER_ONLY */ =20 general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); @@ -2606,6 +2611,8 @@ static const Property riscv_cpu_properties[] =3D { DEFAULT_RNMI_IRQVEC), DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, DEFAULT_RNMI_EXCPVEC), + DEFINE_PROP_UINT16("trigger-count", RISCVCPU, env.trigger_count, + RV_DEFAULT_TRIGGER_COUNT), #endif =20 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), @@ -2749,6 +2756,10 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) { mcc->def->cfg.max_satp_mode =3D VM_1_10_SV32; } + + if (def->trigger_count) { + mcc->def->trigger_count =3D def->trigger_count; + } #endif } if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c98652cd62..361f3cecf3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,7 +189,26 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implie= d_rules[]; #define RV_VLEN_MAX 1024 #define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 -#define RV_MAX_TRIGGERS 2 + +/* + * The Debug 1.0 spec allows a humongous amount of triggers. Section + * "Enumeration" says: "The above algorithm reads back tselect so that + * implementations which have 2^n triggers only need to implement n + * bits of tselect.". tselect can have up to XLEN bits, so the max + * theoretical RV_MAX_TRIGGERS value is 2^XLEN. + * + * Alas, we need to carry over migration state for all these folks, + * even if not utilized, so setting 2^XLEN isn't an option. + * + * We're setting a smaller default based on what we see current + * hardware use (most chips uses 2-4 triggers per hart, RISC-V + * Server Ref requires at least 11). + * + * 128 seems like a good amount for current and future usage without + * a lot of footprint on our side. + */ +#define RV_MAX_TRIGGERS 128 +#define RV_DEFAULT_TRIGGER_COUNT 2 =20 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) @@ -475,6 +494,7 @@ struct CPUArchState { QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; int64_t last_icount; bool itrigger_enabled; + uint16_t trigger_count; =20 /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(void *); @@ -570,6 +590,7 @@ typedef struct RISCVCPUDef { RISCVCPUConfig cfg; bool bare; const RISCVCSR *custom_csrs; + uint16_t trigger_count; } RISCVCPUDef; =20 /** diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ec931a8c3d..6aa4a321c7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5436,7 +5436,7 @@ static RISCVException read_tdata(CPURISCVState *env, = int csrno, target_ulong *val) { /* return 0 in tdata1 to end the trigger enumeration */ - if (env->trigger_cur >=3D RV_MAX_TRIGGERS && csrno =3D=3D CSR_TDATA1) { + if (env->trigger_cur >=3D env->trigger_count && csrno =3D=3D CSR_TDATA= 1) { *val =3D 0; return RISCV_EXCP_NONE; } diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 30d39ee5cd..78b84591b4 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -172,7 +172,7 @@ target_ulong tselect_csr_read(CPURISCVState *env) =20 void tselect_csr_write(CPURISCVState *env, target_ulong val) { - if (val < RV_MAX_TRIGGERS) { + if (val < env->trigger_count) { env->trigger_cur =3D val; } } @@ -701,7 +701,7 @@ static bool check_itrigger_priv(CPURISCVState *env, int= index) bool riscv_itrigger_enabled(CPURISCVState *env) { int count; - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->trigger_count; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -721,7 +721,7 @@ bool riscv_itrigger_enabled(CPURISCVState *env) void helper_itrigger_match(CPURISCVState *env) { int count; - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->trigger_count; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -750,7 +750,7 @@ static void riscv_itrigger_update_count(CPURISCVState *= env) int64_t last_icount =3D env->last_icount, current_icount; current_icount =3D env->last_icount =3D icount_get_raw(); =20 - for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (int i =3D 0; i < env->trigger_count; i++) { if (get_trigger_type(env, i) !=3D TRIGGER_TYPE_INST_CNT) { continue; } @@ -950,7 +950,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) int i; =20 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->trigger_count; i++) { trigger_type =3D get_trigger_type(env, i); =20 if (!trigger_common_match(env, trigger_type, i)) { @@ -996,7 +996,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) int flags; int i; =20 - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->trigger_count; i++) { trigger_type =3D get_trigger_type(env, i); =20 if (!trigger_common_match(env, trigger_type, i)) { @@ -1049,7 +1049,7 @@ void riscv_trigger_realize(CPURISCVState *env) { int i; =20 - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->trigger_count; i++) { env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_itrigger_timer_cb, env= ); } @@ -1061,7 +1061,7 @@ void riscv_trigger_reset_hold(CPURISCVState *env) int i; =20 /* init to type 2 triggers */ - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + for (i =3D 0; i < env->trigger_count; i++) { /* * type =3D TRIGGER_TYPE_AD_MATCH * dmode =3D 0 (both debug and M-mode can write tdata) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 6e70b145a5..a667c06b17 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -240,8 +240,8 @@ static int debug_post_load(void *opaque, int version_id) =20 static const VMStateDescription vmstate_debug =3D { .name =3D "cpu/debug", - .version_id =3D 3, - .minimum_version_id =3D 3, + .version_id =3D 4, + .minimum_version_id =3D 4, .needed =3D debug_needed, .post_load =3D debug_post_load, .fields =3D (const VMStateField[]) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b73e3e9dd4..9b657a7544 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1211,6 +1211,13 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, = Error **errp) riscv_pmu_timer_cb, cpu); } } + + if (env->trigger_count > RV_MAX_TRIGGERS) { + error_setg(errp, + "Invalid configuration: 'trigger-count' must be less than = %u", + RV_MAX_TRIGGERS); + return; + } #endif } =20 --=20 2.43.0