From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1781009836; cv=none; d=zohomail.com; s=zohoarc; b=BU4mkqHvbIx/w9ny6WxK5S717L4aokgZ/CK4EqzQjkrWoj2Y1p2UPeFxl+lS/9x5wgWLaueUcrI8i25Nnkw3cYINipjBj8/fTbH7/0Q1lCDBAYF4+G5giPXFWZBiQE7PNpkBQfntuGz40OZJX2yNkGE2AkrgEfB2KhgQNXd6fDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781009836; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TVQhRc8dDekoMA1OaYDeOudEU0aw2a7ljZsV7Lahev0=; b=lgs7Y8SQ8BUJUKEcoBe+ADM+lYauBE0BUDPaAbMkQs3NHfAO3E5x+XV6fjkEUyxzrCOiB92euvHtgdWKoxH6cCnwBGmCjfnG3UIU1HhTgRcvN1cvfSbWF1xeVpSO6Y4XaLIPAejr+sDFJCNBxpi+Hv3odzGZaEDvqpZfb20Eqgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1781009836554774.8064637835206; Tue, 9 Jun 2026 05:57:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wWw0y-0001EE-Bf; Tue, 09 Jun 2026 08:57:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wWtxN-0005vH-Db for qemu-devel@nongnu.org; Tue, 09 Jun 2026 06:45:17 -0400 Received: from mailout2.samsung.com ([203.254.224.25]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wWtxK-00051t-Hs for qemu-devel@nongnu.org; Tue, 09 Jun 2026 06:45:17 -0400 Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20260609104506epoutp02ba8931195556d140ab201886f9c73658~3Y8wlCJ2N2804728047epoutp02X for ; Tue, 9 Jun 2026 10:45:06 +0000 (GMT) Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20260609104504epcas5p1308772014546eb7371d7b142a4326203~3Y8vhycwn0554305543epcas5p16; Tue, 9 Jun 2026 10:45:04 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.88]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4gZQXc241xz6B9m6; Tue, 9 Jun 2026 10:45:04 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20260609104503epcas5p12628cd89d0ef9210c856d2518dc790cb~3Y8uSH2Fc0554305543epcas5p1k; Tue, 9 Jun 2026 10:45:03 +0000 (GMT) Received: from unvme-SYS-221H-TN24R.samsungds.net (unknown [107.99.40.127]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260609104501epsmtip12bdcceb0bf7d0b7fce7b04526feba867~3Y8sscY8B2355923559epsmtip1G; Tue, 9 Jun 2026 10:45:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20260609104506epoutp02ba8931195556d140ab201886f9c73658~3Y8wlCJ2N2804728047epoutp02X DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1781001906; bh=TVQhRc8dDekoMA1OaYDeOudEU0aw2a7ljZsV7Lahev0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q8rynW1K25DYDtd5HTDNkCDh6nEAdnvYnmY4Rj54EwGJlc77aeERtFctxPOooW8sD 3s/ENHjsZUhWTVkB/uCPpkVxSGKu61pseun1ktgc/w4aSHfQIdhZ0TYv9S9j4200Le YAPvbmGSi0P++CxbJRblmmdAFyBHzQIWO5MULDZA= From: Shrihari E S To: jic23@kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, cpgs@samsung.com Cc: arun.george@samsung.com, vikash.k5@samsung.com, s.neeraj@samsung.com, shrihari.s@samsung.com, dongjoo.seo1@samsung.com, dave@stgolabs.net, gost.dev@samsung.com Subject: [RFC 1/8] hw/pci: Refactor flitmode from PCIESlot to PCIEPort. Date: Tue, 9 Jun 2026 16:28:29 +0530 Message-Id: <20260609105836.3702787-2-shrihari.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260609105836.3702787-1-shrihari.s@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260609104503epcas5p12628cd89d0ef9210c856d2518dc790cb X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104503epcas5p12628cd89d0ef9210c856d2518dc790cb References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=shrihari.s@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009839095154100 Move the 'flitmode' property from PCIESlot to PCIEPort. This change allows all the derived ports (PCIe ports or CXL ports) to use this property. This is a structural refactor only. There is no functional change in existing behavior. Note: This property was added from Davidlohr's BI patch series[1]. [1]: https://lore.kernel.org/all/20251103195209.1319917-2-dave@stgolabs.net/ Signed-off-by: Shrihari E S --- hw/pci-bridge/cxl_downstream.c | 6 +++--- hw/pci-bridge/cxl_root_port.c | 6 +++--- hw/pci/pcie.c | 2 +- include/hw/pci/pcie_port.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index d1e27994a3..7c7a1d1221 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -118,7 +118,7 @@ static void cxl_dsp_reset(DeviceState *qdev) =20 static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s =3D PCIE_SLOT(d); + PCIEPort *p =3D PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -132,7 +132,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentStat= e *cxl) dvsec =3D (uint8_t *)&(CXLDVSECPortFlexBus){ .cap =3D 0x27, /* Cache, IO, Mem, non-MLD */ .ctrl =3D 0x02, /* IO always enabled */ - .status =3D s->flitmode ? 0x6 : 0x26, /* lack of = 68B */ + .status =3D p->flitmode ? 0x6 : 0x26, /* lack of = 68B */ .rcvd_mod_ts_data_phase1 =3D 0xef, /* WTF? */ }; cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, @@ -259,7 +259,7 @@ static const Property cxl_dsp_props[] =3D { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; =20 static void cxl_dsp_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 0ee18ef5c3..df69c5200f 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -112,7 +112,7 @@ static void latch_registers(CXLRootPort *crp) =20 static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s =3D PCIE_SLOT(d); + PCIEPort *p =3D PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -135,7 +135,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentStat= e *cxl) dvsec =3D (uint8_t *)&(CXLDVSECPortFlexBus){ .cap =3D 0x26, /* IO, Mem, non-MLD */ .ctrl =3D 0x2, - .status =3D s->flitmode ? 0x6 : 0x26, /* lack of = 68B */ + .status =3D p->flitmode ? 0x6 : 0x26, /* lack of = 68B */ .rcvd_mod_ts_data_phase1 =3D 0xef, }; cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, @@ -237,7 +237,7 @@ static const Property gen_rp_props[] =3D { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; =20 static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1de0b1e4fd..d452199d85 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -217,7 +217,7 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ } =20 - pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->flitmode); + pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->parent_obj.flitmode); } =20 int pcie_cap_init(PCIDevice *dev, uint8_t offset, diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 53cd64c5ed..1bcc734649 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -33,6 +33,7 @@ struct PCIEPort { /*< private >*/ PCIBridge parent_obj; /*< public >*/ + bool flitmode; =20 /* pci express switch port */ uint8_t port; @@ -58,7 +59,6 @@ struct PCIESlot { =20 PCIExpLinkSpeed speed; PCIExpLinkWidth width; - bool flitmode; =20 /* Disable ACS (really for a pcie_root_port) */ bool disable_acs; --=20 2.34.1 From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1781009852; cv=none; d=zohomail.com; s=zohoarc; b=XACkDj1YopekP7IIrYNIVnLe2rfAxgUmjxMLmtT5uGyaGMDDxzR7js06owAxUBnddK58t7xPurBJWNIhq13Sc6HalwsrVCLLmW4zcSRMI5Mzzkt/SZ8SUvxuEn3NlTtnldQedRc7/78WI6QSHWgYxSJ/EwgtXN7gmif8Q1tMp+E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781009852; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Date: Tue, 9 Jun 2026 16:28:30 +0530 Message-Id: <20260609105836.3702787-3-shrihari.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260609105836.3702787-1-shrihari.s@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260609104512epcas5p37f4a75a633dd8e5bb22f51e9660ee454 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104512epcas5p37f4a75a633dd8e5bb22f51e9660ee454 References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=shrihari.s@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:40 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009855020154100 Relocate 'x-256b-flit' property from cxl_root_port to its parent pcie_root_port so that both can utilize this property. This is a pure refactor and does not impact any existing behavior. Signed-off-by: Shrihari E S --- hw/pci-bridge/cxl_root_port.c | 1 - hw/pci-bridge/pcie_root_port.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index df69c5200f..e82685d1ab 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -237,7 +237,6 @@ static const Property gen_rp_props[] =3D { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; =20 static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index fe3ced5685..eeee24e042 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -152,6 +152,7 @@ static const Property rp_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; =20 static void rp_instance_post_init(Object *obj) --=20 2.34.1 From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1781009839; cv=none; d=zohomail.com; s=zohoarc; b=fhDHkyMBXGudogdsukB84fzil/sdhfpA2qoKoNs+eufAbJWkI53CM2igKJDIXmsRBhOuHuPqoMjJNEf31isGMt2s9xKzibJwh79dWmytbOOtar3RpL49fvBb4isYZyO9WtwhiNSrr2+zHvAkQIKvxCUHlul+EZv6ndpkI/eMMSk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781009839; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=M8e5GeRyE2solHQvA/awHxp2b9XtLDzcTwdIMuL5KRM=; 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Tue, 9 Jun 2026 10:45:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20260609104520epoutp029e82747e67b51cb2aa5b8976b903eb0f~3Y8968Mxm2730527305epoutp02v DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1781001920; bh=M8e5GeRyE2solHQvA/awHxp2b9XtLDzcTwdIMuL5KRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IOQHSk/ZyEUynAhmSzfBfQ94MK1JqprLcd+s9Pd/cX8iSPCl/5xWEmdl4fKO24Alx EXw7YhXoMOpPewuH7vloGwB4TSXOOdgNLu1KGhYHEdUUOg0HkoeavdUZII55iB16X4 mDVu/THWrtxt0Piz1gKIDwOGl0rib7dJPtfdAYMg= From: Shrihari E S To: jic23@kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, cpgs@samsung.com Cc: arun.george@samsung.com, vikash.k5@samsung.com, s.neeraj@samsung.com, shrihari.s@samsung.com, dongjoo.seo1@samsung.com, dave@stgolabs.net, gost.dev@samsung.com Subject: [RFC 3/8] hw/pci: Add SVC capability and UIO properties to PCIe ports Date: Tue, 9 Jun 2026 16:28:31 +0530 Message-Id: <20260609105836.3702787-4-shrihari.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260609105836.3702787-1-shrihari.s@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260609104517epcas5p222b4fc4a5fd8671b47a68abc785a6422 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104517epcas5p222b4fc4a5fd8671b47a68abc785a6422 References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=shrihari.s@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:36 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009842775158500 From: Dongjoo Seo Implement the Streamlined Virtual Channel (SVC) extended capability for PCIe ports (Root, Upstream, and Downstream). This capability is mandatory for enabling Unordered IO (UIO) traffic as per PCIe 6.4 specification [1]. UIO functionality depends on two key prerequisites: 1. SVC support (SVC3 mandatory, SVC4 optional) 2. 256-byte Flit mode support This patch adds the following experimental properties to PCIe ports: - x-uio-svc: Enable UIO traffic via SVC3 (mandatory path) - x-uio-svc-opt: Enable UIO traffic via SVC4 (optional path) - x-256b-flit: Enable 256B flit mode required for UIO Helper functions are included to manage UIO traffic gating and SVC configuration. This change lays the groundwork for UIO emulation in QEMU. [1]: PCIe 6.4 Specification, Table 2-46 (Streamlined Virtual Channel) Signed-off-by: Dongjoo Seo Signed-off-by: Shrihari E S --- hw/pci-bridge/pcie_root_port.c | 2 ++ hw/pci-bridge/xio3130_downstream.c | 3 +++ hw/pci-bridge/xio3130_upstream.c | 8 ++++++++ include/hw/pci/pcie_port.h | 21 +++++++++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index eeee24e042..20554bd854 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -153,6 +153,8 @@ static const Property rp_props[] =3D { QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), + DEFINE_PROP_BIT("x-uio-svc", PCIEPort, svc, UIO_MANDATORY_SVC, false), + DEFINE_PROP_BIT("x-uio-svc-opt", PCIEPort, svc, UIO_OPTIONAL_SVC, fals= e), }; =20 static void rp_instance_post_init(Object *obj) diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index 0c3fed3053..b0b297bb53 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -137,6 +137,9 @@ static void xio3130_downstream_exitfn(PCIDevice *d) static const Property xio3130_downstream_props[] =3D { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_BIT("x-uio-svc", PCIEPort, svc, UIO_MANDATORY_SVC, false), + DEFINE_PROP_BIT("x-uio-svc-opt", PCIEPort, svc, UIO_OPTIONAL_SVC, fals= e), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), }; =20 static const VMStateDescription vmstate_xio3130_downstream =3D { diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index 40057b749b..925df5add3 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -24,6 +24,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/core/qdev-properties.h" #include "migration/vmstate.h" #include "qemu/module.h" =20 @@ -123,6 +124,12 @@ static const VMStateDescription vmstate_xio3130_upstre= am =3D { } }; =20 +static const Property xio3130_upstream_props[] =3D { + DEFINE_PROP_BIT("x-uio-svc", PCIEPort, svc, UIO_MANDATORY_SVC, false), + DEFINE_PROP_BIT("x-uio-svc-opt", PCIEPort, svc, UIO_OPTIONAL_SVC, fals= e), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), +}; + static void xio3130_upstream_class_init(ObjectClass *klass, const void *da= ta) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -138,6 +145,7 @@ static void xio3130_upstream_class_init(ObjectClass *kl= ass, const void *data) dc->desc =3D "TI X3130 Upstream Port of PCI Express Switch"; device_class_set_legacy_reset(dc, xio3130_upstream_reset); dc->vmsd =3D &vmstate_xio3130_upstream; + device_class_set_props(dc, xio3130_upstream_props); } =20 static const TypeInfo xio3130_upstream_info =3D { diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1bcc734649..a6b1b8a6cf 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -37,8 +37,29 @@ struct PCIEPort { =20 /* pci express switch port */ uint8_t port; + + /* + * This field declares Streamlined Virtual Channel (SVC) capability. + * Per PCIe 6.4 specification section 7.9.29, a pcie port supports + * upto 8 SVCs, in that SVC0 is a default one, SVC3 is for UIO traffic + * and SVC 4 is shared by both UIO and non-UIO traffic. + */ + uint32_t svc; }; =20 +#define UIO_MANDATORY_SVC 3 +#define UIO_OPTIONAL_SVC 4 + +static inline bool get_uio_mandatory_svc(PCIEPort *port) +{ + return (port->svc >> UIO_MANDATORY_SVC) & 1; +} + +static inline bool get_uio_optional_svc(PCIEPort *port) +{ + return (port->svc >> UIO_OPTIONAL_SVC) & 1; +} + void pcie_port_init_reg(PCIDevice *d); =20 PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn); --=20 2.34.1 From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1781009844; cv=none; d=zohomail.com; s=zohoarc; b=UIFSTjAY15Qe4szY3qXgYHBI0+G7vV+u+EdLtKRnvTuMhjHA/urE/RW6ZdSYdOdtiBI/axfIFX+2z90cSTobGiDWnlgXp2/mJbBncEJbFRXXVl57Q9k+rfr1vLCjceJM61jORvVKjky5A5sEg7/tfeh1aXG2HBZf9N6tC7Dmv14= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781009844; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 9 Jun 2026 10:45:21 +0000 (GMT) Received: from unvme-SYS-221H-TN24R.samsungds.net (unknown [107.99.40.127]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260609104520epsmtip111075b924d06186a6f24d55bfc9e6f84~3Y89s12ed2381023810epsmtip1U; Tue, 9 Jun 2026 10:45:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20260609104523epoutp028a751f02dee93c1b77891082d4c33ef0~3Y9AtuqrR2804728047epoutp02h DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1781001923; bh=kMkgTZuJ/C4L91nSM6PkENeTgSP9+Fl1hfo4foCfyvM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kzg8/WpO6518c/xezrBVBNN/zjxo6/epyhT23+3oYX7jF8AJSqxCTRkfZO90NbCKD AfFoQCrbmJyIpZE6CBRK4OgJMarpEGkQ10Z3jOUJ/K+BbN/WDxQMw0U9M0MOIsvyQ/ rcabtg0T/woV+zPbFWLo/LeTQS2nP2OXSRIw3aig= From: Shrihari E S To: jic23@kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, cpgs@samsung.com Cc: arun.george@samsung.com, vikash.k5@samsung.com, s.neeraj@samsung.com, shrihari.s@samsung.com, dongjoo.seo1@samsung.com, dave@stgolabs.net, gost.dev@samsung.com Subject: [RFC 4/8] hw/cxl: Add Streamlined Virtual Channel (SVC) property to CXL ports Date: Tue, 9 Jun 2026 16:28:32 +0530 Message-Id: <20260609105836.3702787-5-shrihari.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260609105836.3702787-1-shrihari.s@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260609104521epcas5p1d91703d83cfe9fd9d38506a64fa276a7 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104521epcas5p1d91703d83cfe9fd9d38506a64fa276a7 References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=shrihari.s@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:42 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009846212158500 Add Unordered IO (UIO) dependent property SVC to CXL ports (Root, Upstream and Downstream). The following properties are added to CXL ports: - x-uio-svc: Enable UIO traffic via SVC3 (mandatory path) - x-uio-svc-opt: Enable UIO traffic via SVC4 (optional path) Note: 256B flit mode property was already added in CXL ports, so reused it. Signed-off-by: Shrihari E S Signed-off-by: Dongjoo Seo --- hw/pci-bridge/cxl_downstream.c | 2 ++ hw/pci-bridge/cxl_root_port.c | 1 + hw/pci-bridge/cxl_upstream.c | 2 ++ include/hw/pci-bridge/cxl_upstream_port.h | 1 + 4 files changed, 6 insertions(+) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 7c7a1d1221..6f6f332c07 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -260,6 +260,8 @@ static const Property cxl_dsp_props[] =3D { DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), + DEFINE_PROP_BIT("x-uio-svc", PCIEPort, svc, UIO_MANDATORY_SVC, false), + DEFINE_PROP_BIT("x-uio-svc-opt", PCIEPort, svc, UIO_OPTIONAL_SVC, fals= e), }; =20 static void cxl_dsp_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index e82685d1ab..83fb5968b8 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -53,6 +53,7 @@ typedef struct CXLRootPort { CPMUState cpmu; MemoryRegion cpmu_registers; PCIResReserve res_reserve; + bool uio_capable; } CXLRootPort; =20 #define TYPE_CXL_ROOT_PORT "cxl-rp" diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index ef5480b116..dadad3e15c 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -437,6 +437,8 @@ static const Property cxl_upstream_props[] =3D { DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort, width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", CXLUpstreamPort, flitmode, false), + DEFINE_PROP_BIT("x-uio-svc", PCIEPort, svc, UIO_MANDATORY_SVC, false), + DEFINE_PROP_BIT("x-uio-svc-opt", PCIEPort, svc, UIO_OPTIONAL_SVC, fals= e), }; =20 static void cxl_upstream_class_init(ObjectClass *oc, const void *data) diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bri= dge/cxl_upstream_port.h index d4186234c8..d23541e23a 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -22,6 +22,7 @@ typedef struct CXLUpstreamPort { PCIExpLinkSpeed speed; PCIExpLinkWidth width; bool flitmode; + bool uio_capable; =20 DOECap doe_cdat; uint64_t sn; --=20 2.34.1 From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1781009867; cv=none; d=zohomail.com; s=zohoarc; b=i43VAHkYxN8v1eEJQKXCW/hDJrbFuBRGyomLHQDwa+oea+Bzdoa0eMVYRNFYgSHVihgXlBUSwp3BnGVAOmedxcksb3C4Eo6IxfPDQTvDbFQLFdCNsDfk3+520MJDOz98R3NiPCPo99iKUHrhuOGuMneZhBpcw2agip0YbnC1mGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1781009867; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 9 Jun 2026 10:45:25 +0000 (GMT) Received: from unvme-SYS-221H-TN24R.samsungds.net (unknown [107.99.40.127]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260609104523epsmtip1c14a135ce5ac2255ceb339b0299225c1~3Y9ArC0xG2221922219epsmtip1m; Tue, 9 Jun 2026 10:45:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20260609104526epoutp018ba289e1904d3b7d51a933599ecb68b3~3Y9DzqBlw3250632506epoutp01x DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1781001926; bh=Uxe8siGpeBw5SZONkkYNgM/0xKYIi23/sklb1yT+pj8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pkqvXNQT/X4M3QJ6ekadT4738oNSD4VOnMvDDdvzwq9XPGS+cJ6pjNpe6tGA3r4BD 5PdpuEMAldm7ga4GhKykY8ZchSjjMUV7kuSvukS35I8Ht050csiNIsVxitwQL+9ilX 7VFzznH3FQxIm3BMnGf7HSGNqDtaG9b7jN3IOfaw= From: Shrihari E S To: jic23@kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, cpgs@samsung.com Cc: arun.george@samsung.com, vikash.k5@samsung.com, s.neeraj@samsung.com, shrihari.s@samsung.com, dongjoo.seo1@samsung.com, dave@stgolabs.net, gost.dev@samsung.com Subject: [RFC 5/8] hw/cxl: Wire UIO capability into HDM decoder registers Date: Tue, 9 Jun 2026 16:28:33 +0530 Message-Id: <20260609105836.3702787-6-shrihari.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260609105836.3702787-1-shrihari.s@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260609104525epcas5p151a4e745f5303e79a2a92432180a6af7 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104525epcas5p151a4e745f5303e79a2a92432180a6af7 References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.24; envelope-from=shrihari.s@samsung.com; helo=mailout1.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:44 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009869372154100 Plumb the 'uio_capable' flag to CXL HDM decoder capability and control register interfaces. The UIO bit in the capability register is now set for CXL Type3 devices and ports when UIO support is advertised via 'x-uio-svc' property. Per CXL 4.0 specification Section 8.2.4.20.7, the decoder control UIO bit is validated against the advertised capability during HDM decoder commit operations. Additionally, replace hardcoded HDM decoder control write masks with spec-aligned 'WRMASK' definitions. Signed-off-by: Shrihari E S Signed-off-by: Dongjoo Seo --- hw/cxl/cxl-component-utils.c | 29 +++++++++++++++++++++++------ hw/mem/cxl_type3.c | 9 ++++++++- hw/pci-bridge/cxl_downstream.c | 2 +- hw/pci-bridge/cxl_root_port.c | 2 +- hw/pci-bridge/cxl_upstream.c | 3 ++- hw/pci-bridge/pci_expander_bridge.c | 3 ++- include/hw/cxl/cxl_component.h | 2 +- include/hw/cxl/cxl_device.h | 2 ++ 8 files changed, 40 insertions(+), 12 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 31bbedb502..9a5b382272 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -13,6 +13,19 @@ #include "hw/pci/pci.h" #include "hw/cxl/cxl.h" =20 +/* CXL 4.0 specification 8.4.2.20.7 */ +#define CXL_HDM_DECODER_CTRL_WRMASK ( \ + (0xfu << 0) | /* IG */ \ + (0xfu << 4) | /* IW */ \ + BIT(8) | /* LOCK_ON_COMMIT */ \ + BIT(9) | /* COMMIT */ \ + BIT(12) | /* TYPE */ \ + BIT(13) | /* BI */ \ + BIT(14) | /* UIO */ \ + (0xfu << 16) | /* UIG */ \ + (0xfu << 20) | /* UIW */ \ + (0xfu << 24)) /* ISP */ + /* CXL r3.1 Section 8.2.4.20.1 CXL HDM Decoder Capability Register */ int cxl_decoder_count_enc(int count) { @@ -305,7 +318,7 @@ static void ras_init_common(uint32_t *reg_state, uint32= _t *write_msk) } =20 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type, bool bi) + enum reg_type type, bool bi, bool uio) { int decoder_count =3D CXL_HDM_DECODER_COUNT; int hdm_inc =3D R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_L= O; @@ -325,9 +338,12 @@ static void hdm_init_common(uint32_t *reg_state, uint3= 2_t *write_msk, ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY= , 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); } - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0); + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, + (type =3D=3D CXL2_TYPE3_DEVICE || CXL2_UPSTREAM_PORT)= && uio); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, - UIO_DECODER_COUNT, 0); + UIO_DECODER_COUNT, + (type =3D=3D CXL2_TYPE3_DEVICE || CXL2_UPSTREAM_PORT)= && uio ? + decoder_count : 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CA= P, 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, SUPPORTED_COHERENCY_MODEL, @@ -341,7 +357,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32= _t *write_msk, write_msk[R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc] =3D 0xffffffff; write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc] =3D 0xf0000000; write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc] =3D 0xffffffff; - write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] =3D 0x13ff; + write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] =3D + CXL_HDM_DECODER_CTRL_WRMASK; if (type =3D=3D CXL2_DEVICE || type =3D=3D CXL2_TYPE3_DEVICE || type =3D=3D CXL2_LOGICAL_DEVICE) { @@ -391,7 +408,7 @@ static void bi_decoder_init_common(uint32_t *reg_state,= uint32_t *write_msk, void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, enum reg_type type, - bool bi) + bool bi, bool uio) { int caps =3D 0; =20 @@ -431,7 +448,7 @@ void cxl_component_register_init_common(uint32_t *reg_s= tate, case CXL2_LOGICAL_DEVICE: /* + HDM */ init_cap_reg(HDM, 5, 1); - hdm_init_common(reg_state, write_msk, type, bi); + hdm_init_common(reg_state, write_msk, type, bi, uio); /* fallthrough */ case CXL2_DOWNSTREAM_PORT: case CXL2_DEVICE: diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index b7ad437cbc..4cdadc3e10 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -590,6 +590,11 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int = which) /* TODO: Sanity checks that the decoder is possible */ ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, ERR, 0); ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); + if (ct3d->uio_capable) { + ct3d->uio_enabled =3D FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, UIO); + } else { + ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, UIO, 0); + } =20 /* Get interleave details for chmu */ ig =3D FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG); @@ -1512,7 +1517,8 @@ void ct3d_reset(DeviceState *dev) pcie_cap_fill_link_ep_usp(PCI_DEVICE(dev), ct3d->width, ct3d->speed, ct3d->flitmode); cxl_component_register_init_common(reg_state, write_msk, - CXL2_TYPE3_DEVICE, ct3d->hdmdb); + CXL2_TYPE3_DEVICE, ct3d->hdmdb, + ct3d->uio_capable); cxl_device_register_init_t3(ct3d, CXL_T3_MSIX_MBOX); =20 /* @@ -1552,6 +1558,7 @@ static const Property ct3_props[] =3D { width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", CXLType3Dev, flitmode, false), DEFINE_PROP_BOOL("hdm-db", CXLType3Dev, hdmdb, false), + DEFINE_PROP_BOOL("x-uio", CXLType3Dev, uio_capable, false), DEFINE_PROP_UINT16("chmu-port", CXLType3Dev, cxl_dstate.chmu[0].port, = 0), }; =20 diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 6f6f332c07..e0fa6cfdc4 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -42,7 +42,7 @@ static void latch_registers(CXLDownstreamPort *dsp) uint32_t *write_msk =3D dsp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, - CXL2_DOWNSTREAM_PORT, true); + CXL2_DOWNSTREAM_PORT, true, false); } =20 /* TODO: Look at sharing this code across all CXL port types */ diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 83fb5968b8..4be2b400f9 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -108,7 +108,7 @@ static void latch_registers(CXLRootPort *crp) uint32_t *write_msk =3D crp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_POR= T, - true); + true, crp->uio_capable); } =20 static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index dadad3e15c..a75d10e7b4 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -136,7 +136,8 @@ static void latch_registers(CXLUpstreamPort *usp) uint32_t *write_msk =3D usp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, - CXL2_UPSTREAM_PORT, usp->flitmode); + CXL2_UPSTREAM_PORT, usp->flitmode, + usp->uio_capable); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, = 8); } =20 diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 25dfee6a9b..18b61eca20 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -301,7 +301,8 @@ static void pxb_cxl_dev_reset(DeviceState *dev) uint32_t *write_msk =3D cxl_cstate->crb.cache_mem_regs_write_mask; int dsp_count =3D 0; =20 - cxl_component_register_init_common(reg_state, write_msk, CXL2_RC, fals= e); + cxl_component_register_init_common(reg_state, write_msk, CXL2_RC, fals= e, + false); /* * The CXL specification allows for host bridges with no HDM decoders * if they only have a single root port. diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index d734f88d2c..662fdb0833 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -315,7 +315,7 @@ void cxl_component_register_block_init(Object *obj, const char *type); void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type, bool bi); + enum reg_type type, bool bi, bool = uio); =20 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, enum reg_type cxl_dev_type, uint16_t lengt= h, diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 3b5dcb5aec..20a1a90014 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -883,6 +883,8 @@ struct CXLType3Dev { PCIExpLinkSpeed speed; PCIExpLinkWidth width; bool flitmode; + bool uio_capable; + bool uio_enabled; =20 /* DOE */ DOECap doe_cdat; --=20 2.34.1 From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1781009860; 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b=ZoaK+X2vlD7oCNFhN4CJ0AzLAKjcg+UmCp38vkxLtyL6YTz+u/MXVE0Pw+P6kRqgm sOrtVy8Wx+NNo6MacoD1+hocAJTKGwO/3kpUwQSpdOBnyMtOnLPhx8+pX9nhvGXbYY xEJZExwq0zQy9+UzdWVD4GMtTVA9LIHPaciEdbG0= From: Shrihari E S To: jic23@kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, cpgs@samsung.com Cc: arun.george@samsung.com, vikash.k5@samsung.com, s.neeraj@samsung.com, shrihari.s@samsung.com, dongjoo.seo1@samsung.com, dave@stgolabs.net, gost.dev@samsung.com Subject: [RFC 6/8] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability. Date: Tue, 9 Jun 2026 16:28:34 +0530 Message-Id: <20260609105836.3702787-7-shrihari.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260609105836.3702787-1-shrihari.s@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260609104528epcas5p4b7379fbb5bcc8ee74461a039e88b1637 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104528epcas5p4b7379fbb5bcc8ee74461a039e88b1637 References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.33; envelope-from=shrihari.s@samsung.com; helo=mailout3.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:49 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009865267154100 From: Dongjoo Seo Implement the PCIe Streamlined Virtual Channel (SVC) Extended Capability by adding support of capability, control and status registers per PCIe 6.4 section 7.9.29. This capability is one of the main requisites for UIO support in both PCIe and CXL ports. Key changes include: - New pcie_svc.c file for SVC capability management. - Updated pcie_cap_fill_lnk() to handle flitmode signaling. - Implement Lifecycle hooks (reset and config_write) to manage SVC state. Signed-off-by: Dongjoo Seo Signed-off-by: Shrihari E S --- hw/pci/meson.build | 2 +- hw/pci/pci.c | 4 + hw/pci/pcie.c | 53 ++++++++++-- hw/pci/pcie_svc.c | 164 +++++++++++++++++++++++++++++++++++++ include/hw/pci/pcie.h | 7 ++ include/hw/pci/pcie_regs.h | 1 + include/hw/pci/pcie_svc.h | 91 ++++++++++++++++++++ 7 files changed, 316 insertions(+), 6 deletions(-) create mode 100644 hw/pci/pcie_svc.c create mode 100644 include/hw/pci/pcie_svc.h diff --git a/hw/pci/meson.build b/hw/pci/meson.build index b9c34b2acf..d55882a0c9 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -14,7 +14,7 @@ pci_ss.add(files( # The functions in these modules can be used by devices too. Since we # allow plugging PCIe devices into PCI buses, include them even if # CONFIG_PCI_EXPRESS=3Dn. -pci_ss.add(files('pcie.c', 'pcie_aer.c')) +pci_ss.add(files('pcie.c', 'pcie_aer.c', 'pcie_svc.c')) pci_ss.add(files('pcie_doe.c')) system_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', 'p= cie_host.c')) system_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 5996229c81..0469250f42 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -30,6 +30,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" +#include "hw/pci/pcie_svc.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-properties-system.h" #include "migration/cpr.h" @@ -568,6 +569,7 @@ static void pci_do_device_reset(PCIDevice *dev) msi_reset(dev); msix_reset(dev); pcie_sriov_pf_reset(dev); + pcie_svc_cap_reset(dev); } =20 /* @@ -1814,6 +1816,8 @@ void pci_default_write_config(PCIDevice *d, uint32_t = addr, uint32_t val_in, int msi_write_config(d, addr, val_in, l); msix_write_config(d, addr, val_in, l); pcie_sriov_config_write(d, addr, val_in, l); + pcie_cap_flit_write_config(d, addr, val_in, l); + pcie_svc_cap_write_config(d, addr, val_in, l); } =20 /***********************************************************/ diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index d452199d85..7c7d948e00 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -112,8 +112,9 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t = type, uint8_t version) } =20 /* Includes setting the target speed default */ -static void pcie_cap_fill_lnk(uint8_t *exp_cap, PCIExpLinkWidth width, - PCIExpLinkSpeed speed, bool flitmode) +static void pcie_cap_fill_lnk(PCIDevice *dev, uint8_t *exp_cap, + PCIExpLinkWidth width, PCIExpLinkSpeed speed, + bool flitmode) { /* Clear and fill LNKCAP from what was configured above */ pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, @@ -160,8 +161,14 @@ static void pcie_cap_fill_lnk(uint8_t *exp_cap, PCIExp= LinkWidth width, } =20 if (flitmode) { - pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA2, + uint32_t pos =3D dev->exp.exp_cap; + + pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_LNKSTA2_FLIT); + pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS, + PCI_EXP_FLAGS_FLIT); + pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_FLIT_DIS); } } =20 @@ -180,9 +187,44 @@ void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpL= inkWidth width, QEMU_PCI_EXP_LNKSTA_NLW(width) | QEMU_PCI_EXP_LNKSTA_CLS(speed)); =20 - pcie_cap_fill_lnk(exp_cap, width, speed, flitmode); + pcie_cap_fill_lnk(dev, exp_cap, width, speed, flitmode); } =20 +void pcie_cap_flit_write_config(PCIDevice *dev, uint32_t addr, uint32_t va= l, + int len) +{ + uint8_t *exp_cap; + uint16_t lnksta2; + uint16_t lnkctl; + uint16_t flags; + + if (!pci_is_express(dev) || !dev->exp.exp_cap) { + return; + } + + if (!ranges_overlap(addr, len, + dev->exp.exp_cap + PCI_EXP_LNKCTL, 2)) { + return; + } + + exp_cap =3D dev->config + dev->exp.exp_cap; + flags =3D pci_get_word(exp_cap + PCI_EXP_FLAGS); + if (!(flags & PCI_EXP_FLAGS_FLIT)) { + return; + } + + lnkctl =3D pci_get_word(exp_cap + PCI_EXP_LNKCTL); + lnksta2 =3D pci_get_word(exp_cap + PCI_EXP_LNKSTA2); + + if (lnkctl & PCI_EXP_LNKCTL_FLIT_DIS) { + lnksta2 &=3D ~PCI_EXP_LNKSTA2_FLIT; + } else { + lnksta2 |=3D PCI_EXP_LNKSTA2_FLIT; + } + + pci_set_word(exp_cap + PCI_EXP_LNKSTA2, lnksta2); + } + static void pcie_cap_fill_slot_lnk(PCIDevice *dev) { PCIESlot *s =3D (PCIESlot *)object_dynamic_cast(OBJECT(dev), TYPE_PCIE= _SLOT); @@ -217,7 +259,8 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ } =20 - pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->parent_obj.flitmode); + pcie_cap_fill_lnk(dev, exp_cap, s->width, s->speed, + s->parent_obj.flitmode); } =20 int pcie_cap_init(PCIDevice *dev, uint8_t offset, diff --git a/hw/pci/pcie_svc.c b/hw/pci/pcie_svc.c new file mode 100644 index 0000000000..84db73de58 --- /dev/null +++ b/hw/pci/pcie_svc.c @@ -0,0 +1,164 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * PCIe Streamlined Virtual Channel (SVC) Extended Capability + * + * Copyright (c) 2026 Samsung Electronics Co., Ltd. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "hw/pci/pci_device.h" +#include "hw/pci/pcie.h" +#include "hw/pci/pcie_svc.h" +#include "hw/pci/pcie_port.h" + +static void pcie_svc_update_map(PCIDevice *dev) +{ + uint32_t non_uio_ctrl =3D SVC_VC0_PROTOCOL | SVC_VC_ENABLE; + uint32_t uio_ctrl =3D SVC_UIO_PROTOCOL_SELECTED | SVC_VC_ENABLE; + int offset; + + if (!pci_is_express(dev) || !dev->exp.svc_cap) { + return; + } + + offset =3D pcie_find_capability(dev, PCI_EXT_CAP_ID_SVC); + + /* SVC VC0 & VC3 initialization */ + pci_set_long(dev->config + offset + SVC_RES_CTRL(0), BIT(0) | non_uio_= ctrl); + pci_set_long(dev->config + offset + SVC_RES_CTRL(3), BIT(3) | uio_ctrl= ); + + /* SVC VC4 initialization - optional */ + if (dev->exp.svc.uio_opt_svc) { + pci_set_long(dev->config + offset + SVC_RES_CTRL(4), BIT(4) | uio_= ctrl); + } +} + +int pcie_config_uio_svc(PCIDevice *d, Error **errp) +{ + PCIEPort *p =3D PCIE_PORT(d); + + if (!get_uio_mandatory_svc(p) + || pcie_svc_cap_init(d, PCI_EXT_CAP_BASE_OFFSET, errp) < 0) { + return -1; + } + + if (get_uio_optional_svc(p)) { + pcie_svc_set_vc4(d, true); + } + + return 0; +} + +int pcie_svc_cap_init(PCIDevice *dev, uint16_t offset, Error **errp) +{ + uint32_t hdr; + + if (!pci_is_express(dev)) { + error_setg(errp, "SVC ECAP requires PCIe"); + return -EINVAL; + } + + /* + * If no other ECAPs are present, make SVC the first at 0x100. + * This avoids pcie_add_capability() asserting on a non-0x100 offset. + */ + hdr =3D pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE); + if (hdr =3D=3D 0) { + offset =3D PCI_CONFIG_SPACE_SIZE; + } + + pcie_add_capability(dev, PCI_EXT_CAP_ID_SVC, 1, offset, + PCI_EXT_CAP_SVC_SIZE); + dev->exp.svc_cap =3D offset; + dev->exp.svc.ctrl =3D 0; + dev->exp.svc.status =3D 0; + dev->exp.svc.uio_mand_svc =3D true; + dev->exp.svc.uio_opt_svc =3D false; + + pci_set_long(dev->config + offset + PCIE_SVC_CAP_HEAD_OFFSET, + (NEXT_CAP_OFF | PCIE_SVC_CAP_VER | PCI_EXT_CAP_ID_SVC)); + pci_set_long(dev->wmask + offset + PCIE_SVC_CTL_OFFSET, + PCIE_SVC_CTL_ENABLE); + pci_set_long(dev->config + offset + PCIE_SVC_CAP_OFFSET, + PCIE_SVC_CAP1_EVCC); + + for (int i =3D 0; i <=3D PCIE_SVC_CAP1_EVCC; i++) { + uint32_t res_cap_value =3D (1U << 8) | SVC_VC_ID(i); + uint32_t res_ctrl_value =3D SVC_TC_VC_MAP_ENABLE + | SVC_VC_PROTOCOL_SELECTED + | SHARED_FLOW_CONTROL_USAGE_LIMIT_ENABLE + | SHARED_FLOW_CONTROL_USAGE_LIMIT + | SVC_VC_ENABLE; + + if (i =3D=3D 0) { + res_cap_value =3D SVC_VC0_PROTOCOL | SVC_VC_ID(i); + } else if (i =3D=3D 3) { + res_cap_value =3D SVC_VC3_PROTOCOL | SVC_VC_ID(i); + } else if (i =3D=3D 4) { + res_cap_value =3D SVC_VC4_PROTOCOL | SVC_VC_ID(i); + } + + pci_set_long(dev->config + offset + SVC_RES_CAP(i), res_cap_value); + pci_set_long(dev->wmask + offset + SVC_RES_CTRL(i), res_ctrl_value= ); + pci_set_long(dev->config + offset + SVC_RES_STATUS(i), 0); + } + pcie_svc_update_map(dev); + return 0; +} + +void pcie_svc_cap_reset(PCIDevice *dev) +{ + uint32_t offset; + + if (!pci_is_express(dev) || !dev->exp.svc_cap) { + return; + } + + offset =3D dev->exp.svc_cap; + dev->exp.svc.ctrl =3D 0; + dev->exp.svc.status =3D 0; + pcie_svc_update_map(dev); + pci_set_long(dev->config + offset + PCIE_SVC_CTL_OFFSET, 0); + pci_set_long(dev->config + offset + PCIE_SVC_STA_OFFSET, 0); +} + +void pcie_svc_set_vc4(PCIDevice *dev, bool enable) +{ + if (!pci_is_express(dev) || !dev->exp.svc_cap) { + return; + } + + dev->exp.svc.uio_opt_svc =3D enable; + pcie_svc_update_map(dev); +} + +static void pcie_svc_apply_gating(PCIDevice *dev) +{ + uint16_t offset =3D dev->exp.svc_cap; + uint32_t ctrl, status; + + if (!offset) { + return; + } + + ctrl =3D pci_get_long(dev->config + offset + PCIE_SVC_CTL_OFFSET); + status =3D pci_get_long(dev->config + offset + PCIE_SVC_STA_OFFSET); + dev->exp.svc.ctrl =3D ctrl; + dev->exp.svc.status =3D status; +} + +void pcie_svc_cap_write_config(PCIDevice *dev, + uint32_t addr, uint32_t val, int len) +{ + uint16_t offset =3D dev->exp.svc_cap; + + if (!offset) { + return; + } + + if (ranges_overlap(addr, len, offset + PCIE_SVC_CTL_OFFSET, 4)) { + pcie_svc_apply_gating(dev); + } +} diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 79808126dc..35db0f0c5e 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -25,6 +25,7 @@ #include "hw/pci/pcie_regs.h" #include "hw/pci/pcie_aer.h" #include "hw/pci/pcie_sriov.h" +#include "hw/pci/pcie_svc.h" #include "hw/core/hotplug.h" =20 typedef struct PCIEPort PCIEPort; @@ -82,6 +83,10 @@ struct PCIExpressDevice { uint16_t sriov_cap; PCIESriovPF sriov_pf; PCIESriovVF sriov_vf; + + /* Streamlined Virtual Channel (SVC) introduced from PCIe 6.1 */ + uint16_t svc_cap; + PCIESvcCap svc; }; =20 #define COMPAT_PROP_PCP "power_controller_present" @@ -143,6 +148,8 @@ void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t off= set, uint64_t ser_num); void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); void pcie_cap_fill_link_ep_usp(PCIDevice *dev, PCIExpLinkWidth width, PCIExpLinkSpeed speed, bool flitmode); +void pcie_cap_flit_write_config(PCIDevice *dev, + uint32_t addr, uint32_t val, int len); =20 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *d= ev, Error **errp); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 33a22229fe..644da744b2 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -81,6 +81,7 @@ typedef enum PCIExpLinkWidth { #define PCI_EXP_DEVCAP2_EETLPP 0x200000 =20 #define PCI_EXP_DEVCTL2_EETLPPB 0x8000 +#define PCI_EXP_LNKCTL_FLIT_DIS 0x2000 =20 /* ARI */ #define PCI_ARI_VER 1 diff --git a/include/hw/pci/pcie_svc.h b/include/hw/pci/pcie_svc.h new file mode 100644 index 0000000000..4872905501 --- /dev/null +++ b/include/hw/pci/pcie_svc.h @@ -0,0 +1,91 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * PCIe Streamlined Virtual Channel (SVC) Extended Capability + * + * Copyright (c) 2026 Samsung Electronics Co., Ltd. + */ + +#ifndef HW_PCIE_SVC_H +#define HW_PCIE_SVC_H + +#include "hw/pci/pci.h" +#include "qemu/bitops.h" + +/* + * The PCIe config space starts from 0x00 till 0xFF. In that + * extended capability starts from 0x100 and each extended capability + * is of dword size (32 bit). So we have to give a proper base offset + * value which should be >=3D 0x100 and <=3D 0xFF and in between other + * capability will also be registerd. We might not know where exactly + * SVC extended capability will sit, so to avoid the overlapping we have + * to give a very high offset. + */ +#define PCI_EXT_CAP_BASE_OFFSET 0x200 +#define PCI_EXT_CAP_ID_SVC 0x35 +#define PCI_EXT_CAP_SVC_SIZE 0x74 + +/* PCIe 6.4 section 7.9.29 */ +#define PCIE_SVC_CAP_HEAD_OFFSET 0x00 +#define PCIE_SVC_CAP_OFFSET 0x04 +#define PCIE_SVC_CTL_OFFSET 0x0c +#define PCIE_SVC_STA_OFFSET 0x10 +#define PCIE_SVC_CTL_ENABLE BIT(0) +#define PCIE_SVC_CAP1_EVCC (0x7 << 0) + +/* 7.9.29.1 SVC extended capability header */ +#define PCIE_SVC_CAP_VER (1 << 16) +#define NEXT_CAP_OFF (0 << 20) + +/* 7.9.29.6 SVC Resource capability Register */ +#define SVC_RES_CAP_BASE 0x14 +#define SVC_RES_CAP(n) (SVC_RES_CAP_BASE + (n) * 0= x0c) + +/* + * As per Specification SVC VC3 is dedicated to UIO and non-UIO traffic ca= nnot + * use that, so for SVC VC3 the value would be 0010. SVC VC4 is an optiona= l VC + * for UIO and VC4 can be used by non-UIO traffic as well. So the protocol= for + * VC4 would be 0011. For SVC VC0, the protocol is 0000. Rest are all rese= rved + * asper table 2-46 in PCIe 6.4 specification. + */ +#define SVC_VC0_PROTOCOL (0x0 << 8) +#define SVC_VC3_PROTOCOL (0x2 << 8) +#define SVC_VC4_PROTOCOL (0x3 << 8) +#define SVC_VC_ID(n) ((n & 0x7) << 12) + +/* 7.9.27.7 SVC Resource Control Register */ +#define SVC_RES_CTRL_BASE 0x18 +#define SVC_RES_CTRL(n) (SVC_RES_CTRL_BASE + (n) * = 0x0c) +#define SVC_VC_ENABLE BIT(31) +#define SHARED_FLOW_CONTROL_USAGE_LIMIT_ENABLE BIT(30) +#define SVC_VC_PROTOCOL_SELECTED (0xf << 8) +#define SVC_UIO_PROTOCOL_SELECTED (0x2 << 8) +/* + * As per Table 7-350 in 7.9.29.7 in PCIe 6.4 Specification, the protocol + * selected should be 0010 for UIO enabled VCs + */ +#define SHARED_FLOW_CONTROL_USAGE_LIMIT (0x7 << 27) +#define SVC_TC_VC_MAP_ENABLE (0xff << 0) +#define SVC_TC_VC_MAP(n) ((n & 0xff) << 0) + +/* 7.9.27.8 SVC Resource Status Register */ +#define SVC_RES_STATUS_BASE 0x1c +#define SVC_RES_STATUS(n) (SVC_RES_STATUS_BASE + \ + (n) * 0x0c) +#define SVC_VC_NEGO BIT(1) + +typedef struct PCIESvcCap { + uint32_t ctrl; + uint32_t status; + bool uio_mand_svc; + bool uio_opt_svc; +} PCIESvcCap; + +int pcie_config_uio_svc(PCIDevice *d, Error **errp); +int pcie_svc_cap_init(PCIDevice *dev, uint16_t offset, Error **errp); +void pcie_svc_cap_reset(PCIDevice *dev); +void pcie_svc_set_vc4(PCIDevice *dev, bool enable); +void pcie_svc_cap_write_config(PCIDevice *dev, + uint32_t addr, uint32_t val, int len); + +#endif /* HW_PCIE_SVC_H */ --=20 2.34.1 From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=samsung.com ARC-Seal: i=1; a=rsa-sha256; t=1781009882; cv=none; d=zohomail.com; s=zohoarc; b=ORMgB/AztGP+FdS6e/N+8AubETG/lxDgFgqvTQkHRQqcdGi6S1oGWthR1rdLsns+ChlfEuqs6cToKObIuE66JmErvqP4/kYNzibk5T/uVTXF0T95weeaY81maMtBkwa1vjlL/cIQs9tfTsgkH4jRIZsUgCBhvFjJcDc9EN/A8wc= ARC-Message-Signature: i=1; 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Date: Tue, 9 Jun 2026 16:28:35 +0530 Message-Id: <20260609105836.3702787-8-shrihari.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260609105836.3702787-1-shrihari.s@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260609104530epcas5p153380a0f04ac6db56fe1edbb252bbb22 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104530epcas5p153380a0f04ac6db56fe1edbb252bbb22 References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.33; envelope-from=shrihari.s@samsung.com; helo=mailout3.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:46 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009883567154100 Integrate Streamlined Virtual Channel (SVC) capability initialization into = the realize() functions of both PCIe and CXL ports. This change ensures that the 'uio_capable' flag is correctly populated in CXL ports during the initializ= ation sequence. 'uio_capable' in CXL ports is responsible for enabling UIO capability in HDM decoder registers. Signed-off-by: Shrihari E S Signed-off-by: Dongjoo Seo --- hw/pci-bridge/cxl_downstream.c | 1 + hw/pci-bridge/cxl_root_port.c | 5 +++++ hw/pci-bridge/cxl_upstream.c | 4 ++++ hw/pci-bridge/pcie_root_port.c | 1 + hw/pci-bridge/xio3130_downstream.c | 1 + hw/pci-bridge/xio3130_upstream.c | 1 + 6 files changed, 13 insertions(+) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index e0fa6cfdc4..a9eaeb81bb 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -229,6 +229,7 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &dsp->bar); + pcie_config_uio_svc(d, errp); =20 return; =20 diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 4be2b400f9..eafcf59f83 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -164,6 +164,7 @@ static void cxl_rp_realize(DeviceState *dev, Error **er= rp) { PCIDevice *pci_dev =3D PCI_DEVICE(dev); PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(dev); + PCIEPort *p =3D PCIE_PORT(dev); CXLRootPort *crp =3D CXL_ROOT_PORT(dev); CXLComponentState *cxl_cstate =3D &crp->cxl_cstate; ComponentRegisters *cregs =3D &cxl_cstate->crb; @@ -212,6 +213,10 @@ static void cxl_rp_realize(DeviceState *dev, Error **e= rrp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &crp->bar); + rc =3D pcie_config_uio_svc(pci_dev, errp); + if (p->flitmode && rc >=3D 0) { + crp->uio_capable =3D true; + } } =20 static void cxl_rp_reset_hold(Object *obj, ResetType type) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index a75d10e7b4..f6f5713437 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -411,6 +411,10 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) goto err_cap; } =20 + rc =3D pcie_config_uio_svc(d, errp); + if (p->flitmode && rc >=3D 0) { + usp->uio_capable =3D true; + } return; =20 err_cap: diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 20554bd854..5a74b0e978 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -97,6 +97,7 @@ static void rp_realize(PCIDevice *d, Error **errp) goto err_int; } =20 + pcie_config_uio_svc(d, errp); pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_dow= nstream.c index b0b297bb53..cc19fb1213 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -93,6 +93,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Erro= r **errp) if (rc < 0) { goto err_msi; } + pcie_config_uio_svc(d, errp); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstr= eam.c index 925df5add3..c28339dabe 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -84,6 +84,7 @@ static void xio3130_upstream_realize(PCIDevice *d, Error = **errp) if (rc < 0) { goto err_msi; } + pcie_config_uio_svc(d, errp); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); =20 --=20 2.34.1 From nobody Tue Jun 9 23:11:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260609104533epcas5p2b80ad53ed807018b3bb4316e4984f89a References: <20260609105836.3702787-1-shrihari.s@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=shrihari.s@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 09 Jun 2026 08:56:47 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1781009845178154100 Add a command-line example demonstrating a topology with three CXL Type-3 devices connected via a switch. This example enables Unordered I/O (UIO) on all ports and endpoints to illustrate the correct usage of UIO-related properties. Signed-off-by: Shrihari E S --- docs/system/devices/cxl.rst | 50 +++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 32b1b5d773..c39721b3f9 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -407,6 +407,56 @@ use HDM-DB for coherence, which requires operating in = Flit mode:: -device cxl-type3,bus=3Dswport3,volatile-memdev=3Dcxl-mem3,id=3Dcxl-mem3= ,sn=3D0x4 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k =20 +Unordered I/O (UIO) Support +--------------------------- + +CXL 3.2 and PCIe 6.1 introduce Unordered I/O (UIO), which allows memory +transactions to bypass strict ordering requirements, potentially improving +performance for certain workloads. UIO support requires: + +1. **256-byte Flit Mode**: Enabled via ``x-256b-flit=3Don`` on all ports a= nd devices +2. **Streamlined Virtual Channel (SVC)**: A PCIe 6.1 extended capability t= hat + provides dedicated virtual channels for UIO traffic + +The SVC capability defines two paths for UIO traffic: + +- **SVC3 (Mandatory)**: Dedicated VC for UIO traffic only (``x-uio-svc=3Do= n``) +- **SVC4 (Optional)**: Shared VC for both UIO and non-UIO traffic + (``x-uio-svc-opt=3Don``) + +Both paths require 256B flit mode. The CXL Type 3 device uses the ``x-uio= =3Don`` +property to advertise UIO capability, which is then reflected in the HDM d= ecoder +capability registers. + +**Note**: Per the CXL specification, downstream switch ports do not track = UIO +capability separately; only root ports and upstream ports maintain the UIO +capability. + +An example of 3 type3 devices with volatile memory below a switch. All the= devices +and ports support Unordered IO (UIO) feature which requires Streamlined Vi= rtual Channel +(SVC) capability and Flit mode:: + + qemu-system-x86_64 -M q35,cxl=3Don -m 4G,maxmem=3D8G,slots=3D8 -smp 4 \ + ... + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Drp13,chassis=3D0,slot=3D2,x-uio= -svc=3Don, + x-uio-svc-opt=3Don,x-256b-flit=3Don,x-speed=3D64,x-width=3D32 \ + -device cxl-upstream,port=3D2,sn=3D1234,bus=3Drp13,id=3Dus0,x-uio-svc=3D= on, + x-uio-svc-opt=3Don,x-256b-flit=3Don,x-speed=3D64,x-width=3D32 \ + -device cxl-downstream,port=3D0,bus=3Dus0,id=3Dswport0,chassis=3D0,slot= =3D4, + x-uio-svc=3Don,x-uio-svc-opt=3Don,x-256b-flit=3Don,x-speed=3D64,x-width= =3D32 \ + -device cxl-downstream,port=3D1,bus=3Dus0,id=3Dswport1,chassis=3D0,slot= =3D5, + x-uio-svc=3Don,x-uio-svc-opt=3Don,x-256b-flit=3Don,x-speed=3D64,x-width= =3D32 \ + -device cxl-downstream,port=3D3,bus=3Dus0,id=3Dswport2,chassis=3D0,slot= =3D6, + x-uio-svc=3Don,x-uio-svc-opt=3Don,x-256b-flit=3Don,x-speed=3D64,x-width= =3D32 \ + -object memory-backend-ram,id=3Dtarget-mem1,size=3D512M \ + -object memory-backend-ram,id=3Dtarget-mem2,size=3D512M \ + -object memory-backend-ram,id=3Dtarget-mem3,size=3D512M \ + -device cxl-type3,id=3Dmem1,bus=3Dswport0,volatile-memdev=3Dtarget-mem1,= x-uio=3Don,x-256b-flit=3Don,sn=3D1233 \ + -device cxl-type3,id=3Dmem2,bus=3Dswport1,volatile-memdev=3Dtarget-mem2,= x-uio=3Don,x-256b-flit=3Don,sn=3D1234 \ + -device cxl-type3,id=3Dmem3,bus=3Dswport2,volatile-memdev=3Dtarget-mem3,= x-uio=3Don,x-256b-flit=3Don,sn=3D1235 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k + A simple arm/virt example featuring a single direct connected CXL Type 3 Volatile Memory device:: =20 --=20 2.34.1