This series introduces enumeration and configuration support for the
PCIe Unordered I/O (UIO) feature across standard PCIe and CXL ports.
UIO, introduced in PCIe 6.1, relaxes strict transaction ordering rules. UIO is
a PCIe transaction layer enhancement which shifts the ordering control from
fabric to the requester device.

This implementation establishes the essential architectural foundation
required for the OS to discover, negotiate, and configure UIO
capabilities.

UIO in CXL follows CXL.io protocol, where a CXL device can send read/write
request to peer .mem device's HDM decoder at fabric level.

      __________________________________________
     |                                          |
     |              CXL Host Bridge             |
     |              (Root Port/RC)              |
     |__________________________________________|
                         |
      ___________________|______________________
     |                                          |
     |               CXL Switch                 |
     |__________________________________________|
        |                  |                 |
     ___|____           ___|_____         ___|____
    |        |         |         |       |        |
    | Dev A  |         | Dev B   |       | Dev C  |
    | (Req)  |         |(Target) |       |(Target)|
    |________|         |_________|       |________|


For example, consider the topology shown above, in that if the requester device
(Dev A) wants to read data from the target device (Dev C), then Dev A can
prepare UIO command with the targeted HPA of Dev C and can send directly to the
Dev C's HDM decoder at switch level. Here host gets bypassed in the data path.
For this to happen, both the devices and the intermediate fabrics should support
UIO and its dependencies.

The implementation relies on two key dependencies:
    - 256B Flit Mode 
    - Streamlined Virtual Channel (SVC) Extended Capability (from PCIe 6.1)

Key changes include:

SVC Capability: Introduced a new hw/pci/pcie_svc.c module to manage the SVC
                extended capability. It handles the mapping of UIO traffic to
                dedicated virtual channels-VC3 (mandatory) and VC4 (optional).

Port Configuration: Added properties (x-uio-svc, x-uio-svc-opt, x-256b-flit) to
                    PCIe and CXL ports to control UIO states.

CXL Integration: Established a dependency chain in CXL root and upstream ports,
                 where UIO is enabled only if both Flit Mode and SVC initialization
                 succeed. The CXL HDM decoders now advertise UIO support per CXL 4.0
                 specifications.

Patch Layout:

Patch 1 and 2: Refactoring: Move Flit mode handling from PCIe slot to PCIe port
               and extend it to all port types.
Patch 3: Properties: Add SVC capability fields and UIO-related properties
         (x-uio-svc, x-uio-svc-opt) to the PCIe port hierarchy.
Patch 4: CXL Properties: Extend SVC properties to CXL ports and add uio_capable
         logic to root/upstream ports.
Patch 5: CXL HDM Decoder: Integrate UIO capability advertising into CXL HDM 
         decoders.
Patch 6: SVC Module: Implement the core PCIe SVC Extended Capability logic
         in pcie_svc.c.
Patch 7: Integration: Hook SVC initialization into the realize functions
         for all PCIe and CXL ports.
Patch 8: Documentation: Add usage examples for UIO-enabled CXL topologies.

Base commit: 3c99db7705c1a885c795b7c14f751c7a3ba29ed8
Repository: https://gitlab.com/jic23/qemu
Branch: cxl-2026-01-09-draft

Testing: Verified through Linux kernel based enumeration and configuration.

Future work: While the current series establishes the configuration
infrastructure, the upcoming series focuses on UIO data transfer support.
A subsequent patch series to be built on top of this series to add support for
UIO data plane.

Shrihari E S (8):
  Refactor flitmode from PCIESlot to PCIEPort.
  Move 'x-256b-flit' property from cxl_root_port to pcie_root_port.
  Add SVC capability and UIO properties to PCIe ports
  Add Streamlined Virtual Channel (SVC) property to CXL ports
  Wire UIO capability into HDM decoder registers
  Add PCIe Streamlined Virtual Channel (SVC) capability.
  Wire SVC initialization into port realize functions.
  Add documentation for UIO-enabled CXL devices

 docs/system/devices/cxl.rst               |  50 +++++++
 hw/cxl/cxl-component-utils.c              |  29 +++-
 hw/mem/cxl_type3.c                        |   9 +-
 hw/pci-bridge/cxl_downstream.c            |  11 +-
 hw/pci-bridge/cxl_root_port.c             |  13 +-
 hw/pci-bridge/cxl_upstream.c              |   9 +-
 hw/pci-bridge/pci_expander_bridge.c       |   3 +-
 hw/pci-bridge/pcie_root_port.c            |   4 +
 hw/pci-bridge/xio3130_downstream.c        |   4 +
 hw/pci-bridge/xio3130_upstream.c          |   9 ++
 hw/pci/meson.build                        |   2 +-
 hw/pci/pci.c                              |   4 +
 hw/pci/pcie.c                             |  53 ++++++-
 hw/pci/pcie_svc.c                         | 164 ++++++++++++++++++++++
 include/hw/cxl/cxl_component.h            |   2 +-
 include/hw/cxl/cxl_device.h               |   2 +
 include/hw/pci-bridge/cxl_upstream_port.h |   1 +
 include/hw/pci/pcie.h                     |   7 +
 include/hw/pci/pcie_port.h                |  23 ++-
 include/hw/pci/pcie_regs.h                |   1 +
 include/hw/pci/pcie_svc.h                 |  91 ++++++++++++
 21 files changed, 466 insertions(+), 25 deletions(-)
 create mode 100644 hw/pci/pcie_svc.c
 create mode 100644 include/hw/pci/pcie_svc.h

-- 
2.34.1