From nobody Tue Aug 25 14:39:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17809989818911012.3426179636397; Tue, 9 Jun 2026 02:56:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wWtB7-00071b-1Y; Tue, 09 Jun 2026 05:55:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wWtAm-0006lS-NL for qemu-devel@nongnu.org; Tue, 09 Jun 2026 05:55:05 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wWtAh-0004tu-1s for qemu-devel@nongnu.org; Tue, 09 Jun 2026 05:55:04 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Bxt3js4idqgDUSAA--.23860S3; Tue, 09 Jun 2026 17:54:52 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJDxSMHg4idqJrGgAA--.28412S8; Tue, 09 Jun 2026 17:54:52 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: Bibo Mao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 06/14] target/loongarch: Use sys_state in tlb_helper.c when accessing CSR registers Date: Tue, 9 Jun 2026 17:28:16 +0800 Message-Id: <20260609092824.227250-7-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20260609092824.227250-1-gaosong@loongson.cn> References: <20260609092824.227250-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxSMHg4idqJrGgAA--.28412S8 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780998983623154100 From: Bibo Mao When accessing CSR registers in file tlb_helper.c, use sys_state rather than env. There is no function change. Signed-off-by: Bibo Mao Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Song Gao Message-ID: <20260605082552.175336-7-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/tcg/tlb_helper.c | 137 +++++++++++++++++------------- 1 file changed, 77 insertions(+), 60 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 892e0eb473..7623f4f9bd 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -36,16 +36,19 @@ static bool tlb_match_asid(bool global, int asid, int t= lb_asid) =20 bool check_ps(CPULoongArchState *env, uint8_t tlb_ps) { + CPUSysState *sys =3D env_sys(env); + if (tlb_ps >=3D 64) { return false; } - return BIT_ULL(tlb_ps) & (env->CSR_PRCFG2); + return BIT_ULL(tlb_ps) & (sys->CSR_PRCFG2); } =20 static void raise_mmu_exception(CPULoongArchState *env, vaddr address, MMUAccessType access_type, TLBRet tlb_erro= r) { CPUState *cs =3D env_cpu(env); + CPUSysState *sys =3D env_sys(env); =20 switch (tlb_error) { default: @@ -62,7 +65,7 @@ static void raise_mmu_exception(CPULoongArchState *env, v= addr address, } else if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D EXCCODE_PIF; } - env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 1); + sys->CSR_TLBRERA =3D FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 1); break; case TLBRET_INVALID: /* TLB match with no valid bit */ @@ -93,19 +96,19 @@ static void raise_mmu_exception(CPULoongArchState *env,= vaddr address, } =20 if (tlb_error =3D=3D TLBRET_NOMATCH) { - env->CSR_TLBRBADV =3D address; + sys->CSR_TLBRBADV =3D address; if (is_la64(env)) { - env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_= 64, + sys->CSR_TLBREHI =3D FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI_= 64, VPPN, extract64(address, 13, 35)); } else { - env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_= 32, + sys->CSR_TLBREHI =3D FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI_= 32, VPPN, extract64(address, 13, 19)); } } else { - if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { - env->CSR_BADV =3D address; + if (!FIELD_EX64(sys->CSR_DBG, CSR_DBG, DST)) { + sys->CSR_BADV =3D address; } - env->CSR_TLBEHI =3D address & (TARGET_PAGE_MASK << 1); + sys->CSR_TLBEHI =3D address & (TARGET_PAGE_MASK << 1); } } =20 @@ -142,8 +145,9 @@ static void invalidate_tlb(CPULoongArchState *env, int = index) LoongArchTLB *tlb; uint16_t csr_asid, tlb_asid, tlb_g; uint8_t tlb_e; + CPUSysState *sys =3D env_sys(env); =20 - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + csr_asid =3D FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID); tlb =3D &env->tlb[index]; tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); if (!tlb_e) { @@ -165,25 +169,26 @@ static void sptw_prepare_context(CPULoongArchState *e= nv, MMUContext *context) { uint64_t lo0, lo1, csr_vppn; uint8_t csr_ps; + CPUSysState *sys =3D env_sys(env); =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - csr_ps =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + csr_ps =3D FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI, PS); if (is_la64(env)) { - csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN= ); + csr_vppn =3D FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI_64, VPPN= ); } else { - csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN= ); + csr_vppn =3D FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI_32, VPPN= ); } - lo0 =3D env->CSR_TLBRELO0; - lo1 =3D env->CSR_TLBRELO1; + lo0 =3D sys->CSR_TLBRELO0; + lo1 =3D sys->CSR_TLBRELO1; } else { - csr_ps =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + csr_ps =3D FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, PS); if (is_la64(env)) { - csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN); + csr_vppn =3D FIELD_EX64(sys->CSR_TLBEHI, CSR_TLBEHI_64, VPPN); } else { - csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN); + csr_vppn =3D FIELD_EX64(sys->CSR_TLBEHI, CSR_TLBEHI_32, VPPN); } - lo0 =3D env->CSR_TLBELO0; - lo1 =3D env->CSR_TLBELO1; + lo0 =3D sys->CSR_TLBELO0; + lo1 =3D sys->CSR_TLBELO1; } =20 context->ps =3D csr_ps; @@ -198,6 +203,7 @@ static void fill_tlb_entry(CPULoongArchState *env, Loon= gArchTLB *tlb, uint64_t lo0, lo1, csr_vppn; uint16_t csr_asid; uint8_t csr_ps; + CPUSysState *sys =3D env_sys(env); =20 csr_vppn =3D context->addr >> R_TLB_MISC_VPPN_SHIFT; csr_ps =3D context->ps; @@ -208,7 +214,7 @@ static void fill_tlb_entry(CPULoongArchState *env, Loon= gArchTLB *tlb, tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + csr_asid =3D FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid); =20 tlb->tlb_entry0 =3D lo0; @@ -241,8 +247,9 @@ static LoongArchTLB *loongarch_tlb_search_cb(CPULoongAr= chState *env, bool tlb_g; int i, compare_shift; uint64_t vpn, tlb_vppn; + CPUSysState *sys =3D env_sys(env); =20 - stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); + stlb_ps =3D FIELD_EX64(sys->CSR_STLBPS, CSR_STLBPS, PS); vpn =3D (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1); stlb_idx =3D vpn & 0xff; /* VA[25:15] <=3D=3D> TLBIDX.index for 16KiB = Page */ compare_shift =3D stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; @@ -289,9 +296,10 @@ static bool loongarch_tlb_search(CPULoongArchState *en= v, vaddr vaddr, int csr_asid; tlb_match func; LoongArchTLB *tlb; + CPUSysState *sys =3D env_sys(env); =20 func =3D tlb_match_any; - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + csr_asid =3D FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID); tlb =3D loongarch_tlb_search_cb(env, vaddr, csr_asid, func); if (tlb) { *index =3D tlb - env->tlb; @@ -304,20 +312,21 @@ static bool loongarch_tlb_search(CPULoongArchState *e= nv, vaddr vaddr, void helper_tlbsrch(CPULoongArchState *env) { int index, match; + CPUSysState *sys =3D env_sys(env); =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - match =3D loongarch_tlb_search(env, env->CSR_TLBREHI, &index); + if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + match =3D loongarch_tlb_search(env, sys->CSR_TLBREHI, &index); } else { - match =3D loongarch_tlb_search(env, env->CSR_TLBEHI, &index); + match =3D loongarch_tlb_search(env, sys->CSR_TLBEHI, &index); } =20 if (match) { - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX,= index); - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0); + sys->CSR_TLBIDX =3D FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX,= index); + sys->CSR_TLBIDX =3D FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 0); return; } =20 - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1); + sys->CSR_TLBIDX =3D FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 1); } =20 void helper_tlbrd(CPULoongArchState *env) @@ -325,29 +334,30 @@ void helper_tlbrd(CPULoongArchState *env) LoongArchTLB *tlb; int index; uint8_t tlb_ps, tlb_e; + CPUSysState *sys =3D env_sys(env); =20 - index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + index =3D FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX); tlb =3D &env->tlb[index]; tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); =20 if (!tlb_e) { /* Invalid TLB entry */ - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1); - env->CSR_ASID =3D FIELD_DP64(env->CSR_ASID, CSR_ASID, ASID, 0); - env->CSR_TLBEHI =3D 0; - env->CSR_TLBELO0 =3D 0; - env->CSR_TLBELO1 =3D 0; - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, PS, 0); + sys->CSR_TLBIDX =3D FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 1); + sys->CSR_ASID =3D FIELD_DP64(sys->CSR_ASID, CSR_ASID, ASID, 0); + sys->CSR_TLBEHI =3D 0; + sys->CSR_TLBELO0 =3D 0; + sys->CSR_TLBELO1 =3D 0; + sys->CSR_TLBIDX =3D FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, PS, 0); } else { /* Valid TLB entry */ - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0); - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, + sys->CSR_TLBIDX =3D FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, NE, 0); + sys->CSR_TLBIDX =3D FIELD_DP64(sys->CSR_TLBIDX, CSR_TLBIDX, PS, (tlb_ps & 0x3f)); - env->CSR_TLBEHI =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) << + sys->CSR_TLBEHI =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) << R_TLB_MISC_VPPN_SHIFT; - env->CSR_TLBELO0 =3D tlb->tlb_entry0; - env->CSR_TLBELO1 =3D tlb->tlb_entry1; + sys->CSR_TLBELO0 =3D tlb->tlb_entry0; + sys->CSR_TLBELO1 =3D tlb->tlb_entry1; } } =20 @@ -380,10 +390,11 @@ static void update_tlb_index(CPULoongArchState *env, = MMUContext *context, =20 void helper_tlbwr(CPULoongArchState *env) { - int index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + CPUSysState *sys =3D env_sys(env); + int index =3D FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX); MMUContext context; =20 - if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) { + if (FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, NE)) { invalidate_tlb(env, index); return; } @@ -400,10 +411,11 @@ static int get_tlb_random_index(CPULoongArchState *en= v, vaddr addr, uint16_t asid, tlb_asid, stlb_ps; LoongArchTLB *tlb; uint8_t tlb_e, tlb_g; + CPUSysState *sys =3D env_sys(env); =20 /* Validity of stlb_ps is checked in helper_csrwr_stlbps() */ - stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + stlb_ps =3D FIELD_EX64(sys->CSR_STLBPS, CSR_STLBPS, PS); + asid =3D FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID); if (pagesize =3D=3D stlb_ps) { /* Only write into STLB bits [47:13] */ address =3D addr & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT); @@ -461,15 +473,16 @@ void helper_tlbfill(CPULoongArchState *env) vaddr entryhi; int index, pagesize; MMUContext context; + CPUSysState *sys =3D env_sys(env); =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - entryhi =3D env->CSR_TLBREHI; + if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + entryhi =3D sys->CSR_TLBREHI; /* Validity of pagesize is checked in helper_ldpte() */ - pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + pagesize =3D FIELD_EX64(sys->CSR_TLBREHI, CSR_TLBREHI, PS); } else { - entryhi =3D env->CSR_TLBEHI; + entryhi =3D sys->CSR_TLBEHI; /* Validity of pagesize is checked in helper_tlbrd() */ - pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + pagesize =3D FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, PS); } =20 sptw_prepare_context(env, &context); @@ -483,9 +496,10 @@ void helper_tlbclr(CPULoongArchState *env) LoongArchTLB *tlb; int i, index; uint16_t csr_asid, tlb_asid, tlb_g; + CPUSysState *sys =3D env_sys(env); =20 - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); - index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + csr_asid =3D FIELD_EX64(sys->CSR_ASID, CSR_ASID, ASID); + index =3D FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX); =20 if (index < LOONGARCH_STLB) { /* STLB. One line per operation */ @@ -515,8 +529,9 @@ void helper_tlbclr(CPULoongArchState *env) void helper_tlbflush(CPULoongArchState *env) { int i, index; + CPUSysState *sys =3D env_sys(env); =20 - index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + index =3D FIELD_EX64(sys->CSR_TLBIDX, CSR_TLBIDX, INDEX); =20 if (index < LOONGARCH_STLB) { /* STLB. One line per operation */ @@ -711,6 +726,7 @@ target_ulong helper_lddir(CPULoongArchState *env, targe= t_ulong base, uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint64_t val; + CPUSysState *sys =3D env_sys(env); =20 if (unlikely((level =3D=3D 0) || (level > 4))) { qemu_log_mask(LOG_GUEST_ERROR, @@ -732,7 +748,7 @@ target_ulong helper_lddir(CPULoongArchState *env, targe= t_ulong base, } } =20 - badvaddr =3D env->CSR_TLBRBADV; + badvaddr =3D sys->CSR_TLBRBADV; base =3D base & palen_mask; get_dir_base_width(env, &dir_base, &dir_width, level); index =3D (badvaddr >> dir_base) & ((1 << dir_width) - 1); @@ -747,10 +763,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulon= g base, target_ulong odd, { CPUState *cs =3D env_cpu(env); hwaddr phys, tmp0, ptindex, ptoffset0, ptoffset1; + CPUSysState *sys =3D env_sys(env); uint64_t pte_raw; uint64_t badv; - uint64_t ptbase =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE); - uint64_t ptwidth =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH); + uint64_t ptbase =3D FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, PTBASE); + uint64_t ptwidth =3D FIELD_EX64(sys->CSR_PWCL, CSR_PWCL, PTWIDTH); uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint8_t ps; @@ -796,7 +813,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, return; } } else { - badv =3D env->CSR_TLBRBADV; + badv =3D sys->CSR_TLBRBADV; =20 base =3D base & palen_mask; =20 @@ -812,11 +829,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulon= g base, target_ulong odd, } =20 if (odd) { - env->CSR_TLBRELO1 =3D tmp0; + sys->CSR_TLBRELO1 =3D tmp0; } else { - env->CSR_TLBRELO0 =3D tmp0; + sys->CSR_TLBRELO0 =3D tmp0; } - env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps); + sys->CSR_TLBREHI =3D FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI, PS, ps); } =20 static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, --=20 2.54.0