From nobody Mon Aug 24 20:43:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780998932930265.514035187995; Tue, 9 Jun 2026 02:55:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wWtAw-0006nk-AB; Tue, 09 Jun 2026 05:55:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wWtAm-0006lP-CI for qemu-devel@nongnu.org; Tue, 09 Jun 2026 05:55:05 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wWtAg-0004sz-Pn for qemu-devel@nongnu.org; Tue, 09 Jun 2026 05:55:02 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxVXjq4idqdjUSAA--.23783S3; Tue, 09 Jun 2026 17:54:50 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJDxSMHg4idqJrGgAA--.28412S4; Tue, 09 Jun 2026 17:54:49 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: Bibo Mao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/14] target/loongarch: Use sys_state in cpu.c when accessing CSR registers Date: Tue, 9 Jun 2026 17:28:12 +0800 Message-Id: <20260609092824.227250-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20260609092824.227250-1-gaosong@loongson.cn> References: <20260609092824.227250-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxSMHg4idqJrGgAA--.28412S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780998938299154100 From: Bibo Mao When accessing CSR register in file cpu.c, use sys_state rather than env. Signed-off-by: Bibo Mao Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Song Gao Message-ID: <20260605082552.175336-3-maobibo@loongson.cn> Signed-off-by: Song Gao --- target/loongarch/cpu.c | 114 ++++++++++++++++++++++------------------- target/loongarch/cpu.h | 5 +- 2 files changed, 63 insertions(+), 56 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 13de1722de..8424f185f2 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -62,6 +62,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) LoongArchCPU *cpu =3D opaque; CPULoongArchState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); + CPUSysState *sys =3D env_sys(env); =20 if (irq < 0 || irq >=3D N_IRQS) { return; @@ -70,8 +71,8 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) if (kvm_enabled()) { kvm_loongarch_set_interrupt(cpu, irq, level); } else if (tcg_enabled()) { - env->CSR_ESTAT =3D deposit64(env->CSR_ESTAT, irq, 1, level !=3D 0); - if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { + sys->CSR_ESTAT =3D deposit64(sys->CSR_ESTAT, irq, 1, level !=3D 0); + if (FIELD_EX64(sys->CSR_ESTAT, CSR_ESTAT, IS)) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -84,9 +85,10 @@ bool cpu_loongarch_hw_interrupts_pending(CPULoongArchSta= te *env) { uint32_t pending; uint32_t status; + CPUSysState *sys =3D env_sys(env); =20 - pending =3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); - status =3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); + pending =3D FIELD_EX64(sys->CSR_ESTAT, CSR_ESTAT, IS); + status =3D FIELD_EX64(sys->CSR_ECFG, CSR_ECFG, LIE); =20 return (pending & status) !=3D 0; } @@ -112,11 +114,12 @@ static void loongarch_la464_init_csr(DeviceState *dev) static bool initialized; LoongArchCPU *cpu =3D LOONGARCH_CPU(dev); CPULoongArchState *env =3D &cpu->env; + CPUSysState *sys =3D env_sys(env); int i, num; =20 if (!initialized) { initialized =3D true; - num =3D FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); + num =3D FIELD_EX64(sys->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); for (i =3D num; i < 16; i++) { set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED); } @@ -275,6 +278,7 @@ static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; + CPUSysState *sys; uint32_t data =3D 0, field; int i; =20 @@ -382,18 +386,19 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); env->cpucfg[20] =3D data; =20 - env->CSR_ASID =3D FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); + sys =3D env_sys(env); + sys->CSR_ASID =3D FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); =20 - env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, = 8); - env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS= , 0x2f); - env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); + sys->CSR_PRCFG1 =3D FIELD_DP64(sys->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, = 8); + sys->CSR_PRCFG1 =3D FIELD_DP64(sys->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS= , 0x2f); + sys->CSR_PRCFG1 =3D FIELD_DP64(sys->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); =20 - env->CSR_PRCFG2 =3D 0x3ffff000; + sys->CSR_PRCFG2 =3D 0x3ffff000; =20 - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, = 2); - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY= , 63); - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS,= 7); - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); + sys->CSR_PRCFG3 =3D FIELD_DP64(sys->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, = 2); + sys->CSR_PRCFG3 =3D FIELD_DP64(sys->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY= , 63); + sys->CSR_PRCFG3 =3D FIELD_DP64(sys->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS,= 7); + sys->CSR_PRCFG3 =3D FIELD_DP64(sys->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); =20 cpu->msgint =3D ON_OFF_AUTO_OFF; cpu->ptw =3D ON_OFF_AUTO_OFF; @@ -595,6 +600,7 @@ static void loongarch_cpu_reset_hold(Object *obj, Reset= Type type) CPUState *cs =3D CPU(obj); LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(obj); CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *sys =3D env_sys(env); =20 if (lacc->parent_phases.hold) { lacc->parent_phases.hold(obj, type); @@ -618,55 +624,55 @@ static void loongarch_cpu_reset_hold(Object *obj, Res= etType type) =20 int n; /* Set csr registers value after reset, see the manual 6.4. */ - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0); - - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); - - env->CSR_MISC =3D 0; - - env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); - env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); - - env->CSR_ESTAT =3D env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); - env->CSR_RVACFG =3D FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); - env->CSR_CPUID =3D cs->cpu_index; - env->CSR_TCFG =3D FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); - env->CSR_LLBCTL =3D FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); - env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); - env->CSR_MERRCTL =3D FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); - env->CSR_TID =3D cs->cpu_index; + sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PLV, 0); + sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, IE, 0); + sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DA, 1); + sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PG, 0); + sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DATF, 0); + sys->CSR_CRMD =3D FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DATM, 0); + + sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, FPE, 0); + sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, SXE, 0); + sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, ASXE, 0); + sys->CSR_EUEN =3D FIELD_DP64(sys->CSR_EUEN, CSR_EUEN, BTE, 0); + + sys->CSR_MISC =3D 0; + + sys->CSR_ECFG =3D FIELD_DP64(sys->CSR_ECFG, CSR_ECFG, VS, 0); + sys->CSR_ECFG =3D FIELD_DP64(sys->CSR_ECFG, CSR_ECFG, LIE, 0); + + sys->CSR_ESTAT =3D sys->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); + sys->CSR_RVACFG =3D FIELD_DP64(sys->CSR_RVACFG, CSR_RVACFG, RBITS, 0); + sys->CSR_CPUID =3D cs->cpu_index; + sys->CSR_TCFG =3D FIELD_DP64(sys->CSR_TCFG, CSR_TCFG, EN, 0); + sys->CSR_LLBCTL =3D FIELD_DP64(sys->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); + sys->CSR_TLBRERA =3D FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); + sys->CSR_MERRCTL =3D FIELD_DP64(sys->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); + sys->CSR_TID =3D cs->cpu_index; /* * Workaround for edk2-stable202408, CSR PGD register is set only if * its value is equal to zero for boot cpu, it causes reboot issue. * * Here clear CSR registers relative with TLB. */ - env->CSR_PGDH =3D 0; - env->CSR_PGDL =3D 0; - env->CSR_PWCH =3D 0; - env->CSR_EENTRY =3D 0; - env->CSR_TLBRENTRY =3D 0; - env->CSR_MERRENTRY =3D 0; + sys->CSR_PGDH =3D 0; + sys->CSR_PGDL =3D 0; + sys->CSR_PWCH =3D 0; + sys->CSR_EENTRY =3D 0; + sys->CSR_TLBRENTRY =3D 0; + sys->CSR_MERRENTRY =3D 0; /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */ - if (env->CSR_PRCFG2 =3D=3D 0) { - env->CSR_PRCFG2 =3D 0x3fffff000; + if (sys->CSR_PRCFG2 =3D=3D 0) { + sys->CSR_PRCFG2 =3D 0x3fffff000; } - tlb_ps =3D ctz32(env->CSR_PRCFG2); - env->CSR_STLBPS =3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps= ); - env->CSR_PWCL =3D FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); + tlb_ps =3D ctz32(sys->CSR_PRCFG2); + sys->CSR_STLBPS =3D FIELD_DP64(sys->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps= ); + sys->CSR_PWCL =3D FIELD_DP64(sys->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); for (n =3D 0; n < 4; n++) { - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); + sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV0, 0); + sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV1, 0); + sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV2, 0); + sys->CSR_DMW[n] =3D FIELD_DP64(sys->CSR_DMW[n], CSR_DMW, PLV3, 0); } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index b087548295..906470f59b 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -503,8 +503,9 @@ static inline bool is_va32(CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 =3D !is_la64(env); - uint64_t plv =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - if (plv >=3D 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << p= lv))) { + CPUSysState *sys =3D env_sys(env); + uint64_t plv =3D FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PLV); + if (plv >=3D 1 && (FIELD_EX64(sys->CSR_MISC, CSR_MISC, VA32) & (1 << p= lv))) { va32 =3D true; } return va32; --=20 2.54.0