From nobody Sun Jun 7 22:19:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=proton.me ARC-Seal: i=1; a=rsa-sha256; t=1780856621; cv=none; d=zohomail.com; s=zohoarc; b=OjmFFZwHQdzLHWLm/RN+StnkCuqcVbp/Gvalf3X7k/iX2CgFrCFaUIYVpGcFpiWG35eVubsKioh+Rma0Hl1El1yD/WttFpZDdJzRuyG3LDNymmSibYoj01iGPED/kUkAjk8k7LkzSrPIBeCc+cu/kQPBIk1m0VmLpVDiCaDKOek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780856621; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZQdAkYVIFVaTOqJuW8j/vIjhopqCarqaDjawrzt2kCU=; b=TLN+GdSe6qGgQurlkHKffuDvdRpv/kqYSJnSNKlOAQFysCwLz4urrsxtsZLiKoi96kKXZyfQA1edialDliu3gjmUPGki2tpf1u/IvOSQHSgl+KIPwYrWWPUpHfBnvBY9o2q2inz68NyODyTvyAVJqOBbxoa5gQfLKso239LjA/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780856621538695.6642555238111; Sun, 7 Jun 2026 11:23:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wWI8z-0008Ia-Dd; Sun, 07 Jun 2026 14:22:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wWI8x-0008Hf-Rt; Sun, 07 Jun 2026 14:22:43 -0400 Received: from mail-07.mail-europe.com ([188.165.51.139]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wWI8u-0001L7-KV; Sun, 07 Jun 2026 14:22:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1780856551; x=1781115751; bh=ZQdAkYVIFVaTOqJuW8j/vIjhopqCarqaDjawrzt2kCU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Lkr51H0LOWhOiK+d/yEhs+wrIyZOTkXPZxXLD/vUJv6Sg5olJHoAiAERomCsUQNNU 589prkdYzL4olq3Eks09E5rqyiS/JPrW+pUeLm9yZteZSpqFLNswG7UW08VL9chssY 1jtWBpA5BlQ+xoGrpua0O3lX8+pdY28Am8H6bNMz5wxbKGZvcyJ+d3mRC1jrSmtjc6 pSaJWg1hcTdGtnnJRgGLkvR83x8Hd5OSrw/IrkI5mAz0W8aDAUJuGymbcbPTVlYYkR 45HEpWUF3OQIJsrsja+Iue69vbxaJTUy5LiQnhL7mVqc2f3Dy6ZKmPAyCnbA46zSjH jCBDpnr+6Ou5g== Date: Sun, 07 Jun 2026 18:22:26 +0000 To: agraf@csgraf.de, peter.maydell@linaro.org From: Jason Wright Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, zenghui.yu@linux.dev, richard.henderson@linaro.org Subject: [PATCH] target/arm/hvf: manually sync ID_AA64ISAR0_EL1 on vCPU init Message-ID: <20260607182221.4357-1-wrigjl@proton.me> In-Reply-To: <745e66c7-2a9b-4185-bae7-77e10623332b@linux.dev> References: <20260529114723.42040-1-peter.maydell@linaro.org> <20260529114723.42040-18-peter.maydell@linaro.org> <745e66c7-2a9b-4185-bae7-77e10623332b@linux.dev> Feedback-ID: 198029889:user:proton X-Pm-Message-ID: 00ef15f4273d06cd7b6cf38421dc48d0aeef72f8 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=188.165.51.139; envelope-from=wrigjl@proton.me; helo=mail-07.mail-europe.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @proton.me) X-ZM-MESSAGEID: 1780856624850158500 Content-Type: text/plain; charset="utf-8" Commit 887eaa8a29 ("target/arm: implement FEAT_RNG_TRAP for RNDR/RNDRRS") gave ID_AA64ISAR0_EL1 a readfn so the RNDR field can reflect SCR_EL3.TRNDR at read time, and marked the cpreg ARM_CP_NO_RAW in the system-emulation path. HVF then trips its hvf_arch_init_vcpu() assertion that no ID register in hvf_sreg_list[] is NO_RAW, aborting on boot on Apple Silicon: Assertion failed: (!(ri->type & ARM_CP_NO_RAW)), function hvf_arch_init_vcpu, file hvf.c, line 1442. Reproduce with: qemu-system-aarch64 -M virt,accel=3Dhvf -cpu host \ -nographic -display none -bios /dev/null Mirror the existing treatment of ID_AA64PFR0_EL1: move HV_SYS_REG_ID_AA64ISAR0_EL1 into the SYNC_NO_RAW_REGS block in sysreg.c.inc so the assert loop skips it, and push QEMU's view of the register to the vCPU at init time. HVF does not expose EL3, so SCR_EL3.TRNDR is never set and the readfn is functionally static there. Reported-by: Zenghui Yu Fixes: 887eaa8a29 ("target/arm: implement FEAT_RNG_TRAP for RNDR/RNDRRS") Signed-off-by: Jason Wright --- target/arm/hvf/hvf.c | 4 ++++ target/arm/hvf/sysreg.c.inc | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index d88cbe7c82..afa1120c8a 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1485,6 +1485,10 @@ int hvf_arch_init_vcpu(CPUState *cpu) ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1= , pfr); assert_hvf_ok(ret); =20 + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64ISAR0_EL= 1, + GET_IDREG(&arm_cpu->isar, ID_AA64ISAR0)); + assert_hvf_ok(ret); + /* We're limited to underlying hardware caps, override internal versio= ns */ ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, &arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc index c11dbf274e..acd5a41364 100644 --- a/target/arm/hvf/sysreg.c.inc +++ b/target/arm/hvf/sysreg.c.inc @@ -89,13 +89,13 @@ DEF_SYSREG(HV_SYS_REG_MDCCINT_EL1, 2, 0, 0, 2, 0) DEF_SYSREG(HV_SYS_REG_MIDR_EL1, 3, 0, 0, 0, 0) DEF_SYSREG(HV_SYS_REG_MPIDR_EL1, 3, 0, 0, 0, 5) DEF_SYSREG(HV_SYS_REG_ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) #endif =20 DEF_SYSREG(HV_SYS_REG_ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) /* Add ID_AA64PFR2_EL1 here when HVF supports it */ DEF_SYSREG(HV_SYS_REG_ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF_SYSREG(HV_SYS_REG_ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) -DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF_SYSREG(HV_SYS_REG_ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) =20 #ifdef SYNC_NO_MMFR0 --=20 2.50.1 (Apple Git-155)