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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=202.12.124.151; envelope-from=chad@jablonski.xyz; helo=fout-b8-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1780775613456158500 Content-Type: text/plain; charset="utf-8" Move register write logic into its own function. This is in preparation for CCE engine support for register writes. MMIO writes will have their own distinct policy that doesn't apply to writes made by the CCE engine. Note: Because of the recursion in the MM_DATA handler the calls to ati_mm_write needed to be changed to ati_reg_write. This means that tracing output changes slightly for MM_DATA writes. Otherwise, this is purely a refactor and does not change behavior. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 58 ++++++++++++++++++++++++++------------------ hw/display/ati_int.h | 2 ++ 2 files changed, 36 insertions(+), 24 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index d77589df67..b4c9086188 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -562,32 +562,10 @@ static inline void ati_reg_write_offs(uint32_t *reg, = int offs, } } =20 -static void ati_mm_write(void *opaque, hwaddr addr, - uint64_t data, unsigned int size) +void ati_reg_write(ATIVGAState *s, hwaddr addr, + uint64_t data, unsigned int size) { - ATIVGAState *s =3D opaque; - - if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { - trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); - } switch (addr) { - case MM_INDEX: - s->regs.mm_index =3D data & ~3; - break; - case MM_DATA ... MM_DATA + 3: - /* indexed access to regs or memory */ - if (s->regs.mm_index & BIT(31)) { - uint32_t idx =3D s->regs.mm_index & ~BIT(31); - if (idx <=3D s->vga.vram_size - size) { - stn_le_p(s->vga.vram_ptr + idx, size, data); - } - } else if (s->regs.mm_index > MM_DATA + 3) { - ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size); - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "ati_mm_write: mm_index too small: %u\n", s->regs.mm_index= ); - } - break; case BIOS_0_SCRATCH ... BUS_CNTL - 1: { int i =3D (addr - BIOS_0_SCRATCH) / 4; @@ -1043,6 +1021,38 @@ static void ati_mm_write(void *opaque, hwaddr addr, } } =20 +static void ati_mm_write(void *opaque, hwaddr addr, + uint64_t data, unsigned int size) +{ + ATIVGAState *s =3D opaque; + + if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { + trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); + } + switch (addr) { + case MM_INDEX: + s->regs.mm_index =3D data & ~3; + break; + case MM_DATA ... MM_DATA + 3: + /* indexed access to regs or memory */ + if (s->regs.mm_index & BIT(31)) { + uint32_t idx =3D s->regs.mm_index & ~BIT(31); + if (idx <=3D s->vga.vram_size - size) { + stn_le_p(s->vga.vram_ptr + idx, size, data); + } + } else if (s->regs.mm_index > MM_DATA + 3) { + ati_reg_write(s, s->regs.mm_index + addr - MM_DATA, data, size= ); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "ati_mm_write: mm_index too small: %u\n", s->regs.mm_index= ); + } + break; + default: + ati_reg_write(s, addr, data, size); + break; + } +} + static const MemoryRegionOps ati_mm_ops =3D { .read =3D ati_mm_read, .write =3D ati_mm_write, diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 0c48934d33..18dca730c3 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -128,6 +128,8 @@ struct ATIVGAState { }; =20 const char *ati_reg_name(int num); +void ati_reg_write(ATIVGAState *s, hwaddr addr, + uint64_t data, unsigned int size); =20 void ati_2d_blt(ATIVGAState *s); bool ati_host_data_flush(ATIVGAState *s); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=202.12.124.155; envelope-from=chad@jablonski.xyz; helo=fhigh-b4-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1780775611703158500 Content-Type: text/plain; charset="utf-8" Move read and write register handlers to chip-specific functions so that register differences are defined in one place for each chip. This prepares for differences that occur in CCE setup. The only behavioral change is that the Rage 128 will now return 0 when reading the HOST_PATH_CNTL register. This is technically more correct in that the Rage 128 doesn't have this register. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 351 ++++++++++++++++++++++++++++------------------- 1 file changed, 211 insertions(+), 140 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index b4c9086188..826c856b1c 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -277,11 +277,86 @@ static inline uint32_t ati_reg_read_offs(uint32_t reg= , int offs, } } =20 +static bool ati_r128_mm_read(ATIVGAState *s, hwaddr addr, unsigned int siz= e, + uint32_t *val) +{ + switch (addr) { + case BIOS_0_SCRATCH ... BUS_CNTL - 1: + { + int i =3D (addr - BIOS_0_SCRATCH) / 4; + if (i <=3D 3) { + *val =3D ati_reg_read_offs(s->regs.bios_scratch[i], + addr - (BIOS_0_SCRATCH + i * 4), size= ); + } + break; + } + case DST_PITCH: + *val =3D s->regs.dst_pitch | s->regs.dst_tile << 16; + break; + case SRC_PITCH: + *val =3D s->regs.src_pitch | s->regs.src_tile << 16; + break; + case DEFAULT_OFFSET: + *val =3D s->regs.default_offset; + break; + default: + return false; + } + + return true; +} + +static bool ati_r100_mm_read(ATIVGAState *s, hwaddr addr, unsigned int siz= e, + uint32_t *val) +{ + switch (addr) { + case BIOS_0_SCRATCH ... BUS_CNTL - 1: + { + int i =3D (addr - BIOS_0_SCRATCH) / 4; + *val =3D ati_reg_read_offs(s->regs.bios_scratch[i], + addr - (BIOS_0_SCRATCH + i * 4), size); + break; + } + case HOST_PATH_CNTL: + *val =3D BIT(23); /* Radeon HDP_APER_CNTL */ + break; + case MEM_SDRAM_MODE_REG: + *val =3D BIT(28) | BIT(20); + break; + case DST_PITCH: + *val =3D s->regs.dst_pitch; + break; + case SRC_PITCH: + *val =3D s->regs.src_pitch; + break; + case DEFAULT_OFFSET: + *val =3D s->regs.default_offset >> 10; + *val |=3D s->regs.default_pitch << 16; + *val |=3D s->regs.default_tile << 30; + break; + default: + return false; + } + + return true; +} + static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) { ATIVGAState *s =3D opaque; uint32_t val =3D 0; =20 + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + if (ati_r128_mm_read(s, addr, size, &val)) { + return val; + } + } else { + if (ati_r100_mm_read(s, addr, size, &val)) { + return val; + } + } + + /* Shared Registers */ switch (addr) { case MM_INDEX: val =3D s->regs.mm_index; @@ -300,16 +375,6 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) "ati_mm_read: mm_index too small: %u\n", s->regs.mm_index); } break; - case BIOS_0_SCRATCH ... BUS_CNTL - 1: - { - int i =3D (addr - BIOS_0_SCRATCH) / 4; - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { - break; - } - val =3D ati_reg_read_offs(s->regs.bios_scratch[i], - addr - (BIOS_0_SCRATCH + i * 4), size); - break; - } case GEN_INT_CNTL: val =3D s->regs.gen_int_cntl; break; @@ -371,17 +436,9 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) case CONFIG_REG_APER_SIZE: val =3D memory_region_size(&s->mm) / 2; break; - case HOST_PATH_CNTL: - val =3D BIT(23); /* Radeon HDP_APER_CNTL */ - break; case MC_STATUS: val =3D 5; break; - case MEM_SDRAM_MODE_REG: - if (s->dev_id !=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val =3D BIT(28) | BIT(20); - } - break; case RBBM_STATUS: case GUI_STAT: val =3D 64; /* free CMDFIFO entries */ @@ -436,12 +493,6 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) case DST_OFFSET: val =3D s->regs.dst_offset; break; - case DST_PITCH: - val =3D s->regs.dst_pitch; - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val |=3D s->regs.dst_tile << 16; - } - break; case DST_WIDTH: val =3D s->regs.dst_width; break; @@ -472,12 +523,6 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) case SRC_OFFSET: val =3D s->regs.src_offset; break; - case SRC_PITCH: - val =3D s->regs.src_pitch; - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val |=3D s->regs.src_tile << 16; - } - break; case DP_BRUSH_BKGD_CLR: val =3D s->regs.dp_brush_bkgd_clr; break; @@ -502,14 +547,6 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) case DP_WRITE_MASK: val =3D s->regs.dp_write_mask; break; - case DEFAULT_OFFSET: - val =3D s->regs.default_offset; - if (s->dev_id !=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val >>=3D 10; - val |=3D s->regs.default_pitch << 16; - val |=3D s->regs.default_tile << 30; - } - break; case DEFAULT_PITCH: val =3D s->regs.default_pitch; val |=3D s->regs.default_tile << 16; @@ -562,20 +599,150 @@ static inline void ati_reg_write_offs(uint32_t *reg,= int offs, } } =20 -void ati_reg_write(ATIVGAState *s, hwaddr addr, - uint64_t data, unsigned int size) +static bool ati_r128_reg_write(ATIVGAState *s, hwaddr addr, uint64_t data, + unsigned int size) { switch (addr) { case BIOS_0_SCRATCH ... BUS_CNTL - 1: { int i =3D (addr - BIOS_0_SCRATCH) / 4; - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) { - break; + if (i <=3D 3) { + ati_reg_write_offs(&s->regs.bios_scratch[i], + addr - (BIOS_0_SCRATCH + i * 4), data, size= ); + } + break; + } + case GEN_INT_STATUS: + data &=3D 0x000f040fUL; + s->regs.gen_int_status &=3D ~data; + ati_vga_update_irq(s); + break; + case GPIO_MONID ... GPIO_MONID + 3: + /* Rage128p accesses DDC via MONID(1-2) with additional mask bit */ + ati_reg_write_offs(&s->regs.gpio_monid, + addr - GPIO_MONID, data, size); + if ((s->regs.gpio_monid & BIT(25)) && + ((addr <=3D GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) || + (addr =3D=3D GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) { + s->regs.gpio_monid =3D ati_i2c(&s->bbi2c, s->regs.gpio_monid, = 1); } + break; + case DST_PITCH: + s->regs.dst_pitch =3D data & 0x3fff; + s->regs.dst_tile =3D (data >> 16) & 1; + break; + case SRC_PITCH_OFFSET: + s->regs.src_offset =3D (data & 0x1fffff) << 5; + s->regs.src_pitch =3D (data & 0x7fe00000) >> 21; + s->regs.src_tile =3D data >> 31; + break; + case DST_PITCH_OFFSET: + s->regs.dst_offset =3D (data & 0x1fffff) << 5; + s->regs.dst_pitch =3D (data & 0x7fe00000) >> 21; + s->regs.dst_tile =3D data >> 31; + break; + case SRC_PITCH: + s->regs.src_pitch =3D data & 0x3fff; + s->regs.src_tile =3D (data >> 16) & 1; + break; + case DEFAULT_OFFSET: + s->regs.default_offset =3D data & 0xfffffff0; + break; + case DEFAULT_PITCH: + s->regs.default_pitch =3D data & 0x3fff; + s->regs.default_tile =3D (data >> 16) & 1; + break; + default: + return false; + } + + return true; +} + +static bool ati_r100_reg_write(ATIVGAState *s, hwaddr addr, uint64_t data, + unsigned int size) +{ + switch (addr) { + case BIOS_0_SCRATCH ... BUS_CNTL - 1: + { + int i =3D (addr - BIOS_0_SCRATCH) / 4; ati_reg_write_offs(&s->regs.bios_scratch[i], addr - (BIOS_0_SCRATCH + i * 4), data, size); break; } + case GEN_INT_STATUS: + data &=3D 0xfc080effUL; + s->regs.gen_int_status &=3D ~data; + ati_vga_update_irq(s); + break; + /* + * GPIO regs for DDC access. Because some drivers access these via + * multiple byte writes we have to be careful when we send bits to + * avoid spurious changes in bitbang_i2c state. Only do it when either + * the enable bits are changed or output bits changed while enabled. + */ + case GPIO_VGA_DDC ... GPIO_VGA_DDC + 3: + /* FIXME: Maybe add a property to select VGA or DVI port? */ + break; + case GPIO_DVI_DDC ... GPIO_DVI_DDC + 3: + ati_reg_write_offs(&s->regs.gpio_dvi_ddc, + addr - GPIO_DVI_DDC, data, size); + if ((addr <=3D GPIO_DVI_DDC + 2 && addr + size > GPIO_DVI_DDC + 2)= || + (addr =3D=3D GPIO_DVI_DDC && (s->regs.gpio_dvi_ddc & 0x30000))= ) { + s->regs.gpio_dvi_ddc =3D ati_i2c(&s->bbi2c, + s->regs.gpio_dvi_ddc, 0); + } + break; + case GPIO_MONID ... GPIO_MONID + 3: + /* FIXME What does Radeon have here? */ + break; + case DST_TILE: + s->regs.dst_tile =3D data & 3; + break; + case DST_PITCH: + s->regs.dst_pitch =3D data & 0x3fff; + break; + case SRC_PITCH_OFFSET: + s->regs.src_offset =3D (data & 0x3fffff) << 10; + s->regs.src_pitch =3D (data & 0x3fc00000) >> 16; + s->regs.src_tile =3D (data >> 30) & 1; + break; + case DST_PITCH_OFFSET: + s->regs.dst_offset =3D (data & 0x3fffff) << 10; + s->regs.dst_pitch =3D (data & 0x3fc00000) >> 16; + s->regs.dst_tile =3D data >> 30; + break; + case SRC_PITCH: + s->regs.src_pitch =3D data & 0x3fff; + break; + case DEFAULT_OFFSET: + /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */ + s->regs.default_offset =3D (data & 0x3fffff) << 10; + s->regs.default_pitch =3D (data & 0x3fc00000) >> 16; + s->regs.default_tile =3D data >> 30; + break; + default: + return false; + } + + return true; +} + +void ati_reg_write(ATIVGAState *s, hwaddr addr, + uint64_t data, unsigned int size) +{ + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + if (ati_r128_reg_write(s, addr, data, size)) { + return; + } + } else { + if (ati_r100_reg_write(s, addr, data, size)) { + return; + } + } + + /* Shared Registers */ + switch (addr) { case GEN_INT_CNTL: s->regs.gen_int_cntl =3D data; if (data & CRTC_VBLANK_INT) { @@ -585,12 +752,6 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, ati_vga_update_irq(s); } break; - case GEN_INT_STATUS: - data &=3D (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF ? - 0x000f040fUL : 0xfc080effUL); - s->regs.gen_int_status &=3D ~data; - ati_vga_update_irq(s); - break; case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3: { uint32_t val =3D s->regs.crtc_gen_cntl; @@ -638,41 +799,6 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, s->regs.dac_cntl =3D data & 0xffffe3ff; s->vga.dac_8bit =3D !!(data & DAC_8BIT_EN); break; - /* - * GPIO regs for DDC access. Because some drivers access these via - * multiple byte writes we have to be careful when we send bits to - * avoid spurious changes in bitbang_i2c state. Only do it when either - * the enable bits are changed or output bits changed while enabled. - */ - case GPIO_VGA_DDC ... GPIO_VGA_DDC + 3: - if (s->dev_id !=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - /* FIXME: Maybe add a property to select VGA or DVI port? */ - } - break; - case GPIO_DVI_DDC ... GPIO_DVI_DDC + 3: - if (s->dev_id !=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - ati_reg_write_offs(&s->regs.gpio_dvi_ddc, - addr - GPIO_DVI_DDC, data, size); - if ((addr <=3D GPIO_DVI_DDC + 2 && addr + size > GPIO_DVI_DDC = + 2) || - (addr =3D=3D GPIO_DVI_DDC && (s->regs.gpio_dvi_ddc & 0x300= 00))) { - s->regs.gpio_dvi_ddc =3D ati_i2c(&s->bbi2c, - s->regs.gpio_dvi_ddc, 0); - } - } - break; - case GPIO_MONID ... GPIO_MONID + 3: - /* FIXME What does Radeon have here? */ - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - /* Rage128p accesses DDC via MONID(1-2) with additional mask b= it */ - ati_reg_write_offs(&s->regs.gpio_monid, - addr - GPIO_MONID, data, size); - if ((s->regs.gpio_monid & BIT(25)) && - ((addr <=3D GPIO_MONID + 2 && addr + size > GPIO_MONID + 2= ) || - (addr =3D=3D GPIO_MONID && (s->regs.gpio_monid & 0x60000)= ))) { - s->regs.gpio_monid =3D ati_i2c(&s->bbi2c, s->regs.gpio_mon= id, 1); - } - } - break; case PALETTE_INDEX ... PALETTE_INDEX + 3: if (size =3D=3D 4) { vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff); @@ -800,18 +926,7 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, ati_cursor_define(s); break; case DST_OFFSET: - s->regs.dst_offset =3D data & 0xfffffff0; - break; - case DST_PITCH: - s->regs.dst_pitch =3D data & 0x3fff; - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.dst_tile =3D (data >> 16) & 1; - } - break; - case DST_TILE: - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RADEON_QY) { - s->regs.dst_tile =3D data & 3; - } + s->regs.dst_offset =3D data & 0xfffffff0; break; case DST_WIDTH: s->regs.dst_width =3D data & 0x3fff; @@ -832,28 +947,6 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, case DST_Y: s->regs.dst_y =3D data & 0x3fff; break; - case SRC_PITCH_OFFSET: - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.src_offset =3D (data & 0x1fffff) << 5; - s->regs.src_pitch =3D (data & 0x7fe00000) >> 21; - s->regs.src_tile =3D data >> 31; - } else { - s->regs.src_offset =3D (data & 0x3fffff) << 10; - s->regs.src_pitch =3D (data & 0x3fc00000) >> 16; - s->regs.src_tile =3D (data >> 30) & 1; - } - break; - case DST_PITCH_OFFSET: - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.dst_offset =3D (data & 0x1fffff) << 5; - s->regs.dst_pitch =3D (data & 0x7fe00000) >> 21; - s->regs.dst_tile =3D data >> 31; - } else { - s->regs.dst_offset =3D (data & 0x3fffff) << 10; - s->regs.dst_pitch =3D (data & 0x3fc00000) >> 16; - s->regs.dst_tile =3D data >> 30; - } - break; case SRC_Y_X: s->regs.src_x =3D data & 0x3fff; s->regs.src_y =3D (data >> 16) & 0x3fff; @@ -915,13 +1008,7 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, s->regs.dst_height =3D (data >> 16) & 0x3fff; break; case SRC_OFFSET: - s->regs.src_offset =3D data & 0xfffffff0; - break; - case SRC_PITCH: - s->regs.src_pitch =3D data & 0x3fff; - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.src_tile =3D (data >> 16) & 1; - } + s->regs.src_offset =3D data & 0xfffffff0; break; case DP_BRUSH_BKGD_CLR: s->regs.dp_brush_bkgd_clr =3D data; @@ -947,22 +1034,6 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, case DP_WRITE_MASK: s->regs.dp_write_mask =3D data; break; - case DEFAULT_OFFSET: - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.default_offset =3D data & 0xfffffff0; - } else { - /* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET = */ - s->regs.default_offset =3D (data & 0x3fffff) << 10; - s->regs.default_pitch =3D (data & 0x3fc00000) >> 16; - s->regs.default_tile =3D data >> 30; - } - break; - case DEFAULT_PITCH: - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - s->regs.default_pitch =3D data & 0x3fff; - s->regs.default_tile =3D (data >> 16) & 1; - } - break; case DEFAULT_SC_BOTTOM_RIGHT: s->regs.default_sc_right =3D data & 0x3fff; s->regs.default_sc_bottom =3D (data >> 16) & 0x3fff; --=20 2.53.0 From nobody Sun Jun 7 22:21:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=202.12.124.155; envelope-from=chad@jablonski.xyz; helo=fhigh-b4-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1780775611625158500 Content-Type: text/plain; charset="utf-8" Implement registers used for loading and reading microcode for the CCE engine. Loading the microcode is the first step for any driver implementing CCE. Reading, while not used by drivers, is very helpful for any reverse engineering and testing work. The microcode is currently stored but not used. This lays the groundwork for future RE work on the microcode. There's some quirky behavior around microcode reads that isn't documented elsewhere. There appear to be two internal pointers, one for reading and one for writing that can get out of sync. Comments in the code expand on this. Tested and validated against a Rage 128 Pro Ultra (PCI 1002:5446) and Radeon QY (RV100) (PCI 1002:5159). Signed-off-by: Chad Jablonski --- hw/display/ati.c | 61 ++++++++++++++++++++++++++++++++++++++++++++ hw/display/ati_int.h | 11 ++++++++ 2 files changed, 72 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index 826c856b1c..73fd5e7d23 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -579,6 +579,36 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) qemu_log_mask(LOG_GUEST_ERROR, "Read from write-only register 0x%x\n", (unsigned)ad= dr); break; + /* r100: CP_ME_RAM_ADDR */ + case PM4_MICROCODE_ADDR: + val =3D s->cce.microcode.addr; + break; + /* r100: CP_ME_RAM_RADDR */ + case PM4_MICROCODE_RADDR: + /* Always returns 0. Tested on hardware. */ + val =3D 0; + break; + /* r100: CP_ME_RAM_DATAH */ + case PM4_MICROCODE_DATAH: + val =3D (s->cce.microcode.microcode[s->cce.microcode.raddr] >> 32)= & + 0xffffffff; + break; + /* r100: CP_ME_RAM_DATAL */ + case PM4_MICROCODE_DATAL: + val =3D s->cce.microcode.microcode[s->cce.microcode.raddr] & 0xfff= fffff; + s->cce.microcode.addr +=3D 1; + /* + * The write address (addr) is always copied into the + * read address (raddr) after a DATAL read. This leads + * to surprising behavior when the PM4_MICROCODE_ADDR + * instead of the PM4_MICROCODE_RADDR register is set to + * a value just before a read. The first read after this + * will reflect the previous raddr before incrementing and + * re-syncing with addr. This is expected and observed on + * the hardware. + */ + s->cce.microcode.raddr =3D s->cce.microcode.addr; + break; default: break; } @@ -1087,6 +1117,37 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, ati_host_data_flush(s); } break; + /* r100: CP_ME_RAM_ADDR */ + case PM4_MICROCODE_ADDR: + s->cce.microcode.addr =3D data; + break; + /* r100: CP_ME_RAM_RADDR */ + case PM4_MICROCODE_RADDR: + s->cce.microcode.raddr =3D data; + s->cce.microcode.addr =3D data; + break; + /* r100: CP_ME_RAM_DATAH */ + case PM4_MICROCODE_DATAH: { + uint64_t curr =3D s->cce.microcode.microcode[s->cce.microcode.addr= ]; + uint64_t low =3D curr & 0xffffffff; + /* + * DATAH mask is one bit wider on r100. Avoid duplicating otherwise + * identical handlers for r128 and r100 + */ + uint64_t high =3D (data & (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE= 128_PF ? + 0x1f : 0x3f)) << 32; + s->cce.microcode.microcode[s->cce.microcode.addr] =3D high | low; + break; + } + /* r100: CP_ME_RAM_DATAL */ + case PM4_MICROCODE_DATAL: { + uint64_t curr =3D s->cce.microcode.microcode[s->cce.microcode.addr= ]; + uint64_t low =3D data & 0xffffffff; + uint64_t high =3D curr & (0xffffffffull << 32); + s->cce.microcode.microcode[s->cce.microcode.addr] =3D high | low; + s->cce.microcode.addr +=3D 1; + break; + } default: break; } diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 18dca730c3..eae3e89617 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -105,6 +105,16 @@ typedef struct ATIHostDataState { uint32_t acc[4]; } ATIHostDataState; =20 +typedef struct ATIMicrocodeState { + uint8_t addr; + uint8_t raddr; + uint64_t microcode[256]; +} ATIMicrocodeState; + +typedef struct ATICCEState { + ATIMicrocodeState microcode; +} ATICCEState; + struct ATIVGAState { PCIDevice dev; VGACommonState vga; @@ -125,6 +135,7 @@ struct ATIVGAState { MemoryRegion mm; ATIVGARegs regs; ATIHostDataState host_data; + ATICCEState cce; }; =20 const char *ati_reg_name(int num); --=20 2.53.0 From nobody Sun Jun 7 22:21:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1780775609; cv=none; d=zohomail.com; s=zohoarc; b=X5I2vWBbZc4x3fF5N9O5sHgTkpnD7XzMpcXisZMTe6/bk3PvNkdcg/vCpI1NTxlUh+mteeApoXu88NZE1NjjL7q4QFwzVTirdK9pCW33NMSeJBJxivId66/ZPl0h84aNUMyTAQ7e9nePdB+H2/tfqXt1jO1wl7SSPpa7n0LPPsI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780775609; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=202.12.124.151; envelope-from=chad@jablonski.xyz; helo=fout-b8-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1780775611630158500 Content-Type: text/plain; charset="utf-8" The PM4_BUFFER_CNTL register is used to set up the CCE FIFO for r128. These are straightforward reads and writes. Future CCE patches make use of this state. The PM4_MICRO_CNTL register has a single flag that is used by drivers to enable processing of CCE commands from the CCE FIFO. Reverse engineering uncovered additional debug fields, many of which have an unclear purpose. They have been omitted for now but could be added if needed. These registers are not covered by available register references. They are implemented based on their use in Linux 6.2 (drivers/gpu/drm/r128/r128_cce.c). Signed-off-by: Chad Jablonski --- hw/display/ati.c | 16 ++++++++++++++++ hw/display/ati_int.h | 6 ++++++ hw/display/ati_regs.h | 14 ++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index 73fd5e7d23..7724be863f 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -299,6 +299,14 @@ static bool ati_r128_mm_read(ATIVGAState *s, hwaddr ad= dr, unsigned int size, case DEFAULT_OFFSET: *val =3D s->regs.default_offset; break; + case PM4_BUFFER_CNTL: + *val =3D ((s->cce.buffer_mode & 0xf) << 28) | + (s->cce.no_update << 27) | + (s->cce.buffer_size_l2qw & 0x7ffffff); + break; + case PM4_MICRO_CNTL: + *val =3D s->cce.freerun ? PM4_MICRO_FREERUN : 0; + break; default: return false; } @@ -682,6 +690,14 @@ static bool ati_r128_reg_write(ATIVGAState *s, hwaddr = addr, uint64_t data, s->regs.default_pitch =3D data & 0x3fff; s->regs.default_tile =3D (data >> 16) & 1; break; + case PM4_BUFFER_CNTL: + s->cce.buffer_size_l2qw =3D data & 0x7ffffff; + s->cce.no_update =3D (data >> 27) & 1; + s->cce.buffer_mode =3D (data >> 28) & 0xf; + break; + case PM4_MICRO_CNTL: + s->cce.freerun =3D !!(data & PM4_MICRO_FREERUN); + break; default: return false; } diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index eae3e89617..9259373733 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -113,6 +113,12 @@ typedef struct ATIMicrocodeState { =20 typedef struct ATICCEState { ATIMicrocodeState microcode; + /* MicroCntl */ + bool freerun; + /* BufferCntl */ + uint32_t buffer_size_l2qw; + bool no_update; + uint8_t buffer_mode; } ATICCEState; =20 struct ATIVGAState { diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index b813fa119e..6591c6587f 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -387,7 +387,21 @@ #define PC_BUSY 0x80000000 =20 #define BUS_MASTER_DIS 0x00000040 + +/* PM4_BUFFER_CNTL buffer mode bit constants */ #define PM4_BUFFER_CNTL_NONPM4 0x00000000 +#define PM4_BUFFER_CNTL_192PIO 0x00000001 +#define PM4_BUFFER_CNTL_192BM 0x00000002 +#define PM4_BUFFER_CNTL_128PIO_64INDBM 0x00000003 +#define PM4_BUFFER_CNTL_128BM_64INDBM 0x00000004 +#define PM4_BUFFER_CNTL_64PIO_128INDBM 0x00000005 +#define PM4_BUFFER_CNTL_64BM_128INDBM 0x00000006 +#define PM4_BUFFER_CNTL_64PIO_64VCBM_64INDBM 0x00000007 +#define PM4_BUFFER_CNTL_64BM_64VCBM_64INDBM 0x00000008 +#define PM4_BUFFER_CNTL_64PIO_64VCPIO_64INPIO 0x0000000f + +/* PM4_MICRO_CNTL bit constants */ +#define PM4_MICRO_FREERUN 0x40000000 =20 /* DP_DATATYPE bit constants */ #define DST_8BPP 0x00000002 --=20 2.53.0 From nobody Sun Jun 7 22:21:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=202.12.124.151; envelope-from=chad@jablonski.xyz; helo=fout-b8-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1780775621952158500 Content-Type: text/plain; charset="utf-8" CCE setup for the r100 is simpler in that it defaults to freerun. The mode just needs to be set via the CP_CSQ_CNTL register. Modes are explicitly stated to be compatible with r128 by the M6 register reference guide. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 8 ++++++++ hw/display/ati_regs.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index 7724be863f..e1ba64747b 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -342,6 +342,9 @@ static bool ati_r100_mm_read(ATIVGAState *s, hwaddr add= r, unsigned int size, *val |=3D s->regs.default_pitch << 16; *val |=3D s->regs.default_tile << 30; break; + case CP_CSQ_CNTL: + *val =3D s->cce.buffer_mode << 28; + break; default: return false; } @@ -767,6 +770,9 @@ static bool ati_r100_reg_write(ATIVGAState *s, hwaddr a= ddr, uint64_t data, s->regs.default_pitch =3D (data & 0x3fc00000) >> 16; s->regs.default_tile =3D data >> 30; break; + case CP_CSQ_CNTL: + s->cce.buffer_mode =3D (data >> 28) & 0xf; + break; default: return false; } @@ -1318,6 +1324,8 @@ static void ati_vga_reset(DeviceState *dev) s->host_data.next =3D 0; s->host_data.row =3D 0; s->host_data.col =3D 0; + memset(&s->cce, 0, sizeof(s->cce)); + s->cce.freerun =3D s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF ? 0 := 1; } =20 static void ati_vga_exit(PCIDevice *dev) diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 6591c6587f..ab2b5b59b0 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -128,6 +128,7 @@ #define PM4_IW_INDOFF 0x0738 #define PM4_IW_INDSIZE 0x073c #define PM4_FPU_FPX0 0x0740 +#define CP_CSQ_CNTL 0x0740 #define PM4_FPU_FPY0 0x0744 #define PM4_FPU_FPX1 0x0748 #define PM4_FPU_FPY1 0x074c --=20 2.53.0 From nobody Sun Jun 7 22:21:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1780775630; cv=none; d=zohomail.com; s=zohoarc; b=HTXRGR2fccLYsXHU01XV2bP6/X1R9ArDLxTlB1zTjRAEIVWqPI6vKNof5HqLa740df4v9s8rtIKEIu4CvTAIf7yDnm4hiioD2TeBR0ckCbdR/Zjy7RGWKj/Eh2lEguKE8vjEa3f2fzZ7Xp0s5sjPavvmgCnyVMmF0+AVi7FleH0= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=202.12.124.151; envelope-from=chad@jablonski.xyz; helo=fout-b8-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1780775632791154100 Content-Type: text/plain; charset="utf-8" When the CCE engine is enabled, real r128 hardware ignores any MMIO writes = to GUI registers (0x1400-0x1fff range). Writes made by the CCE engine are not affected by this. Testing on r100 shows that this behavior is specific to r128. Tested and validated against a Rage 128 Pro Ultra (PCI 1002:5446) and Radeon QY (RV100) (PCI 1002:5159). Signed-off-by: Chad Jablonski --- hw/display/ati.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index e1ba64747b..582c646a3d 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -1183,6 +1183,15 @@ static void ati_mm_write(void *opaque, hwaddr addr, if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) { trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data); } + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF && + s->cce.buffer_mode && addr >=3D 0x1400 && addr <=3D 0x1fff) { + qemu_log_mask(LOG_GUEST_ERROR, + "ati_mm_write: wrote 0x%"PRIx64" to gui register " + "0x%"PRIx64" while cce engine enabled, ignored.\n", + data, addr); + return; + } + switch (addr) { case MM_INDEX: s->regs.mm_index =3D data & ~3; --=20 2.53.0 From nobody Sun Jun 7 22:21:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=202.12.124.151; envelope-from=chad@jablonski.xyz; helo=fout-b8-smtp.messagingengine.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1780775611697158500 Content-Type: text/plain; charset="utf-8" While drivers use bus mastering modes, PIO is the simplest place to start. This implements the PM4_FIFO_DATA_EVEN/ODD registers. Writing to these registers in sequence places packets into the CCE FIFO directly without need for a ring buffer. This enables testing of the CCE packet processing itself. Ring buffer registers will follow in a future patch. Type-0 and Type-1 packets write to registers. Type-2 packets are NOPs. Type-3 packet headers are parsed but only logged as of now. Hardware testing and poking at the microcode suggests that Type-0/1/2 packets may be implemented in hardware and not the microcode. Type-3, however, definitely depends on the microcode. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 10 +++ hw/display/ati_cce.c | 154 ++++++++++++++++++++++++++++++++++++++++ hw/display/ati_int.h | 54 ++++++++++++++ hw/display/meson.build | 3 +- hw/display/trace-events | 9 +++ 5 files changed, 229 insertions(+), 1 deletion(-) create mode 100644 hw/display/ati_cce.c diff --git a/hw/display/ati.c b/hw/display/ati.c index 582c646a3d..25de3ff544 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -1170,6 +1170,16 @@ void ati_reg_write(ATIVGAState *s, hwaddr addr, s->cce.microcode.addr +=3D 1; break; } + /* R100: CP_CSQ_APER_PRIMARY */ + case PM4_FIFO_DATA_EVEN: + case PM4_FIFO_DATA_ODD: + /* + * R128 does seem to behave differently when the even/odd + * sequence is not strictly adhered to but it's difficult to deter= mine + * exactly what is happening. So for now we treat them the same. + */ + ati_cce_receive_data(s, data); + break; default: break; } diff --git a/hw/display/ati_cce.c b/hw/display/ati_cce.c new file mode 100644 index 0000000000..bf87e4017c --- /dev/null +++ b/hw/display/ati_cce.c @@ -0,0 +1,154 @@ +/* + * QEMU ATI SVGA emulation + * CCE engine functions + * + * Copyright (c) 2025 Chad Jablonski + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "ati_regs.h" +#include "ati_int.h" +#include "trace.h" +#include "qemu/log.h" + +static inline uint32_t ati_cce_data_packets_remaining(const ATIPacketState= *p) +{ + switch (p->type) { + case ATI_CCE_TYPE0: + return p->t0.count - p->dwords_processed; + case ATI_CCE_TYPE1: + return 2 - p->dwords_processed; + case ATI_CCE_TYPE2: + return 0; + case ATI_CCE_TYPE3: + return p->t3.count - p->dwords_processed; + default: + /* This should never happen, type is 2-bits wide */ + g_assert_not_reached(); + return 0; + } +} + +static void ati_cce_parse_packet_header(ATIPacketState *p, uint32_t header) +{ + p->dwords_processed =3D 0; + p->type =3D (header & ATI_CCE_TYPE_MASK) >> ATI_CCE_TYPE_SHIFT; + switch (p->type) { + case ATI_CCE_TYPE0: { + ATIType0Header t0 =3D { + /* Packet stores base_reg as word offset, convert to byte offs= et */ + .base_reg =3D ((header & ATI_CCE_TYPE0_BASE_REG_MASK) >> + ATI_CCE_TYPE0_BASE_REG_SHIFT) << 2, + /* Packet stores count as n-1, convert to actual count */ + .count =3D ((header & ATI_CCE_TYPE0_COUNT_MASK) >> + ATI_CCE_TYPE0_COUNT_SHIFT) + 1, + .one_reg_wr =3D !!(header & ATI_CCE_TYPE0_ONE_REG_WR), + }; + p->t0 =3D t0; + trace_ati_cce_packet_type0(t0.base_reg, t0.count, t0.one_reg_wr); + break; + } + case ATI_CCE_TYPE1: { + ATIType1Header t1 =3D { + /* Packet stores reg0 as word offset, convert to byte offset */ + .reg0 =3D ((header & ATI_CCE_TYPE1_REG0_MASK) >> + ATI_CCE_TYPE1_REG0_SHIFT) << 2, + /* Packet stores reg1 as word offset, convert to byte offset */ + .reg1 =3D ((header & ATI_CCE_TYPE1_REG1_MASK) >> + ATI_CCE_TYPE1_REG1_SHIFT) << 2, + }; + p->t1 =3D t1; + trace_ati_cce_packet_type1(t1.reg0, t1.reg1); + break; + } + case ATI_CCE_TYPE2: { + /* Type-2 is a no-op, it has no header state */ + trace_ati_cce_packet_type2(); + break; + } + case ATI_CCE_TYPE3: { + ATIType3Header t3 =3D { + .opcode =3D (header & ATI_CCE_TYPE3_OPCODE_MASK) >> + ATI_CCE_TYPE3_OPCODE_SHIFT, + /* Packet stores count as n-1, convert to actual count */ + .count =3D ((header & ATI_CCE_TYPE3_COUNT_MASK) >> + ATI_CCE_TYPE3_COUNT_SHIFT) + 1, + }; + p->t3 =3D t3; + qemu_log_mask(LOG_UNIMP, "Type-3 CCE packets not yet implemented\n= "); + trace_ati_cce_packet_type3(t3.opcode, t3.count); + break; + } + default: + /* This should never happen, type is 2-bits wide */ + g_assert_not_reached(); + break; + } +} + +static void ati_cce_process_type0_data(ATIVGAState *s, uint32_t data) +{ + ATIPacketState *p =3D &s->cce.cur_packet; + uint32_t offset =3D p->t0.one_reg_wr ? 0 : + (p->dwords_processed * sizeof(uint32_t)); + uint32_t reg =3D p->t0.base_reg + offset; + trace_ati_cce_packet_type0_data(p->dwords_processed, reg, data); + ati_reg_write(s, reg, data, sizeof(uint32_t)); +} + +static void ati_cce_process_type1_data(ATIVGAState *s, uint32_t data) +{ + ATIPacketState *p =3D &s->cce.cur_packet; + uint32_t reg =3D p->dwords_processed =3D=3D 0 ? p->t1.reg0 : p->t1.reg= 1; + trace_ati_cce_packet_type1_data(p->dwords_processed, reg, data); + ati_reg_write(s, reg, data, sizeof(uint32_t)); +} + +static void ati_cce_process_type3_data(ATIVGAState *s, uint32_t data) +{ + ATIPacketState *p =3D &s->cce.cur_packet; + uint32_t opcode =3D p->t3.opcode; + trace_ati_cce_packet_type3_data(p->dwords_processed, opcode, data); +} + +static void ati_cce_process_packet_data(ATIVGAState *s, uint32_t data) +{ + ATIPacketState *p =3D &s->cce.cur_packet; + switch (p->type) { + case ATI_CCE_TYPE0: { + ati_cce_process_type0_data(s, data); + p->dwords_processed +=3D 1; + break; + } + case ATI_CCE_TYPE1: { + ati_cce_process_type1_data(s, data); + p->dwords_processed +=3D 1; + break; + } + case ATI_CCE_TYPE2: + /* Type-2 packets have no data, we should never end up here */ + g_assert_not_reached(); + break; + case ATI_CCE_TYPE3: { + ati_cce_process_type3_data(s, data); + p->dwords_processed +=3D 1; + break; + } + default: + /* This should never happen, type is 2-bits wide */ + g_assert_not_reached(); + break; + } +} + +void ati_cce_receive_data(ATIVGAState *s, uint32_t data) +{ + uint32_t remaining =3D ati_cce_data_packets_remaining(&s->cce.cur_pack= et); + if (remaining =3D=3D 0) { + /* We're ready to start processing a new packet header */ + ati_cce_parse_packet_header(&s->cce.cur_packet, data); + return; + } + ati_cce_process_packet_data(s, data); +} diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 9259373733..8eea0a7c6f 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -38,6 +38,30 @@ #define TYPE_ATI_VGA "ati-vga" OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA) =20 +#define ATI_CCE_TYPE_MASK 0xc0000000 +#define ATI_CCE_TYPE_SHIFT 30 + +#define ATI_CCE_TYPE0 0 +#define ATI_CCE_TYPE0_BASE_REG_MASK 0x00007fff +#define ATI_CCE_TYPE0_BASE_REG_SHIFT 0 +#define ATI_CCE_TYPE0_ONE_REG_WR 0x00008000 +#define ATI_CCE_TYPE0_COUNT_MASK 0x3fff0000 +#define ATI_CCE_TYPE0_COUNT_SHIFT 16 + +#define ATI_CCE_TYPE1 1 +#define ATI_CCE_TYPE1_REG0_MASK 0x000007ff +#define ATI_CCE_TYPE1_REG0_SHIFT 0 +#define ATI_CCE_TYPE1_REG1_MASK 0x003ff800 +#define ATI_CCE_TYPE1_REG1_SHIFT 11 + +#define ATI_CCE_TYPE2 2 + +#define ATI_CCE_TYPE3 3 +#define ATI_CCE_TYPE3_OPCODE_MASK 0x0000ff00 +#define ATI_CCE_TYPE3_OPCODE_SHIFT 8 +#define ATI_CCE_TYPE3_COUNT_MASK 0x3fff0000 +#define ATI_CCE_TYPE3_COUNT_SHIFT 16 + typedef struct ATIVGARegs { uint32_t mm_index; uint32_t bios_scratch[8]; @@ -105,6 +129,34 @@ typedef struct ATIHostDataState { uint32_t acc[4]; } ATIHostDataState; =20 +typedef struct ATIType0Header { + uint32_t base_reg; + uint16_t count; + bool one_reg_wr; +} ATIType0Header; + +typedef struct ATIType1Header { + uint32_t reg0; + uint32_t reg1; +} ATIType1Header; + +/* Type-2 headers are a no-op and have no state */ + +typedef struct ATIType3Header { + uint8_t opcode; + uint16_t count; +} ATIType3Header; + +typedef struct ATIPacketState { + uint8_t type; + uint16_t dwords_processed; + union { + ATIType0Header t0; + ATIType1Header t1; + ATIType3Header t3; + }; +} ATIPacketState; + typedef struct ATIMicrocodeState { uint8_t addr; uint8_t raddr; @@ -115,6 +167,7 @@ typedef struct ATICCEState { ATIMicrocodeState microcode; /* MicroCntl */ bool freerun; + ATIPacketState cur_packet; /* BufferCntl */ uint32_t buffer_size_l2qw; bool no_update; @@ -152,4 +205,5 @@ void ati_2d_blt(ATIVGAState *s); bool ati_host_data_flush(ATIVGAState *s); void ati_host_data_finish(ATIVGAState *s); =20 +void ati_cce_receive_data(ATIVGAState *s, uint32_t data); #endif /* ATI_INT_H */ diff --git a/hw/display/meson.build b/hw/display/meson.build index ffecedbf70..5a44d4c12f 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -60,7 +60,8 @@ system_ss.add(when: 'CONFIG_XLNX_DISPLAYPORT', if_true: f= iles('xlnx_dp.c')) =20 system_ss.add(when: 'CONFIG_ARTIST', if_true: files('artist.c')) =20 -system_ss.add(when: 'CONFIG_ATI_VGA', if_true: [files('ati.c', 'ati_2d.c',= 'ati_dbg.c'), pixman]) +system_ss.add(when: 'CONFIG_ATI_VGA', + if_true: [files('ati.c', 'ati_2d.c', 'ati_dbg.c', 'ati_cce.c= '), pixman]) =20 system_ss.add(when: [pvg, 'CONFIG_MAC_PVG_PCI'], if_true: [files('appl= e-gfx.m', 'apple-gfx-pci.m')]) system_ss.add(when: [pvg, 'CONFIG_MAC_PVG_MMIO'], if_true: [files('appl= e-gfx.m', 'apple-gfx-mmio.m')]) diff --git a/hw/display/trace-events b/hw/display/trace-events index 4bfc457fba..8e9c91a99f 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -147,6 +147,15 @@ sii9022_switch_mode(const char *mode) "mode: %s" ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t v= al) "%u 0x%"PRIx64 " %s -> 0x%"PRIx64 ati_mm_write(unsigned int size, uint64_t addr, const char *name, uint64_t = val) "%u 0x%"PRIx64 " %s <- 0x%"PRIx64 =20 +# ati_cce.c +ati_cce_packet_type0(uint32_t base_reg, uint32_t count, bool one_reg_wr) "= base_reg=3D0x%x count=3D%u one_reg_wr=3D%u" +ati_cce_packet_type0_data(uint32_t data_idx, uint32_t reg, uint32_t data) = "data_idx=3D%u reg=3D0x%x data=3D0x%x" +ati_cce_packet_type1(uint32_t reg0, uint32_t reg1) "reg0=3D0x%x reg1=3D0x%= x" +ati_cce_packet_type1_data(uint32_t data_idx, uint32_t reg, uint32_t data) = "data_idx=3D%u reg=3D0x%x data=3D0x%x" +ati_cce_packet_type2(void) "" +ati_cce_packet_type3(uint8_t opcode, uint32_t count) "opcode=3D0x%x count= =3D%u" +ati_cce_packet_type3_data(uint32_t data_idx, uint8_t opcode, uint32_t data= ) "data_idx=3D%u opcode=3D0x%x data=3D0x%x" + # artist.c artist_reg_read(unsigned int size, uint64_t addr, const char *name, uint64= _t val) "%u 0x%"PRIx64 "%s -> 0x%08"PRIx64 artist_reg_write(unsigned int size, uint64_t addr, const char *name, uint6= 4_t val) "%u 0x%"PRIx64 "%s <- 0x%08"PRIx64 --=20 2.53.0