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Wed, 03 Jun 2026 17:07:37 -0700 (PDT) From: Jithu Joseph To: clg@kaod.org, jamin_lin@aspeedtech.com, komlodi@google.com Cc: nabihestefan@google.com, philmd@linaro.org, jithu.joseph@oss.qualcomm.com, qemu-devel@nongnu.org Subject: [PATCH v2 1/3] hw/i3c: fix CMD/data FIFO depth reset values to match real silicon Date: Wed, 3 Jun 2026 17:07:32 -0700 Message-ID: <20260604000734.1094382-2-jithu.joseph@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260604000734.1094382-1-jithu.joseph@oss.qualcomm.com> References: <20260529014034.864722-1-jithu.joseph@oss.qualcomm.com> <20260604000734.1094382-1-jithu.joseph@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: KsCIobLB-gWmNxwkCE5wwd8oPg5OP5rh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAzMDIzNSBTYWx0ZWRfX9bxQpw9GhG0N N4qjqproVfitetWFcQFemnjZwU8O1mpSaUfKy9SV6OjSHx89PxibS5EfTonCtYkDMZsPF5JSDgg 7u6FJ6wV9MTePyKLpc5OXQcI7rzWD77w9CQ9PYY7DUviCg0k+rBAE9vn/FHilI/bUp+1ulpRBfl A3vjfGxrV8Dm5eqOqIzEAO2r6syXXUlX0p4VRef2h+sKFIB0IF0R7uKZHLJWJSko2sFYK917dhk CD7PL/Mph1soWEnzpSWRHdQ4LnDDnlvihYHuf2RzZd6Gz9Krw7GRKKzRuJ6NfjL58E3gVsCUXEa X7EdHxBRO2Nb+qF6074Io5YNrO+YYSK/4eTRFS/dFj76YX85mBOm+Z8VtGgu8kyij/rz+Rh3xbu T+vReLsHSpB0z5HfUYMY5jXY7nOZxAxic+CnqT8MvTm+qe7xJTWzsrGIpB5or2MuEL/cf6URDvj ZoAwb98yoPC79SpF5FA== X-Authority-Analysis: v=2.4 cv=E779Y6dl c=1 sm=1 tr=0 ts=6a20c1ca cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=69wJf7TsAAAA:8 a=EUspDBNiAAAA:8 a=1Cgkl99JUvOo6gf9qOkA:9 a=PxkB5W3o20Ba91AHUih5:22 a=Fg1AiH1G6rFz08G2ETeA:22 X-Proofpoint-GUID: KsCIobLB-gWmNxwkCE5wwd8oPg5OP5rh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-03_06,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606030235 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=jithu.joseph@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780531704967154100 Content-Type: text/plain; charset="utf-8" The Linux DW-I3C master driver infers controller queue depths at probe by reading two status registers that report free queue slots, which at probe (queues empty) equals the full depth. It then uses those values to gate every I3C transfer -- any batch whose word count exceeds the advertised depth is rejected with -EOPNOTSUPP. QUEUE_STATUS_LEVEL (0x4c) [7:0] -> cmdfifodepth (cmd slots) DATA_BUFFER_STATUS_LEVEL (0x50) [7:0] -> datafifodepth (32-bit words) Per the AST2600 datasheet the reset values are 0x10 and 0x40 (16 cmd slots, 64 words =3D 256 B). QEMU was advertising 0x02 and 0x10, making the kernel believe the controller can only do 64-byte transfers. The visible symptom was -EOPNOTSUPP on any I3C transfer whose payload exceeded 64 B (datafifodepth =3D 0x10 =3D 16 words =3D 64 B). The underlying FIFOs in QEMU were already allocated at the right size (fifo32_create takes word counts; the existing defaults give 16 cmd slots and 64 data words). Only the advertised reset values were wrong. Correct the reset values in dw_i3c_resets[], and additionally drive the advertised depths from the queue-capacity configs in the reset handlers (as is already done for the device/char table pointers), so a configured override is reflected in what the guest reads instead of being silently ignored. The advertised fields are 8-bit, so the depth saturates at 255 regardless of the wider capacity configs. With this fix the guest sees datafifodepth=3D64 words and accepts transfers up to 256 B. Fixes: e974c6957576 ("hw/i3c/dw-i3c: Add more reset values") Cc: qemu-stable@nongnu.org Signed-off-by: Jithu Joseph --- hw/i3c/dw-i3c.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index 17ff484c5df1..06c2d55f5958 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -282,8 +282,8 @@ static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] =3D= { [R_QUEUE_THLD_CTRL] =3D 0x01000101, [R_DATA_BUFFER_THLD_CTRL] =3D 0x01010100, [R_SLV_EVENT_CTRL] =3D 0x0000000b, - [R_QUEUE_STATUS_LEVEL] =3D 0x00000002, - [R_DATA_BUFFER_STATUS_LEVEL] =3D 0x00000010, + [R_QUEUE_STATUS_LEVEL] =3D 0x00000010, + [R_DATA_BUFFER_STATUS_LEVEL] =3D 0x00000040, [R_PRESENT_STATE] =3D 0x00000003, [R_I3C_VER_ID] =3D 0x3130302a, [R_I3C_VER_TYPE] =3D 0x6c633033, @@ -947,6 +947,10 @@ static void dw_i3c_reset(DeviceState *dev) s->cfg.dev_char_table_pointer); ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, s->cfg.dev_char_table_depth); + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, + s->cfg.cmd_resp_queue_capacity_bytes); + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, + s->cfg.tx_rx_queue_capacity_bytes); =20 dw_i3c_cmd_queue_reset(s); dw_i3c_resp_queue_reset(s); @@ -1793,6 +1797,10 @@ static void dw_i3c_reset_enter(Object *obj, ResetTyp= e type) s->cfg.dev_char_table_pointer); ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, s->cfg.dev_char_table_depth); + ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, + s->cfg.cmd_resp_queue_capacity_bytes); + ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, + s->cfg.tx_rx_queue_capacity_bytes); } =20 static void dw_i3c_realize(DeviceState *dev, Error **errp) --=20 2.43.0