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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1780490667; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=nJq3Yilomoh4G5pgvKSFT1iRcAg4pY+FxWyDgGLLhzk=; b=XYG460jzhSIdJlw50OkOawPNqjGa/MKH1bVGVufdDWcXOW4xt3/hMzTyoZ8BU7b7jvMTZs FDe+BPPDPGSvRUQHuOAQPqgjdX8e7YV3AFltIyUuTYkI/G2Pn+OrVikj3qnJpJjkNld8yi OQLF/kjrZYYEqzySn79My/nyzX4yL6Q= X-MC-Unique: NTO66vpZMfy8LfZMvBnHfw-1 X-Mimecast-MFC-AGG-ID: NTO66vpZMfy8LfZMvBnHfw_1780490662 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, mst@redhat.com, skolothumtho@nvidia.com, nicolinc@nvidia.com, nathanc@nvidia.com Subject: [PATCH v2] hw/pci/pci: Enforce pci_setup_iommu_per_bus() is called only once per bus Date: Wed, 3 Jun 2026 14:44:13 +0200 Message-ID: <20260603124415.1120808-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1780490708474154100 Currently it is possible to attach several arm-smmuv3 devices to the same bus although it is a wrong setup. Change the prototype of pci_setup_iommu_per_bus to pass an error handle. This latter is set when iommu_per_bus is already set and used by the single caller (smmu_base_realize) to report a useful error to the end-user. While at it document pci_setup_iommu_per_bus callback in the header. Fixes: 66d2f665e163 ("hw/arm/virt: Allow user-creatable SMMUv3 dev instanti= ation") Signed-off-by: Eric Auger Tested-by: Nathan Chen Reviewed-by: Shameer Kolothum Reviewed-by: Nicolin Chen Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v1 -> v2: - in smmu_base_realize, return if pci_setup_iommu_per_bus returns false (Philippe) --- include/hw/pci/pci.h | 16 +++++++++++++++- hw/arm/smmu-common.c | 4 +++- hw/pci/pci.c | 9 +++++++-- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 5b179091de..f2448e941a 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -863,7 +863,21 @@ int pci_iommu_unregister_iotlb_notifier(PCIDevice *dev= , uint32_t pasid, */ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque); =20 -void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, void *op= aque); +/** + * pci_setup_iommu_per_bus: Initialize specific IOMMU handlers for a PCIBus + * + * Similar to pci_setup_iommu but enforces that the iommu only protects + * @bus downstream end points and no other bus hierarchy + * + * @bus: the #PCIBus being updated. + * @ops: the #PCIIOMMUOps + * @opaque: passed to callbacks of the @ops structure. + * @errp: error handle + * + * Returns false on failure with @errp set, true on success + */ +bool pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, + void *opaque, Error **errp); =20 pcibus_t pci_bar_address(PCIDevice *d, int reg, uint8_t type, pcibus_t size); diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 58c4452b1f..8e40ba603d 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -981,7 +981,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) } =20 if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s); + if (!pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s, errp)) { + return; + } } else { pci_setup_iommu(pci_bus, s->iommu_ops, s); } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 4298adf5a0..6d54524c9b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -3307,11 +3307,16 @@ void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps= *ops, void *opaque) * IOMMU ops are returned, avoiding the use of the parent=E2=80=99s IOMMU = when * it's not appropriate. */ -void pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, - void *opaque) +bool pci_setup_iommu_per_bus(PCIBus *bus, const PCIIOMMUOps *ops, + void *opaque, Error **errp) { + if (bus->iommu_per_bus) { + error_setg(errp, "An iommu is already attached to this bus"); + return false; + } pci_setup_iommu(bus, ops, opaque); bus->iommu_per_bus =3D true; + return true; } =20 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) --=20 2.53.0