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bh=0GzQITYdSQ4PHvEFsqv3NmxgB55AenqB8H6OKIA9d80=; b=knH64CXodu9Iam92hszB3tOuwIpCfJMfWJqRyms2KrevnKHPswWdqrzDNotgLGPBV8T9Cy4s2v1paRB29OdPjz8L3lJ+tphxjXxnBnB1t9+6mubA1W8YXrTqJN1XcK1Vjqg7fjpBvL/VygoBI+bcDRrZAKcb+NPH+RI+ErvttyxBOOw6/5XHk53FUdD9dTWnR51HgZzfZOeAVMBXrIFqTSypfVnw6ZCM3aJDjjnaYyPa0+q9LFKAHNdzrA8WuzeWGVeUzHCOuYRf9F2yleckg34nBY2nX8JlFNkwNLYijChMVmoEksMFkN8feP0Ht+IEJWLQHpHEVEaHX8M8zg8SJg== From: Steven Lee To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: Troy Lee , "longzl2@lenovo.com" , Yunlin Tang Subject: [RESEND PATCH 1/6] hw/misc/aspeed_scu: Add AST1040 SCU model Thread-Topic: [RESEND PATCH 1/6] hw/misc/aspeed_scu: Add AST1040 SCU model Thread-Index: AQHc8yOEJotrwQ0ri0q1fUaX2ZNe6Q== Date: Wed, 3 Jun 2026 06:37:59 +0000 Message-ID: <20260603063756.1481524-2-steven_lee@aspeedtech.com> References: <20260603063756.1481524-1-steven_lee@aspeedtech.com> In-Reply-To: <20260603063756.1481524-1-steven_lee@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c406::3; envelope-from=steven_lee@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @aspeedtech.com) X-ZM-MESSAGEID: 1780468750396154100 Content-Type: text/plain; charset="utf-8" Add an AST1040 variant of the ASPEED SCU with reset values, APB clock calcu= lation, clock-stop handling, and CPTRA page-select registers. Expose the Caliptra page aperture as a QOM link so the SoC model can wire t= he remap window without callbacks. Signed-off-by: Steven Lee --- include/hw/misc/aspeed_scu.h | 10 ++ hw/misc/aspeed_scu.c | 251 +++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 2 + 3 files changed, 263 insertions(+) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index c30940ab76..6445ae5cf4 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -22,6 +22,7 @@ OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEE= D_SCU) #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700" #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700" #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030" +#define TYPE_ASPEED_1040_SCU TYPE_ASPEED_SCU "-ast1040" =20 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) @@ -39,6 +40,15 @@ struct AspeedSCUState { uint32_t hw_strap1; uint32_t hw_strap2; uint32_t hw_prot_key; + + /* + * AST1040 only: alias region (the Caliptra MCI page aperture) whose + * target offset is selected by SCU_CPTRA_PAGE_REG0, linked in by the = SoC. + * cptra_page_window_base is its base in the address map, used to reje= ct a + * self-referential remap. + */ + MemoryRegion *cptra_page_window; + uint64_t cptra_page_window_base; }; =20 #define AST2400_A1_SILICON_REV 0x02010303U diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 19da6c075f..028677880f 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -17,6 +17,7 @@ #include "qapi/visitor.h" #include "qemu/bitops.h" #include "qemu/log.h" +#include "qemu/range.h" #include "qemu/guest-random.h" #include "qemu/module.h" #include "trace.h" @@ -179,6 +180,41 @@ #define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388) #define AST2700_SCUIO_FREQ_CNT_CTL TO_REG(0x3A0) =20 +/* AST1040 SCU */ +#define AST1040_SILICON_REV TO_REG(0x00) +#define AST1040_HW_STRAP1 TO_REG(0x10) +#define AST1040_HW_STRAP1_CLR TO_REG(0x14) +#define AST1040_HW_STRAP1_LOCK TO_REG(0x20) +#define AST1040_HW_STRAP1_SEC1 TO_REG(0x24) +#define AST1040_SCU_CPTRA_PAGE_REG0 TO_REG(0x120) +#define AST1040_SCU_CPTRA_PAGE_REG1 TO_REG(0x124) +#define AST1040_SCU_CPTRA_PAGE_REG2 TO_REG(0x128) +#define AST1040_SCU_CPTRA_PAGE_REG3 TO_REG(0x12C) +#define AST1040_SCU_CPTRA_PAGE_REG4 TO_REG(0x130) +#define AST1040_SCU_CPTRA_PAGE_REG5 TO_REG(0x134) +#define AST1040_SCU_CLK_STOP_CTL_1 TO_REG(0x240) +#define AST1040_SCU_CLK_STOP_CLR_1 TO_REG(0x244) +#define AST1040_SCU_CLK_STOP_CTL_2 TO_REG(0x260) +#define AST1040_SCU_CLK_STOP_CLR_2 TO_REG(0x264) +#define AST1040_SCU_CLK_SEL_1 TO_REG(0x280) +#define AST1040_SCU_CLK_SEL_2 TO_REG(0x284) +#define AST1040_SCU_HPLL_PARAM TO_REG(0x300) +#define AST1040_SCU_HPLL_EXT_PARAM TO_REG(0x304) +#define AST1040_SCU_APLL_PARAM TO_REG(0x310) +#define AST1040_SCU_APLL_EXT_PARAM TO_REG(0x314) +#define AST1040_SCU_DPLL_PARAM TO_REG(0x320) +#define AST1040_SCU_DPLL_EXT_PARAM TO_REG(0x324) +#define AST1040_SCU_DPLL_PARAM_READ TO_REG(0x328) +#define AST1040_SCU_DPLL_EXT_PARAM_READ TO_REG(0x32c) +#define AST1040_SCU_UARTCLK_GEN TO_REG(0x330) +#define AST1040_SCU_HUARTCLK_GEN TO_REG(0x334) +#define AST1040_SCU_CLK_DUTY_MEAS_RST TO_REG(0x388) +#define AST1040_SCU_FREQ_CNT_CTL TO_REG(0x3A0) +#define AST1040_SCU_CLK_GET_PCLK_DIV(x) (((x) >> 18) & 0x7) + +#define ASPEED_AST1040_SCU_NR_REGS (0xE20 >> 2) +#define AST1040_SCU_CPTRA_PAGE_SIZE 0x1000 + #define SCU_IO_REGION_SIZE 0x1000 =20 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] =3D { @@ -1165,6 +1201,220 @@ static const TypeInfo aspeed_1030_scu_info =3D { .class_init =3D aspeed_1030_scu_class_init, }; =20 +/* AST1040 SCU */ + +static void aspeed_ast1040_scu_update_cptra_page(AspeedSCUState *s) +{ + hwaddr page_base =3D s->regs[AST1040_SCU_CPTRA_PAGE_REG0] & + ~(hwaddr)(AST1040_SCU_CPTRA_PAGE_SIZE - 1); + + if (!s->cptra_page_window) { + return; + } + + if (ranges_overlap(page_base, AST1040_SCU_CPTRA_PAGE_SIZE, + s->cptra_page_window_base, + AST1040_SCU_CPTRA_PAGE_SIZE)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: refusing self-referential remap to 0x%" HWADDR_= PRIx + "\n", __func__, page_base); + memory_region_set_enabled(s->cptra_page_window, false); + return; + } + + memory_region_set_alias_offset(s->cptra_page_window, page_base); + memory_region_set_enabled(s->cptra_page_window, true); +} + +static uint64_t aspeed_ast1040_scu_read(void *opaque, hwaddr offset, + unsigned size) +{ + AspeedSCUState *s =3D ASPEED_SCU(opaque); + int reg =3D TO_REG(offset); + + if (reg >=3D ASPEED_AST1040_SCU_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, offset); + return 0; + } + + trace_aspeed_ast1040_scu_read(offset, size, s->regs[reg]); + return s->regs[reg]; +} + +static void aspeed_ast1040_scu_write(void *opaque, hwaddr offset, + uint64_t data64, unsigned size) +{ + AspeedSCUState *s =3D ASPEED_SCU(opaque); + int reg =3D TO_REG(offset); + uint32_t data =3D data64; + bool updated =3D false; + + if (reg >=3D ASPEED_AST1040_SCU_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, offset); + return; + } + + trace_aspeed_ast1040_scu_write(offset, size, data); + + switch (reg) { + case AST1040_SCU_CLK_STOP_CTL_1: + case AST1040_SCU_CLK_STOP_CTL_2: + s->regs[reg] |=3D data; + updated =3D true; + break; + case AST1040_SCU_CLK_STOP_CLR_1: + case AST1040_SCU_CLK_STOP_CLR_2: + s->regs[reg - 1] &=3D ~data; + updated =3D true; + break; + case AST1040_SCU_FREQ_CNT_CTL: + s->regs[reg] =3D deposit32(s->regs[reg], 6, 1, !!(data & BIT(1))); + updated =3D true; + break; + case AST1040_SCU_CPTRA_PAGE_REG0: + s->regs[reg] =3D data; + aspeed_ast1040_scu_update_cptra_page(s); + updated =3D true; + break; + case AST1040_SCU_CPTRA_PAGE_REG1: + case AST1040_SCU_CPTRA_PAGE_REG2: + case AST1040_SCU_CPTRA_PAGE_REG3: + case AST1040_SCU_CPTRA_PAGE_REG4: + case AST1040_SCU_CPTRA_PAGE_REG5: + s->regs[reg] =3D data; + updated =3D true; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + break; + } + + if (!updated) { + s->regs[reg] =3D data; + } +} + +static const MemoryRegionOps aspeed_ast1040_scu_ops =3D { + .read =3D aspeed_ast1040_scu_read, + .write =3D aspeed_ast1040_scu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 8, + .valid.unaligned =3D false, +}; + +static uint32_t aspeed_1040_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll= _reg) +{ + uint32_t multiplier =3D 1; + uint32_t clkin =3D aspeed_scu_get_clkin(s); + + if (hpll_reg & SCU_AST2600_H_PLL_OFF) { + return 0; + } + + if (!(hpll_reg & SCU_AST2600_H_PLL_BYPASS_EN)) { + uint32_t p =3D (hpll_reg >> 19) & 0xf; + uint32_t n =3D (hpll_reg >> 13) & 0x3f; + uint32_t m =3D hpll_reg & 0x1fff; + + multiplier =3D ((m + 1) / (n + 1)) / (p + 1); + } + + return clkin * multiplier; +} + +static uint32_t aspeed_1040_scu_get_apb_freq(AspeedSCUState *s) +{ + AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(s); + uint32_t hpll =3D asc->calc_hpll(s, s->regs[AST1040_SCU_HPLL_PARAM]); + + return hpll / + (AST1040_SCU_CLK_GET_PCLK_DIV(s->regs[AST1040_SCU_CLK_SEL_1]) + 1) + / asc->apb_divider; +} + +static void aspeed_ast1040_scu_reset_hold(Object *obj, ResetType type) +{ + AspeedSCUState *s =3D ASPEED_SCU(obj); + AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(obj); + + memcpy(s->regs, asc->resets, asc->nr_regs * 4); + s->regs[AST1040_SILICON_REV] =3D s->silicon_rev; + s->regs[AST1040_HW_STRAP1] =3D s->hw_strap1; + aspeed_ast1040_scu_update_cptra_page(s); +} + +static const uint32_t ast1040_a0_scu_resets[ASPEED_AST1040_SCU_NR_REGS] = =3D { + [AST1040_HW_STRAP1_CLR] =3D 0xFFF0FFF0, + [AST1040_HW_STRAP1_LOCK] =3D 0x00000FFF, + [AST1040_HW_STRAP1_SEC1] =3D 0x000000FF, + [AST1040_SCU_CLK_STOP_CTL_1] =3D 0xffff8400, + [AST1040_SCU_CLK_STOP_CTL_2] =3D 0x00005f30, + [AST1040_SCU_CLK_SEL_1] =3D 0x86900000, + [AST1040_SCU_CLK_SEL_2] =3D 0x00400000, + [AST1040_SCU_HPLL_PARAM] =3D 0x10000027, + [AST1040_SCU_HPLL_EXT_PARAM] =3D 0x80000014, + [AST1040_SCU_APLL_PARAM] =3D 0x1000001f, + [AST1040_SCU_APLL_EXT_PARAM] =3D 0x8000000f, + [AST1040_SCU_DPLL_PARAM] =3D 0x106e42ce, + [AST1040_SCU_DPLL_EXT_PARAM] =3D 0x80000167, + [AST1040_SCU_DPLL_PARAM_READ] =3D 0x106e42ce, + [AST1040_SCU_DPLL_EXT_PARAM_READ] =3D 0x80000167, + [AST1040_SCU_UARTCLK_GEN] =3D 0x00014506, + [AST1040_SCU_HUARTCLK_GEN] =3D 0x000145c0, + [AST1040_SCU_CLK_DUTY_MEAS_RST] =3D 0x0c9100d2, + [AST1040_SCU_FREQ_CNT_CTL] =3D 0x00000080, +}; + +static const Property aspeed_1040_scu_props[] =3D { + DEFINE_PROP_UINT64("cptra-page-window-base", AspeedSCUState, + cptra_page_window_base, 0), +}; + +static void aspeed_1040_scu_init(Object *obj) +{ + AspeedSCUState *s =3D ASPEED_SCU(obj); + + object_property_add_link(obj, "cptra-page-window", TYPE_MEMORY_REGION, + (Object **)&s->cptra_page_window, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); +} + +static void aspeed_1040_scu_class_init(ObjectClass *klass, const void *dat= a) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + AspeedSCUClass *asc =3D ASPEED_SCU_CLASS(klass); + + dc->desc =3D "ASPEED 1040 System Control Unit"; + rc->phases.hold =3D aspeed_ast1040_scu_reset_hold; + device_class_set_props(dc, aspeed_1040_scu_props); + asc->resets =3D ast1040_a0_scu_resets; + asc->calc_hpll =3D aspeed_1040_scu_calc_hpll; + asc->get_apb =3D aspeed_1040_scu_get_apb_freq; + asc->apb_divider =3D 2; + asc->nr_regs =3D ASPEED_AST1040_SCU_NR_REGS; + asc->clkin_25Mhz =3D true; + asc->ops =3D &aspeed_ast1040_scu_ops; +} + +static const TypeInfo aspeed_1040_scu_info =3D { + .name =3D TYPE_ASPEED_1040_SCU, + .parent =3D TYPE_ASPEED_SCU, + .instance_size =3D sizeof(AspeedSCUState), + .instance_init =3D aspeed_1040_scu_init, + .class_init =3D aspeed_1040_scu_class_init, +}; + static void aspeed_scu_register_types(void) { type_register_static(&aspeed_scu_info); @@ -1174,6 +1424,7 @@ static void aspeed_scu_register_types(void) type_register_static(&aspeed_1030_scu_info); type_register_static(&aspeed_2700_scu_info); type_register_static(&aspeed_2700_scuio_info); + type_register_static(&aspeed_1040_scu_info); } =20 type_init(aspeed_scu_register_types); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index b88accc437..82ddbf4d15 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -103,6 +103,8 @@ aspeed_ast2700_scu_write(uint64_t offset, unsigned size= , uint32_t data) "To 0x%" aspeed_ast2700_scu_read(uint64_t offset, unsigned size, uint32_t data) "To= 0x%" PRIx64 " of size %u: 0x%" PRIx32 aspeed_ast2700_scuio_write(uint64_t offset, unsigned size, uint32_t data) = "To 0x%" PRIx64 " of size %u: 0x%" PRIx32 aspeed_ast2700_scuio_read(uint64_t offset, unsigned size, uint32_t data) "= To 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_ast1040_scu_write(uint64_t offset, unsigned size, uint32_t data) "T= o 0x%" PRIx64 " of size %u: 0x%" PRIx32 +aspeed_ast1040_scu_read(uint64_t offset, unsigned size, uint32_t data) "To= 0x%" PRIx64 " of size %u: 0x%" PRIx32 =20 # mps2-scc.c mps2_scc_read(uint64_t offset, uint64_t data, unsigned size) "MPS2 SCC rea= d: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" --=20 2.43.0