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bh=Vcw+OCaWjlS94VeEpOQL0QCFpkLSIQmZiDUlXQsfais=; b=nGS62Ex6pk9TLkriNcJvgpw2LzMx5/wrqFH2DI87KlF7FjBKWO617IKPgQgZ/z/7J+z83a85IOEU5CXsk7Ww9v93BHht+EbE7MioUBkLZ5g7cyJOnbqk9eYl8Nt0sK9incpuneErESzH48Yc1WXqmlVS6IZfJUd31R3rpfvRCJc3M959HD+UkXLs2+nrLiNr0YUfYCUutYI4gEP9x62Pm7djhmOpRyJx93iKwhEk1kVlNfMo0JRQGrVNdDRJbffE+iDbsraTMSDJuGUqTOHEXOcgp1nK64eFGrEMMOp2pX1kXMZYFr3eRkwLoxwKx/NTGPvfd5dqIeuiVkkSKCEkVg== From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v3 01/10] hw/i2c/aspeed_i2c: Introduce dma_addr_lo_mask to unify DMA address handling Thread-Topic: [PATCH v3 01/10] hw/i2c/aspeed_i2c: Introduce dma_addr_lo_mask to unify DMA address handling Thread-Index: AQHc8w2E8LG9mTwF50q43NKlevPhtg== Date: Wed, 3 Jun 2026 04:00:29 +0000 Message-ID: <20260603040027.938816-2-jamin_lin@aspeedtech.com> References: <20260603040027.938816-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260603040027.938816-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @aspeedtech.com) X-ZM-MESSAGEID: 1780459322930158500 Content-Type: text/plain; charset="utf-8" The Aspeed I2C controller has two register layouts. The AST2500 uses the old mode with a single DMA address register (I2CD_DMA_= ADDR) where the address is 4-byte aligned and masked to 0x3ffffffc. From AST2600 onwards, the new mode provides separate master TX/RX and slave= RX DMA address registers (I2CM_DMA_TX_ADDR, I2CM_DMA_RX_ADDR, I2CS_DMA_RX_ADDR) with different address widths per SoC: AST2600 (new mode): 0x7fffffff - bits[30:0] AST1030 (new mode): 0x7fffffff - bits[30:0] AST1060 (new mode): 0x7fffffff - bits[30:0] AST2700 (new mode): 0xffffffff - bits[31:0] Introduce dma_addr_lo_mask as a per-class attribute and apply it uniformly when storing DMA address register writes and when loading the address into dma_dram_offset for both master and slave paths. This replaces the previous FIELD_EX32 extractions (which incorrectly stripped bit 31 on AST2700) and the hardcoded 0x3ffffffc literal in the old-mode path. Fixes: 1809ab6a67359e0876981cd05d2a50b2843eabad ("hw/i2c/aspeed: Add AST270= 0 support") Signed-off-by: Jamin Lin --- include/hw/i2c/aspeed_i2c.h | 5 +---- hw/i2c/aspeed_i2c.c | 24 ++++++++++++++---------- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index d42cb4865a..1fc229f699 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -209,13 +209,9 @@ REG32(I2CS_DMA_LEN, 0x2c) FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11) REG32(I2CM_DMA_TX_ADDR, 0x30) - FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31) REG32(I2CM_DMA_RX_ADDR, 0x34) - FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31) REG32(I2CS_DMA_TX_ADDR, 0x38) - FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31) REG32(I2CS_DMA_RX_ADDR, 0x3c) - FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31) REG32(I2CS_DEV_ADDR, 0x40) REG32(I2CM_DMA_LEN_STS, 0x48) FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13) @@ -303,6 +299,7 @@ struct AspeedI2CClass { bool has_share_pool; uint64_t mem_size; bool has_dma64; + uint32_t dma_addr_lo_mask; }; =20 static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 4a6732a185..9d4e72c858 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -236,7 +236,7 @@ static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2C= Bus *bus) value =3D bus->regs[R_I2CM_DMA_TX_ADDR]; bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32, - FIELD_EX32(value, I2CM_DMA_TX_ADDR, ADDR)); + value & aic->dma_addr_lo_mask); if (aic->has_dma64) { value =3D bus->regs[R_I2CM_DMA_TX_ADDR_HI]; bus->dma_dram_offset =3D @@ -246,7 +246,7 @@ static void aspeed_i2c_set_tx_dma_dram_offset(AspeedI2C= Bus *bus) } else { value =3D bus->regs[R_I2CD_DMA_ADDR]; bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32, - value & 0x3ffffffc); + value & aic->dma_addr_lo_mask); } } =20 @@ -261,7 +261,7 @@ static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2C= Bus *bus) value =3D bus->regs[R_I2CM_DMA_RX_ADDR]; bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32, - FIELD_EX32(value, I2CM_DMA_RX_ADDR, ADDR)); + value & aic->dma_addr_lo_mask); if (aic->has_dma64) { value =3D bus->regs[R_I2CM_DMA_RX_ADDR_HI]; bus->dma_dram_offset =3D @@ -271,7 +271,7 @@ static void aspeed_i2c_set_rx_dma_dram_offset(AspeedI2C= Bus *bus) } else { value =3D bus->regs[R_I2CD_DMA_ADDR]; bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32, - value & 0x3ffffffc); + value & aic->dma_addr_lo_mask); } } =20 @@ -735,12 +735,10 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bu= s, hwaddr offset, aspeed_i2c_bus_raise_interrupt(bus); break; case A_I2CM_DMA_TX_ADDR: - bus->regs[R_I2CM_DMA_TX_ADDR] =3D FIELD_EX32(value, I2CM_DMA_TX_AD= DR, - ADDR); + bus->regs[R_I2CM_DMA_TX_ADDR] =3D value & aic->dma_addr_lo_mask; break; case A_I2CM_DMA_RX_ADDR: - bus->regs[R_I2CM_DMA_RX_ADDR] =3D FIELD_EX32(value, I2CM_DMA_RX_AD= DR, - ADDR); + bus->regs[R_I2CM_DMA_RX_ADDR] =3D value & aic->dma_addr_lo_mask; break; case A_I2CM_DMA_LEN: w1t =3D FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) || @@ -777,7 +775,7 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,= hwaddr offset, bus->regs[R_I2CS_DEV_ADDR] =3D value; break; case A_I2CS_DMA_RX_ADDR: - bus->regs[R_I2CS_DMA_RX_ADDR] =3D value; + bus->regs[R_I2CS_DMA_RX_ADDR] =3D value & aic->dma_addr_lo_mask; break; case A_I2CS_DMA_LEN: if (FIELD_EX32(value, I2CS_DMA_LEN, RX_BUF_LEN_W1T)) { @@ -1375,6 +1373,8 @@ static void aspeed_i2c_class_init(ObjectClass *klass,= const void *data) static int aspeed_i2c_bus_new_slave_event(AspeedI2CBus *bus, enum i2c_event event) { + AspeedI2CClass *aic =3D ASPEED_I2C_GET_CLASS(bus->controller); + switch (event) { case I2C_START_SEND_ASYNC: if (!SHARED_ARRAY_FIELD_EX32(bus->regs, R_I2CS_CMD, RX_DMA_EN)) { @@ -1385,7 +1385,7 @@ static int aspeed_i2c_bus_new_slave_event(AspeedI2CBu= s *bus, ARRAY_FIELD_DP32(bus->regs, I2CS_DMA_LEN_STS, RX_LEN, 0); bus->dma_dram_offset =3D deposit64(bus->dma_dram_offset, 0, 32, - ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_RX_ADDR, ADDR)); + bus->regs[R_I2CS_DMA_RX_ADDR] & aic->dma_addr_lo_mas= k); bus->regs[R_I2CC_DMA_LEN] =3D ARRAY_FIELD_EX32(bus->regs, I2CS_DMA_LEN, RX_BUF_LEN) + 1; i2c_ack(bus->bus); @@ -1608,6 +1608,7 @@ static void aspeed_2500_i2c_class_init(ObjectClass *k= lass, const void *data) aic->check_sram =3D true; aic->has_dma =3D true; aic->mem_size =3D 0x1000; + aic->dma_addr_lo_mask =3D 0x3ffffffc; } =20 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) @@ -1631,6 +1632,7 @@ static void aspeed_2600_i2c_class_init(ObjectClass *k= lass, const void *data) aic->bus_pool_base =3D aspeed_2500_i2c_bus_pool_base; aic->has_dma =3D true; aic->mem_size =3D 0x1000; + aic->dma_addr_lo_mask =3D 0x7fffffff; } =20 static void aspeed_1030_i2c_class_init(ObjectClass *klass, const void *dat= a) @@ -1649,6 +1651,7 @@ static void aspeed_1030_i2c_class_init(ObjectClass *k= lass, const void *data) aic->bus_pool_base =3D aspeed_2500_i2c_bus_pool_base; aic->has_dma =3D true; aic->mem_size =3D 0x10000; + aic->dma_addr_lo_mask =3D 0x7fffffff; } =20 static void aspeed_2700_i2c_class_init(ObjectClass *klass, const void *dat= a) @@ -1670,6 +1673,7 @@ static void aspeed_2700_i2c_class_init(ObjectClass *k= lass, const void *data) aic->has_dma =3D true; aic->mem_size =3D 0x2000; aic->has_dma64 =3D true; + aic->dma_addr_lo_mask =3D 0xffffffff; } =20 static const TypeInfo aspeed_i2c_types[] =3D { --=20 2.43.0