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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=160.30.148.34; envelope-from=liu.xuemei1@zte.com.cn; helo=mxhk.zte.com.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780381810111158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuemei Liu Create common function kvm_riscv_aia_access_reg to access APLIC and IMSIC regs Signed-off-by: Xuemei Liu --- target/riscv/kvm/kvm-cpu.c | 7 ++++++- target/riscv/kvm/kvm_riscv.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 17ba38403a..879b4d610d 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -58,6 +58,7 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int l= evel) } static bool cap_has_mp_state; +static int aia_fd =3D -1; #define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 = | \ type | idx) @@ -1817,13 +1818,17 @@ void kvm_arch_accel_class_init(ObjectClass *oc) "auto"); } +void kvm_riscv_aia_access_reg(int group, uint64_t addr, void *val, bool wr= ite) +{ + kvm_device_access(aia_fd, group, addr, val, write, &error_abort); +} + void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, uint64_t aia_irq_num, uint64_t aia_msi_num, uint64_t aplic_base, uint64_t imsic_base, uint64_t guest_num) { int ret, i; - int aia_fd =3D -1; uint64_t default_aia_mode; uint64_t socket_count =3D riscv_socket_count(machine); uint64_t max_hart_per_socket =3D 0; diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index b2bcd1041f..b0ef0bc2d0 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -23,6 +23,7 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +void kvm_riscv_aia_access_reg(int group, uint64_t addr, void *val, bool wr= ite); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, uint64_t aia_irq_num, uint64_t aia_msi_num, uint64_t aplic_base, uint64_t imsic_base, --=20 2.27.0 From nobody Mon Jun 8 04:29:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=zte.com.cn Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780381962433545.9253123270826; Mon, 1 Jun 2026 23:32:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wUIfM-0004lG-MH; Tue, 02 Jun 2026 02:31:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wUIfE-0004km-Q1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=183.62.165.209; envelope-from=liu.xuemei1@zte.com.cn; helo=mxct.zte.com.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780381965662158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuemei Liu Add save and restore function if riscv_use_emulated_aplic return false, it is to get and set APLIC irqchip state from KVM kernel. Signed-off-by: Xuemei Liu --- hw/intc/riscv_aplic.c | 190 +++++++++++++++++++++++++++++----- include/hw/intc/riscv_aplic.h | 4 + 2 files changed, 168 insertions(+), 26 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 0f61b67fc5..f544733954 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -975,9 +975,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error= **errp) } aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; - aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); aplic->state =3D g_new0(uint32_t, aplic->num_irqs); - aplic->target =3D g_new0(uint32_t, aplic->num_irqs); aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); @@ -989,8 +987,16 @@ static void riscv_aplic_realize(DeviceState *dev, Erro= r **errp) if (kvm_enabled()) { aplic->kvm_splitmode =3D true; } + } else { + aplic->nr_words =3D BITS_TO_U32S(aplic->num_irqs); + aplic->setip =3D g_new0(uint32_t, aplic->nr_words); + aplic->clrip =3D g_new0(uint32_t, aplic->nr_words); + aplic->setie =3D g_new0(uint32_t, aplic->nr_words); } + aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); + aplic->target =3D g_new0(uint32_t, aplic->num_irqs); + /* * Only root APLICs have hardware IRQ lines. All non-root APLICs * have IRQ lines delegated by their parent APLIC. @@ -1016,47 +1022,179 @@ static const Property riscv_aplic_properties[] =3D= { DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0), }; -static bool riscv_aplic_state_needed(void *opaque) +static bool riscv_aplic_emul_state_needed(void *opaque) { RISCVAPLICState *aplic =3D opaque; return riscv_use_emulated_aplic(aplic->msimode); } +static const VMStateDescription vmstate_riscv_aplic_emul =3D { + .name =3D "riscv_aplic_emul", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D riscv_aplic_emul_state_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_VARRAY_UINT32(state, RISCVAPLICState, + num_irqs, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState), + VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState), + VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState), + VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState), + VMSTATE_UINT32(kvm_msicfgaddr, RISCVAPLICState), + VMSTATE_UINT32(kvm_msicfgaddrH, RISCVAPLICState), + VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState, + num_harts, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState, + num_harts, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState, + num_harts, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + +static bool riscv_aplic_in_kernel_state_needed(void *opaque) +{ + RISCVAPLICState *aplic =3D opaque; + + return !riscv_use_emulated_aplic(aplic->msimode); +} + +static int riscv_aplic_in_kernel_pre_save(void *opaque) +{ + RISCVAPLICState *aplic =3D opaque; + + if (!riscv_use_emulated_aplic(aplic->msimode)) { + for (uint32_t i =3D 0; i < aplic->nr_words; i++) { + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_SETIP_BASE + i * 4, + aplic->setip + i, false); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_CLRIP_BASE + i * 4, + aplic->clrip + i, false); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_SETIE_BASE + i * 4, + aplic->setie + i, false); + } + } + + return 0; +} + +static int riscv_aplic_in_kernel_post_load(void *opaque, int version_id) +{ + RISCVAPLICState *aplic =3D opaque; + + if (!riscv_use_emulated_aplic(aplic->msimode)) { + for (uint32_t i =3D 0; i < aplic->nr_words; i++) { + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_SETIP_BASE + i * 4, + aplic->setip + i, true); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_CLRIP_BASE + i * 4, + aplic->clrip + i, true); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_SETIE_BASE + i * 4, + aplic->setie + i, true); + } + } + + return 0; +} + +static const VMStateDescription vmstate_riscv_aplic_in_kernel =3D { + .name =3D "riscv_aplic_in_kernel", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D riscv_aplic_in_kernel_state_needed, + .pre_save =3D riscv_aplic_in_kernel_pre_save, + .post_load =3D riscv_aplic_in_kernel_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_VARRAY_UINT32(setip, RISCVAPLICState, + nr_words, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(clrip, RISCVAPLICState, + nr_words, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(setie, RISCVAPLICState, + nr_words, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + +static int riscv_aplic_pre_save(void *opaque) +{ + RISCVAPLICState *aplic =3D opaque; + + if (!riscv_use_emulated_aplic(aplic->msimode)) { + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, APLIC_DOMAIN= CFG, + &aplic->domaincfg, false); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, APLIC_GENMSI, + &aplic->genmsi, false); + + for (uint32_t i =3D 1; i < aplic->num_irqs; i++) { + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_SOURCECFG_BASE + (i - 1) * 4, + aplic->sourcecfg + i, false); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_TARGET_BASE + (i - 1) * 4, + aplic->target + i, false); + } + } + + return 0; +} + +static int riscv_aplic_post_load(void *opaque, int version_id) +{ + RISCVAPLICState *aplic =3D opaque; + + if (!riscv_use_emulated_aplic(aplic->msimode)) { + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, APLIC_DOMAIN= CFG, + &aplic->domaincfg, true); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, APLIC_GENMSI, + &aplic->genmsi, true); + + for (uint32_t i =3D 1; i < aplic->num_irqs; i++) { + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_SOURCECFG_BASE + (i - 1) * 4, + aplic->sourcecfg + i, true); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_APLIC, + APLIC_TARGET_BASE + (i - 1) * 4, + aplic->target + i, true); + } + } + + return 0; +} + static const VMStateDescription vmstate_riscv_aplic =3D { .name =3D "riscv_aplic", - .version_id =3D 3, - .minimum_version_id =3D 3, - .needed =3D riscv_aplic_state_needed, + .version_id =3D 4, + .minimum_version_id =3D 4, + .pre_save =3D riscv_aplic_pre_save, + .post_load =3D riscv_aplic_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32(domaincfg, RISCVAPLICState), - VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState), - VMSTATE_UINT32(mmsicfgaddrH, RISCVAPLICState), - VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState), - VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState), VMSTATE_UINT32(genmsi, RISCVAPLICState), - VMSTATE_UINT32(kvm_msicfgaddr, RISCVAPLICState), - VMSTATE_UINT32(kvm_msicfgaddrH, RISCVAPLICState), - VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState, - num_irqs, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(state, RISCVAPLICState, + VMSTATE_VARRAY_UINT32(sourcecfg , RISCVAPLICState, num_irqs, 0, vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(target, RISCVAPLICState, num_irqs, 0, vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(idelivery, RISCVAPLICState, - num_harts, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(iforce, RISCVAPLICState, - num_harts, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(ithreshold, RISCVAPLICState, - num_harts, 0, - vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() - } + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_riscv_aplic_emul, + &vmstate_riscv_aplic_in_kernel, + NULL + } }; static void riscv_aplic_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index c7a4d4ad01..1976bea68c 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -53,6 +53,9 @@ struct RISCVAPLICState { uint32_t *idelivery; uint32_t *iforce; uint32_t *ithreshold; + uint32_t *setip; + uint32_t *clrip; + uint32_t *setie; /* topology */ #define QEMU_APLIC_MAX_CHILDREN 16 @@ -66,6 +69,7 @@ struct RISCVAPLICState { uint32_t num_harts; uint32_t iprio_mask; uint32_t num_irqs; + uint32_t nr_words; bool msimode; bool mmode; --=20 2.27.0 From nobody Mon Jun 8 04:29:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=zte.com.cn Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780382086283702.7958831092043; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=183.62.165.209; envelope-from=liu.xuemei1@zte.com.cn; helo=mxct.zte.com.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780382092724154100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuemei Liu Add save and restore funtction if kvm_irqchip_in_kernel() return true, it is to get and set IMSIC irqchip state from KVM kernel. Signed-off-by: Xuemei Liu --- hw/intc/riscv_imsic.c | 171 +++++++++++++++++++++++++++++++--- include/hw/intc/riscv_imsic.h | 3 + include/qemu/bitops.h | 1 + migration/vmstate-types.c | 1 - 4 files changed, 161 insertions(+), 15 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 6dbbc152a2..bfce181af9 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -34,6 +34,7 @@ #include "system/system.h" #include "system/kvm.h" #include "migration/vmstate.h" +#include "kvm/kvm_riscv.h" #define IMSIC_MMIO_PAGE_LE 0x00 #define IMSIC_MMIO_PAGE_BE 0x04 @@ -382,11 +383,16 @@ static void riscv_imsic_realize(DeviceState *dev, Err= or **errp) qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages); imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; - imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); - imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + } else { + imsic->nr_eix =3D 2 * BITS_TO_U64S(imsic->num_irqs); + imsic->eie =3D g_new0(uint32_t, imsic->nr_eix); + imsic->eip =3D g_new0(uint32_t, imsic->nr_eix); } + imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); + imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); + memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, imsic, TYPE_RISCV_IMSIC, IMSIC_MMIO_SIZE(imsic->num_pages)); @@ -417,23 +423,17 @@ static const Property riscv_imsic_properties[] =3D { DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0), }; -static bool riscv_imsic_state_needed(void *opaque) +static bool riscv_imsic_emul_state_needed(void *opaque) { return !kvm_irqchip_in_kernel(); } -static const VMStateDescription vmstate_riscv_imsic =3D { - .name =3D "riscv_imsic", - .version_id =3D 2, - .minimum_version_id =3D 2, - .needed =3D riscv_imsic_state_needed, +static const VMStateDescription vmstate_riscv_imsic_emul =3D { + .name =3D "riscv_imsic_emul", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D riscv_imsic_emul_state_needed, .fields =3D (const VMStateField[]) { - VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState, - num_pages, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState, - num_pages, 0, - vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(eistate, RISCVIMSICState, num_eistate, 0, vmstate_info_uint32, uint32_t), @@ -441,6 +441,149 @@ static const VMStateDescription vmstate_riscv_imsic = =3D { } }; +static bool riscv_imsic_in_kernel_state_needed(void *opaque) +{ + return kvm_irqchip_in_kernel(); +} + +static int riscv_imsic_in_kernel_pre_save(void *opaque) +{ + RISCVIMSICState *imsic =3D opaque; + RISCVCPU *rcpu =3D RISCV_CPU(cpu_by_arch_id(imsic->hartid)); + bool is_32bit =3D riscv_cpu_is_32bit(rcpu); + uint32_t inc =3D 2; + uint64_t attr; + + if (is_32bit) { + inc =3D 1; + } + + if (kvm_irqchip_in_kernel()) { + for (uint32_t i =3D 0; i < imsic->nr_eix; i +=3D inc) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIE0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eie + i, false); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIP0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eip + i, false); + } + } + + return 0; +} + +static int riscv_imsic_in_kernel_post_load(void *opaque, int version_id) +{ + RISCVIMSICState *imsic =3D opaque; + RISCVCPU *rcpu =3D RISCV_CPU(cpu_by_arch_id(imsic->hartid)); + bool is_32bit =3D riscv_cpu_is_32bit(rcpu); + uint32_t inc =3D 2; + uint64_t attr; + + if (is_32bit) { + inc =3D 1; + } + + if (kvm_irqchip_in_kernel()) { + for (uint32_t i =3D 0; i < imsic->nr_eix; i +=3D inc) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIE0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eie + i, true); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIP0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eip + i, true); + } + } + + return 0; +} + +static const VMStateDescription vmstate_riscv_imsic_in_kernel =3D { + .name =3D "riscv_imsic_in_kernel", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D riscv_imsic_in_kernel_state_needed, + .pre_save =3D riscv_imsic_in_kernel_pre_save, + .post_load =3D riscv_imsic_in_kernel_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_VARRAY_UINT32(eie, RISCVIMSICState, + nr_eix, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(eip, RISCVIMSICState, + nr_eix, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + +static int riscv_imsic_pre_save(void *opaque) +{ + RISCVIMSICState *imsic =3D opaque; + uint64_t attr; + + if (kvm_irqchip_in_kernel()) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIDELIVERY); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eidelivery, false); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EITHRESHOLD); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eithreshold, false); + } + + return 0; +} + +static int riscv_imsic_post_load(void *opaque, int version_id) +{ + RISCVIMSICState *imsic =3D opaque; + uint64_t attr; + + if (kvm_irqchip_in_kernel()) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIDELIVERY); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eidelivery, true); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EITHRESHOLD); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eithreshold, true); + } + + return 0; +} + +static const VMStateDescription vmstate_riscv_imsic =3D { + .name =3D "riscv_imsic", + .version_id =3D 3, + .minimum_version_id =3D 3, + .pre_save =3D riscv_imsic_pre_save, + .post_load =3D riscv_imsic_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState, + num_pages, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState, + num_pages, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_riscv_imsic_emul, + &vmstate_riscv_imsic_in_kernel, + NULL + } +}; + static void riscv_imsic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h index fae999731d..2206d82e0c 100644 --- a/include/hw/intc/riscv_imsic.h +++ b/include/hw/intc/riscv_imsic.h @@ -54,12 +54,15 @@ struct RISCVIMSICState { uint32_t *eidelivery; uint32_t *eithreshold; uint32_t *eistate; + uint32_t *eip; + uint32_t *eie; /* config */ bool mmode; uint32_t hartid; uint32_t num_pages; uint32_t num_irqs; + uint32_t nr_eix; }; DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index c7b838a628..a7f86f2ee0 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -20,6 +20,7 @@ #define BITS_PER_LONG (sizeof (unsigned long) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(lo= ng)) #define BITS_TO_U32S(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(ui= nt32_t)) +#define BITS_TO_U64S(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(ui= nt64_t)) #define BIT(nr) (1UL << (nr)) #define BIT_ULL(nr) (1ULL << (nr)) diff --git a/migration/vmstate-types.c b/migration/vmstate-types.c index ae465c5c2c..7e6f37f8c4 100644 --- a/migration/vmstate-types.c +++ b/migration/vmstate-types.c @@ -597,7 +597,6 @@ const VMStateInfo vmstate_info_tmp =3D { * is an array of 'unsigned long', which may be either 32 or 64 bits. */ /* This is the number of 64 bit words sent over the wire */ -#define BITS_TO_U64S(nr) DIV_ROUND_UP(nr, 64) static bool load_bitmap(QEMUFile *f, void *pv, size_t size, const VMStateField *field, Error **errp) { --=20 2.27.0