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Tue, 02 Jun 2026 15:42:20 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1780386457; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=bC5APgQSccMcMwPowh1j/zrujNKfyybUz8KbJ3l6djI=; b=hg+bF9f3i43YoAu4Hc5UvrHPGtHl2f+CsI0BcmwehwX8D82grNwIOYH5KbkHCKTFGX+1ej3raXAaD0qs5aX/6lekKOnlBMVAtvLJUrHcAIW7gMle41hAS0fPizE5PxgcWKD/4J52pqrXuc9bNKuWLqohjfxj9akopNEmyHcCQ5A= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R181e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037026112; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0X43o4N5_1780386140; From: Chen Pei To: pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, jonathan.cameron@huawei.com, fan.ni@samsung.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Chen Pei Subject: [PATCH 1/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Date: Tue, 2 Jun 2026 15:41:24 +0800 Message-ID: <20260602074127.63819-2-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602074127.63819-1-cp0613@linux.alibaba.com> References: <20260602074127.63819-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.133 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Enable CXL support on the RISC-V virt machine following the same approach used by the ARM virt machine: - Add PXB and ACPI_CXL Kconfig selections - Add CXLState and PCIBus pointer to RISCVVirtState - Register CXL machine properties via cxl_machine_init() - Create CXL host register region above the PCIe high MMIO region - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at machine_done time - Map Fixed Memory Windows above the CXL host register region - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c Signed-off-by: Chen Pei --- hw/riscv/Kconfig | 2 ++ hw/riscv/virt-acpi-build.c | 20 ++++++++++++++++++ hw/riscv/virt.c | 42 ++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 +++ 4 files changed, 67 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2518b04175..ebd0355f09 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -66,8 +66,10 @@ config RISCV_VIRT select VIRTIO_MMIO select FW_CFG_DMA select PLATFORM_BUS + select PXB select ACPI select ACPI_PCI + select ACPI_CXL =20 config SHAKTI_C bool diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 413d47d70e..309d64b322 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -29,12 +29,16 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/pci.h" #include "hw/acpi/utils.h" +#include "hw/acpi/cxl.h" #include "hw/intc/riscv_aclint.h" #include "hw/nvram/fw_cfg_acpi.h" #include "hw/pci-host/gpex.h" +#include "hw/pci/pci_bus.h" #include "hw/riscv/virt.h" #include "hw/riscv/numa.h" #include "hw/virtio/virtio-acpi.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -503,6 +507,17 @@ static void build_dsdt(GArray *table_data, acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES= * 2); } =20 + if (s->cxl_devices_state.is_enabled) { + Aml *cxl_dev =3D aml_device("CXLM"); + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(cxl_dev, method); + build_cxl_dsm_method(cxl_dev); + + aml_append(scope, cxl_dev); + } + aml_append(dsdt, scope); =20 /* copy AML table into ACPI tables blob and patch header there */ @@ -910,6 +925,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBui= ldTables *tables) s->oem_table_id); } =20 + if (s->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + s->oem_id, s->oem_table_id, &s->cxl_devices_state); + } + if (ms->numa_state->num_nodes > 0) { acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, s); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ce64eaaef7..899f632de7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -55,6 +55,8 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" @@ -1259,9 +1261,27 @@ static inline DeviceState *gpex_pcie_init(MemoryRegi= on *sys_mem, } =20 GPEX_HOST(dev)->gpex_cfg.bus =3D PCI_HOST_BRIDGE(dev)->bus; + s->bus =3D PCI_HOST_BRIDGE(dev)->bus; return dev; } =20 +static void create_cxl_host_reg_region(RISCVVirtState *s) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &s->cxl_devices_state.host_mr; + hwaddr base; + + if (!s->cxl_devices_state.is_enabled) { + return; + } + + base =3D virt_high_pcie_memmap.base + virt_high_pcie_memmap.size; + base =3D ROUND_UP(base, 64 * KiB); + + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16); + memory_region_add_subregion(sysmem, base, mr); +} + static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { FWCfgState *fw_cfg; @@ -1426,6 +1446,15 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) machine_done); MachineState *machine =3D MACHINE(s); hwaddr start_addr =3D s->memmap[VIRT_DRAM].base; + + if (s->bus) { + cxl_hook_up_pxb_registers(s->bus, &s->cxl_devices_state, + &error_fatal); + } + + if (s->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } hwaddr firmware_end_addr; vaddr kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); @@ -1663,6 +1692,17 @@ static void virt_machine_init(MachineState *machine) ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 + create_cxl_host_reg_region(s); + + if (s->cxl_devices_state.is_enabled) { + hwaddr cxl_base =3D virt_high_pcie_memmap.base + + virt_high_pcie_memmap.size; + cxl_base +=3D memory_region_size(&s->cxl_devices_state.host_mr); + cxl_base =3D ROUND_UP(cxl_base, 256 * MiB); + cxl_fmws_set_memmap(cxl_base, UINT64_MAX); + cxl_fmws_update_mmio(); + } + /* register system main memory (actual RAM) */ memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, machine->ram); @@ -1769,6 +1809,8 @@ static void virt_machine_instance_init(Object *obj) s->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); s->acpi =3D ON_OFF_AUTO_AUTO; s->iommu_sys =3D ON_OFF_AUTO_AUTO; + + cxl_machine_init(obj, &s->cxl_devices_state); } =20 static char *virt_get_aia_guests(Object *obj, Error **errp) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 18a2a323a3..c3201588bb 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,6 +24,7 @@ #include "hw/core/sysbus.h" #include "hw/block/flash.h" #include "hw/intc/riscv_imsic.h" +#include "hw/cxl/cxl.h" =20 #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) @@ -64,6 +65,8 @@ struct RISCVVirtState { struct GPEXHost *gpex_host; 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RN=14; SR=0; TI=SMTPD_---0X43o4NG_1780386140; From: Chen Pei To: pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, jonathan.cameron@huawei.com, fan.ni@samsung.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Chen Pei Subject: [PATCH 2/4] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Date: Tue, 2 Jun 2026 15:41:25 +0800 Message-ID: <20260602074127.63819-3-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602074127.63819-1-cp0613@linux.alibaba.com> References: <20260602074127.63819-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.130 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" On RISC-V QEMU virt platform with CXL enabled, the probe ordering of acpi_pci_root (ACPI0016) and cxl_acpi (ACPI0017) is not guaranteed. If cxl_acpi probes before acpi_pci_root has attached the CXL host bridges, the CXL port topology will be incomplete because to_cxl_host_bridge() silently skips devices whose PCI root is not yet ready. Add a _DEP object to the ACPI0017 device in the DSDT, declaring its dependency on the ACPI0016 CXL host bridge devices. This tells the OS to defer ACPI0017 enumeration until all ACPI0016 devices have been attached by acpi_pci_root. This requires a corresponding kernel change to call acpi_dev_clear_dependencies() in acpi_pci_root_add(). Signed-off-by: Chen Pei --- hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 309d64b322..a5bafd1dcf 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -510,6 +510,38 @@ static void build_dsdt(GArray *table_data, if (s->cxl_devices_state.is_enabled) { Aml *cxl_dev =3D aml_device("CXLM"); aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + /* + * Declare a _DEP on every ACPI0016 CXL host bridge so the OS + * defers ACPI0017 enumeration until acpi_pci_root has attached + * the CXL host bridges. Without this, cxl_acpi may probe before + * to_cxl_host_bridge() can resolve the PCI root and the CXL + * port topology comes up empty. + */ + if (s->bus) { + PCIBus *bus; + uint32_t num_cxl_hbs =3D 0; + + QLIST_FOREACH(bus, &s->bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + num_cxl_hbs++; + } + } + + if (num_cxl_hbs > 0) { + Aml *dep_pkg =3D aml_package(num_cxl_hbs); + + QLIST_FOREACH(bus, &s->bus->child, sibling) { + if (pci_bus_is_root(bus) && pci_bus_is_cxl(bus)) { + aml_append(dep_pkg, + aml_name("\\_SB.PC%.02X", + pci_bus_num(bus))); + } + } + aml_append(cxl_dev, aml_name_decl("_DEP", dep_pkg)); + } + } + Aml *method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); aml_append(method, aml_return(aml_int(0x0B))); aml_append(cxl_dev, method); --=20 2.50.1 From nobody Mon Jun 8 04:25:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linux.alibaba.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780386541585992.1542177277865; Tue, 2 Jun 2026 00:49:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wUJr1-00068T-2Q; Tue, 02 Jun 2026 03:48:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wUJqz-000689-Lf; Tue, 02 Jun 2026 03:48:01 -0400 Received: from [115.124.30.133] (helo=out30-133.freemail.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wUJqv-0004vj-V1; Tue, 02 Jun 2026 03:48:01 -0400 Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0X43o4NT_1780386141 cluster:ay36) by smtp.aliyun-inc.com; Tue, 02 Jun 2026 15:42:22 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1780386456; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=LSpWwvDx1CUjwIUD1WW3vUX1vTZa1uNjr2amItlJDVU=; b=mO94ktL+aCLKN0ruzJvwc1RG47TBoOdWdGaLgMWTDKbpFH40ZmAQ+vd4F9Jf39hCdXxXqiszUDkmyQ1Lqdgj7DTwyprqVxyXOqS1CjJ9n/98s3aTb/RfJKmBauelHJ01v82s7KFKuX1S86tnO4whrq7FPu0znB4DilHz2RGMjr8= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R511e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam011083073210; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0X43o4NT_1780386141; From: Chen Pei To: pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, jonathan.cameron@huawei.com, fan.ni@samsung.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Chen Pei Subject: [PATCH 3/4] hw/riscv/virt, gpex: Provide 32-bit MMIO window for CXL host bridges Date: Tue, 2 Jun 2026 15:41:26 +0800 Message-ID: <20260602074127.63819-4-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602074127.63819-1-cp0613@linux.alibaba.com> References: <20260602074127.63819-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.133 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.30.133; envelope-from=cp0613@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -166 X-Spam_score: -16.7 X-Spam_bar: ---------------- X-Spam_report: (-16.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1780386545133154100 Content-Type: text/plain; charset="utf-8" CXL component register BAR (BAR0 on CXL Root Port and Type3 device) and the CXL device register BAR (BAR2 on Type3 device) are declared as 64-bit non-prefetchable memory. A standard PCIe-to-PCI bridge exposes a 32-bit non-prefetchable memory window plus an (optional) 64-bit prefetchable memory window, but no 64-bit non-prefetchable window. Linux therefore places 64-bit non-prefetchable BARs in the 32-bit non-prefetchable bridge window, which requires the bridge to own enough address space below 4 GiB. On RISC-V virt the 32-bit PCIe MMIO range (1 GiB at 0x40000000) is currently consumed entirely by PCI0, so CXL host bridges (ACPI0016) have no non-prefetchable window and Linux fails to assign these BARs. Marking the BARs prefetchable would work around it, but the CXL component registers have read/write side effects and are not prefetchable per the PCIe specification. Reserve the top 256 MiB of the 32-bit MMIO window exclusively for CXL host bridges: - Shrink PCI0's mmio32 window by 256 MiB in virt.c so that UEFI's PciHostBridgeDxe and the ACPI _CRS for PCI0 never claim that range - Store the reserved range in a new gpex_cfg.cxl_mmio32 field - In gpex-acpi.c, emit the cxl_mmio32 range as the Memory resource in the CXL host bridge _CRS instead of re-using build_crs() (which returns an empty set when UEFI has not assigned resources yet) - Reduce the FDT 'ranges' for PCI0 by the same 256 MiB so that UEFI firmware driven by device-tree also respects the reservation Signed-off-by: Chen Pei --- hw/pci-host/gpex-acpi.c | 36 +++++++++++++++++++++-- hw/riscv/virt.c | 58 +++++++++++++++++++++++++++++++------- include/hw/pci-host/gpex.h | 1 + 3 files changed, 83 insertions(+), 12 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index d9820f9b41..d8b943b665 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -158,9 +158,41 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig = *cfg) * Resources defined for PXBs are composed of the following pa= rts: * 1. The resources the pci-bridge/pcie-root-port need. * 2. The resources the devices behind pxb need. + * + * For CXL host bridges on platforms where UEFI (driven by + * FDT 'ranges') does not assign PCI resources for the CXL + * root bridge before ACPI table construction, build_crs() + * would return an empty resource set. When the platform + * has reserved a dedicated MMIO window for CXL host bridges + * (cfg->cxl_mmio32), emit that window as a static _CRS + * instead. The platform is responsible for shrinking PCI0's + * mmio32 window so the two do not overlap. */ - crs =3D build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_rang= e_set, - cfg->pio.base, 0, 0, 0); + if (is_cxl && cfg->cxl_mmio32.size) { + uint64_t cxl_base =3D cfg->cxl_mmio32.base; + uint64_t cxl_size =3D cfg->cxl_mmio32.size; + + crs =3D aml_resource_template(); + + /* 32-bit MMIO range for CXL devices */ + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, 0, + cxl_base, + cxl_base + cxl_size - 1, + 0, cxl_size)); + + /* Bus number range */ + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, 0, + bus_num, bus_num + 15, + 0, 16)); + } else { + crs =3D build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), + &crs_range_set, cfg->pio.base, 0, 0, 0); + } aml_append(dev, aml_name_decl("_CRS", crs)); =20 if (is_cxl) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 899f632de7..929c01fb26 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -113,6 +113,9 @@ static const MemMapEntry virt_memmap[] =3D { /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) =20 +/* 32-bit MMIO range carved out of VIRT_PCIE_MMIO for CXL host bridges */ +#define VIRT_CXL_MMIO32_SIZE (256 * MiB) + static MemMapEntry virt_high_pcie_memmap; =20 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) @@ -890,15 +893,28 @@ static void create_fdt_pcie(RISCVVirtState *s, } qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", - 1, FDT_PCI_RANGE_IOPORT, 2, 0, - 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, - 1, FDT_PCI_RANGE_MMIO, - 2, s->memmap[VIRT_PCIE_MMIO].base, - 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].si= ze, - 1, FDT_PCI_RANGE_MMIO_64BIT, - 2, virt_high_pcie_memmap.base, - 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); + { + /* + * When CXL is enabled, reserve the last 256 MiB of the 32-bit + * MMIO window for CXL host bridges and exclude it from the main + * PCIe host bridge's FDT 'ranges' so UEFI's PciHostBridgeDxe + * does not allocate that range to PCI0. The CXL host bridge + * _CRS declares this range independently. + */ + hwaddr mmio32_size =3D s->memmap[VIRT_PCIE_MMIO].size; + if (s->cxl_devices_state.is_enabled) { + mmio32_size -=3D VIRT_CXL_MMIO32_SIZE; + } + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, 0, + 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].= size, + 1, FDT_PCI_RANGE_MMIO, + 2, s->memmap[VIRT_PCIE_MMIO].base, + 2, s->memmap[VIRT_PCIE_MMIO].base, 2, mmio32_size, + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, virt_high_pcie_memmap.base, + 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); + } =20 if (virt_is_iommu_sys_enabled(s)) { qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", @@ -1730,7 +1746,29 @@ static void virt_machine_init(MachineState *machine) qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); } =20 - gpex_pcie_init(system_memory, pcie_irqchip, s); + DeviceState *pcie_dev =3D gpex_pcie_init(system_memory, pcie_irqchip, = s); + + /* + * If CXL is enabled, reserve the last 256 MiB of the 32-bit MMIO + * window for CXL host bridges so the bridge non-prefetchable window + * can hold CXL device BARs (component registers and similar 64-bit + * non-prefetchable BARs that need a < 4 GiB address). + * + * - Shrink PCI0's mmio32 advertised in the ACPI _CRS by the same + * 256 MiB so the two ranges do not overlap (the FDT 'ranges' + * shrink happens in create_fdt_pcie()). + * - Store the reserved range in cxl_mmio32 so gpex-acpi.c can emit + * a correct _CRS for the CXL host bridge (ACPI0016). + */ + if (s->cxl_devices_state.is_enabled) { + GPEXHost *gpex =3D GPEX_HOST(pcie_dev); + gpex->gpex_cfg.cxl_mmio32.size =3D VIRT_CXL_MMIO32_SIZE; + gpex->gpex_cfg.cxl_mmio32.base =3D + s->memmap[VIRT_PCIE_MMIO].base + + s->memmap[VIRT_PCIE_MMIO].size - VIRT_CXL_MMIO32_SIZE; + /* Shrink PCI0's advertised 32-bit MMIO window to exclude CXL rang= e */ + gpex->gpex_cfg.mmio32.size -=3D VIRT_CXL_MMIO32_SIZE; + } =20 create_platform_bus(s, mmio_irqchip); =20 diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 1da9c85bce..d38fbbacd6 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -43,6 +43,7 @@ struct GPEXConfig { MemMapEntry mmio32; MemMapEntry mmio64; MemMapEntry pio; + MemMapEntry cxl_mmio32; int irq; PCIBus *bus; bool pci_native_hotplug; --=20 2.50.1 From nobody Mon Jun 8 04:25:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1780386456; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=8lZQdxMRvn1C3XUCXtvDihVYcgry9SAPjkeEBCgc8SQ=; b=SsYjWI6zOTUfs52tBALhoWyP4sY8WvVh5g+JhRleINXuoD1SOBzdLEZOPrJRggQKUj69V+8DcMI/oFbe5ONKr81qn5Sn0c1QIDZn9HS/C1vWw0p3UGCqZyTPBH05yA0XuHuDroWwdjH8K/EbekAFf8KaMNe6bvieu6WoKvYRCUk= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R191e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045133197; MF=cp0613@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0X43o4Na_1780386142; From: Chen Pei To: pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, jonathan.cameron@huawei.com, fan.ni@samsung.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Chen Pei Subject: [PATCH 4/4] hw/cxl: Map committed HDM decoder ranges as RAM for direct DMA Date: Tue, 2 Jun 2026 15:41:27 +0800 Message-ID: <20260602074127.63819-5-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602074127.63819-1-cp0613@linux.alibaba.com> References: <20260602074127.63819-1-cp0613@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.30.97 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The CXL Fixed Memory Window (CFMW) is registered with memory_region_init_io() and has no backing ram_block. As a result address_space_map() on a guest physical address inside the CFMW takes the bounce-buffer path and is bounded by DEFAULT_MAX_BOUNCE_BUFFER_SIZE (4 KiB by default for the system AddressSpace). Once a Type-3 device is brought online as system RAM (daxctl online-memory), the kernel happily allocates DMA buffers from the CFMW range and any virtio operation whose scatter list exceeds 4 KiB or that overlaps with another in-flight transfer fails with: qemu-system-riscv64: virtio: bogus descriptor or out of resources The bug is not RISC-V specific: CFMW registration and the bounce buffer limit are both arch-agnostic, so any guest that onlines CXL memory and issues DMA larger than 4 KiB into it is affected. It shows up first on RISC-V virt because that is where the rest of this series enables the daxctl + virtio path end-to-end. Reproduce on RISC-V virt with cxl=3Don and a single Type-3 device: cxl create-region -m -t ram -d decoder0.0 -w 1 mem0 -s 4G daxctl online-memory dax0.0 free -h # triggers the error and stalls the guest Fix it by overlaying a RAM alias of the device's memory backend (hostvmem / hostpmem) at the committed HDM decoder's HPA range, with higher priority than the CFMW I/O region. flatview_translate() then hits the alias, address_space_map() returns a direct host pointer, and DMA proceeds without bouncing. This mirrors the existing QEMU pattern of PCI BAR and IOMMU MR overlays. The alias is torn down on hdm_decoder_uncommit() so subsequent region tear-down + re-creation works. Signed-off-by: Chen Pei --- hw/mem/cxl_type3.c | 81 +++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 4 ++ 2 files changed, 85 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 4739239da3..f962bce66a 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -24,6 +24,7 @@ #include "qemu/module.h" #include "qemu/pmem.h" #include "qemu/range.h" +#include "system/address-spaces.h" #include "qemu/rcu.h" #include "qemu/guest-random.h" #include "system/hostmem.h" @@ -420,6 +421,11 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int = which) ComponentRegisters *cregs =3D &ct3d->cxl_cstate.crb; uint32_t *cache_mem =3D cregs->cache_mem_registers; uint32_t ctrl; + uint32_t low, high; + uint64_t decoder_base, decoder_size; + MemoryRegion *mr =3D NULL; + uint64_t dpa_offset =3D 0; + char *alias_name; =20 ctrl =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_in= c); /* TODO: Sanity checks that the decoder is possible */ @@ -427,6 +433,73 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int = which) ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); =20 stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl); + + /* + * Create a RAM alias in system memory for the committed decoder range. + * This enables direct DMA mapping (address_space_map) for devices like + * virtio that need to DMA to/from CXL memory. Without this, the CFMW + * I/O region would require bounce buffering which is limited to 4KB. + */ + low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + which * hdm_= inc); + high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + which * hdm= _inc); + decoder_base =3D ((uint64_t)high << 32) | (low & 0xf0000000); + + low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + which * hdm_= inc); + high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + which * hdm= _inc); + decoder_size =3D ((uint64_t)high << 32) | (low & 0xf0000000); + + if (!decoder_base || !decoder_size) { + return; + } + + /* Calculate DPA offset by summing sizes of preceding decoders */ + for (int i =3D 0; i < which; i++) { + uint32_t prev_low, prev_high; + uint64_t prev_size; + uint32_t prev_ctrl; + + prev_ctrl =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + + i * hdm_inc); + if (!FIELD_EX32(prev_ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) { + continue; + } + prev_low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + + i * hdm_inc); + prev_high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + + i * hdm_inc); + prev_size =3D ((uint64_t)prev_high << 32) | (prev_low & 0xf0000000= ); + dpa_offset +=3D prev_size; + } + + /* Determine which memory backend to alias */ + if (ct3d->hostvmem) { + MemoryRegion *vmr =3D host_memory_backend_get_memory(ct3d->hostvme= m); + uint64_t vmr_size =3D memory_region_size(vmr); + + if (dpa_offset < vmr_size) { + mr =3D vmr; + } + } + if (!mr && ct3d->hostpmem) { + MemoryRegion *pmr =3D host_memory_backend_get_memory(ct3d->hostpme= m); + uint64_t vmr_size =3D ct3d->hostvmem ? + memory_region_size( + host_memory_backend_get_memory(ct3d->hostvmem)) : 0; + mr =3D pmr; + dpa_offset -=3D vmr_size; + } + + if (!mr) { + return; + } + + alias_name =3D g_strdup_printf("cxl-hdm%d-ram-alias", which); + memory_region_init_alias(&ct3d->hdm_ram_alias[which], OBJECT(ct3d), + alias_name, mr, dpa_offset, decoder_size); + memory_region_add_subregion_overlap(get_system_memory(), decoder_base, + &ct3d->hdm_ram_alias[which], 1); + ct3d->hdm_ram_alias_valid[which] =3D true; + g_free(alias_name); } =20 static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int which) @@ -442,6 +515,14 @@ static void hdm_decoder_uncommit(CXLType3Dev *ct3d, in= t which) ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); =20 stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl); + + /* Remove the RAM alias if it was added during commit */ + if (ct3d->hdm_ram_alias_valid[which]) { + memory_region_del_subregion(get_system_memory(), + &ct3d->hdm_ram_alias[which]); + object_unparent(OBJECT(&ct3d->hdm_ram_alias[which])); + ct3d->hdm_ram_alias_valid[which] =3D false; + } } =20 static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 393f312217..07deef2e2c 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -714,6 +714,10 @@ struct CXLType3Dev { /* State */ AddressSpace hostvmem_as; AddressSpace hostpmem_as; + + /* RAM aliases for HDM decoders - enables direct DMA mapping */ + MemoryRegion hdm_ram_alias[CXL_HDM_DECODER_COUNT]; + bool hdm_ram_alias_valid[CXL_HDM_DECODER_COUNT]; CXLComponentState cxl_cstate; CXLDeviceState cxl_dstate; CXLCCI cci; /* Primary PCI mailbox CCI */ --=20 2.50.1