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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780219958206158500 The DPM0-3 and CPM0-3 entries had wrong addresses and were never used. Replace with the correct per-protection-set enable bitmask registers (CPXE, DPRE, DPWE) per the TriCore architecture manual. Signed-off-by: Parthiban Nallathambi --- target/tricore/csfr.h.inc | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/target/tricore/csfr.h.inc b/target/tricore/csfr.h.inc index cdfaf1d662..24d8310947 100644 --- a/target/tricore/csfr.h.inc +++ b/target/tricore/csfr.h.inc @@ -83,14 +83,18 @@ A(0xDC10, CPR3_2L, TRICORE_FEATURE_13) A(0xDC14, CPR3_2U, TRICORE_FEATURE_13) A(0xDC18, CPR3_3L, TRICORE_FEATURE_13) A(0xDC1C, CPR3_3U, TRICORE_FEATURE_13) -A(0xE000, DPM0, TRICORE_FEATURE_13) -A(0xE080, DPM1, TRICORE_FEATURE_13) -A(0xE100, DPM2, TRICORE_FEATURE_13) -A(0xE180, DPM3, TRICORE_FEATURE_13) -A(0xE200, CPM0, TRICORE_FEATURE_13) -A(0xE280, CPM1, TRICORE_FEATURE_13) -A(0xE300, CPM2, TRICORE_FEATURE_13) -A(0xE380, CPM3, TRICORE_FEATURE_13) +A(0xE000, CPXE_0, TRICORE_FEATURE_13) +A(0xE004, CPXE_1, TRICORE_FEATURE_13) +A(0xE008, CPXE_2, TRICORE_FEATURE_13) +A(0xE00C, CPXE_3, TRICORE_FEATURE_13) +A(0xE010, DPRE_0, TRICORE_FEATURE_13) +A(0xE014, DPRE_1, TRICORE_FEATURE_13) +A(0xE018, DPRE_2, TRICORE_FEATURE_13) +A(0xE01C, DPRE_3, TRICORE_FEATURE_13) +A(0xE020, DPWE_0, TRICORE_FEATURE_13) +A(0xE024, DPWE_1, TRICORE_FEATURE_13) +A(0xE028, DPWE_2, TRICORE_FEATURE_13) +A(0xE02C, DPWE_3, TRICORE_FEATURE_13) /* memory management registers */ A(0x8000, MMU_CON, TRICORE_FEATURE_13) A(0x8004, MMU_ASI, TRICORE_FEATURE_13) --=20 2.47.3 From nobody Mon Jun 8 08:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780219958192158500 raise_mmu_exception() was an empty stub and get_physical_address() always returned full RWX permissions. Fill in the MPU: - Walk 16 DPR ranges against DPRE/DPWE bitmasks for R/W - Walk 16 CPR ranges against CPXE bitmasks for X - Block instruction fetch from peripheral space (segments E/F) - Dispatch TRAPC_PROT / TRAPC_SYSBUS in raise_mmu_exception() Also fix a missing else in FIELD_SETTER_WITH_FEATURE and stop force-adding PAGE_EXEC in tricore_cpu_tlb_fill(). Signed-off-by: Parthiban Nallathambi --- target/tricore/helper.c | 242 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 237 insertions(+), 5 deletions(-) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index ce1693622b..e50ea09a92 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -27,6 +27,9 @@ #include "qemu/qemu-print.h" =20 enum { + TLBRET_MPX =3D -12, + TLBRET_MPW =3D -11, + TLBRET_MPR =3D -10, TLBRET_DIRTY =3D -4, TLBRET_INVALID =3D -3, TLBRET_NOMATCH =3D -2, @@ -34,6 +37,207 @@ enum { TLBRET_MATCH =3D 0 }; =20 +static uint32_t tricore_mpu_dpr_lower(CPUTriCoreState *env, int idx) +{ + switch (idx) { + case 0: return env->DPR0_0L; + case 1: return env->DPR0_1L; + case 2: return env->DPR0_2L; + case 3: return env->DPR0_3L; + case 4: return env->DPR1_0L; + case 5: return env->DPR1_1L; + case 6: return env->DPR1_2L; + case 7: return env->DPR1_3L; + case 8: return env->DPR2_0L; + case 9: return env->DPR2_1L; + case 10: return env->DPR2_2L; + case 11: return env->DPR2_3L; + case 12: return env->DPR3_0L; + case 13: return env->DPR3_1L; + case 14: return env->DPR3_2L; + case 15: return env->DPR3_3L; + default: return 0; + } +} + +static uint32_t tricore_mpu_dpr_upper(CPUTriCoreState *env, int idx) +{ + switch (idx) { + case 0: return env->DPR0_0U; + case 1: return env->DPR0_1U; + case 2: return env->DPR0_2U; + case 3: return env->DPR0_3U; + case 4: return env->DPR1_0U; + case 5: return env->DPR1_1U; + case 6: return env->DPR1_2U; + case 7: return env->DPR1_3U; + case 8: return env->DPR2_0U; + case 9: return env->DPR2_1U; + case 10: return env->DPR2_2U; + case 11: return env->DPR2_3U; + case 12: return env->DPR3_0U; + case 13: return env->DPR3_1U; + case 14: return env->DPR3_2U; + case 15: return env->DPR3_3U; + default: return 0; + } +} + +static uint32_t tricore_mpu_cpr_lower(CPUTriCoreState *env, int idx) +{ + switch (idx) { + case 0: return env->CPR0_0L; + case 1: return env->CPR0_1L; + case 2: return env->CPR0_2L; + case 3: return env->CPR0_3L; + case 4: return env->CPR1_0L; + case 5: return env->CPR1_1L; + case 6: return env->CPR1_2L; + case 7: return env->CPR1_3L; + case 8: return env->CPR2_0L; + case 9: return env->CPR2_1L; + case 10: return env->CPR2_2L; + case 11: return env->CPR2_3L; + case 12: return env->CPR3_0L; + case 13: return env->CPR3_1L; + case 14: return env->CPR3_2L; + case 15: return env->CPR3_3L; + default: return 0; + } +} + +static uint32_t tricore_mpu_cpr_upper(CPUTriCoreState *env, int idx) +{ + switch (idx) { + case 0: return env->CPR0_0U; + case 1: return env->CPR0_1U; + case 2: return env->CPR0_2U; + case 3: return env->CPR0_3U; + case 4: return env->CPR1_0U; + case 5: return env->CPR1_1U; + case 6: return env->CPR1_2U; + case 7: return env->CPR1_3U; + case 8: return env->CPR2_0U; + case 9: return env->CPR2_1U; + case 10: return env->CPR2_2U; + case 11: return env->CPR2_3U; + case 12: return env->CPR3_0U; + case 13: return env->CPR3_1U; + case 14: return env->CPR3_2U; + case 15: return env->CPR3_3U; + default: return 0; + } +} + +static uint32_t tricore_mpu_dpre(CPUTriCoreState *env, int prs) +{ + switch (prs) { + case 0: return env->DPRE_0; + case 1: return env->DPRE_1; + case 2: return env->DPRE_2; + case 3: return env->DPRE_3; + default: return 0; + } +} + +static uint32_t tricore_mpu_dpwe(CPUTriCoreState *env, int prs) +{ + switch (prs) { + case 0: return env->DPWE_0; + case 1: return env->DPWE_1; + case 2: return env->DPWE_2; + case 3: return env->DPWE_3; + default: return 0; + } +} + +static uint32_t tricore_mpu_cpxe(CPUTriCoreState *env, int prs) +{ + switch (prs) { + case 0: return env->CPXE_0; + case 1: return env->CPXE_1; + case 2: return env->CPXE_2; + case 3: return env->CPXE_3; + default: return 0; + } +} + +static bool tricore_mpu_enabled(CPUTriCoreState *env) +{ + /* + * The MPU is enabled when SYSCON.MPEN (bit 1) is set. + * As a pragmatic fallback, also treat the MPU as enabled + * when any enable bitmap is nonzero, since some RTOS ports + * program the range/enable registers without setting SYSCON.MPEN. + */ + if (env->SYSCON & MASK_SYSCON_PRO_TEN) { + return true; + } + return (env->DPRE_0 | env->DPRE_1 | env->DPRE_2 | env->DPRE_3 | + env->DPWE_0 | env->DPWE_1 | env->DPWE_2 | env->DPWE_3 | + env->CPXE_0 | env->CPXE_1 | env->CPXE_2 | env->CPXE_3) !=3D 0; +} + +static int tricore_mpu_check(CPUTriCoreState *env, vaddr address, + MMUAccessType access_type, int *prot) +{ + int prs =3D (env->PSW & MASK_PSW_PRS) >> 12; + uint32_t dpre =3D tricore_mpu_dpre(env, prs); + uint32_t dpwe =3D tricore_mpu_dpwe(env, prs); + uint32_t cpxe =3D tricore_mpu_cpxe(env, prs); + int i; + + *prot =3D 0; + + /* Walk the 16 data protection ranges */ + for (i =3D 0; i < 16; i++) { + uint32_t lower =3D tricore_mpu_dpr_lower(env, i); + uint32_t upper =3D tricore_mpu_dpr_upper(env, i); + + if (address >=3D lower && address < upper) { + if (dpre & (1u << i)) { + *prot |=3D PAGE_READ; + } + if (dpwe & (1u << i)) { + *prot |=3D PAGE_WRITE; + } + } + } + + /* Walk the 16 code protection ranges */ + for (i =3D 0; i < 16; i++) { + uint32_t lower =3D tricore_mpu_cpr_lower(env, i); + uint32_t upper =3D tricore_mpu_cpr_upper(env, i); + + if (address >=3D lower && address < upper) { + if (cpxe & (1u << i)) { + *prot |=3D PAGE_EXEC; + } + } + } + + /* Check the requested access against accumulated permissions */ + switch (access_type) { + case MMU_DATA_LOAD: + if (!(*prot & PAGE_READ)) { + return TLBRET_MPR; + } + break; + case MMU_DATA_STORE: + if (!(*prot & PAGE_WRITE)) { + return TLBRET_MPW; + } + break; + case MMU_INST_FETCH: + if (!(*prot & PAGE_EXEC)) { + return TLBRET_MPX; + } + break; + } + + return TLBRET_MATCH; +} + static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, int *prot, vaddr address, MMUAccessType access_type, int mmu_idx) @@ -43,6 +247,19 @@ static int get_physical_address(CPUTriCoreState *env, h= waddr *physical, *physical =3D address & 0xFFFFFFFF; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; =20 + /* + * Block instruction fetch from peripheral space + * (segments 0xE and 0xF). + */ + if (access_type =3D=3D MMU_INST_FETCH && + (address & 0xE0000000) =3D=3D 0xE0000000) { + return TLBRET_MPX; + } + + if (tricore_mpu_enabled(env)) { + ret =3D tricore_mpu_check(env, address, access_type, prot); + } + return ret; } =20 @@ -60,10 +277,25 @@ hwaddr tricore_cpu_get_phys_addr_debug(CPUState *cs, v= addr addr) return phys_addr; } =20 -/* TODO: Add exception support */ static void raise_mmu_exception(CPUTriCoreState *env, vaddr address, int rw, int tlb_error) { + CPUState *cs =3D env_cpu(env); + + switch (tlb_error) { + case TLBRET_MPR: + cs->exception_index =3D TRAPC_PROT; + break; + case TLBRET_MPW: + cs->exception_index =3D TRAPC_PROT; + break; + case TLBRET_MPX: + cs->exception_index =3D TRAPC_PROT; + break; + default: + cs->exception_index =3D TRAPC_SYSBUS; + break; + } } =20 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -73,9 +305,8 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, CPUTriCoreState *env =3D cpu_env(cs); hwaddr physical; int prot; - int ret =3D 0; + int ret; =20 - rw &=3D 1; ret =3D get_physical_address(env, &physical, &prot, address, rw, mmu_idx); =20 @@ -85,7 +316,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, =20 if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } else { @@ -170,8 +401,9 @@ void NAME(CPUTriCoreState *env, uint32_t val) = \ { \ if (tricore_has_feature(env, TRICORE_FEATURE_##FEATURE)) { \ env->REG =3D FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val)= ; \ + } else { \ + env->REG =3D FIELD_DP32(env->REG, REG, FIELD ## _13, val); = \ } \ - env->REG =3D FIELD_DP32(env->REG, REG, FIELD ## _13, val); = \ } =20 #define FIELD_SETTER(NAME, REG, FIELD) \ --=20 2.47.3 From nobody Mon Jun 8 08:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=linumiz.com) ARC-Seal: i=2; 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Same ISA as tc37x but a different chip family (6-core AURIX 2nd gen). Signed-off-by: Parthiban Nallathambi --- target/tricore/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 472c24ae32..e62ccd55c0 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -166,6 +166,13 @@ static void tc37x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_162); } =20 +static void tc39x_initfn(Object *obj) +{ + TriCoreCPU *cpu =3D TRICORE_CPU(obj); + + set_feature(&cpu->env, TRICORE_FEATURE_162); +} + static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { /* Interrupts are not implemented */ @@ -243,6 +250,7 @@ static const TypeInfo tricore_cpu_type_infos[] =3D { DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn), DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn), DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn), + DEFINE_TRICORE_CPU_TYPE("tc39x", tc39x_initfn), }; =20 DEFINE_TYPES(tricore_cpu_type_infos) --=20 2.47.3 From nobody Mon Jun 8 08:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780219961126154100 Model the TriCore IR which manages Service Request Nodes (SRNs). Each SRN has priority, enable, TOS (CPU selector) and request flag bits. The IR picks the highest-priority pending SRN per TOS and raises the corresponding CPU output line. Originally-by: David Brenken Signed-off-by: Parthiban Nallathambi --- hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/intc/tricore_ir.c | 264 +++++++++++++++++++++++++++++++++++++++= ++++ include/hw/intc/tricore_ir.h | 62 ++++++++++ 4 files changed, 330 insertions(+) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 636d00b7e8..686c7d22fe 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -117,3 +117,6 @@ config LOONGARCH_EXTIOI =20 config LOONGARCH_DINTC bool + +config TRICORE_IRBUS + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index fac2d228f9..10c316b62b 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -88,3 +88,4 @@ specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true:= files('loongarch_extio specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_LOONGARCH_EXTIOI'], if_true: files('loongarch_extioi_kvm.c')) specific_ss.add(when: 'CONFIG_LOONGARCH_DINTC', if_true: files('loongarch_= dintc.c')) +system_ss.add(when: 'CONFIG_TRICORE_IRBUS', if_true: files('tricore_ir.c')) diff --git a/hw/intc/tricore_ir.c b/hw/intc/tricore_ir.c new file mode 100644 index 0000000000..44861bf899 --- /dev/null +++ b/hw/intc/tricore_ir.c @@ -0,0 +1,264 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU TriCore Interrupt Router (IR) + * + * Copyright (c) 2017 David Brenken + * Copyright (c) 2026 Parthiban Nallathambi + */ + +#include "qemu/osdep.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/registerfields.h" +#include "hw/core/sysbus.h" +#include "hw/intc/tricore_ir.h" +#include "qemu/log.h" + +static void irq_evaluate(void *opaque) +{ + TriCoreIRState *s =3D opaque; + uint16_t tos_irq[8] =3D { + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, + }; + uint8_t tos_priority[8] =3D { 0 }; + uint32_t srcnum; + uint8_t tos_idx; + + for (srcnum =3D 0; srcnum < s->num_irqs; srcnum++) { + uint32_t src_reg =3D s->src_regs[srcnum]; + uint8_t priority =3D FIELD_EX32(src_reg, SRC, SRPN); + uint8_t tos =3D FIELD_EX32(src_reg, SRC_TC3X, TOS); + + if ((src_reg & R_SRC_SRR_MASK) && + (src_reg & R_SRC_TC3X_SRE_MASK)) { + if (qemu_loglevel_mask(CPU_LOG_INT)) { + qemu_log("tricore_ir: pending irq #%u" + " (priority %u, TOS %u)\n", + srcnum, priority, tos); + } + tos_priority[tos] =3D priority; + tos_irq[tos] =3D srcnum; + } + } + + for (tos_idx =3D 0; tos_idx < s->num_isps; tos_idx++) { + if (tos_irq[tos_idx] =3D=3D 0xFFFF) { + s->lwsr[tos_idx] =3D 0; + qemu_irq_lower(s->isp_irqs[tos_idx]); + } else { + s->lwsr[tos_idx] =3D + FIELD_DP32(0, LWSR, STAT, 1) | + FIELD_DP32(0, LWSR, ID, tos_irq[tos_idx]) | + FIELD_DP32(0, LWSR, VALID, 1) | + FIELD_DP32(0, LWSR, PN, tos_priority[tos_idx]); + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + qemu_log("tricore_ir: raise TOS %u irq line" + " (irq: %u, priority: %u)\n", + tos_idx, tos_irq[tos_idx], + tos_priority[tos_idx]); + } + qemu_irq_raise(s->isp_irqs[tos_idx]); + } + } +} + +static void irq_handler(void *opaque, int srcnum, int level) +{ + TriCoreIRState *s =3D opaque; + uint32_t src_reg =3D s->src_regs[srcnum]; + + if (level) { + if (src_reg & R_SRC_SRR_MASK) { + src_reg |=3D R_SRC_IOV_MASK; + } + src_reg |=3D R_SRC_SRR_MASK; + } + s->src_regs[srcnum] =3D src_reg; + + irq_evaluate(opaque); +} + +void tricore_ir_irq_acknowledge(TriCoreIRState *s, uint16_t irq, uint8_t v= m) +{ + uint32_t src_reg; + + if (!s || irq >=3D s->num_irqs || vm >=3D ARRAY_SIZE(s->lwsr)) { + return; + } + + /* Capture LWSR into LASR before clearing */ + s->lasr =3D s->lwsr[vm] | FIELD_DP32(0, LASR, ENTER, 1); + + src_reg =3D s->src_regs[irq]; + src_reg &=3D ~R_SRC_SRR_MASK; + s->src_regs[irq] =3D src_reg; + + if (FIELD_EX32(s->lwsr[vm], LWSR, ID) =3D=3D irq) { + irq_evaluate(s); + } +} + +static uint64_t tricore_ir_src_regs_read(void *opaque, hwaddr offset, + unsigned size) +{ + TriCoreIRState *s =3D opaque; + hwaddr srcnum =3D offset >> 2; + + if (srcnum < s->num_irqs) { + return s->src_regs[srcnum]; + } + + return 0; +} + +static void tricore_ir_src_regs_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + TriCoreIRState *s =3D opaque; + hwaddr srcnum =3D offset >> 2; + uint32_t srcc; + bool setr; + bool clrr; + + if (srcnum >=3D s->num_irqs) { + qemu_log_mask(LOG_GUEST_ERROR, + "tricore_ir: write to unmapped SRC offset" + " 0x%" HWADDR_PRIx "\n", offset); + return; + } + + srcc =3D value & ~(R_SRC_SETR_MASK | R_SRC_CLRR_MASK); + setr =3D value & R_SRC_SETR_MASK; + clrr =3D value & R_SRC_CLRR_MASK; + + if (setr && !clrr) { + srcc |=3D R_SRC_SRR_MASK; + } else if (clrr && !setr) { + srcc &=3D ~R_SRC_SRR_MASK; + } + + s->src_regs[srcnum] =3D srcc; + + irq_evaluate(opaque); +} + +static const MemoryRegionOps tricore_ir_src_regs_ops =3D { + .read =3D tricore_ir_src_regs_read, + .write =3D tricore_ir_src_regs_write, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +/* + * IR INT registers (LWSR, LASR) + * + * TC3x LWSR offset: 0x200 + x * 0x10 (x =3D CPU index) + * TC3x LASR offset: 0x200 + x * 0x10 + 4 + */ +#define IR_INT_LWSR_BASE 0x200 +#define IR_INT_CPU_STRIDE 0x10 +#define IR_INT_ID_OFF 0x08 + +/* Module ID: IR module number 0x00B9, type 0xC0, rev 0x13 */ +#define IR_INT_MOD_ID 0x00B9C013 + +static uint64_t tricore_ir_intregs_read(void *opaque, hwaddr offset, + unsigned size) +{ + TriCoreIRState *s =3D opaque; + uint32_t x; + uint32_t sub; + + if (offset =3D=3D IR_INT_ID_OFF) { + return IR_INT_MOD_ID; + } + + /* TC3x LWSR: 0x200 + x*0x10, LASR: 0x200 + x*0x10 + 4 */ + if (offset >=3D IR_INT_LWSR_BASE && + offset < IR_INT_LWSR_BASE + IR_INT_CPU_STRIDE * 8) { + x =3D (offset - IR_INT_LWSR_BASE) / IR_INT_CPU_STRIDE; + sub =3D (offset - IR_INT_LWSR_BASE) % IR_INT_CPU_STRIDE; + if (sub =3D=3D 0 && x < 8) { + return s->lwsr[x]; + } + if (sub =3D=3D 4 && x < 8) { + return s->lasr; + } + } + + return 0; +} + +static void tricore_ir_intregs_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + /* LWSR/LASR are read-only from software side */ +} + +static const MemoryRegionOps tricore_ir_intregs_ops =3D { + .read =3D tricore_ir_intregs_read, + .write =3D tricore_ir_intregs_write, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void tricore_ir_init(Object *obj) +{ + TriCoreIRState *s =3D TRICORE_IR(obj); + + memory_region_init_io(&s->src_region, obj, &tricore_ir_src_regs_ops, + s, "tricore_ir.src", 0x4000); + memory_region_init_io(&s->int_region, obj, &tricore_ir_intregs_ops, + s, "tricore_ir.int", 0x1000); +} + +static void tricore_ir_realize(DeviceState *dev, Error **errp) +{ + TriCoreIRState *s =3D TRICORE_IR(dev); + + s->src_regs =3D g_malloc0_n(s->num_irqs, sizeof(uint32_t)); + s->isp_irqs =3D g_malloc_n(s->num_isps, sizeof(qemu_irq)); + + qdev_init_gpio_in_named(DEVICE(s), irq_handler, "irq", s->num_irqs); + qdev_init_gpio_out_named(DEVICE(s), s->isp_irqs, "isp", s->num_isps); + + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->int_region); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->src_region); +} + +static const Property tricore_ir_properties[] =3D { + DEFINE_PROP_UINT8("num-isps", TriCoreIRState, num_isps, 1), + DEFINE_PROP_UINT16("num-irqs", TriCoreIRState, num_irqs, 256), +}; + +static void tricore_ir_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->user_creatable =3D false; + dc->realize =3D tricore_ir_realize; + device_class_set_props(dc, tricore_ir_properties); +} + +static const TypeInfo tricore_ir_info =3D { + .name =3D TYPE_TRICORE_IR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TriCoreIRState), + .instance_init =3D tricore_ir_init, + .class_init =3D tricore_ir_class_init, +}; + +static void tricore_ir_register(void) +{ + type_register_static(&tricore_ir_info); +} + +type_init(tricore_ir_register) diff --git a/include/hw/intc/tricore_ir.h b/include/hw/intc/tricore_ir.h new file mode 100644 index 0000000000..d7b167e50d --- /dev/null +++ b/include/hw/intc/tricore_ir.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU TriCore Interrupt Router (IR) + * + * Copyright (c) 2017 David Brenken + * Copyright (c) 2026 Parthiban Nallathambi + */ + +#ifndef HW_TRICORE_IR_H +#define HW_TRICORE_IR_H + +#include "hw/core/sysbus.h" +#include "hw/core/registerfields.h" +#include "qom/object.h" + +#define TYPE_TRICORE_IR "tricore_ir" +OBJECT_DECLARE_SIMPLE_TYPE(TriCoreIRState, TRICORE_IR) + +/* SRC register fields common to all TriCore variants */ +FIELD(SRC, SRPN, 0, 8) +FIELD(SRC, SRR, 24, 1) +FIELD(SRC, CLRR, 25, 1) +FIELD(SRC, SETR, 26, 1) +FIELD(SRC, IOV, 27, 1) +FIELD(SRC, IOVCLR, 28, 1) + +/* TC3x SRC bit layout */ +FIELD(SRC_TC3X, SRE, 10, 1) +FIELD(SRC_TC3X, TOS, 11, 3) + +/* LWSR register fields */ +FIELD(LWSR, PN, 0, 8) +FIELD(LWSR, VALID, 12, 1) +FIELD(LWSR, ID, 16, 9) +FIELD(LWSR, STAT, 31, 1) + +/* LASR register fields */ +FIELD(LASR, PN, 0, 8) +FIELD(LASR, ID, 16, 11) +FIELD(LASR, ENTER, 31, 1) + +struct TriCoreIRState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion src_region; + MemoryRegion int_region; + + uint32_t *src_regs; + uint32_t lwsr[8]; + uint32_t lasr; + + qemu_irq *isp_irqs; + + uint8_t num_isps; + uint16_t num_irqs; +}; + +void tricore_ir_irq_acknowledge(TriCoreIRState *s, uint16_t irq, uint8_t v= m); + +#endif /* HW_TRICORE_IR_H */ --=20 2.47.3 From nobody Mon Jun 8 08:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=linumiz.com) ARC-Seal: i=2; a=rsa-sha256; t=1780219956; cv=pass; d=zohomail.com; s=zohoarc; b=F+QkqeieP243R8Yu14Qm86tP/ej9BOGot/EX817KtTS6jeIWnm7TPMVhZAi/+EFtZDS7j1SlwFmSevGkzrjMvfQNH2QTkOxbsbctpsPldORK4fG0iaLW4wlIJgv5xWgH1rPW5Gwkya2yfkKSu1bZUS5YohZRJy5YGAE9X1VTyfI= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780219956; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780219958308158500 Model the ASCLIN in UART mode. TX writes go to the chardev backend, RX fills a ring buffer. FLAGS tracks FIFO status and three sysbus IRQ lines (TX, RX, ERR) are pulsed on flag edges. Originally-by: David Brenken Signed-off-by: Parthiban Nallathambi --- hw/char/Kconfig | 3 + hw/char/meson.build | 1 + hw/char/tricore_asclin.c | 457 +++++++++++++++++++++++++++++++++++= ++++ include/hw/char/tricore_asclin.h | 89 ++++++++ 4 files changed, 550 insertions(+) diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 020c0a84bb..5e540241af 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -95,3 +95,6 @@ config IP_OCTAL_232 bool default y depends on IPACK + +config TRICORE_ASCLIN + bool diff --git a/hw/char/meson.build b/hw/char/meson.build index fc3d7ee506..4a7deb3ece 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -35,6 +35,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files(= 'sifive_uart.c')) system_ss.add(when: 'CONFIG_SH_SCI', if_true: files('sh_serial.c')) system_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_us= art.c')) system_ss.add(when: 'CONFIG_STM32L4X5_USART', if_true: files('stm32l4x5_us= art.c')) +system_ss.add(when: 'CONFIG_TRICORE_ASCLIN', if_true: files('tricore_ascli= n.c')) system_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc= _mmuart.c')) system_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) system_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.c'= )) diff --git a/hw/char/tricore_asclin.c b/hw/char/tricore_asclin.c new file mode 100644 index 0000000000..724dddb38c --- /dev/null +++ b/hw/char/tricore_asclin.c @@ -0,0 +1,457 @@ +/* + * TriCore ASCLIN (Asynchronous/Synchronous Interface) UART controller + * + * Copyright (c) 2017 David Brenken + * Copyright (c) 2024 Siemens AG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/core/sysbus.h" +#include "hw/core/irq.h" +#include "hw/core/registerfields.h" +#include "chardev/char-fe.h" +#include "chardev/char-serial.h" +#include "migration/vmstate.h" +#include "hw/char/tricore_asclin.h" +#include "hw/core/qdev-properties-system.h" + +/* + * Register offsets (byte address / 4) for TC3x ASCLIN. + * Each register occupies one 4-byte slot from 0x00 to 0x50. + */ +enum { + R_CLC =3D 0, + R_IOCR, + R_ID, + R_TXFIFOCON, + R_RXFIFOCON, + R_BITCON, + R_FRAMECON, + R_DATCON, + R_BRG, + R_BRD, + R_LINCON, + R_LINBTIMER, + R_LINHTIMER, + R_FLAGS, + R_FLAGSSET, + R_FLAGSCLEAR, + R_FLAGSENABLE, + R_TXDATA, + R_RXDATA, + R_CSR, + R_RXDATAD, +}; + +static void asclin_rx_buf_reset(TriCoreASCLINState *s) +{ + memset(s->rxbuf, 0, ASCLIN_RX_BUF_SIZE); + s->rx_rdidx =3D 0; + s->rx_wridx =3D 0; +} + +static uint32_t asclin_rx_buf_used(TriCoreASCLINState *s) +{ + return ((s->rx_wridx + ASCLIN_RX_BUF_SIZE) - s->rx_rdidx) + % ASCLIN_RX_BUF_SIZE; +} + +static uint32_t asclin_rx_buf_free(TriCoreASCLINState *s) +{ + return (ASCLIN_RX_BUF_SIZE - 1) - asclin_rx_buf_used(s); +} + +/* + * Pulse the appropriate IRQ line for each flag bit that is both + * set and enabled. The TriCore interrupt router is edge-triggered. + */ +static void asclin_pulse_irq(TriCoreASCLINState *s, uint32_t pulse_mask) +{ + uint32_t fired =3D pulse_mask & s->regs[R_FLAGSENABLE]; + + if (fired & ASCLIN_TX_INT_MASK) { + qemu_irq_pulse(s->irq_tx); + } + if (fired & ASCLIN_RX_INT_MASK) { + qemu_irq_pulse(s->irq_rx); + } + if (fired & ASCLIN_ERR_INT_MASK) { + qemu_irq_pulse(s->irq_err); + } +} + +/* + * Watch callback: retries TX when the chardev was previously busy. + */ +static gboolean asclin_tx_watch(void *do_not_use, GIOCondition cond, + void *opaque) +{ + TriCoreASCLINState *s =3D TRICORE_ASCLIN(opaque); + int ret; + + s->watch_tag =3D 0; + + ret =3D qemu_chr_fe_write_all(&s->chr, (uint8_t *)&s->txbuf, 1); + if (ret <=3D 0) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, + G_IO_OUT | G_IO_HUP, + asclin_tx_watch, s); + if (!s->watch_tag) { + goto drained; + } + return G_SOURCE_REMOVE; + } + +drained: + qatomic_or(&s->regs[R_FLAGS], ASCLIN_FLAGS_TFL | ASCLIN_FLAGS_TC); + asclin_pulse_irq(s, ASCLIN_FLAGS_TFL | ASCLIN_FLAGS_TC); + return G_SOURCE_REMOVE; +} + +/* + * Transmit one byte immediately. Re-asserts TFL and TC flags so that + * interrupt-driven drivers can continue filling the FIFO. + */ +static void asclin_txdata_write(TriCoreASCLINState *s, uint32_t value) +{ + int ret; + + s->txbuf =3D value; + ret =3D qemu_chr_fe_write_all(&s->chr, (uint8_t *)&s->txbuf, 1); + if (ret <=3D 0) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, + G_IO_OUT | G_IO_HUP, + asclin_tx_watch, s); + if (!s->watch_tag) { + goto drained; + } + return; + } + +drained: + qatomic_or(&s->regs[R_FLAGS], ASCLIN_FLAGS_TFL | ASCLIN_FLAGS_TC); + asclin_pulse_irq(s, ASCLIN_FLAGS_TFL | ASCLIN_FLAGS_TC); +} + +static void asclin_txfifocon_write(TriCoreASCLINState *s, uint32_t value) +{ + /* FILL field is read-only hardware status */ + s->regs[R_TXFIFOCON] =3D value & ~ASCLIN_FILL_MASK; +} + +static uint32_t asclin_txfifocon_read(TriCoreASCLINState *s) +{ + /* Instant-TX model: FILL always reads as 0 */ + return s->regs[R_TXFIFOCON] & ~ASCLIN_FILL_MASK; +} + +static void asclin_rxfifocon_write(TriCoreASCLINState *s, uint32_t value) +{ + s->regs[R_RXFIFOCON] =3D value & ~ASCLIN_FILL_MASK; + + if (value & ASCLIN_RXFIFOCON_FLUSH) { + asclin_rx_buf_reset(s); + } + if (value & ASCLIN_RXFIFOCON_ENI) { + qemu_chr_fe_accept_input(&s->chr); + } +} + +static uint32_t asclin_rxfifocon_read(TriCoreASCLINState *s) +{ + uint32_t used =3D asclin_rx_buf_used(s); + uint32_t fill =3D MIN(used, ASCLIN_HW_FIFO_DEPTH); + + return (s->regs[R_RXFIFOCON] & ~ASCLIN_FILL_MASK) | + (fill << ASCLIN_FILL_SHIFT); +} + +static uint32_t asclin_rxdata_read(TriCoreASCLINState *s, bool peek) +{ + uint32_t r; + + if (s->rx_rdidx =3D=3D s->rx_wridx) { + return 0; + } + + r =3D s->rxbuf[s->rx_rdidx]; + if (!peek) { + s->rx_rdidx =3D (s->rx_rdidx + 1) % ASCLIN_RX_BUF_SIZE; + } + return r; +} + +static uint32_t asclin_csr_read(TriCoreASCLINState *s) +{ + uint32_t csr =3D s->regs[R_CSR]; + + /* CLKSEL valid: set CON bit (bit 31) when a clock is selected */ + if (csr & 0x1f) { + csr |=3D (1u << 31); + } + return csr; +} + +static void asclin_flagsset_write(TriCoreASCLINState *s, uint32_t value) +{ + qatomic_or(&s->regs[R_FLAGS], value); + asclin_pulse_irq(s, value); +} + +static void asclin_flagsclear_write(TriCoreASCLINState *s, uint32_t value) +{ + qatomic_and(&s->regs[R_FLAGS], ~value); +} + +/* + * FLAGSENABLE write: newly-enabled bits whose FLAGS is already set + * must produce a rising edge on the corresponding interrupt line. + */ +static void asclin_flagsenable_write(TriCoreASCLINState *s, uint32_t value) +{ + uint32_t old_en =3D s->regs[R_FLAGSENABLE]; + uint32_t newly_enabled =3D value & ~old_en; + + s->regs[R_FLAGSENABLE] =3D value; + asclin_pulse_irq(s, newly_enabled & s->regs[R_FLAGS]); +} + +static uint64_t asclin_read(void *opaque, hwaddr offset, unsigned size) +{ + TriCoreASCLINState *s =3D opaque; + hwaddr reg =3D offset >> 2; + + switch (reg) { + case R_CLC: + case R_IOCR: + case R_ID: + case R_BITCON: + case R_FRAMECON: + case R_DATCON: + case R_BRG: + case R_BRD: + case R_LINCON: + case R_LINBTIMER: + case R_LINHTIMER: + case R_FLAGS: + case R_FLAGSENABLE: + return s->regs[reg]; + case R_TXFIFOCON: + return asclin_txfifocon_read(s); + case R_RXFIFOCON: + return asclin_rxfifocon_read(s); + case R_FLAGSSET: + case R_FLAGSCLEAR: + return 0; + case R_TXDATA: + return 0; + case R_RXDATA: + return asclin_rxdata_read(s, false); + case R_CSR: + return asclin_csr_read(s); + case R_RXDATAD: + return asclin_rxdata_read(s, true); + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from unknown offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return 0; + } +} + +static void asclin_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + TriCoreASCLINState *s =3D opaque; + hwaddr reg =3D offset >> 2; + uint32_t val =3D (uint32_t)value; + + switch (reg) { + case R_CLC: + case R_IOCR: + case R_ID: + case R_BITCON: + case R_FRAMECON: + case R_DATCON: + case R_BRG: + case R_BRD: + case R_LINCON: + case R_LINBTIMER: + case R_LINHTIMER: + s->regs[reg] =3D val; + break; + case R_TXFIFOCON: + asclin_txfifocon_write(s, val); + break; + case R_RXFIFOCON: + asclin_rxfifocon_write(s, val); + break; + case R_FLAGS: + /* read-only hardware status */ + break; + case R_FLAGSSET: + asclin_flagsset_write(s, val); + break; + case R_FLAGSCLEAR: + asclin_flagsclear_write(s, val); + break; + case R_FLAGSENABLE: + asclin_flagsenable_write(s, val); + break; + case R_TXDATA: + asclin_txdata_write(s, val); + break; + case R_RXDATA: + case R_RXDATAD: + /* read-only */ + break; + case R_CSR: + s->regs[R_CSR] =3D val; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to unknown offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + break; + } +} + +static const MemoryRegionOps asclin_ops =3D { + .read =3D asclin_read, + .write =3D asclin_write, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void asclin_uart_rx(void *opaque, const uint8_t *buf, int size) +{ + TriCoreASCLINState *s =3D opaque; + + while (size > 0) { + if (asclin_rx_buf_free(s) =3D=3D 0) { + qatomic_or(&s->regs[R_FLAGS], ASCLIN_FLAGS_RFO); + asclin_pulse_irq(s, ASCLIN_FLAGS_RFO); + break; + } + s->rxbuf[s->rx_wridx] =3D *buf++; + s->rx_wridx =3D (s->rx_wridx + 1) % ASCLIN_RX_BUF_SIZE; + size--; + } + + if (s->rx_rdidx !=3D s->rx_wridx) { + qatomic_or(&s->regs[R_FLAGS], ASCLIN_FLAGS_RFL); + asclin_pulse_irq(s, ASCLIN_FLAGS_RFL); + } +} + +static int asclin_uart_can_rx(void *opaque) +{ + TriCoreASCLINState *s =3D TRICORE_ASCLIN(opaque); + + if ((s->regs[R_RXFIFOCON] & ASCLIN_RXFIFOCON_ENI) && + asclin_rx_buf_free(s) > 0) { + return 1; + } + return 0; +} + +static void asclin_uart_event(void *opaque, QEMUChrEvent event) +{ +} + +static void asclin_uart_reset_hold(Object *obj, ResetType type) +{ + TriCoreASCLINState *s =3D TRICORE_ASCLIN(obj); + int i; + + for (i =3D 0; i < ASCLIN_R_MAX; i++) { + s->regs[i] =3D 0; + } + asclin_rx_buf_reset(s); +} + +static void asclin_uart_realize(DeviceState *dev, Error **errp) +{ + TriCoreASCLINState *s =3D TRICORE_ASCLIN(dev); + + qemu_chr_fe_set_handlers(&s->chr, asclin_uart_can_rx, + asclin_uart_rx, asclin_uart_event, + NULL, s, NULL, true); +} + +static void asclin_uart_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + TriCoreASCLINState *s =3D TRICORE_ASCLIN(obj); + + memory_region_init_io(&s->iomem, obj, &asclin_ops, s, + TYPE_TRICORE_ASCLIN, 0x100); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_rx); + sysbus_init_irq(sbd, &s->irq_tx); + sysbus_init_irq(sbd, &s->irq_err); +} + +static int asclin_uart_post_load(void *opaque, int version_id) +{ + TriCoreASCLINState *s =3D TRICORE_ASCLIN(opaque); + + if (s->regs[R_FLAGS] & ASCLIN_FLAGS_TFL) { + s->watch_tag =3D qemu_chr_fe_add_watch(&s->chr, + G_IO_OUT | G_IO_HUP, + asclin_tx_watch, s); + } + return 0; +} + +static const VMStateDescription vmstate_asclin_uart =3D { + .name =3D TYPE_TRICORE_ASCLIN, + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D asclin_uart_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, TriCoreASCLINState, ASCLIN_R_MAX), + VMSTATE_END_OF_LIST() + }, +}; + +static const Property asclin_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", TriCoreASCLINState, chr), +}; + +static void asclin_uart_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D asclin_uart_realize; + rc->phases.hold =3D asclin_uart_reset_hold; + dc->vmsd =3D &vmstate_asclin_uart; + device_class_set_props(dc, asclin_uart_properties); +} + +static const TypeInfo asclin_uart_info =3D { + .name =3D TYPE_TRICORE_ASCLIN, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TriCoreASCLINState), + .instance_init =3D asclin_uart_init, + .class_init =3D asclin_uart_class_init, +}; + +static void asclin_uart_register_types(void) +{ + type_register_static(&asclin_uart_info); +} + +type_init(asclin_uart_register_types) diff --git a/include/hw/char/tricore_asclin.h b/include/hw/char/tricore_asc= lin.h new file mode 100644 index 0000000000..b142515c50 --- /dev/null +++ b/include/hw/char/tricore_asclin.h @@ -0,0 +1,89 @@ +/* + * TriCore ASCLIN (Asynchronous/Synchronous Interface) UART controller + * + * Copyright (c) 2017 David Brenken + * Copyright (c) 2024 Siemens AG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_TRICORE_ASCLIN_H +#define HW_TRICORE_ASCLIN_H + +#include "chardev/char-fe.h" +#include "hw/core/sysbus.h" +#include "qom/object.h" + +/* FLAGS register bits */ +#define ASCLIN_FLAGS_TH (1u << 0) +#define ASCLIN_FLAGS_TR (1u << 1) +#define ASCLIN_FLAGS_RH (1u << 2) +#define ASCLIN_FLAGS_RR (1u << 3) +#define ASCLIN_FLAGS_FED (1u << 5) +#define ASCLIN_FLAGS_RED (1u << 6) +#define ASCLIN_FLAGS_PE (1u << 16) +#define ASCLIN_FLAGS_TC (1u << 17) +#define ASCLIN_FLAGS_FE (1u << 18) +#define ASCLIN_FLAGS_HT (1u << 19) +#define ASCLIN_FLAGS_RT (1u << 20) +#define ASCLIN_FLAGS_BD (1u << 21) +#define ASCLIN_FLAGS_LP (1u << 22) +#define ASCLIN_FLAGS_LA (1u << 23) +#define ASCLIN_FLAGS_LC (1u << 24) +#define ASCLIN_FLAGS_CE (1u << 25) +#define ASCLIN_FLAGS_RFO (1u << 26) +#define ASCLIN_FLAGS_RFU (1u << 27) +#define ASCLIN_FLAGS_RFL (1u << 28) +#define ASCLIN_FLAGS_TFO (1u << 30) +#define ASCLIN_FLAGS_TFL (1u << 31) + +/* RXFIFOCON bits */ +#define ASCLIN_RXFIFOCON_FLUSH 0x1 +#define ASCLIN_RXFIFOCON_ENI 0x2 + +/* Interrupt line grouping masks */ +#define ASCLIN_TX_INT_MASK (ASCLIN_FLAGS_TH | ASCLIN_FLAGS_TR | \ + ASCLIN_FLAGS_TFL) +#define ASCLIN_RX_INT_MASK (ASCLIN_FLAGS_RH | ASCLIN_FLAGS_RR | \ + ASCLIN_FLAGS_RFL) +#define ASCLIN_ERR_INT_MASK (ASCLIN_FLAGS_FED | ASCLIN_FLAGS_RED | \ + ASCLIN_FLAGS_PE | ASCLIN_FLAGS_TC | \ + ASCLIN_FLAGS_FE | ASCLIN_FLAGS_HT | \ + ASCLIN_FLAGS_RT | ASCLIN_FLAGS_BD | \ + ASCLIN_FLAGS_LP | ASCLIN_FLAGS_LA | \ + ASCLIN_FLAGS_LC | ASCLIN_FLAGS_CE | \ + ASCLIN_FLAGS_RFO | ASCLIN_FLAGS_RFU | \ + ASCLIN_FLAGS_TFO) + +/* FIFO depth and FILL field position in TX/RXFIFOCON */ +#define ASCLIN_HW_FIFO_DEPTH 16 +#define ASCLIN_FILL_SHIFT 16 +#define ASCLIN_FILL_MASK (0x1fu << ASCLIN_FILL_SHIFT) + +#define ASCLIN_R_MAX 21 +#define ASCLIN_RX_BUF_SIZE 8192 + +#define TYPE_TRICORE_ASCLIN "tricore_asclin" +OBJECT_DECLARE_SIMPLE_TYPE(TriCoreASCLINState, TRICORE_ASCLIN) + +struct TriCoreASCLINState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + CharFrontend chr; + qemu_irq irq_rx; + qemu_irq irq_tx; + qemu_irq irq_err; + + guint watch_tag; + uint32_t regs[ASCLIN_R_MAX]; + uint32_t txbuf; + + uint8_t rxbuf[ASCLIN_RX_BUF_SIZE]; + uint32_t rx_wridx; + uint32_t rx_rdidx; +}; + +#endif --=20 2.47.3 From nobody Mon Jun 8 08:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=linumiz.com) ARC-Seal: i=2; a=rsa-sha256; t=1780219963; cv=pass; d=zohomail.com; s=zohoarc; b=UgEHLRoN6iLfdqztg0JPARPkFTwRNBJBvMkgztCziXczlzWFS4yc0GEpICvD0rOn8o0VrqwZxno7vnRGtIOXT+EAOlmjXeXlqgWqJIxU6RIuxc7vkMjPoS9tn843qC8UlsgxgqUJJXli5cYp82hRSrnX2JGxQjll77ap4s13S1E= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780219963; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780219965592158500 Free-running 64-bit counter with compare match interrupt. TIM0..TIM6 give shifted views of the counter, CMP0 fires when the masked counter matches the programmed value. Originally-by: Christoph Seitz Signed-off-by: Parthiban Nallathambi --- hw/timer/Kconfig | 4 + hw/timer/meson.build | 2 + hw/timer/tricore_stm.c | 328 +++++++++++++++++++++++++++++++++++++= ++++ include/hw/timer/tricore_stm.h | 76 ++++++++++ 4 files changed, 410 insertions(+) diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index b3d823ce2c..250452b3fa 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -65,3 +65,7 @@ config STELLARIS_GPTM =20 config AVR_TIMER16 bool + +config TRICORE_STM + bool + select TRICORE_IRBUS diff --git a/hw/timer/meson.build b/hw/timer/meson.build index 201b5d8316..78d67a7e69 100644 --- a/hw/timer/meson.build +++ b/hw/timer/meson.build @@ -34,3 +34,5 @@ specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex= _timer.c')) system_ss.add(when: 'CONFIG_SIFIVE_PWM', if_true: files('sifive_pwm.c')) =20 system_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c')) + +system_ss.add(when: 'CONFIG_TRICORE_STM', if_true: files('tricore_stm.c')) diff --git a/hw/timer/tricore_stm.c b/hw/timer/tricore_stm.c new file mode 100644 index 0000000000..376e680bc7 --- /dev/null +++ b/hw/timer/tricore_stm.c @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU TriCore System Timer Module (STM) + * + * Copyright (c) 2024 Infineon Technologies AG + */ + +#include "qemu/osdep.h" +#include "hw/core/clock.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-clock.h" +#include "hw/timer/tricore_stm.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/timer.h" + +enum { + R_CLC, + R_RESERVED1, + R_ID, + R_RESERVED2, + R_TIM0, + R_TIM1, + R_TIM2, + R_TIM3, + R_TIM4, + R_TIM5, + R_TIM6, + R_CAP, + R_CMP0, + R_CMP1, + R_CMCON, + R_ICR, + R_ISCR, + R_RESERVED3, + R_TIM0SV =3D 0x50 / 4, + R_CAPSV, + R_RESERVED4, + R_OCS =3D 0xE8 / 4, + R_KRSTCLR, + R_KRST1, + R_KRST0, + R_ACCEN1, + R_ACCEN0, +}; + +static void tricore_stm_tim_update(TriCoreSTMState *s) +{ + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + s->tim_counter +=3D clock_ns_to_ticks(s->fstm, now - s->tim_base_ns); + s->tim_base_ns =3D now; +} + +static void tricore_stm_timer_update(TriCoreSTMState *s) +{ + uint32_t mstart =3D (s->regs[R_CMCON] & MASK_CMCON_MSTART0) >> 8; + uint32_t msize =3D s->regs[R_CMCON] & MASK_CMCON_MSIZE0; + uint32_t nbits =3D msize + 1; + uint64_t tim_target =3D s->tim_counter; + + if (!(s->regs[R_ICR] & MASK_ICR_CMP0EN) && + (s->regs[R_ICR] & MASK_ICR_CMP0IR)) { + return; + } + + /* Calculate the target TIM value */ + if (mstart) { + tim_target =3D deposit64(tim_target, 0, mstart, 0); + } + tim_target =3D deposit64(tim_target, mstart, nbits, + (uint64_t)s->regs[R_CMP0]); + + /* Wrap around if needed */ + if (tim_target <=3D s->tim_counter) { + tim_target +=3D (1ULL << (mstart + nbits)); + } + + timer_mod(s->timer, + s->tim_base_ns + + clock_ticks_to_ns(s->fstm, tim_target - s->tim_counter)); +} + +static void tricore_stm_clock_update(void *opaque, enum ClockEvent event) +{ + TriCoreSTMState *s =3D TRICORE_STM(opaque); + + if (event =3D=3D ClockPreUpdate) { + tricore_stm_tim_update(s); + } else { + tricore_stm_timer_update(s); + } +} + +static void tricore_stm_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + TriCoreSTMState *s =3D TRICORE_STM(opaque); + hwaddr reg_addr =3D offset >> 2; + + switch (reg_addr) { + case R_CLC: + case R_ID: + case R_TIM0: + case R_TIM1: + case R_TIM2: + case R_TIM3: + case R_TIM4: + case R_TIM5: + case R_TIM6: + case R_CAP: + s->regs[reg_addr] =3D value; + break; + case R_CMP0: + s->regs[reg_addr] =3D value; + tricore_stm_tim_update(s); + tricore_stm_timer_update(s); + break; + case R_CMP1: + case R_ICR: + s->regs[reg_addr] =3D value; + tricore_stm_timer_update(s); + break; + case R_CMCON: + s->regs[reg_addr] =3D value; + tricore_stm_tim_update(s); + tricore_stm_timer_update(s); + break; + case R_ISCR: + if (value & MASK_ISCR_CMP0IRR) { + qatomic_and(&s->regs[R_ICR], ~MASK_ICR_CMP0IR); + } + if (value & MASK_ISCR_CMP1IRR) { + qatomic_and(&s->regs[R_ICR], ~MASK_ICR_CMP1IR); + } + if (value & MASK_ISCR_CMP0IRS) { + qatomic_or(&s->regs[R_ICR], MASK_ICR_CMP0IR); + } + if (value & MASK_ISCR_CMP1IRS) { + qatomic_or(&s->regs[R_ICR], MASK_ICR_CMP1IR); + } + tricore_stm_timer_update(s); + break; + case R_TIM0SV: + case R_CAPSV: + case R_OCS: + case R_KRSTCLR: + case R_KRST1: + case R_KRST0: + case R_ACCEN1: + case R_ACCEN0: + s->regs[reg_addr] =3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, + "tricore_stm: write to unknown register 0x%" + HWADDR_PRIx "\n", offset); + break; + } +} + +static uint64_t tricore_stm_read(void *opaque, hwaddr offset, + unsigned size) +{ + TriCoreSTMState *s =3D TRICORE_STM(opaque); + uint64_t r =3D 0; + hwaddr reg_addr =3D offset >> 2; + + if ((reg_addr >=3D R_TIM0 && reg_addr <=3D R_TIM6) || + reg_addr =3D=3D R_TIM0SV) { + tricore_stm_tim_update(s); + s->regs[R_CAP] =3D (uint32_t)(s->tim_counter >> 32); + } + + switch (reg_addr) { + case R_CLC: + case R_ID: + r =3D s->regs[reg_addr]; + break; + case R_TIM0: + case R_TIM1: + case R_TIM2: + case R_TIM3: + case R_TIM4: + case R_TIM5: + case R_TIM6: + r =3D s->tim_counter << (reg_addr - R_TIM0) * 4; + break; + case R_CAP: + r =3D s->regs[R_CAP]; + break; + case R_ISCR: + r =3D 0; + break; + case R_CMP0: + case R_CMP1: + case R_CMCON: + case R_ICR: + r =3D s->regs[reg_addr]; + break; + case R_TIM0SV: + r =3D s->tim_counter; + break; + case R_CAPSV: + r =3D s->regs[R_CAP]; + break; + case R_OCS: + case R_KRSTCLR: + case R_KRST1: + case R_KRST0: + case R_ACCEN1: + case R_ACCEN0: + r =3D s->regs[reg_addr]; + break; + default: + qemu_log_mask(LOG_UNIMP, + "tricore_stm: read from unknown register 0x%" + HWADDR_PRIx "\n", offset); + r =3D 0; + break; + } + + return r; +} + +static void tricore_stm_reset(DeviceState *dev) +{ + TriCoreSTMState *s =3D TRICORE_STM(dev); + + s->regs[R_CLC] =3D RESET_TRICORE_STM_CLC; + s->regs[R_ID] =3D RESET_TRICORE_STM_ID; + s->regs[R_TIM0] =3D RESET_TRICORE_STM_TIM0; + s->regs[R_TIM1] =3D RESET_TRICORE_STM_TIM1; + s->regs[R_TIM2] =3D RESET_TRICORE_STM_TIM2; + s->regs[R_TIM3] =3D RESET_TRICORE_STM_TIM3; + s->regs[R_TIM4] =3D RESET_TRICORE_STM_TIM4; + s->regs[R_TIM5] =3D RESET_TRICORE_STM_TIM5; + s->regs[R_TIM6] =3D RESET_TRICORE_STM_TIM6; + s->regs[R_CAP] =3D RESET_TRICORE_STM_CAP; + s->regs[R_CMP0] =3D RESET_TRICORE_STM_CMP0; + s->regs[R_CMP1] =3D RESET_TRICORE_STM_CMP1; + s->regs[R_CMCON] =3D RESET_TRICORE_STM_CMCON; + s->regs[R_ICR] =3D RESET_TRICORE_STM_ICR; + s->regs[R_ISCR] =3D RESET_TRICORE_STM_ISCR; + s->regs[R_TIM0SV] =3D RESET_TRICORE_STM_TIM0SV; + s->regs[R_CAPSV] =3D RESET_TRICORE_STM_CAPSV; + s->regs[R_OCS] =3D RESET_TRICORE_STM_OCS; + s->regs[R_KRSTCLR] =3D RESET_TRICORE_STM_KRSTCLR; + s->regs[R_KRST1] =3D RESET_TRICORE_STM_KRST1; + s->regs[R_KRST0] =3D RESET_TRICORE_STM_KRST0; + s->regs[R_ACCEN1] =3D RESET_TRICORE_STM_ACCEN1; + s->regs[R_ACCEN0] =3D RESET_TRICORE_STM_ACCEN0; + + s->tim_counter =3D 0; + s->tim_base_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); +} + +static const MemoryRegionOps tricore_stm_ops =3D { + .read =3D tricore_stm_read, + .write =3D tricore_stm_write, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void tricore_stm_timer_hit(void *opaque) +{ + TriCoreSTMState *s =3D TRICORE_STM(opaque); + + qatomic_or(&s->regs[R_ICR], MASK_ICR_CMP0IR); + + if (s->regs[R_ICR] & MASK_ICR_CMP0EN) { + qemu_irq_pulse(s->irq); + } + + tricore_stm_tim_update(s); + tricore_stm_timer_update(s); +} + +static void tricore_stm_realize(DeviceState *dev, Error **errp) +{ + TriCoreSTMState *s =3D TRICORE_STM(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, tricore_stm_timer_hit, s= ); + s->tim_base_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + s->tim_counter =3D 0; + + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static void tricore_stm_init(Object *obj) +{ + TriCoreSTMState *s =3D TRICORE_STM(obj); + + memory_region_init_io(&s->iomem, OBJECT(s), &tricore_stm_ops, s, + "tricore_stm", 0x100); + s->fstm =3D qdev_init_clock_in(DEVICE(s), "fstm", + tricore_stm_clock_update, s, + ClockPreUpdate | ClockUpdate); +} + +static void tricore_stm_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->legacy_reset =3D tricore_stm_reset; + dc->realize =3D tricore_stm_realize; +} + +static const TypeInfo tricore_stm_info =3D { + .name =3D TYPE_TRICORE_STM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TriCoreSTMState), + .instance_init =3D tricore_stm_init, + .class_init =3D tricore_stm_class_init, +}; + +static void tricore_stm_register_types(void) +{ + type_register_static(&tricore_stm_info); +} + +type_init(tricore_stm_register_types) diff --git a/include/hw/timer/tricore_stm.h b/include/hw/timer/tricore_stm.h new file mode 100644 index 0000000000..48345f5181 --- /dev/null +++ b/include/hw/timer/tricore_stm.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU TriCore System Timer Module (STM) + * + * Copyright (c) 2024 Infineon Technologies AG + */ + +#ifndef HW_TRICORE_STM_H +#define HW_TRICORE_STM_H + +#include "hw/core/clock.h" +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "qemu/timer.h" + +#define TYPE_TRICORE_STM "tricore_stm" +OBJECT_DECLARE_SIMPLE_TYPE(TriCoreSTMState, TRICORE_STM) + +#define MASK_ICR_CMP0EN 0x01 +#define MASK_ICR_CMP0IR 0x02 +#define MASK_ICR_CMP1EN 0x10 +#define MASK_ICR_CMP1IR 0x20 + +#define MASK_ISCR_CMP0IRR 0x1 +#define MASK_ISCR_CMP0IRS 0x2 +#define MASK_ISCR_CMP1IRR 0x4 +#define MASK_ISCR_CMP1IRS 0x8 + +#define MASK_CMCON_MSIZE0 0x1F +#define MASK_CMCON_MSTART0 0x1F00 +#define MASK_CMCON_MSIZE1 0x1F0000 +#define MASK_CMCON_MSTART1 0x1F000000 + +#define STM_R_MAX (0x100 / 4) + +/* Reset values */ +#define RESET_TRICORE_STM_CLC 0x0 +#define RESET_TRICORE_STM_ID 0x0000C000 +#define RESET_TRICORE_STM_TIM0 0x0 +#define RESET_TRICORE_STM_TIM1 0x0 +#define RESET_TRICORE_STM_TIM2 0x0 +#define RESET_TRICORE_STM_TIM3 0x0 +#define RESET_TRICORE_STM_TIM4 0x0 +#define RESET_TRICORE_STM_TIM5 0x0 +#define RESET_TRICORE_STM_TIM6 0x0 +#define RESET_TRICORE_STM_CAP 0x0 +#define RESET_TRICORE_STM_CMP0 0x0 +#define RESET_TRICORE_STM_CMP1 0x0 +#define RESET_TRICORE_STM_CMCON 0x0 +#define RESET_TRICORE_STM_ICR 0x0 +#define RESET_TRICORE_STM_ISCR 0x0 +#define RESET_TRICORE_STM_TIM0SV 0x0 +#define RESET_TRICORE_STM_CAPSV 0x0 +#define RESET_TRICORE_STM_OCS 0x0 +#define RESET_TRICORE_STM_KRSTCLR 0x0 +#define RESET_TRICORE_STM_KRST1 0x0 +#define RESET_TRICORE_STM_KRST0 0x0 +#define RESET_TRICORE_STM_ACCEN1 0x0 +#define RESET_TRICORE_STM_ACCEN0 0xFFFFFFFF + +struct TriCoreSTMState { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion iomem; + QEMUTimer *timer; + Clock *fstm; + qemu_irq irq; + + uint32_t regs[STM_R_MAX]; + uint64_t tim_counter; + int64_t tim_base_ns; +}; + +#endif /* HW_TRICORE_STM_H */ --=20 2.47.3 From nobody Mon Jun 8 08:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=linumiz.com) ARC-Seal: i=2; a=rsa-sha256; t=1780219990; cv=pass; d=zohomail.com; s=zohoarc; b=fMPJFuIlWx5aB2/470qNQhs2ghJxSCxbfaCNHteKm5kpcOLqWvUdYrR6x3rG0IFq9fDnlxDWOuyDIEMdOEeedVRUXMsQWzZ63Qh1WTfUwnqBrnGwnTICzOlg0N4xDlEYhLLEufy5ir+G48Td2nElc7A7wtq2gHUTHNlfSqribXA= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780219990; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780219991596158501 Stub the PLL, oscillator and clock control registers that firmware reads during boot. PLL always reports locked so startup code does not time out. Originally-by: David Brenken Originally-by: Christoph Seitz Signed-off-by: Parthiban Nallathambi --- hw/tricore/meson.build | 2 + hw/tricore/tricore_scu.c | 240 +++++++++++++++++++++++++++++++++++= ++++ include/hw/tricore/tricore_scu.h | 103 +++++++++++++++++ 3 files changed, 345 insertions(+) diff --git a/hw/tricore/meson.build b/hw/tricore/meson.build index 7e3585daf8..96e367f996 100644 --- a/hw/tricore/meson.build +++ b/hw/tricore/meson.build @@ -3,5 +3,7 @@ tricore_ss.add(when: 'CONFIG_TRICORE_TESTBOARD', if_true: f= iles('tricore_testboa tricore_ss.add(when: 'CONFIG_TRICORE_TESTBOARD', if_true: files('tricore_t= estdevice.c')) tricore_ss.add(when: 'CONFIG_TRIBOARD', if_true: files('triboard.c')) tricore_ss.add(when: 'CONFIG_TC27X_SOC', if_true: files('tc27x_soc.c')) +tricore_ss.add(when: 'CONFIG_TC39X_SOC', if_true: files('tc39xb_soc.c')) +tricore_ss.add(when: 'CONFIG_TRICORE_SCU', if_true: files('tricore_scu.c')) =20 hw_arch +=3D {'tricore': tricore_ss} diff --git a/hw/tricore/tricore_scu.c b/hw/tricore/tricore_scu.c new file mode 100644 index 0000000000..4baabc7d82 --- /dev/null +++ b/hw/tricore/tricore_scu.c @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU TriCore System Control Unit (SCU) + * + * Copyright (c) 2017 David Brenken + * Copyright (c) 2024 Infineon Technologies AG + */ + +#include "qemu/osdep.h" +#include "hw/tricore/tricore_scu.h" +#include "qemu/log.h" +#include "qemu/module.h" + +/* Register offsets */ +enum { + A_OSCCON =3D 0x10, + A_PLLSTAT =3D 0x14, + A_PLLCON0 =3D 0x18, + A_PLLCON1 =3D 0x1C, + A_PLLCON2 =3D 0x20, + A_PLLERAYSTAT =3D 0x24, + A_CCUCON0 =3D 0x30, + A_CCUCON1 =3D 0x34, + A_CCUCON2 =3D 0x40, + A_CCUCON3 =3D 0x44, + A_CCUCON4 =3D 0x48, + A_CCUCON5 =3D 0x4C, + A_WDTSCON0 =3D 0xF0, + A_WDTCPU0CON0 =3D 0x100, + A_CHIPID =3D 0x140, +}; + +static void tricore_scu_update_ccucon(TriCoreSCUState *s) +{ + if ((s->ccucon[0] & MASK_CCUCON0_UP) || + (s->ccucon[1] & MASK_CCUCON1_UP) || + (s->ccucon[5] & MASK_CCUCON5_UP)) { + s->ccucon[0] &=3D ~(MASK_CCUCON0_UP | (1U << 31)); + s->ccucon[1] &=3D ~(MASK_CCUCON1_UP | (1U << 31)); + s->ccucon[5] &=3D ~(MASK_CCUCON5_UP | (1U << 31)); + } +} + +static uint64_t tricore_scu_read(void *opaque, hwaddr offset, + unsigned size) +{ + TriCoreSCUState *s =3D TRICORE_SCU(opaque); + + switch (offset) { + case A_OSCCON: + return s->osccon; + case A_PLLSTAT: + /* + * Report PLL as always locked: VCOLOCK=3D1, K1RDY=3D1, K2RDY=3D1. + * Firmware polls these bits during clock initialisation. + */ + return 0x00000077; + case A_PLLCON0: + return s->pllcon[0]; + case A_PLLCON1: + return s->pllcon[1]; + case A_PLLCON2: + return s->pllcon[2]; + case A_PLLERAYSTAT: + return 0x00000077; + case A_CCUCON0: + return s->ccucon[0]; + case A_CCUCON1: + return s->ccucon[1]; + case A_CCUCON2: + return s->ccucon[2]; + case A_CCUCON3: + return s->ccucon[3]; + case A_CCUCON4: + return s->ccucon[4]; + case A_CCUCON5: + return s->ccucon[5]; + case A_WDTSCON0: + return s->wdtscon1; + case A_WDTCPU0CON0: + return s->wdtcpu0con0; + case A_CHIPID: + return 0x47477172 | (1U << 31); + default: + if (offset < SCU_REG_SIZE) { + return s->regs[offset / 4]; + } + qemu_log_mask(LOG_GUEST_ERROR, + "tricore_scu: read at bad offset 0x%" HWADDR_PRIx "\= n", + offset); + return 0; + } +} + +static void tricore_scu_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + TriCoreSCUState *s =3D TRICORE_SCU(opaque); + + switch (offset) { + case A_OSCCON: + s->osccon =3D (uint32_t)value; + /* + * Real silicon raises PLLHV and PLLLV once the external + * oscillator is stable. Mark stable immediately. + */ + s->osccon |=3D MASK_OSCCON_PLLHV | MASK_OSCCON_PLLLV; + break; + case A_PLLCON0: + s->pllcon[0] =3D (uint32_t)value; + if (s->pllcon[0] & MASK_PLLCON0_SETFINDIS) { + s->pllstat |=3D MASK_PLLSTAT_FINDIS; + } + if (s->pllcon[0] & MASK_PLLCON0_CLRFINDIS) { + s->pllstat &=3D ~MASK_PLLSTAT_FINDIS; + } + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_PLLCON1: + s->pllcon[1] =3D (uint32_t)value; + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_PLLCON2: + s->pllcon[2] =3D (uint32_t)value; + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_CCUCON0: + s->ccucon[0] =3D (uint32_t)value; + tricore_scu_update_ccucon(s); + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_CCUCON1: + s->ccucon[1] =3D (uint32_t)value; + tricore_scu_update_ccucon(s); + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_CCUCON2: + s->ccucon[2] =3D (uint32_t)value & ~(1U << 31); + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_CCUCON3: + s->ccucon[3] =3D (uint32_t)value & ~(1U << 31); + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_CCUCON4: + s->ccucon[4] =3D (uint32_t)value & ~(1U << 31); + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_CCUCON5: + s->ccucon[5] =3D (uint32_t)value; + tricore_scu_update_ccucon(s); + s->pllstat |=3D MASK_PLLSTAT_VCOLOCK; + break; + case A_WDTSCON0: + s->wdtscon1 =3D (uint32_t)value; + break; + case A_WDTCPU0CON0: + s->wdtcpu0con0 =3D (uint32_t)value; + break; + default: + if (offset < SCU_REG_SIZE) { + s->regs[offset / 4] =3D (uint32_t)value & ~(1U << 31); + return; + } + qemu_log_mask(LOG_GUEST_ERROR, + "tricore_scu: write at bad offset 0x%" + HWADDR_PRIx "\n", offset); + break; + } +} + +static const MemoryRegionOps tricore_scu_ops =3D { + .read =3D tricore_scu_read, + .write =3D tricore_scu_write, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void tricore_scu_reset_hold(Object *obj, ResetType type) +{ + TriCoreSCUState *s =3D TRICORE_SCU(obj); + + s->ccucon[0] =3D RESET_TRICORE_CCUCON0; + s->ccucon[1] =3D RESET_TRICORE_CCUCON1; + s->ccucon[2] =3D RESET_TRICORE_CCUCON2; + s->ccucon[3] =3D RESET_TRICORE_CCUCON3; + s->ccucon[4] =3D RESET_TRICORE_CCUCON4; + s->ccucon[5] =3D RESET_TRICORE_CCUCON5; + s->fdr =3D RESET_TRICORE_FDR; + s->extcon =3D RESET_TRICORE_EXTCON; + + s->osccon =3D RESET_TRICORE_OSCCON | MASK_OSCCON_PLLHV | MASK_OSCCON_P= LLLV; + + s->pllcon[0] =3D RESET_TRICORE_PLLCON0; + s->pllcon[1] =3D RESET_TRICORE_PLLCON1; + s->pllcon[2] =3D RESET_TRICORE_PLLCON2; + s->plleraycon[0] =3D RESET_TRICORE_PLLERAYCON0; + s->plleraycon[1] =3D RESET_TRICORE_PLLERAYCON1; + s->plleraystat =3D RESET_TRICORE_PLLERAYSTAT; + s->pllstat =3D RESET_TRICORE_PLLSTAT | MASK_PLLSTAT_VCOLOCK; + + s->wdtcpu0con0 =3D RESET_TRICORE_WDTCPU0CON0; + s->wdtscon0 =3D RESET_TRICORE_WDTSCON0; + s->wdtscon1 =3D RESET_TRICORE_WDTSCON1; +} + +static void tricore_scu_init(Object *obj) +{ + TriCoreSCUState *s =3D TRICORE_SCU(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &tricore_scu_ops, s, + TYPE_TRICORE_SCU, SCU_REG_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void tricore_scu_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D tricore_scu_reset_hold; +} + +static const TypeInfo tricore_scu_info =3D { + .name =3D TYPE_TRICORE_SCU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TriCoreSCUState), + .instance_init =3D tricore_scu_init, + .class_init =3D tricore_scu_class_init, +}; + +static void tricore_scu_register_types(void) +{ + type_register_static(&tricore_scu_info); +} + +type_init(tricore_scu_register_types) diff --git a/include/hw/tricore/tricore_scu.h b/include/hw/tricore/tricore_= scu.h new file mode 100644 index 0000000000..9cb7c916d0 --- /dev/null +++ b/include/hw/tricore/tricore_scu.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU TriCore System Control Unit (SCU) + * + * Copyright (c) 2017 David Brenken + * Copyright (c) 2024 Infineon Technologies AG + */ + +#ifndef HW_TRICORE_SCU_H +#define HW_TRICORE_SCU_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define TYPE_TRICORE_SCU "tricore_scu" +OBJECT_DECLARE_SIMPLE_TYPE(TriCoreSCUState, TRICORE_SCU) + +/* OSCCON bit positions (iLLD IfxScu_bf.h) */ +#define MASK_OSCCON_PLLLV 0x00000002 /* bit 1 */ +#define MASK_OSCCON_PLLHV 0x00000100 /* bit 8 */ + +/* PLLCON0 fields */ +#define MASK_PLLCON0_VCOBYP 0x00000001 +#define MASK_PLLCON0_SETFINDIS 0x00000010 +#define MASK_PLLCON0_CLRFINDIS 0x00000020 +#define MASK_PLLCON0_NDIV 0x0000FE00 +#define MASK_PLLCON0_PDIV 0x0F000000 + +/* PLLCON1 fields */ +#define MASK_PLLCON1_K1DIV 0x007F0000 +#define MASK_PLLCON1_K2DIV 0x0000003F + +/* PLLSTAT fields */ +#define MASK_PLLSTAT_VCOBYST 0x00000001 +#define MASK_PLLSTAT_VCOLOCK 0x00000004 +#define MASK_PLLSTAT_FINDIS 0x00000008 + +/* CCUCON fields */ +#define MASK_CCUCON0_SRIDIV 0x00000F00 +#define MASK_CCUCON0_SPBDIV 0x000F0000 +#define MASK_CCUCON0_UP 0x40000000 +#define MASK_CCUCON1_STMDIV 0x00000F00 +#define MASK_CCUCON1_INSEL 0x30000000 +#define MASK_CCUCON1_INSEL_BACKUP 0x00000000 +#define MASK_CCUCON1_INSEL_OSC0 0x10000000 +#define MASK_CCUCON1_UP 0x40000000 +#define MASK_CCUCON5_UP 0x40000000 + +/* Reset values */ +#define RESET_TRICORE_OSCCON 0x00000112 +#define RESET_TRICORE_PLLSTAT 0x00000038 +#define RESET_TRICORE_PLLCON0 0x0001C600 +#define RESET_TRICORE_PLLCON1 0x0002020F +#define RESET_TRICORE_PLLCON2 0x00000000 +#define RESET_TRICORE_PLLERAYSTAT 0x00000038 +#define RESET_TRICORE_PLLERAYCON0 0x00012E00 +#define RESET_TRICORE_PLLERAYCON1 0x000F020F +#define RESET_TRICORE_CCUCON0 0x01120148 +#define RESET_TRICORE_CCUCON1 0x00002211 +#define RESET_TRICORE_CCUCON2 0x00000002 +#define RESET_TRICORE_CCUCON3 0x00000000 +#define RESET_TRICORE_CCUCON4 0x00000000 +#define RESET_TRICORE_CCUCON5 0x00000041 +#define RESET_TRICORE_FDR 0x00000000 +#define RESET_TRICORE_EXTCON 0x00000000 +#define RESET_TRICORE_WDTSCON0 0xFFFC000E +#define RESET_TRICORE_WDTSCON1 0x00000000 +#define RESET_TRICORE_WDTCPU0CON0 0xFFFC000E + +/* Clock frequencies */ +#define SCU_FBACKUP 100000000 +#define SCU_XTAL1 20000000 + +#define SCU_REG_SIZE 0x1000 +#define SCU_NUM_REGS (SCU_REG_SIZE / 4) + +struct TriCoreSCUState { + /* private */ + SysBusDevice parent_obj; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780220030639154100 Map IR, STM, ASCLIN and SCU into the tc27x SoC at their hardware addresses. ASCLIN0 gets serial_hd(0), peripheral IRQs are routed to the IR. Interrupt delivery to the CPU is not yet wired -- that needs do_interrupt and CPU-side GPIO inputs (follow-up series). Signed-off-by: Parthiban Nallathambi --- hw/tricore/Kconfig | 15 ++++++++++ hw/tricore/tc27x_soc.c | 62 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/tricore/tc27x_soc.h | 13 +++++++++ 3 files changed, 90 insertions(+) diff --git a/hw/tricore/Kconfig b/hw/tricore/Kconfig index 6c04f64949..fd589f7b78 100644 --- a/hw/tricore/Kconfig +++ b/hw/tricore/Kconfig @@ -8,6 +8,21 @@ config TRIBOARD default y depends on TRICORE select TC27X_SOC + select TC39X_SOC =20 config TC27X_SOC bool + select TRICORE_ASCLIN + select TRICORE_IRBUS + select TRICORE_SCU + select TRICORE_STM + +config TC39X_SOC + bool + select TRICORE_ASCLIN + select TRICORE_IRBUS + select TRICORE_SCU + select TRICORE_STM + +config TRICORE_SCU + bool diff --git a/hw/tricore/tc27x_soc.c b/hw/tricore/tc27x_soc.c index 5b1b07cee1..2995ef8631 100644 --- a/hw/tricore/tc27x_soc.c +++ b/hw/tricore/tc27x_soc.c @@ -20,10 +20,13 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "hw/core/clock.h" +#include "hw/core/qdev-clock.h" #include "hw/core/sysbus.h" #include "hw/core/loader.h" #include "qemu/units.h" #include "hw/misc/unimp.h" +#include "system/system.h" =20 #include "hw/tricore/tc27x_soc.h" #include "hw/tricore/triboard.h" @@ -61,6 +64,11 @@ const MemmapEntry tc27x_soc_memmap[] =3D { [TC27XD_EMEM_U] =3D { 0xBF000000, 0x0 }, [TC27XD_PSPRX] =3D { 0xC0000000, 0x0 }, [TC27XD_DSPRX] =3D { 0xD0000000, 0x0 }, + [TC27XD_IR_INT] =3D { 0xF0037000, 0x0 }, + [TC27XD_IR_SRC] =3D { 0xF0038000, 0x0 }, + [TC27XD_STM0] =3D { 0xF0001000, 0x0 }, + [TC27XD_ASCLIN0] =3D { 0xF0000600, 0x0 }, + [TC27XD_SCU] =3D { 0xF0036000, 0x0 }, }; =20 /* @@ -179,9 +187,17 @@ static void tc27x_soc_init_memory_mapping(DeviceState = *dev_soc) sc->memmap[TC27XD_EMEM_U].base); } =20 +/* TC27x interrupt source indices (SRC register numbers) */ +#define TC27X_SRC_STM0_SR0 0xC0 +#define TC27X_SRC_ASCLIN0_TX 0x14 +#define TC27X_SRC_ASCLIN0_RX 0x15 +#define TC27X_SRC_ASCLIN0_ERR 0x16 + static void tc27x_soc_realize(DeviceState *dev_soc, Error **errp) { TC27XSoCState *s =3D TC27X_SOC(dev_soc); + TC27XSoCClass *sc =3D TC27X_SOC_GET_CLASS(s); + Clock *fstm; Error *err =3D NULL; =20 qdev_realize(DEVICE(&s->cpu), NULL, &err); @@ -191,6 +207,48 @@ static void tc27x_soc_realize(DeviceState *dev_soc, Er= ror **errp) } =20 tc27x_soc_init_memory_mapping(dev_soc); + + /* STM clock: 50 MHz (fSTM derived from fSPB) */ + fstm =3D clock_new(OBJECT(dev_soc), "fstm"); + clock_set_hz(fstm, 50000000); + qdev_connect_clock_in(DEVICE(&s->stm), "fstm", fstm); + + /* Connect ASCLIN to first serial device */ + qdev_prop_set_chr(DEVICE(&s->asclin), "chardev", serial_hd(0)); + + /* Realize peripherals */ + sysbus_realize(SYS_BUS_DEVICE(&s->ir), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->stm), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->asclin), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->scu), &error_fatal); + + /* Map peripheral MMIO regions */ + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ir), 0, + sc->memmap[TC27XD_IR_INT].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ir), 1, + sc->memmap[TC27XD_IR_SRC].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->stm), 0, + sc->memmap[TC27XD_STM0].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->asclin), 0, + sc->memmap[TC27XD_ASCLIN0].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[TC27XD_SCU].base); + + /* Connect ASCLIN IRQs to interrupt router */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->asclin), 0, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC27X_SRC_ASCLIN0_RX)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->asclin), 1, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC27X_SRC_ASCLIN0_TX)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->asclin), 2, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC27X_SRC_ASCLIN0_ERR)); + + /* Connect STM compare match IRQ to interrupt router */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->stm), 0, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC27X_SRC_STM0_SR0)); } =20 static void tc27x_soc_init(Object *obj) @@ -199,6 +257,10 @@ static void tc27x_soc_init(Object *obj) TC27XSoCClass *sc =3D TC27X_SOC_GET_CLASS(s); =20 object_initialize_child(obj, "tc27x", &s->cpu, sc->cpu_type); + object_initialize_child(obj, "ir", &s->ir, TYPE_TRICORE_IR); + object_initialize_child(obj, "stm", &s->stm, TYPE_TRICORE_STM); + object_initialize_child(obj, "asclin", &s->asclin, TYPE_TRICORE_ASCLIN= ); + object_initialize_child(obj, "scu", &s->scu, TYPE_TRICORE_SCU); } =20 static void tc27x_soc_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/tricore/tc27x_soc.h b/include/hw/tricore/tc27x_soc.h index 2d2bdca3fd..4e24789d4d 100644 --- a/include/hw/tricore/tc27x_soc.h +++ b/include/hw/tricore/tc27x_soc.h @@ -22,6 +22,10 @@ #define TC27X_SOC_H =20 #include "hw/core/sysbus.h" +#include "hw/char/tricore_asclin.h" +#include "hw/intc/tricore_ir.h" +#include "hw/timer/tricore_stm.h" +#include "hw/tricore/tricore_scu.h" #include "target/tricore/cpu.h" #include "qom/object.h" =20 @@ -65,6 +69,10 @@ typedef struct TC27XSoCState { =20 /*< public >*/ TriCoreCPU cpu; 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Add maintainer and register the new peripheral files that live outside hw/tricore/. Signed-off-by: Parthiban Nallathambi --- MAINTAINERS | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 7752917d8c..489be83fb2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -454,10 +454,17 @@ F: include/hw/xtensa/xtensa-isa.h F: configs/devices/xtensa*/default.mak =20 TriCore TCG CPUs -S: Orphan +M: Parthiban Nallathambi +S: Maintained F: target/tricore/ F: hw/tricore/ F: include/hw/tricore/ +F: hw/intc/tricore_ir.c +F: include/hw/intc/tricore_ir.h +F: hw/char/tricore_asclin.c +F: include/hw/char/tricore_asclin.h +F: hw/timer/tricore_stm.c +F: include/hw/timer/tricore_stm.h F: tests/docker/dockerfiles/debian-tricore-cross.docker F: tests/tcg/tricore/ =20 --=20 2.47.3 From nobody Mon Jun 8 08:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=linumiz.com) ARC-Seal: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=parthiban@linumiz.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1780220023546158500 TC39x SoC with the TC397B memory map: 6x 240K DSPR, 6x 64K PSPR, 6 flash banks, DLMU, LMU, 4M EMEM. Only CPU0 runs. Same peripheral wiring pattern as tc27x. Originally-by: Andreas Konopik Originally-by: David Brenken Signed-off-by: Parthiban Nallathambi --- hw/tricore/tc39xb_soc.c | 366 ++++++++++++++++++++++++++++++++++++= ++++ hw/tricore/triboard.c | 32 +++- include/hw/tricore/tc39xb_soc.h | 115 +++++++++++++ include/hw/tricore/triboard.h | 2 + 4 files changed, 514 insertions(+), 1 deletion(-) diff --git a/hw/tricore/tc39xb_soc.c b/hw/tricore/tc39xb_soc.c new file mode 100644 index 0000000000..f1d696efff --- /dev/null +++ b/hw/tricore/tc39xb_soc.c @@ -0,0 +1,366 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Infineon TC39x SoC System emulation. + * + * Copyright (c) 2020 Andreas Konopik + * Copyright (c) 2020 David Brenken + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/core/clock.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/sysbus.h" +#include "hw/core/loader.h" +#include "qemu/units.h" +#include "hw/misc/unimp.h" +#include "system/system.h" + +#include "hw/tricore/tc39xb_soc.h" +#include "hw/tricore/tc27x_soc.h" + +const MemmapEntry tc39xb_soc_memmap[] =3D { + [TC39XB_DSPR5] =3D { 0x10000000, 240 * KiB }, + [TC39XB_DCACHE5] =3D { 0x10018000, 16 * KiB }, + [TC39XB_DTAG5] =3D { 0x100C0000, 6 * KiB }, + [TC39XB_PSPR5] =3D { 0x10100000, 64 * KiB }, + [TC39XB_PCACHE5] =3D { 0x10108000, 32 * KiB }, + [TC39XB_PTAG5] =3D { 0x101C0000, 12 * KiB }, + [TC39XB_DSPR4] =3D { 0x30000000, 240 * KiB }, + [TC39XB_DCACHE4] =3D { 0x30018000, 16 * KiB }, + [TC39XB_DTAG4] =3D { 0x300C0000, 6 * KiB }, + [TC39XB_PSPR4] =3D { 0x30100000, 64 * KiB }, + [TC39XB_PCACHE4] =3D { 0x30108000, 32 * KiB }, + [TC39XB_PTAG4] =3D { 0x301C0000, 12 * KiB }, + [TC39XB_DSPR3] =3D { 0x40000000, 240 * KiB }, + [TC39XB_DCACHE3] =3D { 0x40018000, 16 * KiB }, + [TC39XB_DTAG3] =3D { 0x400C0000, 6 * KiB }, + [TC39XB_PSPR3] =3D { 0x40100000, 64 * KiB }, + [TC39XB_PCACHE3] =3D { 0x40108000, 32 * KiB }, + [TC39XB_PTAG3] =3D { 0x401C0000, 12 * KiB }, + [TC39XB_DSPR2] =3D { 0x50000000, 240 * KiB }, + [TC39XB_DCACHE2] =3D { 0x5001E000, 16 * KiB }, + [TC39XB_DTAG2] =3D { 0x500C0000, 6 * KiB }, + [TC39XB_PSPR2] =3D { 0x50100000, 64 * KiB }, + [TC39XB_PCACHE2] =3D { 0x50108000, 32 * KiB }, + [TC39XB_PTAG2] =3D { 0x501C0000, 12 * KiB }, + [TC39XB_DSPR1] =3D { 0x60000000, 240 * KiB }, + [TC39XB_DCACHE1] =3D { 0x6001E000, 16 * KiB }, + [TC39XB_DTAG1] =3D { 0x600C0000, 6 * KiB }, + [TC39XB_PSPR1] =3D { 0x60100000, 64 * KiB }, + [TC39XB_PCACHE1] =3D { 0x60108000, 32 * KiB }, + [TC39XB_PTAG1] =3D { 0x601C0000, 12 * KiB }, + [TC39XB_DSPR0] =3D { 0x70000000, 240 * KiB }, + [TC39XB_DCACHE0] =3D { 0x7001E000, 16 * KiB }, + [TC39XB_DTAG0] =3D { 0x700C0000, 6 * KiB }, + [TC39XB_PSPR0] =3D { 0x70100000, 64 * KiB }, + [TC39XB_PCACHE0] =3D { 0x70108000, 32 * KiB }, + [TC39XB_PTAG0] =3D { 0x701C0000, 12 * KiB }, + [TC39XB_PFLASH0_C] =3D { 0x80000000, 3 * MiB }, + [TC39XB_PFLASH1_C] =3D { 0x80300000, 3 * MiB }, + [TC39XB_PFLASH2_C] =3D { 0x80600000, 3 * MiB }, + [TC39XB_PFLASH3_C] =3D { 0x80900000, 3 * MiB }, + [TC39XB_PFLASH4_C] =3D { 0x80C00000, 3 * MiB }, + [TC39XB_PFLASH5_C] =3D { 0x80F00000, 1 * MiB }, + [TC39XB_OLDA_C] =3D { 0x8FE00000, 512 * KiB }, + [TC39XB_BROM_C] =3D { 0x8FFF0000, 64 * KiB }, + [TC39XB_DLMU0_C] =3D { 0x90000000, 64 * KiB }, + [TC39XB_DLMU1_C] =3D { 0x90010000, 64 * KiB }, + [TC39XB_DLMU2_C] =3D { 0x90020000, 64 * KiB }, + [TC39XB_DLMU3_C] =3D { 0x90030000, 64 * KiB }, + [TC39XB_LMU0_C] =3D { 0x90040000, 256 * KiB }, + [TC39XB_LMU1_C] =3D { 0x90080000, 256 * KiB }, + [TC39XB_LMU2_C] =3D { 0x900C0000, 256 * KiB }, + [TC39XB_DLMU4_C] =3D { 0x90100000, 64 * KiB }, + [TC39XB_DLMU5_C] =3D { 0x90110000, 64 * KiB }, + [TC39XB_EMEM] =3D { 0x99000000, 4 * MiB }, + [TC39XB_PFLASH0_U] =3D { 0xA0000000, 0x0 }, + [TC39XB_PFLASH1_U] =3D { 0xA0300000, 0x0 }, + [TC39XB_PFLASH2_U] =3D { 0xA0600000, 0x0 }, + [TC39XB_PFLASH3_U] =3D { 0xA0900000, 0x0 }, + [TC39XB_PFLASH4_U] =3D { 0xA0C00000, 0x0 }, + [TC39XB_PFLASH5_U] =3D { 0xA0F00000, 0x0 }, + [TC39XB_DFLASH0] =3D { 0xAF000000, 1 * MiB }, + [TC39XB_DFLASH1] =3D { 0xAFC00000, 128 * KiB }, + [TC39XB_OLDA_U] =3D { 0xAFE00000, 0x0 }, + [TC39XB_BROM_U] =3D { 0xAFFF0000, 0x0 }, + [TC39XB_DLMU0_U] =3D { 0xB0000000, 0x0 }, + [TC39XB_DLMU1_U] =3D { 0xB0010000, 0x0 }, + [TC39XB_DLMU2_U] =3D { 0xB0020000, 0x0 }, + [TC39XB_DLMU3_U] =3D { 0xB0030000, 0x0 }, + [TC39XB_LMU0_U] =3D { 0xB0040000, 0x0 }, + [TC39XB_LMU1_U] =3D { 0xB0080000, 0x0 }, + [TC39XB_LMU2_U] =3D { 0xB00C0000, 0x0 }, + [TC39XB_DLMU4_U] =3D { 0xB0100000, 0x0 }, + [TC39XB_DLMU5_U] =3D { 0xB0110000, 0x0 }, + [TC39XB_PSPRX] =3D { 0xC0000000, 0x0 }, + [TC39XB_DSPRX] =3D { 0xD0000000, 0x0 }, + [TC39XB_IR_INT] =3D { 0xF0037000, 0x0 }, + [TC39XB_IR_SRC] =3D { 0xF0038000, 0x0 }, + [TC39XB_STM0] =3D { 0xF0001000, 0x0 }, + [TC39XB_ASCLIN0] =3D { 0xF0000600, 0x0 }, + [TC39XB_SCU] =3D { 0xF0036000, 0x0 }, +}; + +static void make_rom(MemoryRegion *mr, const char *name, + hwaddr base, hwaddr size) +{ + memory_region_init_rom(mr, NULL, name, size, &error_fatal); + memory_region_add_subregion(get_system_memory(), base, mr); +} + +static void make_ram(MemoryRegion *mr, const char *name, + hwaddr base, hwaddr size) +{ + memory_region_init_ram(mr, NULL, name, size, &error_fatal); + memory_region_add_subregion(get_system_memory(), base, mr); +} + +static void make_alias(MemoryRegion *mr, const char *name, + MemoryRegion *orig, hwaddr base) +{ + memory_region_init_alias(mr, NULL, name, orig, 0, + memory_region_size(orig)); + memory_region_add_subregion(get_system_memory(), base, mr); +} + +static void tc39xb_soc_init_memory_mapping(DeviceState *dev_soc) +{ + TC39XBSoCState *s =3D TC39XB_SOC(dev_soc); + TC39XBSoCClass *sc =3D TC39XB_SOC_GET_CLASS(s); + const MemmapEntry *map =3D sc->memmap; + TC39XBSoCCPUMemState *c0 =3D &s->cpu0mem; + TC39XBSoCCPUMemState *c1 =3D &s->cpu1mem; + TC39XBSoCCPUMemState *c2 =3D &s->cpu2mem; + TC39XBSoCCPUMemState *c3 =3D &s->cpu3mem; + TC39XBSoCCPUMemState *c4 =3D &s->cpu4mem; + TC39XBSoCCPUMemState *c5 =3D &s->cpu5mem; + TC39XBSoCFlashMemState *f =3D &s->flashmem; + + /* CPU scratch-pad memories */ + make_ram(&c0->dspr, "CPU0.DSPR", + map[TC39XB_DSPR0].base, map[TC39XB_DSPR0].size); + make_ram(&c0->pspr, "CPU0.PSPR", + map[TC39XB_PSPR0].base, map[TC39XB_PSPR0].size); + make_ram(&c1->dspr, "CPU1.DSPR", + map[TC39XB_DSPR1].base, map[TC39XB_DSPR1].size); + make_ram(&c1->pspr, "CPU1.PSPR", + map[TC39XB_PSPR1].base, map[TC39XB_PSPR1].size); + make_ram(&c2->dspr, "CPU2.DSPR", + map[TC39XB_DSPR2].base, map[TC39XB_DSPR2].size); + make_ram(&c2->pspr, "CPU2.PSPR", + map[TC39XB_PSPR2].base, map[TC39XB_PSPR2].size); + make_ram(&c3->dspr, "CPU3.DSPR", + map[TC39XB_DSPR3].base, map[TC39XB_DSPR3].size); + make_ram(&c3->pspr, "CPU3.PSPR", + map[TC39XB_PSPR3].base, map[TC39XB_PSPR3].size); + make_ram(&c4->dspr, "CPU4.DSPR", + map[TC39XB_DSPR4].base, map[TC39XB_DSPR4].size); + make_ram(&c4->pspr, "CPU4.PSPR", + map[TC39XB_PSPR4].base, map[TC39XB_PSPR4].size); + make_ram(&c5->dspr, "CPU5.DSPR", + map[TC39XB_DSPR5].base, map[TC39XB_DSPR5].size); + make_ram(&c5->pspr, "CPU5.PSPR", + map[TC39XB_PSPR5].base, map[TC39XB_PSPR5].size); + + /* + * TriCore QEMU executes CPU0 only, thus it is sufficient to map + * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0. + */ + make_alias(&s->psprX, "LOCAL.PSPR", + &c0->pspr, map[TC39XB_PSPRX].base); + make_alias(&s->dsprX, "LOCAL.DSPR", + &c0->dspr, map[TC39XB_DSPRX].base); + + /* Program flash (6 banks) */ + make_ram(&c0->pflash_c, "PF0", + map[TC39XB_PFLASH0_C].base, map[TC39XB_PFLASH0_C].size); + make_ram(&c1->pflash_c, "PF1", + map[TC39XB_PFLASH1_C].base, map[TC39XB_PFLASH1_C].size); + make_ram(&c2->pflash_c, "PF2", + map[TC39XB_PFLASH2_C].base, map[TC39XB_PFLASH2_C].size); + make_ram(&c3->pflash_c, "PF3", + map[TC39XB_PFLASH3_C].base, map[TC39XB_PFLASH3_C].size); + make_ram(&c4->pflash_c, "PF4", + map[TC39XB_PFLASH4_C].base, map[TC39XB_PFLASH4_C].size); + make_ram(&c5->pflash_c, "PF5", + map[TC39XB_PFLASH5_C].base, map[TC39XB_PFLASH5_C].size); + + /* DLMU (per-CPU local memory) */ + make_ram(&c0->dlmu_c, "DLMU0", + map[TC39XB_DLMU0_C].base, map[TC39XB_DLMU0_C].size); + make_ram(&c1->dlmu_c, "DLMU1", + map[TC39XB_DLMU1_C].base, map[TC39XB_DLMU1_C].size); + make_ram(&c2->dlmu_c, "DLMU2", + map[TC39XB_DLMU2_C].base, map[TC39XB_DLMU2_C].size); + make_ram(&c3->dlmu_c, "DLMU3", + map[TC39XB_DLMU3_C].base, map[TC39XB_DLMU3_C].size); + make_ram(&c4->dlmu_c, "DLMU4", + map[TC39XB_DLMU4_C].base, map[TC39XB_DLMU4_C].size); + make_ram(&c5->dlmu_c, "DLMU5", + map[TC39XB_DLMU5_C].base, map[TC39XB_DLMU5_C].size); + + /* Shared memories */ + make_ram(&f->dflash0, "DF0", + map[TC39XB_DFLASH0].base, map[TC39XB_DFLASH0].size); + make_ram(&f->dflash1, "DF1", + map[TC39XB_DFLASH1].base, map[TC39XB_DFLASH1].size); + make_ram(&f->olda_c, "OLDA", + map[TC39XB_OLDA_C].base, map[TC39XB_OLDA_C].size); + make_rom(&f->brom_c, "BROM", + map[TC39XB_BROM_C].base, map[TC39XB_BROM_C].size); + make_ram(&f->lmu0_c, "LMU0", + map[TC39XB_LMU0_C].base, map[TC39XB_LMU0_C].size); + make_ram(&f->lmu1_c, "LMU1", + map[TC39XB_LMU1_C].base, map[TC39XB_LMU1_C].size); + make_ram(&f->lmu2_c, "LMU2", + map[TC39XB_LMU2_C].base, map[TC39XB_LMU2_C].size); + make_ram(&f->emem, "EMEM", + map[TC39XB_EMEM].base, map[TC39XB_EMEM].size); + + /* Uncached aliases for program flash */ + make_alias(&c0->pflash_u, "PF0.U", + &c0->pflash_c, map[TC39XB_PFLASH0_U].base); + make_alias(&c1->pflash_u, "PF1.U", + &c1->pflash_c, map[TC39XB_PFLASH1_U].base); + make_alias(&c2->pflash_u, "PF2.U", + &c2->pflash_c, map[TC39XB_PFLASH2_U].base); + make_alias(&c3->pflash_u, "PF3.U", + &c3->pflash_c, map[TC39XB_PFLASH3_U].base); + make_alias(&c4->pflash_u, "PF4.U", + &c4->pflash_c, map[TC39XB_PFLASH4_U].base); + make_alias(&c5->pflash_u, "PF5.U", + &c5->pflash_c, map[TC39XB_PFLASH5_U].base); + + /* Uncached aliases for DLMU */ + make_alias(&c0->dlmu_u, "DLMU0.U", + &c0->dlmu_c, map[TC39XB_DLMU0_U].base); + make_alias(&c1->dlmu_u, "DLMU1.U", + &c1->dlmu_c, map[TC39XB_DLMU1_U].base); + make_alias(&c2->dlmu_u, "DLMU2.U", + &c2->dlmu_c, map[TC39XB_DLMU2_U].base); + make_alias(&c3->dlmu_u, "DLMU3.U", + &c3->dlmu_c, map[TC39XB_DLMU3_U].base); + make_alias(&c4->dlmu_u, "DLMU4.U", + &c4->dlmu_c, map[TC39XB_DLMU4_U].base); + make_alias(&c5->dlmu_u, "DLMU5.U", + &c5->dlmu_c, map[TC39XB_DLMU5_U].base); + + /* Uncached aliases for shared memories */ + make_alias(&f->olda_u, "OLDA.U", + &f->olda_c, map[TC39XB_OLDA_U].base); + make_alias(&f->brom_u, "BROM.U", + &f->brom_c, map[TC39XB_BROM_U].base); + make_alias(&f->lmu0_u, "LMU0.U", + &f->lmu0_c, map[TC39XB_LMU0_U].base); + make_alias(&f->lmu1_u, "LMU1.U", + &f->lmu1_c, map[TC39XB_LMU1_U].base); + make_alias(&f->lmu2_u, "LMU2.U", + &f->lmu2_c, map[TC39XB_LMU2_U].base); +} + +/* TC39x interrupt source indices */ +#define TC39X_SRC_STM0_SR0 0xC0 +#define TC39X_SRC_ASCLIN0_TX 0x14 +#define TC39X_SRC_ASCLIN0_RX 0x15 +#define TC39X_SRC_ASCLIN0_ERR 0x16 + +static void tc39xb_soc_realize(DeviceState *dev_soc, Error **errp) +{ + TC39XBSoCState *s =3D TC39XB_SOC(dev_soc); + TC39XBSoCClass *sc =3D TC39XB_SOC_GET_CLASS(s); + Clock *fstm; + Error *err =3D NULL; + + qdev_realize(DEVICE(&s->cpu), NULL, &err); + if (err) { + error_propagate(errp, err); + return; + } + + tc39xb_soc_init_memory_mapping(dev_soc); + + /* STM clock: 50 MHz */ + fstm =3D clock_new(OBJECT(dev_soc), "fstm"); + clock_set_hz(fstm, 50000000); + qdev_connect_clock_in(DEVICE(&s->stm), "fstm", fstm); + + qdev_prop_set_chr(DEVICE(&s->asclin), "chardev", serial_hd(0)); + + sysbus_realize(SYS_BUS_DEVICE(&s->ir), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->stm), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->asclin), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->scu), &error_fatal); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ir), 0, + sc->memmap[TC39XB_IR_INT].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ir), 1, + sc->memmap[TC39XB_IR_SRC].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->stm), 0, + sc->memmap[TC39XB_STM0].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->asclin), 0, + sc->memmap[TC39XB_ASCLIN0].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, + sc->memmap[TC39XB_SCU].base); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->asclin), 0, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC39X_SRC_ASCLIN0_RX)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->asclin), 1, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC39X_SRC_ASCLIN0_TX)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->asclin), 2, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC39X_SRC_ASCLIN0_ERR)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->stm), 0, + qdev_get_gpio_in_named(DEVICE(&s->ir), "irq", + TC39X_SRC_STM0_SR0)); +} + +static void tc39xb_soc_init(Object *obj) +{ + TC39XBSoCState *s =3D TC39XB_SOC(obj); + TC39XBSoCClass *sc =3D TC39XB_SOC_GET_CLASS(s); + + object_initialize_child(obj, "tc39x", &s->cpu, sc->cpu_type); + object_initialize_child(obj, "ir", &s->ir, TYPE_TRICORE_IR); + object_initialize_child(obj, "stm", &s->stm, TYPE_TRICORE_STM); + object_initialize_child(obj, "asclin", &s->asclin, TYPE_TRICORE_ASCLIN= ); + object_initialize_child(obj, "scu", &s->scu, TYPE_TRICORE_SCU); +} + +static void tc39xb_soc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D tc39xb_soc_realize; +} + +static void tc397b_soc_class_init(ObjectClass *oc, const void *data) +{ + TC39XBSoCClass *sc =3D TC39XB_SOC_CLASS(oc); + + sc->name =3D "tc397b-soc"; + sc->cpu_type =3D TRICORE_CPU_TYPE_NAME("tc39x"); + sc->memmap =3D tc39xb_soc_memmap; + sc->num_cpus =3D 1; +} + +static const TypeInfo tc39xb_soc_types[] =3D { + { + .name =3D "tc397b-soc", + .parent =3D TYPE_TC39XB_SOC, + .class_init =3D tc397b_soc_class_init, + }, { + .name =3D TYPE_TC39XB_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TC39XBSoCState), + .instance_init =3D tc39xb_soc_init, + .class_size =3D sizeof(TC39XBSoCClass), + .class_init =3D tc39xb_soc_class_init, + .abstract =3D true, + }, +}; + +DEFINE_TYPES(tc39xb_soc_types) diff --git a/hw/tricore/triboard.c b/hw/tricore/triboard.c index 23f11cf0a1..c16a6bc8f7 100644 --- a/hw/tricore/triboard.c +++ b/hw/tricore/triboard.c @@ -64,6 +64,20 @@ static void triboard_machine_init(MachineState *machine) } } =20 +static void triboard_machine_tc397b_init(MachineState *machine) +{ + TriBoardMachineState *ms =3D TRIBOARD_MACHINE(machine); + TriBoardMachineClass *amc =3D TRIBOARD_MACHINE_GET_CLASS(machine); + + object_initialize_child(OBJECT(machine), "soc", &ms->tc39xb_soc, + amc->soc_name); + sysbus_realize(SYS_BUS_DEVICE(&ms->tc39xb_soc), &error_fatal); + + if (machine->kernel_filename) { + tricore_load_kernel(&ms->tc39xb_soc.cpu, machine->kernel_filename); + } +} + static void triboard_machine_tc277d_class_init(ObjectClass *oc, const void *data) { @@ -74,13 +88,29 @@ static void triboard_machine_tc277d_class_init(ObjectCl= ass *oc, mc->desc =3D "Infineon AURIX TriBoard TC277 (D-Step)"; mc->max_cpus =3D 1; amc->soc_name =3D "tc277d-soc"; -}; +} + +static void triboard_machine_tc397b_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + TriBoardMachineClass *amc =3D TRIBOARD_MACHINE_CLASS(oc); + + mc->init =3D triboard_machine_tc397b_init; + mc->desc =3D "Infineon AURIX TriBoard TC397 (B-Step)"; + mc->max_cpus =3D 1; + amc->soc_name =3D "tc397b-soc"; +} =20 static const TypeInfo triboard_machine_types[] =3D { { .name =3D MACHINE_TYPE_NAME("KIT_AURIX_TC277_TRB"), .parent =3D TYPE_TRIBOARD_MACHINE, .class_init =3D triboard_machine_tc277d_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("KIT_AURIX_TC397_TRB"), + .parent =3D TYPE_TRIBOARD_MACHINE, + .class_init =3D triboard_machine_tc397b_class_init, }, { .name =3D TYPE_TRIBOARD_MACHINE, .parent =3D TYPE_MACHINE, diff --git a/include/hw/tricore/tc39xb_soc.h b/include/hw/tricore/tc39xb_so= c.h new file mode 100644 index 0000000000..66af339db1 --- /dev/null +++ b/include/hw/tricore/tc39xb_soc.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Infineon TC39x SoC System emulation. + * + * Copyright (c) 2020 Andreas Konopik + * Copyright (c) 2020 David Brenken + */ + +#ifndef TC39XB_SOC_H +#define TC39XB_SOC_H + +#include "hw/core/sysbus.h" +#include "hw/char/tricore_asclin.h" +#include "hw/intc/tricore_ir.h" +#include "hw/timer/tricore_stm.h" +#include "hw/tricore/tricore_scu.h" +#include "target/tricore/cpu.h" +#include "qom/object.h" + +#define TYPE_TC39XB_SOC ("tc39xb-soc") +OBJECT_DECLARE_TYPE(TC39XBSoCState, TC39XBSoCClass, TC39XB_SOC) + +typedef struct TC39XBSoCCPUMemState { + MemoryRegion dspr; + MemoryRegion pspr; + MemoryRegion pflash_c; + MemoryRegion pflash_u; + MemoryRegion dlmu_c; + MemoryRegion dlmu_u; +} TC39XBSoCCPUMemState; + +typedef struct TC39XBSoCFlashMemState { + MemoryRegion dflash0; + MemoryRegion dflash1; + MemoryRegion olda_c; + MemoryRegion olda_u; + MemoryRegion brom_c; + MemoryRegion brom_u; + MemoryRegion lmu0_c; + MemoryRegion lmu0_u; + MemoryRegion lmu1_c; + MemoryRegion lmu1_u; + MemoryRegion lmu2_c; + MemoryRegion lmu2_u; + MemoryRegion emem; +} TC39XBSoCFlashMemState; + +typedef struct MemmapEntry MemmapEntry; + +typedef struct TC39XBSoCState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + TriCoreCPU cpu; + TriCoreIRState ir; + TriCoreSTMState stm; + TriCoreASCLINState asclin; + TriCoreSCUState scu; + + MemoryRegion dsprX; + MemoryRegion psprX; + + TC39XBSoCCPUMemState cpu0mem; + TC39XBSoCCPUMemState cpu1mem; + TC39XBSoCCPUMemState cpu2mem; + TC39XBSoCCPUMemState cpu3mem; + TC39XBSoCCPUMemState cpu4mem; + TC39XBSoCCPUMemState cpu5mem; + + TC39XBSoCFlashMemState flashmem; +} TC39XBSoCState; + +typedef struct TC39XBSoCClass { + DeviceClass parent_class; + + const char *name; + const char *cpu_type; + const MemmapEntry *memmap; + uint32_t num_cpus; +} TC39XBSoCClass; + +enum { + TC39XB_DSPR5, TC39XB_DCACHE5, TC39XB_DTAG5, + TC39XB_PSPR5, TC39XB_PCACHE5, TC39XB_PTAG5, + TC39XB_DSPR4, TC39XB_DCACHE4, TC39XB_DTAG4, + TC39XB_PSPR4, TC39XB_PCACHE4, TC39XB_PTAG4, + TC39XB_DSPR3, TC39XB_DCACHE3, TC39XB_DTAG3, + TC39XB_PSPR3, TC39XB_PCACHE3, TC39XB_PTAG3, + TC39XB_DSPR2, TC39XB_DCACHE2, TC39XB_DTAG2, + TC39XB_PSPR2, TC39XB_PCACHE2, TC39XB_PTAG2, + TC39XB_DSPR1, TC39XB_DCACHE1, TC39XB_DTAG1, + TC39XB_PSPR1, TC39XB_PCACHE1, TC39XB_PTAG1, + TC39XB_DSPR0, TC39XB_DCACHE0, TC39XB_DTAG0, + TC39XB_PSPR0, TC39XB_PCACHE0, TC39XB_PTAG0, + TC39XB_PFLASH0_C, TC39XB_PFLASH1_C, TC39XB_PFLASH2_C, + TC39XB_PFLASH3_C, TC39XB_PFLASH4_C, TC39XB_PFLASH5_C, + TC39XB_OLDA_C, TC39XB_BROM_C, + TC39XB_DLMU0_C, TC39XB_DLMU1_C, TC39XB_DLMU2_C, + TC39XB_DLMU3_C, TC39XB_LMU0_C, TC39XB_LMU1_C, + TC39XB_LMU2_C, TC39XB_DLMU4_C, TC39XB_DLMU5_C, + TC39XB_EMEM, + TC39XB_PFLASH0_U, TC39XB_PFLASH1_U, TC39XB_PFLASH2_U, + TC39XB_PFLASH3_U, TC39XB_PFLASH4_U, TC39XB_PFLASH5_U, + TC39XB_DFLASH0, TC39XB_DFLASH1, + TC39XB_OLDA_U, TC39XB_BROM_U, + TC39XB_DLMU0_U, TC39XB_DLMU1_U, TC39XB_DLMU2_U, + TC39XB_DLMU3_U, TC39XB_LMU0_U, TC39XB_LMU1_U, + TC39XB_LMU2_U, TC39XB_DLMU4_U, TC39XB_DLMU5_U, + TC39XB_PSPRX, TC39XB_DSPRX, + TC39XB_IR_INT, TC39XB_IR_SRC, + TC39XB_STM0, TC39XB_ASCLIN0, TC39XB_SCU, +}; + +#endif diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h index c6be4dc3f3..bc84c26f32 100644 --- a/include/hw/tricore/triboard.h +++ b/include/hw/tricore/triboard.h @@ -25,6 +25,7 @@ #include "qom/object.h" =20 #include "hw/tricore/tc27x_soc.h" +#include "hw/tricore/tc39xb_soc.h" =20 #define TYPE_TRIBOARD_MACHINE MACHINE_TYPE_NAME("triboard") typedef struct TriBoardMachineState TriBoardMachineState; @@ -37,6 +38,7 @@ struct TriBoardMachineState { MachineState parent; =20 TC27XSoCState tc27x_soc; + TC39XBSoCState tc39xb_soc; }; =20 struct TriBoardMachineClass { --=20 2.47.3