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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092157468158500 Content-Type: text/plain; charset="utf-8" Some of the system registers are shared among all threads in the core. This object contains the representation and interface to the system registers. Reviewed-by: Sid Manning Acked-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon_globalreg.h | 55 ++++++ hw/hexagon/hexagon_globalreg.c | 243 +++++++++++++++++++++++++ 2 files changed, 298 insertions(+) create mode 100644 include/hw/hexagon/hexagon_globalreg.h create mode 100644 hw/hexagon/hexagon_globalreg.c diff --git a/include/hw/hexagon/hexagon_globalreg.h b/include/hw/hexagon/he= xagon_globalreg.h new file mode 100644 index 00000000000..950099808fd --- /dev/null +++ b/include/hw/hexagon/hexagon_globalreg.h @@ -0,0 +1,55 @@ +/* + * Hexagon Global Registers QOM Object + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_GLOBALREG_H +#define HEXAGON_GLOBALREG_H + +#include "hw/core/qdev.h" +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "target/hexagon/cpu.h" + +#define TYPE_HEXAGON_GLOBALREG "hexagon-globalreg" +OBJECT_DECLARE_SIMPLE_TYPE(HexagonGlobalRegState, HEXAGON_GLOBALREG) + +struct HexagonGlobalRegState { + SysBusDevice parent_obj; + + /* Array of system registers */ + uint32_t regs[NUM_SREGS]; + + /* Global performance cycle counter base */ + uint64_t g_pcycle_base; + + /* Properties for global register reset values */ + uint32_t boot_evb; /* Boot Exception Vector Base (HEX_SREG_E= VB) */ + uint64_t config_table_addr; /* Configuration table base */ + uint32_t dsp_rev; /* DSP revision register (HEX_SREG_REV) */ + + /* ISDB properties */ + bool isdben_etm_enable; /* ISDB ETM enable bit */ + bool isdben_dfd_enable; /* ISDB DFD enable bit */ + bool isdben_trusted; /* ISDB trusted mode bit */ + bool isdben_secure; /* ISDB secure mode bit */ +}; + +/* Public interface functions */ +uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg, + uint32_t htid); +void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg, + uint32_t value, uint32_t htid); +uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t= reg, + uint32_t value); +void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg, + uint32_t value); + +/* Global performance cycle counter access */ +uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s); +void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s, + uint64_t value); + +#endif /* HEXAGON_GLOBALREG_H */ diff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c new file mode 100644 index 00000000000..28cb5a4158d --- /dev/null +++ b/hw/hexagon/hexagon_globalreg.c @@ -0,0 +1,243 @@ +/* + * Hexagon Global Registers + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/hexagon_globalreg.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/sysbus.h" +#include "hw/core/resettable.h" +#include "migration/vmstate.h" +#include "qom/object.h" +#include "target/hexagon/cpu.h" +#include "target/hexagon/hex_regs.h" +#include "qemu/log.h" +#include "qapi/error.h" + +#define IMMUTABLE (~0) +#define INVALID_REG_VAL 0xdeadbeef + +/* Global system register mutability masks */ +static const uint32_t global_sreg_immut_masks[NUM_SREGS] =3D { + [HEX_SREG_EVB] =3D 0x000000ff, + [HEX_SREG_MODECTL] =3D IMMUTABLE, + [HEX_SREG_SYSCFG] =3D 0x80001c00, + [HEX_SREG_IPENDAD] =3D IMMUTABLE, + [HEX_SREG_VID] =3D 0xfc00fc00, + [HEX_SREG_VID1] =3D 0xfc00fc00, + [HEX_SREG_BESTWAIT] =3D 0xfffffe00, + [HEX_SREG_IAHL] =3D 0x00000000, + [HEX_SREG_SCHEDCFG] =3D 0xfffffee0, + [HEX_SREG_CFGBASE] =3D IMMUTABLE, + [HEX_SREG_DIAG] =3D 0x00000000, + [HEX_SREG_REV] =3D IMMUTABLE, + [HEX_SREG_ISDBST] =3D IMMUTABLE, + [HEX_SREG_ISDBCFG0] =3D 0xe0000000, + [HEX_SREG_BRKPTPC0] =3D 0x00000003, + [HEX_SREG_BRKPTCFG0] =3D 0xfc007000, + [HEX_SREG_BRKPTPC1] =3D 0x00000003, + [HEX_SREG_BRKPTCFG1] =3D 0xfc007000, + [HEX_SREG_ISDBMBXIN] =3D IMMUTABLE, + [HEX_SREG_ISDBMBXOUT] =3D 0x00000000, + [HEX_SREG_ISDBEN] =3D 0xfffffffe, + [HEX_SREG_TIMERLO] =3D IMMUTABLE, + [HEX_SREG_TIMERHI] =3D IMMUTABLE, +}; + +static void hexagon_globalreg_init(Object *obj) +{ + HexagonGlobalRegState *s =3D HEXAGON_GLOBALREG(obj); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static inline uint32_t apply_write_mask(uint32_t new_val, uint32_t cur_val, + uint32_t reg_mask) +{ + if (reg_mask) { + return (new_val & ~reg_mask) | (cur_val & reg_mask); + } + return new_val; +} + +uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg, + uint32_t htid) +{ + uint32_t value; + + if (!s) { + return 0; + } + g_assert(reg < NUM_SREGS); + g_assert(reg >=3D HEX_SREG_GLB_START); + + value =3D s->regs[reg]; + + return value; +} + +void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg, + uint32_t value, uint32_t htid) +{ + if (!s) { + return; + } + g_assert(reg < NUM_SREGS); + g_assert(reg >=3D HEX_SREG_GLB_START); + s->regs[reg] =3D value; +} + +uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t= reg, + uint32_t value) +{ + uint32_t reg_mask; + + if (!s) { + return value; + } + g_assert(reg < NUM_SREGS); + g_assert(reg >=3D HEX_SREG_GLB_START); + reg_mask =3D global_sreg_immut_masks[reg]; + return reg_mask =3D=3D IMMUTABLE ? + s->regs[reg] : + apply_write_mask(value, s->regs[reg], reg_mask); +} + +void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg, + uint32_t value) +{ + if (!s) { + return; + } + s->regs[reg] =3D hexagon_globalreg_masked_value(s, reg, value); +} + +uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s) +{ + g_assert(s); + return s->g_pcycle_base; +} + +void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s, + uint64_t value) +{ + g_assert(s); + s->g_pcycle_base =3D value; +} + +static void do_hexagon_globalreg_reset(HexagonGlobalRegState *s) +{ + uint32_t isdben_val =3D 0; + + g_assert(s); + memset(s->regs, 0, sizeof(s->regs)); + + s->g_pcycle_base =3D 0; + + s->regs[HEX_SREG_EVB] =3D s->boot_evb; + s->regs[HEX_SREG_CFGBASE] =3D HEXAGON_CFG_ADDR_BASE(s->config_table_ad= dr); + s->regs[HEX_SREG_REV] =3D s->dsp_rev; + + if (s->isdben_etm_enable) { + isdben_val |=3D (1 << 0); /* ETM enable bit */ + } + if (s->isdben_dfd_enable) { + isdben_val |=3D (1 << 1); /* DFD enable bit */ + } + if (s->isdben_trusted) { + isdben_val |=3D (1 << 2); /* Trusted bit */ + } + if (s->isdben_secure) { + isdben_val |=3D (1 << 3); /* Secure bit */ + } + s->regs[HEX_SREG_ISDBEN] =3D isdben_val; + s->regs[HEX_SREG_MODECTL] =3D 0x1; + + /* + * These register indices are placeholders in these arrays + * and their actual values are synthesized from state elsewhere. + * We can initialize these with invalid values so that if we + * mistakenly generate reads, they will look obviously wrong. + */ + s->regs[HEX_SREG_PCYCLELO] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PCYCLEHI] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_TIMERLO] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_TIMERHI] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT0] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT1] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT2] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT3] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT4] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT5] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT6] =3D INVALID_REG_VAL; + s->regs[HEX_SREG_PMUCNT7] =3D INVALID_REG_VAL; +} + +static void hexagon_globalreg_reset_hold(Object *obj, ResetType type) +{ + HexagonGlobalRegState *s =3D HEXAGON_GLOBALREG(obj); + do_hexagon_globalreg_reset(s); +} + +static const VMStateDescription vmstate_hexagon_globalreg =3D { + .name =3D "hexagon_globalreg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT32_ARRAY(regs, HexagonGlobalRegState, NUM_SREGS), + VMSTATE_UINT64(g_pcycle_base, HexagonGlobalRegState), + VMSTATE_UINT32(boot_evb, HexagonGlobalRegState), + VMSTATE_UINT64(config_table_addr, HexagonGlobalRegState), + VMSTATE_UINT32(dsp_rev, HexagonGlobalRegState), + VMSTATE_BOOL(isdben_etm_enable, HexagonGlobalRegState), + VMSTATE_BOOL(isdben_dfd_enable, HexagonGlobalRegState), + VMSTATE_BOOL(isdben_trusted, HexagonGlobalRegState), + VMSTATE_BOOL(isdben_secure, HexagonGlobalRegState), + VMSTATE_END_OF_LIST() + } +}; + +static const Property hexagon_globalreg_properties[] =3D { + DEFINE_PROP_UINT32("boot-evb", HexagonGlobalRegState, boot_evb, 0x0), + DEFINE_PROP_UINT64("config-table-addr", HexagonGlobalRegState, + config_table_addr, 0xffffffffULL), + DEFINE_PROP_UINT32("dsp-rev", HexagonGlobalRegState, dsp_rev, 0), + DEFINE_PROP_BOOL("isdben-etm-enable", HexagonGlobalRegState, + isdben_etm_enable, false), + DEFINE_PROP_BOOL("isdben-dfd-enable", HexagonGlobalRegState, + isdben_dfd_enable, false), + DEFINE_PROP_BOOL("isdben-trusted", HexagonGlobalRegState, + isdben_trusted, false), + DEFINE_PROP_BOOL("isdben-secure", HexagonGlobalRegState, + isdben_secure, false), +}; + +static void hexagon_globalreg_class_init(ObjectClass *klass, const void *d= ata) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D hexagon_globalreg_reset_hold; + dc->vmsd =3D &vmstate_hexagon_globalreg; + dc->user_creatable =3D false; + device_class_set_props(dc, hexagon_globalreg_properties); +} + +static const TypeInfo hexagon_globalreg_info =3D { + .name =3D TYPE_HEXAGON_GLOBALREG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexagonGlobalRegState), + .instance_init =3D hexagon_globalreg_init, + .class_init =3D hexagon_globalreg_class_init, +}; + +static void hexagon_globalreg_register_types(void) +{ + type_register_static(&hexagon_globalreg_info); +} + +type_init(hexagon_globalreg_register_types) --=20 2.34.1 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1780092147; cv=none; d=zohomail.com; s=zohoarc; b=fP3ZN6HSJLURQII1w7VoX1oDvro7LcqNo9rsbzixuOIg/35sDLSK780ip7M2LRxT7idz0qLMrfdKB//rXZk4mn4D+S9t7I42JkujoTWwBPuXEBnYUitTlzf3d3hpG/mTGhjOrsb9PRuMRh/FdJAoWHcF6YThAhftMDXAwz1DSUU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092149325158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Brian Cain --- meson.build | 1 + hw/hexagon/trace.h | 2 + hw/hexagon/hexagon_globalreg.c | 73 ++++++++++++++++++++++++++++++++++ hw/hexagon/trace-events | 3 ++ 4 files changed, 79 insertions(+) create mode 100644 hw/hexagon/trace.h create mode 100644 hw/hexagon/trace-events diff --git a/meson.build b/meson.build index eb074918193..84b39682c7a 100644 --- a/meson.build +++ b/meson.build @@ -3599,6 +3599,7 @@ if have_system 'hw/display', 'hw/dma', 'hw/fsi', + 'hw/hexagon', 'hw/hyperv', 'hw/i2c', 'hw/i3c', diff --git a/hw/hexagon/trace.h b/hw/hexagon/trace.h new file mode 100644 index 00000000000..9e0b39f3c66 --- /dev/null +++ b/hw/hexagon/trace.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include "trace/trace-hw_hexagon.h" diff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c index 28cb5a4158d..b5e5913507e 100644 --- a/hw/hexagon/hexagon_globalreg.c +++ b/hw/hexagon/hexagon_globalreg.c @@ -16,11 +16,82 @@ #include "target/hexagon/cpu.h" #include "target/hexagon/hex_regs.h" #include "qemu/log.h" +#include "trace.h" #include "qapi/error.h" =20 #define IMMUTABLE (~0) #define INVALID_REG_VAL 0xdeadbeef =20 +static const char *hex_sreg_names[] =3D { + [HEX_SREG_SGP0] =3D "sgp0", + [HEX_SREG_SGP1] =3D "sgp1", + [HEX_SREG_STID] =3D "stid", + [HEX_SREG_ELR] =3D "elr", + [HEX_SREG_BADVA0] =3D "badva0", + [HEX_SREG_BADVA1] =3D "badva1", + [HEX_SREG_SSR] =3D "ssr", + [HEX_SREG_CCR] =3D "ccr", + [HEX_SREG_HTID] =3D "htid", + [HEX_SREG_BADVA] =3D "badva", + [HEX_SREG_IMASK] =3D "imask", + [HEX_SREG_GEVB] =3D "gevb", + [HEX_SREG_EVB] =3D "evb", + [HEX_SREG_MODECTL] =3D "modectl", + [HEX_SREG_SYSCFG] =3D "syscfg", + [HEX_SREG_IPENDAD] =3D "ipendad", + [HEX_SREG_VID] =3D "vid", + [HEX_SREG_VID1] =3D "vid1", + [HEX_SREG_BESTWAIT] =3D "bestwait", + [HEX_SREG_IEL] =3D "iel", + [HEX_SREG_SCHEDCFG] =3D "schedcfg", + [HEX_SREG_IAHL] =3D "iahl", + [HEX_SREG_CFGBASE] =3D "cfgbase", + [HEX_SREG_DIAG] =3D "diag", + [HEX_SREG_REV] =3D "rev", + [HEX_SREG_PCYCLELO] =3D "pcyclelo", + [HEX_SREG_PCYCLEHI] =3D "pcyclehi", + [HEX_SREG_ISDBST] =3D "isdbst", + [HEX_SREG_ISDBCFG0] =3D "isdbcfg0", + [HEX_SREG_ISDBCFG1] =3D "isdbcfg1", + [HEX_SREG_LIVELOCK] =3D "livelock", + [HEX_SREG_BRKPTPC0] =3D "brkptpc0", + [HEX_SREG_BRKPTCFG0] =3D "brkptcfg0", + [HEX_SREG_BRKPTPC1] =3D "brkptpc1", + [HEX_SREG_BRKPTCFG1] =3D "brkptcfg1", + [HEX_SREG_ISDBMBXIN] =3D "isdbmbxin", + [HEX_SREG_ISDBMBXOUT] =3D "isdbmbxout", + [HEX_SREG_ISDBEN] =3D "isdben", + [HEX_SREG_ISDBGPR] =3D "isdbgpr", + [HEX_SREG_PMUCNT4] =3D "pmucnt4", + [HEX_SREG_PMUCNT5] =3D "pmucnt5", + [HEX_SREG_PMUCNT6] =3D "pmucnt6", + [HEX_SREG_PMUCNT7] =3D "pmucnt7", + [HEX_SREG_PMUCNT0] =3D "pmucnt0", + [HEX_SREG_PMUCNT1] =3D "pmucnt1", + [HEX_SREG_PMUCNT2] =3D "pmucnt2", + [HEX_SREG_PMUCNT3] =3D "pmucnt3", + [HEX_SREG_PMUEVTCFG] =3D "pmuevtcfg", + [HEX_SREG_PMUSTID0] =3D "pmustid0", + [HEX_SREG_PMUEVTCFG1] =3D "pmuevtcfg1", + [HEX_SREG_PMUSTID1] =3D "pmustid1", + [HEX_SREG_TIMERLO] =3D "timerlo", + [HEX_SREG_TIMERHI] =3D "timerhi", + [HEX_SREG_PMUCFG] =3D "pmucfg", + [HEX_SREG_S59] =3D "s59", + [HEX_SREG_S60] =3D "s60", + [HEX_SREG_S61] =3D "s61", + [HEX_SREG_S62] =3D "s62", + [HEX_SREG_S63] =3D "s63", +}; + +static const char *get_sreg_name(uint32_t reg) +{ + if (reg < ARRAY_SIZE(hex_sreg_names) && hex_sreg_names[reg]) { + return hex_sreg_names[reg]; + } + return "UNKNOWN"; +} + /* Global system register mutability masks */ static const uint32_t global_sreg_immut_masks[NUM_SREGS] =3D { [HEX_SREG_EVB] =3D 0x000000ff, @@ -77,6 +148,7 @@ uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s= , uint32_t reg, =20 value =3D s->regs[reg]; =20 + trace_hexagon_globalreg_read(htid, get_sreg_name(reg), value); return value; } =20 @@ -89,6 +161,7 @@ void hexagon_globalreg_write(HexagonGlobalRegState *s, u= int32_t reg, g_assert(reg < NUM_SREGS); g_assert(reg >=3D HEX_SREG_GLB_START); s->regs[reg] =3D value; + trace_hexagon_globalreg_write(htid, get_sreg_name(reg), value); } =20 uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t= reg, diff --git a/hw/hexagon/trace-events b/hw/hexagon/trace-events new file mode 100644 index 00000000000..5d623ed2516 --- /dev/null +++ b/hw/hexagon/trace-events @@ -0,0 +1,3 @@ +# Hexagon global register access +hexagon_globalreg_read(uint32_t htid, const char *reg_name, uint32_t value= ) "htid=3D%u reg=3D%s value=3D0x%x" +hexagon_globalreg_write(uint32_t htid, const char *reg_name, uint32_t valu= e) "htid=3D%u reg=3D%s value=3D0x%x" --=20 2.34.1 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092124144154100 Add the hexagon TLB QOM device model implementation. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- hw/hexagon/hexagon_tlb.c | 466 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 466 insertions(+) create mode 100644 hw/hexagon/hexagon_tlb.c diff --git a/hw/hexagon/hexagon_tlb.c b/hw/hexagon/hexagon_tlb.c new file mode 100644 index 00000000000..d218e97446c --- /dev/null +++ b/hw/hexagon/hexagon_tlb.c @@ -0,0 +1,466 @@ +/* + * Hexagon TLB QOM Device + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/hexagon/hexagon_tlb.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/resettable.h" +#include "migration/vmstate.h" +#include "monitor/monitor.h" +#include "qapi/error.h" +#include "exec/target_page.h" +#include "target/hexagon/cpu.h" +#include "target/hexagon/cpu_bits.h" + +/* PTE (TLB entry) field extraction */ +#define GET_PTE_PPD(entry) extract64((entry), 0, 24) +#define GET_PTE_C(entry) extract64((entry), 24, 4) +#define GET_PTE_U(entry) extract64((entry), 28, 1) +#define GET_PTE_R(entry) extract64((entry), 29, 1) +#define GET_PTE_W(entry) extract64((entry), 30, 1) +#define GET_PTE_X(entry) extract64((entry), 31, 1) +#define GET_PTE_VPN(entry) extract64((entry), 32, 20) +#define GET_PTE_ASID(entry) extract64((entry), 52, 7) +#define GET_PTE_ATR0(entry) extract64((entry), 59, 1) +#define GET_PTE_ATR1(entry) extract64((entry), 60, 1) +#define GET_PTE_PA35(entry) extract64((entry), 61, 1) +#define GET_PTE_G(entry) extract64((entry), 62, 1) +#define GET_PTE_V(entry) extract64((entry), 63, 1) + +/* PPD (physical page descriptor) */ +static inline uint64_t GET_PPD(uint64_t entry) +{ + return GET_PTE_PPD(entry) | (GET_PTE_PA35(entry) << 24); +} + +#define NO_ASID (1 << 8) + +typedef enum { + PGSIZE_4K, + PGSIZE_16K, + PGSIZE_64K, + PGSIZE_256K, + PGSIZE_1M, + PGSIZE_4M, + PGSIZE_16M, + PGSIZE_64M, + PGSIZE_256M, + PGSIZE_1G, +} tlb_pgsize_t; + +#define NUM_PGSIZE_TYPES (PGSIZE_1G + 1) + +static const char *pgsize_str[NUM_PGSIZE_TYPES] =3D { + "4K", + "16K", + "64K", + "256K", + "1M", + "4M", + "16M", + "64M", + "256M", + "1G", +}; + +#define INVALID_MASK 0xffffffffLL + +static const uint64_t encmask_2_mask[] =3D { + 0x0fffLL, /* 4k, 0000 */ + 0x3fffLL, /* 16k, 0001 */ + 0xffffLL, /* 64k, 0010 */ + 0x3ffffLL, /* 256k, 0011 */ + 0xfffffLL, /* 1m, 0100 */ + 0x3fffffLL, /* 4m, 0101 */ + 0xffffffLL, /* 16m, 0110 */ + 0x3ffffffLL, /* 64m, 0111 */ + 0xfffffffLL, /* 256m, 1000 */ + 0x3fffffffLL, /* 1g, 1001 */ + INVALID_MASK, /* RSVD, 1010 */ +}; + +static inline tlb_pgsize_t hex_tlb_pgsize_type(uint64_t entry) +{ + if (entry =3D=3D 0) { + qemu_log_mask(CPU_LOG_MMU, "%s: Supplied TLB entry was 0!\n", + __func__); + return 0; + } + tlb_pgsize_t size =3D ctz64(entry); + g_assert(size < NUM_PGSIZE_TYPES); + return size; +} + +static inline uint64_t hex_tlb_page_size_bytes(uint64_t entry) +{ + return 1ull << (qemu_target_page_bits() + 2 * hex_tlb_pgsize_type(entr= y)); +} + +static inline uint64_t hex_tlb_phys_page_num(uint64_t entry) +{ + uint32_t ppd =3D GET_PPD(entry); + return ppd >> 1; +} + +static inline uint64_t hex_tlb_phys_addr(uint64_t entry) +{ + uint64_t pagemask =3D encmask_2_mask[hex_tlb_pgsize_type(entry)]; + uint64_t pagenum =3D hex_tlb_phys_page_num(entry); + uint64_t PA =3D (pagenum << qemu_target_page_bits()) & (~pagemask); + return PA; +} + +static inline uint64_t hex_tlb_virt_addr(uint64_t entry) +{ + return (uint64_t)GET_PTE_VPN(entry) << qemu_target_page_bits(); +} + +bool hexagon_tlb_dump_entry(Monitor *mon, uint64_t entry) +{ + if (GET_PTE_V(entry)) { + uint64_t PA =3D hex_tlb_phys_addr(entry); + uint64_t VA =3D hex_tlb_virt_addr(entry); + monitor_printf(mon, "0x%016" PRIx64 ": ", entry); + monitor_printf(mon, "V:%" PRId64 " G:%" PRId64 + " A1:%" PRId64 " A0:%" PRId64, + GET_PTE_V(entry), + GET_PTE_G(entry), + GET_PTE_ATR1(entry), + GET_PTE_ATR0(entry)); + monitor_printf(mon, " ASID:0x%02" PRIx64 " VA:0x%08" PRIx64, + GET_PTE_ASID(entry), VA); + monitor_printf(mon, + " X:%" PRId64 " W:%" PRId64 " R:%" PRId64 + " U:%" PRId64 " C:%" PRId64, + GET_PTE_X(entry), + GET_PTE_W(entry), + GET_PTE_R(entry), + GET_PTE_U(entry), + GET_PTE_C(entry)); + monitor_printf(mon, " PA:0x%09" PRIx64 " SZ:%s (0x%" PRIx64 ")", + PA, pgsize_str[hex_tlb_pgsize_type(entry)], + hex_tlb_page_size_bytes(entry)); + monitor_printf(mon, "\n"); + return true; + } + + /* Not valid */ + return false; +} + +static inline bool hex_tlb_entry_match_noperm(uint64_t entry, uint32_t asi= d, + uint64_t VA) +{ + if (GET_PTE_V(entry)) { + if (GET_PTE_G(entry)) { + /* Global entry - ignore ASID */ + } else if (asid !=3D NO_ASID) { + uint32_t tlb_asid =3D GET_PTE_ASID(entry); + if (tlb_asid !=3D asid) { + return false; + } + } + + uint64_t page_size =3D hex_tlb_page_size_bytes(entry); + uint64_t page_start =3D + ROUND_DOWN(hex_tlb_virt_addr(entry), page_size); + if (page_start <=3D VA && VA < page_start + page_size) { + return true; + } + } + return false; +} + +static inline void hex_tlb_entry_get_perm(uint64_t entry, + MMUAccessType access_type, + int mmu_idx, int *prot, + int32_t *excp, int *cause_code) +{ + bool perm_x =3D GET_PTE_X(entry); + bool perm_w =3D GET_PTE_W(entry); + bool perm_r =3D GET_PTE_R(entry); + bool perm_u =3D GET_PTE_U(entry); + bool user_idx =3D mmu_idx =3D=3D MMU_USER_IDX; + + if (mmu_idx =3D=3D MMU_KERNEL_IDX) { + *prot =3D PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return; + } + + *prot =3D PAGE_VALID; + switch (access_type) { + case MMU_INST_FETCH: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_FETCH_NO_UPAGE; + } else if (!perm_x) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_FETCH_NO_XPAGE; + } + break; + case MMU_DATA_LOAD: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_UREAD; + } else if (!perm_r) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_READ; + } + break; + case MMU_DATA_STORE: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_UWRITE; + } else if (!perm_w) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_WRITE; + } + break; + } + + if (!user_idx || perm_u) { + if (perm_x) { + *prot |=3D PAGE_EXEC; + } + if (perm_r) { + *prot |=3D PAGE_READ; + } + if (perm_w) { + *prot |=3D PAGE_WRITE; + } + } +} + +static inline bool hex_tlb_entry_match(uint64_t entry, uint8_t asid, + uint32_t VA, + MMUAccessType access_type, hwaddr *= PA, + int *prot, uint64_t *size, + int32_t *excp, int *cause_code, + int mmu_idx) +{ + if (hex_tlb_entry_match_noperm(entry, asid, VA)) { + hex_tlb_entry_get_perm(entry, access_type, mmu_idx, prot, excp, + cause_code); + *PA =3D hex_tlb_phys_addr(entry); + *size =3D hex_tlb_page_size_bytes(entry); + return true; + } + return false; +} + +static bool hex_tlb_is_match(uint64_t entry1, uint64_t entry2, + bool consider_gbit) +{ + bool valid1 =3D GET_PTE_V(entry1); + bool valid2 =3D GET_PTE_V(entry2); + uint64_t size1 =3D hex_tlb_page_size_bytes(entry1); + uint64_t vaddr1 =3D ROUND_DOWN(hex_tlb_virt_addr(entry1), size1); + uint64_t size2 =3D hex_tlb_page_size_bytes(entry2); + uint64_t vaddr2 =3D ROUND_DOWN(hex_tlb_virt_addr(entry2), size2); + int asid1 =3D GET_PTE_ASID(entry1); + int asid2 =3D GET_PTE_ASID(entry2); + bool gbit1 =3D GET_PTE_G(entry1); + bool gbit2 =3D GET_PTE_G(entry2); + + if (!valid1 || !valid2) { + return false; + } + + if (((vaddr1 <=3D vaddr2) && (vaddr2 < (vaddr1 + size1))) || + ((vaddr2 <=3D vaddr1) && (vaddr1 < (vaddr2 + size2)))) { + if (asid1 =3D=3D asid2) { + return true; + } + if ((consider_gbit && gbit1) || gbit2) { + return true; + } + } + return false; +} + +/* Public API */ + +uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index) +{ + g_assert(index < tlb->num_entries); + return tlb->entries[index]; +} + +void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t valu= e) +{ + g_assert(index < tlb->num_entries); + tlb->entries[index] =3D value; +} + +bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, MMUAccessType access_type, + hwaddr *PA, int *prot, uint64_t *size, + int32_t *excp, int *cause_code, int mmu_idx) +{ + *PA =3D 0; + *prot =3D 0; + *size =3D 0; + *excp =3D 0; + *cause_code =3D 0; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + if (hex_tlb_entry_match(tlb->entries[i], asid, VA, access_type, + PA, prot, size, excp, cause_code, mmu_idx)= ) { + return true; + } + } + return false; +} + +uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, int *cause_code) +{ + uint32_t not_found =3D 0x80000000; + uint32_t idx =3D not_found; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + uint64_t entry =3D tlb->entries[i]; + if (hex_tlb_entry_match_noperm(entry, asid, VA)) { + if (idx !=3D not_found) { + *cause_code =3D HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH; + break; + } + idx =3D i; + } + } + + if (idx =3D=3D not_found) { + qemu_log_mask(CPU_LOG_MMU, + "%s: 0x%" PRIx32 ", 0x%08" PRIx32 " =3D> NOT FOUND\n= ", + __func__, asid, VA); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: 0x%" PRIx32 ", 0x%08" PRIx32 " =3D> %d\n", + __func__, asid, VA, idx); + } + + return idx; +} + +/* + * Return codes: + * 0 or positive index of match + * -1 multiple matches + * -2 no match + */ +int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry, + uint64_t index) +{ + int matches =3D 0; + int last_match =3D 0; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + if (hex_tlb_is_match(entry, tlb->entries[i], false)) { + matches++; + last_match =3D i; + } + } + + if (matches =3D=3D 1) { + return last_match; + } + if (matches =3D=3D 0) { + return -2; + } + return -1; +} + +void hexagon_tlb_dump(Monitor *mon, HexagonTLBState *tlb) +{ + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + hexagon_tlb_dump_entry(mon, tlb->entries[i]); + } +} + +uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb) +{ + return tlb->num_entries; +} + +/* QOM lifecycle */ + +static void hexagon_tlb_init(Object *obj) +{ +} + +static void hexagon_tlb_realize(DeviceState *dev, Error **errp) +{ + HexagonTLBState *s =3D HEXAGON_TLB(dev); + + if (s->num_entries =3D=3D 0 || s->num_entries > MAX_TLB_ENTRIES) { + error_setg(errp, "Invalid TLB num-entries: %" PRIu32, + s->num_entries); + return; + } + s->entries =3D g_new0(uint64_t, s->num_entries); +} + +static void hexagon_tlb_unrealize(DeviceState *dev) +{ + HexagonTLBState *s =3D HEXAGON_TLB(dev); + g_free(s->entries); + s->entries =3D NULL; +} + +static void hexagon_tlb_reset_hold(Object *obj, ResetType type) +{ + HexagonTLBState *s =3D HEXAGON_TLB(obj); + if (s->entries) { + memset(s->entries, 0, sizeof(uint64_t) * s->num_entries); + } +} + +static const VMStateDescription vmstate_hexagon_tlb =3D { + .name =3D "hexagon-tlb", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(num_entries, HexagonTLBState), + VMSTATE_VARRAY_UINT32_ALLOC(entries, HexagonTLBState, num_entries, + 0, vmstate_info_uint64, uint64_t), + VMSTATE_END_OF_LIST() + }, +}; + +static const Property hexagon_tlb_properties[] =3D { + DEFINE_PROP_UINT32("num-entries", HexagonTLBState, num_entries, + MAX_TLB_ENTRIES), +}; + +static void hexagon_tlb_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D hexagon_tlb_realize; + dc->unrealize =3D hexagon_tlb_unrealize; + rc->phases.hold =3D hexagon_tlb_reset_hold; + dc->vmsd =3D &vmstate_hexagon_tlb; + dc->user_creatable =3D false; + device_class_set_props(dc, hexagon_tlb_properties); +} + +static const TypeInfo hexagon_tlb_info =3D { + .name =3D TYPE_HEXAGON_TLB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexagonTLBState), + .instance_init =3D hexagon_tlb_init, + .class_init =3D hexagon_tlb_class_init, +}; + +static void hexagon_tlb_register_types(void) +{ + type_register_static(&hexagon_tlb_info); +} + +type_init(hexagon_tlb_register_types) --=20 2.34.1 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092101983154100 From: Brian Cain Some header includes are modified here: these are uniquely required for basic system emulation functionality and had not been required for linux-us= er. Acked-by: Markus Armbruster Co-authored-by: Mike Lambert Co-authored-by: Sid Manning Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- MAINTAINERS | 14 +- include/hw/hexagon/hexagon.h | 161 ++++++++++++++++++ hw/hexagon/machine_cfg_v66g_1024.h.inc | 64 +++++++ hw/hexagon/hexagon_dsp.c | 220 +++++++++++++++++++++++++ system/qdev-monitor.c | 2 +- target/hexagon/translate.c | 1 + hw/Kconfig | 1 + hw/hexagon/Kconfig | 4 + hw/hexagon/meson.build | 6 + hw/meson.build | 1 + 10 files changed, 471 insertions(+), 3 deletions(-) create mode 100644 include/hw/hexagon/hexagon.h create mode 100644 hw/hexagon/machine_cfg_v66g_1024.h.inc create mode 100644 hw/hexagon/hexagon_dsp.c create mode 100644 hw/hexagon/Kconfig create mode 100644 hw/hexagon/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index e670e22c197..0528387ce17 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -260,8 +260,6 @@ F: configs/targets/hexagon-linux-user/default.mak F: docker/dockerfiles/debian-hexagon-cross.docker F: gdbstub/gdb-xml/hexagon*.xml F: docs/system/target-hexagon.rst -F: docs/system/hexagon/ -F: docs/devel/hexagon-sys.rst T: git https://github.com/quic/qemu.git hex-next =20 Hexagon idef-parser @@ -1348,6 +1346,18 @@ F: pc-bios/hppa-firmware.img F: roms/seabios-hppa/ F: tests/functional/hppa/ =20 +Hexagon Machines +---------------- +V66G_1024, V68N_1024, sa8775-cdsp0 +M: Brian Cain +R: Pierrick Bouvier +S: Supported +F: hw/hexagon/ +F: include/hw/hexagon/ +F: configs/devices/hexagon-softmmu/default.mak +F: docs/system/hexagon/ +F: docs/devel/hexagon-sys.rst + LoongArch Machines ------------------ Virt diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h new file mode 100644 index 00000000000..1034b09c2ac --- /dev/null +++ b/include/hw/hexagon/hexagon.h @@ -0,0 +1,161 @@ +/* + * Hexagon Baseboard System emulation. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + +#ifndef HW_HEXAGON_H +#define HW_HEXAGON_H + +#include "system/memory.h" +#include "hw/core/boards.h" + +struct hexagon_board_boot_info { + uint64_t ram_size; + const char *kernel_filename; + uint32_t kernel_elf_flags; +}; + +typedef enum { + unknown_rev =3D 0, + v66_rev =3D 0xa666, + v67_rev =3D 0x2667, + v68_rev =3D 0x8d68, + v69_rev =3D 0x8c69, + v71_rev =3D 0x8c71, + v73_rev =3D 0x8c73, + v73m_rev =3D 0xcc73, +} Rev_t; +#define HEXAGON_LATEST_REV v73 +#define HEXAGON_LATEST_REV_UPPER V73 + +/* + * Config table address bases represent bits [35:16]. + */ +#define HEXAGON_CFG_ADDR_BASE(addr) (((addr) >> 16) & 0x0fffff) + +#define HEXAGON_CFGSPACE_ENTRIES (128) + +union hexagon_config_table { + struct { + /* Base address of L2TCM space */ + uint32_t l2tcm_base; + uint32_t reserved0; + /* Base address of subsystem space */ + uint32_t subsystem_base; + /* Base address of ETM space */ + uint32_t etm_base; + /* Base address of L2 configuration space */ + uint32_t l2cfg_base; + uint32_t reserved1; + /* Base address of L1S */ + uint32_t l1s0_base; + /* Base address of AXI2 */ + uint32_t axi2_lowaddr; + /* Base address of streamer base */ + uint32_t streamer_base; + uint32_t reserved2; + /* Base address of fast L2VIC */ + uint32_t fastl2vic_base; + /* Number of entries in JTLB */ + uint32_t jtlb_size_entries; + /* Coprocessor type */ + uint32_t coproc_present; + /* Number of extension execution contexts available */ + uint32_t ext_contexts; + /* Base address of Hexagon Vector Tightly Coupled Memory (VTCM) */ + uint32_t vtcm_base; + /* Size of VTCM (in KB) */ + uint32_t vtcm_size_kb; + /* L2 tag size */ + uint32_t l2tag_size; + /* Amount of physical L2 memory in released version */ + uint32_t l2ecomem_size; + /* Hardware threads available on the core */ + uint32_t thread_enable_mask; + /* Base address of the ECC registers */ + uint32_t eccreg_base; + /* L2 line size */ + uint32_t l2line_size; + /* Small Core processor (also implies audio extension) */ + uint32_t tiny_core; + /* Size of L2TCM */ + uint32_t l2itcm_size; + /* Base address of L2-ITCM */ + uint32_t l2itcm_base; + uint32_t reserved3; + /* DTM is present */ + uint32_t dtm_present; + /* Version of the DMA */ + uint32_t dma_version; + /* Native HVX vector length in log of bytes */ + uint32_t hvx_vec_log_length; + /* Core ID of the multi-core */ + uint32_t core_id; + /* Number of multi-core cores */ + uint32_t core_count; + uint32_t coproc2_reg0; + uint32_t coproc2_reg1; + /* Supported HVX vector length */ + uint32_t v2x_mode; + uint32_t coproc2_reg2; + uint32_t coproc2_reg3; + uint32_t coproc2_reg4; + uint32_t coproc2_reg5; + uint32_t coproc2_reg6; + uint32_t coproc2_reg7; + /* Voltage droop mitigation technique parameter */ + uint32_t acd_preset; + /* Voltage droop mitigation technique parameter */ + uint32_t mnd_preset; + /* L1 data cache size (in KB) */ + uint32_t l1d_size_kb; + /* L1 instruction cache size in (KB) */ + uint32_t l1i_size_kb; + /* L1 data cache write policy: see HexagonL1WritePolicy */ + uint32_t l1d_write_policy; + /* VTCM bank width */ + uint32_t vtcm_bank_width; + uint32_t reserved4; + uint32_t reserved5; + uint32_t reserved6; + uint32_t coproc2_cvt_mpy_size; + uint32_t consistency_domain; + uint32_t capacity_domain; + uint32_t axi3_lowaddr; + uint32_t coproc2_int8_subcolumns; + uint32_t corecfg_present; + uint32_t coproc2_fp16_acc_exp; + uint32_t AXIM2_secondary_base; + }; + uint32_t raw[HEXAGON_CFGSPACE_ENTRIES]; +}; + +struct hexagon_machine_config { + /* Base address of config table */ + uint32_t cfgbase; + /* Size of L2 TCM */ + uint32_t l2tcm_size; + /* Base address of L2VIC */ + uint32_t l2vic_base; + /* Size of L2VIC region */ + uint32_t l2vic_size; + /* QTimer csr base */ + uint32_t csr_base; + uint32_t qtmr_region; + union hexagon_config_table cfgtable; +}; + +#define TYPE_HEXAGON_COMMON_MACHINE "hexagon-common-machine" +OBJECT_DECLARE_SIMPLE_TYPE(HexagonCommonMachineState, HEXAGON_COMMON_MACHI= NE) + +struct HexagonCommonMachineState { + MachineState parent_obj; + + MemoryRegion ram; + MemoryRegion cfgtable_rom; +}; + +#endif diff --git a/hw/hexagon/machine_cfg_v66g_1024.h.inc b/hw/hexagon/machine_cf= g_v66g_1024.h.inc new file mode 100644 index 00000000000..cc4d89b89c9 --- /dev/null +++ b/hw/hexagon/machine_cfg_v66g_1024.h.inc @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v66g_1024 =3D { + .cfgbase =3D 0xd8180000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, + .reserved0 =3D 0x0000d400, + .subsystem_base =3D 0x0000fc90, + .etm_base =3D 0x0000d805, + .l2cfg_base =3D 0x0000d81a, + .reserved1 =3D 0x00000000, + .l1s0_base =3D 0x0000d820, + .axi2_lowaddr =3D 0x00003000, + .streamer_base =3D 0x00000000, + .reserved2 =3D 0x0000d819, + .fastl2vic_base =3D 0x0000d81e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x00000001, + .ext_contexts =3D 0x00000004, + .vtcm_base =3D 0x0000d820, + .vtcm_size_kb =3D 0x00000100, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x0000000f, + .eccreg_base =3D 0x0000d81f, + .l2line_size =3D 0x00000080, + .tiny_core =3D 0x00000000, + .l2itcm_size =3D 0x00000000, + .l2itcm_base =3D 0x0000d820, + .reserved3 =3D 0x00000000, + .dtm_present =3D 0x00000000, + .dma_version =3D 0x00000000, + .hvx_vec_log_length =3D 0x00000080, + .core_id =3D 0x00000000, + .core_count =3D 0x00000000, + .coproc2_reg0 =3D 0x00000000, + .coproc2_reg1 =3D 0x00000000, + .v2x_mode =3D 0x00000000, + .coproc2_reg2 =3D 0x00000000, + .coproc2_reg3 =3D 0x00000000, + .coproc2_reg4 =3D 0x00000000, + .coproc2_reg5 =3D 0x00000000, + .coproc2_reg6 =3D 0x00000000, + .coproc2_reg7 =3D 0x00000000, + .acd_preset =3D 0x00000000, + .mnd_preset =3D 0x00000000, + .l1d_size_kb =3D 0x00000000, + .l1i_size_kb =3D 0x00000000, + .l1d_write_policy =3D 0x00000000, + .vtcm_bank_width =3D 0x00000000, + .reserved4 =3D 0x00000000, + .reserved5 =3D 0x00000000, + .reserved6 =3D 0x00000000, + .coproc2_cvt_mpy_size =3D 0x00000000, + .consistency_domain =3D 0x00000000, + .capacity_domain =3D 0x00000000, + .axi3_lowaddr =3D 0x00000000, + }, +}; diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c new file mode 100644 index 00000000000..5934a99b522 --- /dev/null +++ b/hw/hexagon/hexagon_dsp.c @@ -0,0 +1,220 @@ +/* + * Hexagon DSP Subsystem emulation. This represents a generic DSP + * subsystem with few peripherals, like the Compute DSP. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "system/address-spaces.h" +#include "hw/core/boards.h" +#include "hw/core/qdev-properties.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_tlb.h" +#include "hw/core/loader.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "elf.h" +#include "cpu.h" +#include "migration/cpu.h" +#include "system/system.h" +#include "target/hexagon/internal.h" +#include "system/reset.h" + +#include "machine_cfg_v66g_1024.h.inc" + +#define TYPE_HEXAGON_DSP_MACHINE "hexagon-dsp-machine" +OBJECT_DECLARE_SIMPLE_TYPE(HexagonDspMachineState, HEXAGON_DSP_MACHINE) + +struct HexagonDspMachineState { + HexagonCommonMachineState parent_obj; + + hwaddr isdb_secure_flag; + hwaddr isdb_trusted_flag; +}; + +static HexagonDspMachineState *current_dms; + +static void hex_symbol_callback(const char *st_name, int st_info, + uint64_t st_value, uint64_t st_size) +{ + if (!g_strcmp0("isdb_secure_flag", st_name)) { + current_dms->isdb_secure_flag =3D st_value; + } + if (!g_strcmp0("isdb_trusted_flag", st_name)) { + current_dms->isdb_trusted_flag =3D st_value; + } +} + +/* Board init. */ +static struct hexagon_board_boot_info hexagon_binfo; + +static void hexagon_load_kernel(HexagonDspMachineState *dms, HexagonCPU *c= pu) +{ + uint64_t pentry; + long kernel_size; + + current_dms =3D dms; + kernel_size =3D load_elf_ram_sym(hexagon_binfo.kernel_filename, NULL, = NULL, + NULL, &pentry, NULL, NULL, + &hexagon_binfo.kernel_elf_flags, 0, EM_HEXAGON, 0, 0, + &address_space_memory, false, hex_symbol_callback); + current_dms =3D NULL; + + if (kernel_size <=3D 0) { + error_report("no kernel file '%s'", + hexagon_binfo.kernel_filename); + exit(1); + } + + qdev_prop_set_uint32(DEVICE(cpu), "exec-start-addr", pentry); +} + +static void hexagon_init_bootstrap(HexagonDspMachineState *dms, HexagonCPU= *cpu) +{ + MachineState *machine =3D MACHINE(dms); + + if (machine->kernel_filename) { + uint32_t mem =3D 1; + + hexagon_load_kernel(dms, cpu); + if (dms->isdb_secure_flag) { + cpu_physical_memory_write(dms->isdb_secure_flag, + &mem, sizeof(mem)); + } + if (dms->isdb_trusted_flag) { + cpu_physical_memory_write(dms->isdb_trusted_flag, + &mem, sizeof(mem)); + } + } +} + +static void do_cpu_reset(void *opaque) +{ + HexagonCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + cpu_reset(cs); +} + +static void hexagon_common_init(MachineState *machine, Rev_t rev, + const struct hexagon_machine_config *m_cfg) +{ + HexagonCommonMachineState *hms =3D HEXAGON_COMMON_MACHINE(machine); + HexagonDspMachineState *dms =3D HEXAGON_DSP_MACHINE(machine); + MemoryRegion *address_space; + DeviceState *glob_regs_dev; + DeviceState *tlb_dev; + + memset(&hexagon_binfo, 0, sizeof(hexagon_binfo)); + if (machine->kernel_filename) { + hexagon_binfo.ram_size =3D machine->ram_size; + hexagon_binfo.kernel_filename =3D machine->kernel_filename; + } + + machine->enable_graphics =3D 0; + + address_space =3D get_system_memory(); + + memory_region_init_rom(&hms->cfgtable_rom, NULL, "config_table.rom", + sizeof(m_cfg->cfgtable), &error_fatal); + memory_region_add_subregion(address_space, m_cfg->cfgbase, + &hms->cfgtable_rom); + + memory_region_init_ram(&hms->ram, NULL, "ddr.ram", + machine->ram_size, &error_fatal); + memory_region_add_subregion(address_space, 0x0, &hms->ram); + + glob_regs_dev =3D qdev_new(TYPE_HEXAGON_GLOBALREG); + object_property_add_child(OBJECT(machine), "global-regs", + OBJECT(glob_regs_dev)); + qdev_prop_set_uint64(glob_regs_dev, "config-table-addr", m_cfg->cfgbas= e); + qdev_prop_set_uint32(glob_regs_dev, "dsp-rev", rev); + sysbus_realize_and_unref(SYS_BUS_DEVICE(glob_regs_dev), &error_fatal); + + tlb_dev =3D qdev_new(TYPE_HEXAGON_TLB); + object_property_add_child(OBJECT(machine), "tlb", OBJECT(tlb_dev)); + qdev_prop_set_uint32(tlb_dev, "num-entries", + m_cfg->cfgtable.jtlb_size_entries); + sysbus_realize_and_unref(SYS_BUS_DEVICE(tlb_dev), &error_fatal); + + for (int i =3D 0; i < machine->smp.cpus; i++) { + HexagonCPU *cpu =3D HEXAGON_CPU(object_new(machine->cpu_type)); + qemu_register_reset(do_cpu_reset, cpu); + + /* + * CPU #0 is the only CPU running at boot, others must be + * explicitly enabled via start instruction. + */ + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i !=3D 0)); + if (i =3D=3D 0) { + hexagon_init_bootstrap(dms, cpu); + } + object_property_set_link(OBJECT(cpu), "global-regs", + OBJECT(glob_regs_dev), &error_fatal); + object_property_set_link(OBJECT(cpu), "tlb", + OBJECT(tlb_dev), &error_fatal); + qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); + } +} + +static void init_mc(MachineClass *mc) +{ + mc->block_default_type =3D IF_SD; + mc->default_ram_size =3D 4 * GiB; + mc->no_parallel =3D 1; + mc->no_floppy =3D 1; + mc->no_cdrom =3D 1; + mc->no_serial =3D 1; + mc->is_default =3D false; + mc->max_cpus =3D 8; +} + +/* ----------------------------------------------------------------- */ +/* Core-specific configuration settings are defined below this line. */ +/* Config table values defined in machine_configs.h.inc */ +/* ----------------------------------------------------------------- */ + +static void v66g_1024_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v66_rev, &v66g_1024); +} + +static void v66g_1024_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon V66G_1024"; + mc->init =3D v66g_1024_config_init; + init_mc(mc); + mc->is_default =3D true; + mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V66; + mc->default_cpus =3D 4; +} + +static const TypeInfo hexagon_machine_types[] =3D { + { + .name =3D TYPE_HEXAGON_COMMON_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(HexagonCommonMachineState), + .abstract =3D true, + }, + { + .name =3D TYPE_HEXAGON_DSP_MACHINE, + .parent =3D TYPE_HEXAGON_COMMON_MACHINE, + .instance_size =3D sizeof(HexagonDspMachineState), + .abstract =3D true, + }, + { + .name =3D MACHINE_TYPE_NAME("V66G_1024"), + .parent =3D TYPE_HEXAGON_DSP_MACHINE, + .class_init =3D v66g_1024_init, + }, +}; + +DEFINE_TYPES(hexagon_machine_types) diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c index dfc95a08c10..00fed791cce 100644 --- a/system/qdev-monitor.c +++ b/system/qdev-monitor.c @@ -71,7 +71,7 @@ typedef struct QDevAlias QEMU_ARCH_SPARC | \ QEMU_ARCH_XTENSA) #define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X) -#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K) +#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K | QEMU_ARCH_HEXAGON) =20 /* Please keep this table sorted by typename. */ static const QDevAlias qdev_alias_table[] =3D { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index c37770bd92e..6979cf8c0d8 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -32,6 +32,7 @@ #include "translate.h" #include "genptr.h" #include "printinsn.h" +#include "exec/target_page.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/hw/Kconfig b/hw/Kconfig index c109f5537b2..c92ca2b13a3 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -53,6 +53,7 @@ source arm/Kconfig source cpu/Kconfig source alpha/Kconfig source avr/Kconfig +source hexagon/Kconfig source hppa/Kconfig source i386/Kconfig source loongarch/Kconfig diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig new file mode 100644 index 00000000000..cdf7770a305 --- /dev/null +++ b/hw/hexagon/Kconfig @@ -0,0 +1,4 @@ +config HEX_DSP + bool + default y + depends on HEXAGON diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build new file mode 100644 index 00000000000..f528d2bc4ab --- /dev/null +++ b/hw/hexagon/meson.build @@ -0,0 +1,6 @@ +hexagon_ss =3D ss.source_set() +hexagon_ss.add(files('hexagon_tlb.c')) +hexagon_ss.add(files('hexagon_globalreg.c')) +hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c')) + +hw_arch +=3D {'hexagon': hexagon_ss} diff --git a/hw/meson.build b/hw/meson.build index ef65ba51950..7fa81db453e 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,6 +3,7 @@ subdir('alpha') subdir('arm') subdir('avr') subdir('hppa') +subdir('hexagon') subdir('xenpv') # i386 uses it subdir('i386') subdir('loongarch') --=20 2.34.1 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092114018154100 Content-Type: text/plain; charset="utf-8" From: Brian Cain Acked-by: Taylor Simpson Acked-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc | 64 ++++++++++++++++++++++ hw/hexagon/machine_cfg_v68n_1024.h.inc | 65 +++++++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc create mode 100644 hw/hexagon/machine_cfg_v68n_1024.h.inc diff --git a/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc b/hw/hexagon/machine= _cfg_sa8775_cdsp0.h.inc new file mode 100644 index 00000000000..442cbe3be31 --- /dev/null +++ b/hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config SA8775P_cdsp0 =3D { + .cfgbase =3D 0x24000000 + 0x180000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0x26300000 + 0x90000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0x26300000, + .qtmr_region =3D 0x26300000 + 0xA1000, + .cfgtable =3D { + .l2tcm_base =3D 0x00002400, + .reserved0 =3D 0x00000000, + .subsystem_base =3D 0x00002638, + .etm_base =3D 0x00002419, + .l2cfg_base =3D 0x0000241a, + .reserved1 =3D 0x0000241b, + .l1s0_base =3D 0x00002500, + .axi2_lowaddr =3D 0x00000000, + .streamer_base =3D 0x00000000, + .reserved2 =3D 0x00000000, + .fastl2vic_base =3D 0x0000241e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x00000001, + .ext_contexts =3D 0x00000004, + .vtcm_base =3D 0x00002500, + .vtcm_size_kb =3D 0x00002000, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000000, + .thread_enable_mask =3D 0x0000003f, + .eccreg_base =3D 0x0000241f, + .l2line_size =3D 0x00000080, + .tiny_core =3D 0x00000000, + .l2itcm_size =3D 0x00000000, + .l2itcm_base =3D 0x00002400, + .reserved3 =3D 0x00000000, + .dtm_present =3D 0x00000000, + .dma_version =3D 0x00000003, + .hvx_vec_log_length =3D 0x00000007, + .core_id =3D 0x00000000, + .core_count =3D 0x00000000, + .coproc2_reg0 =3D 0x00000040, + .coproc2_reg1 =3D 0x00000020, + .v2x_mode =3D 0x00000001, + .coproc2_reg2 =3D 0x00000008, + .coproc2_reg3 =3D 0x00000020, + .coproc2_reg4 =3D 0x00000000, + .coproc2_reg5 =3D 0x00000002, + .coproc2_reg6 =3D 0x00000016, + .coproc2_reg7 =3D 0x00000006, + .acd_preset =3D 0x00000001, + .mnd_preset =3D 0x00000000, + .l1d_size_kb =3D 0x00000010, + .l1i_size_kb =3D 0x00000020, + .l1d_write_policy =3D 0x00000002, + .vtcm_bank_width =3D 0x00000080, + .reserved4 =3D 0x00000001, + .reserved5 =3D 0x00000000, + .reserved6 =3D 0x00000003, + .coproc2_cvt_mpy_size =3D 0x0000000a, + .consistency_domain =3D 0x000000e0, + .capacity_domain =3D 0x00000080, + .axi3_lowaddr =3D 0x00000000, + }, +}; diff --git a/hw/hexagon/machine_cfg_v68n_1024.h.inc b/hw/hexagon/machine_cf= g_v68n_1024.h.inc new file mode 100644 index 00000000000..82619c42ac1 --- /dev/null +++ b/hw/hexagon/machine_cfg_v68n_1024.h.inc @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v68n_1024 =3D { + .cfgbase =3D 0xde000000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, + .reserved0 =3D 0x00000000, + .subsystem_base =3D 0x0000fc90, + .etm_base =3D 0x0000d819, + .l2cfg_base =3D 0x0000d81a, + .reserved1 =3D 0x00000000, + .l1s0_base =3D 0x0000d840, + .axi2_lowaddr =3D 0x00003000, + .streamer_base =3D 0x0000d81c, + .reserved2 =3D 0x0000d81d, + .fastl2vic_base =3D 0x0000d81e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x00000001, + .ext_contexts =3D 0x00000004, + .vtcm_base =3D 0x0000d840, + .vtcm_size_kb =3D 0x00001000, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x0000003f, + .eccreg_base =3D 0x0000d81f, + .l2line_size =3D 0x00000080, + .tiny_core =3D 0x00000000, + .l2itcm_size =3D 0x00000000, + .l2itcm_base =3D 0x0000d820, + .reserved3 =3D 0x00000000, + .dtm_present =3D 0x00000000, + .dma_version =3D 0x00000001, + .hvx_vec_log_length =3D 0x00000007, + .core_id =3D 0x00000000, + .core_count =3D 0x00000000, + .coproc2_reg0 =3D 0x00000040, + .coproc2_reg1 =3D 0x00000020, + .v2x_mode =3D 0x1f1f1f1f, + .coproc2_reg2 =3D 0x1f1f1f1f, + .coproc2_reg3 =3D 0x1f1f1f1f, + .coproc2_reg4 =3D 0x1f1f1f1f, + .coproc2_reg5 =3D 0x1f1f1f1f, + .coproc2_reg6 =3D 0x1f1f1f1f, + .coproc2_reg7 =3D 0x1f1f1f1f, + .acd_preset =3D 0x1f1f1f1f, + .mnd_preset =3D 0x1f1f1f1f, + .l1d_size_kb =3D 0x1f1f1f1f, + .l1i_size_kb =3D 0x1f1f1f1f, + .l1d_write_policy =3D 0x1f1f1f1f, + .vtcm_bank_width =3D 0x1f1f1f1f, + .reserved4 =3D 0x1f1f1f1f, + .reserved5 =3D 0x1f1f1f1f, + .reserved6 =3D 0x1f1f1f1f, + .coproc2_cvt_mpy_size =3D 0x1f1f1f1f, + .consistency_domain =3D 0x1f1f1f1f, + .capacity_domain =3D 0x1f1f1f1f, + .axi3_lowaddr =3D 0x1f1f1f1f, + }, +}; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092148537154100 From: Sid Manning Reviewed-by: Taylor Simpson Signed-off-by: Sid Manning --- hw/hexagon/hexagon_dsp.c | 4 ++++ target/hexagon/cpu.c | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c index 5934a99b522..f3b13199678 100644 --- a/hw/hexagon/hexagon_dsp.c +++ b/hw/hexagon/hexagon_dsp.c @@ -161,6 +161,10 @@ static void hexagon_common_init(MachineState *machine,= Rev_t rev, OBJECT(tlb_dev), &error_fatal); qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); } + + rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable, + sizeof(m_cfg->cfgtable), m_cfg->cfgbase, + &address_space_memory); } =20 static void init_mc(MachineClass *mc) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 895afa2c1ff..39ec8139542 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -399,7 +399,6 @@ void hexagon_cpu_soft_reset(CPUHexagonState *env) } #endif =20 - static void hexagon_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); --=20 2.34.1 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1780092126; cv=none; d=zohomail.com; s=zohoarc; b=VPu85v02lBRTk+VIHvQ1PuCCAVsq5Znk/Hs9vNT9A8m+uP/OYNtuHp3diq06b7qrqfoHms98ukSbegjH5Y0Ngp8r18FqIJK2LIo9fNQ1l60oitWR1vZU4YaDDtwrN1MVfKm5Vh0u/r5t10z38VzB4E1vrhVq4v6RNarvf2Wad5g= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092128269154100 Reviewed-by: Taylor Simpson Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- MAINTAINERS | 1 + configs/devices/hexagon-softmmu/default.mak | 7 +++++++ configs/targets/hexagon-softmmu.mak | 7 +++++++ target/hexagon/cpu.h | 7 +------ target/Kconfig | 1 + target/hexagon/Kconfig | 2 ++ target/hexagon/meson.build | 13 ++++++++++++- 7 files changed, 31 insertions(+), 7 deletions(-) create mode 100644 configs/devices/hexagon-softmmu/default.mak create mode 100644 configs/targets/hexagon-softmmu.mak create mode 100644 target/hexagon/Kconfig diff --git a/MAINTAINERS b/MAINTAINERS index 0528387ce17..2e87f8da738 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -257,6 +257,7 @@ F: linux-user/hexagon/ F: tests/tcg/hexagon/ F: disas/hexagon.c F: configs/targets/hexagon-linux-user/default.mak +F: configs/devices/hexagon-softmmu/default.mak F: docker/dockerfiles/debian-hexagon-cross.docker F: gdbstub/gdb-xml/hexagon*.xml F: docs/system/target-hexagon.rst diff --git a/configs/devices/hexagon-softmmu/default.mak b/configs/devices/= hexagon-softmmu/default.mak new file mode 100644 index 00000000000..08e709aea72 --- /dev/null +++ b/configs/devices/hexagon-softmmu/default.mak @@ -0,0 +1,7 @@ +# Default configuration for hexagon-softmmu + +# Uncomment the following lines to disable these optional devices: + +# Boards are selected by default, uncomment to keep out of the build. +# CONFIG_HEX_DSP=3Dy +# CONFIG_L2VIC=3Dy diff --git a/configs/targets/hexagon-softmmu.mak b/configs/targets/hexagon-= softmmu.mak new file mode 100644 index 00000000000..fdfa29b4f39 --- /dev/null +++ b/configs/targets/hexagon-softmmu.mak @@ -0,0 +1,7 @@ +# Default configuration for hexagon-softmmu + +TARGET_ARCH=3Dhexagon +TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml +TARGET_LONG_BITS=3D32 +TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy +TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index b188ccc3c6d..7694fd91fa8 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -38,12 +38,7 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegSta= te; #include "hw/core/registerfields.h" #include "qemu/bitmap.h" =20 -#ifndef CONFIG_USER_ONLY -#error "Hexagon does not support system emulation" -#endif - -#ifndef CONFIG_USER_ONLY -#endif +#include "target/hexagon/reg_fields.h" =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 diff --git a/target/Kconfig b/target/Kconfig index 3c73e3bae01..0288a3f4164 100644 --- a/target/Kconfig +++ b/target/Kconfig @@ -16,6 +16,7 @@ source sh4/Kconfig source sparc/Kconfig source tricore/Kconfig source xtensa/Kconfig +source hexagon/Kconfig =20 config TARGET_BIG_ENDIAN bool diff --git a/target/hexagon/Kconfig b/target/hexagon/Kconfig new file mode 100644 index 00000000000..7e556f35063 --- /dev/null +++ b/target/hexagon/Kconfig @@ -0,0 +1,2 @@ +config HEXAGON + bool diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 528beca3cd0..bc7a292e47b 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -235,6 +235,7 @@ decodetree_trans_funcs_generated =3D custom_target( command: [python, files('gen_trans_funcs.py'), semantics_generated, '@= OUTPUT@'], ) hexagon_ss.add(decodetree_trans_funcs_generated) +hexagon_softmmu_ss =3D ss.source_set() =20 hexagon_ss.add(files( 'cpu.c', @@ -253,6 +254,14 @@ hexagon_ss.add(files( 'mmvec/system_ext_mmvec.c', )) =20 +hexagon_softmmu_ss.add(files( + 'cpu_helper.c', + 'hex_mmu.c', + 'hex_interrupts.c', + 'hexswi.c', + 'machine.c', +)) + # # Step 4.5 # We use flex/bison based idef-parser to generate TCG code for a lot @@ -262,7 +271,8 @@ hexagon_ss.add(files( # idef-generated-enabled-instructions # idef_parser_enabled =3D get_option('hexagon_idef_parser') -if idef_parser_enabled and 'hexagon-linux-user' in target_dirs +if idef_parser_enabled and ('hexagon-linux-user' in target_dirs or + 'hexagon-softmmu' in target_dirs) idef_parser_input_generated =3D custom_target( 'idef_parser_input.h.inc', output: 'idef_parser_input.h.inc', @@ -390,3 +400,4 @@ analyze_funcs_generated =3D custom_target( hexagon_ss.add(analyze_funcs_generated) =20 target_arch +=3D {'hexagon': hexagon_ss} +target_system_arch +=3D {'hexagon': hexagon_softmmu_ss} --=20 2.34.1 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092127401158500 From: Brian Cain Signed-off-by: Brian Cain --- configs/devices/hexagon-softmmu/default.mak | 1 + configs/targets/hexagon-softmmu.mak | 1 + include/hw/hexagon/virt.h | 31 ++ hw/hexagon/virt.c | 463 ++++++++++++++++++++ hw/hexagon/Kconfig | 10 + hw/hexagon/meson.build | 1 + tests/qemu-iotests/testenv.py | 1 + 7 files changed, 508 insertions(+) create mode 100644 include/hw/hexagon/virt.h create mode 100644 hw/hexagon/virt.c diff --git a/configs/devices/hexagon-softmmu/default.mak b/configs/devices/= hexagon-softmmu/default.mak index 08e709aea72..37b4f9f3237 100644 --- a/configs/devices/hexagon-softmmu/default.mak +++ b/configs/devices/hexagon-softmmu/default.mak @@ -3,5 +3,6 @@ # Uncomment the following lines to disable these optional devices: =20 # Boards are selected by default, uncomment to keep out of the build. +# CONFIG_HEX_VIRT=3Dy # CONFIG_HEX_DSP=3Dy # CONFIG_L2VIC=3Dy diff --git a/configs/targets/hexagon-softmmu.mak b/configs/targets/hexagon-= softmmu.mak index fdfa29b4f39..a77c100f0c5 100644 --- a/configs/targets/hexagon-softmmu.mak +++ b/configs/targets/hexagon-softmmu.mak @@ -5,3 +5,4 @@ TARGET_XML_FILES=3Dhexagon-core.xml hexagon-hvx.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy +TARGET_NEED_FDT=3Dy diff --git a/include/hw/hexagon/virt.h b/include/hw/hexagon/virt.h new file mode 100644 index 00000000000..9df1348bda0 --- /dev/null +++ b/include/hw/hexagon/virt.h @@ -0,0 +1,31 @@ +/* + * Definitions for hexagon virt board. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_HEXAGONVIRT_H +#define HW_HEXAGONVIRT_H + +#include "hw/hexagon/hexagon.h" +#include "target/hexagon/cpu.h" + +struct HexagonVirtMachineState { + HexagonCommonMachineState parent_obj; + + int fdt_size; + MemoryRegion *sys; + MemoryRegion tcm; + MemoryRegion vtcm; + MemoryRegion bios; + DeviceState *l2vic; + Clock *apb_clk; +}; + +void hexagon_load_fdt(const struct HexagonVirtMachineState *vms); + +#define TYPE_HEXAGON_VIRT_MACHINE MACHINE_TYPE_NAME("virt") +OBJECT_DECLARE_SIMPLE_TYPE(HexagonVirtMachineState, HEXAGON_VIRT_MACHINE) + +#endif /* HW_HEXAGONVIRT_H */ diff --git a/hw/hexagon/virt.c b/hw/hexagon/virt.c new file mode 100644 index 00000000000..a0aa6dad7d2 --- /dev/null +++ b/hw/hexagon/virt.c @@ -0,0 +1,463 @@ +/* + * Hexagon virt emulation + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/hexagon/virt.h" +#include "elf.h" +#include "hw/char/pl011.h" +#include "hw/core/clock.h" +#include "hw/core/sysbus-fdt.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_tlb.h" +#include "hw/core/loader.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/register.h" +#include "qemu/error-report.h" +#include "qemu/guest-random.h" +#include "qemu/units.h" +#include "machine_cfg_v68n_1024.h.inc" +#include "system/address-spaces.h" +#include "system/device_tree.h" +#include "system/reset.h" +#include "system/system.h" +#include + +enum { + VIRT_UART0, + VIRT_QTMR0, + VIRT_QTMR1, + VIRT_GPT, + VIRT_MMIO, + VIRT_FDT, +}; + +static const int VIRTIO_DEV_COUNT =3D 8; + +static const MemMapEntry base_memmap[] =3D { + [VIRT_UART0] =3D { 0x10000000, 0x00000200 }, + [VIRT_MMIO] =3D { 0x11000000, 0x1000000, }, + [VIRT_GPT] =3D { 0xab000000, 0x00001000 }, + [VIRT_FDT] =3D { 0x99800000, 0x00400000 }, +}; + +static const int irqmap[] =3D { + [VIRT_MMIO] =3D 18, /* ...to 18 + VIRTIO_DEV_COUNT - 1 */ + [VIRT_GPT] =3D 12, + [VIRT_UART0] =3D 15, + [VIRT_QTMR0] =3D 2, + [VIRT_QTMR1] =3D 4, +}; + + +static void create_fdt(HexagonVirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + void *fdt =3D create_device_tree(&vms->fdt_size); + uint8_t rng_seed[32]; + + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + ms->fdt =3D fdt; + + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); + qemu_fdt_setprop_string(fdt, "/", "model", "hexagon-virt,qemu"); + qemu_fdt_setprop_string(fdt, "/", "compatible", "qcom,sm8150"); + + qemu_fdt_add_subnode(fdt, "/soc"); + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); + + qemu_fdt_add_subnode(fdt, "/chosen"); + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed= )); +} + +static void fdt_add_hvx(HexagonVirtMachineState *vms, + const struct hexagon_machine_config *m_cfg) +{ + const MachineState *ms =3D MACHINE(vms); + uint32_t vtcm_size_bytes =3D m_cfg->cfgtable.vtcm_size_kb * 1024; + if (vtcm_size_bytes > 0) { + memory_region_init_ram(&vms->vtcm, NULL, "vtcm.ram", vtcm_size_byt= es, + &error_fatal); + memory_region_add_subregion(vms->sys, m_cfg->cfgtable.vtcm_base <<= 16, + &vms->vtcm); + + qemu_fdt_add_subnode(ms->fdt, "/soc/vtcm"); + qemu_fdt_setprop_string(ms->fdt, "/soc/vtcm", "compatible", + "qcom,hexagon_vtcm"); + + assert(sizeof(m_cfg->cfgtable.vtcm_base) =3D=3D sizeof(uint32_t)); + qemu_fdt_setprop_cells(ms->fdt, "/soc/vtcm", "reg", 0, + m_cfg->cfgtable.vtcm_base << 16, + vtcm_size_bytes); + } + + if (m_cfg->cfgtable.ext_contexts > 0) { + qemu_fdt_add_subnode(ms->fdt, "/soc/hvx"); + qemu_fdt_setprop_string(ms->fdt, "/soc/hvx", "compatible", + "qcom,hexagon-hvx"); + qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-max-ctxts", + m_cfg->cfgtable.ext_contexts); + qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-vlength", + m_cfg->cfgtable.hvx_vec_log_length); + } +} + +static int32_t fdt_add_hvm_pic_node(HexagonVirtMachineState *vms, + const struct hexagon_machine_config *= m_cfg) +{ + MachineState *ms =3D MACHINE(vms); + int32_t irq_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + + qemu_fdt_setprop_cell(ms->fdt, "/soc", "interrupt-parent", + irq_phandle); + + qemu_fdt_add_subnode(ms->fdt, "/soc/interrupt-controller"); + qemu_fdt_setprop_cell(ms->fdt, "/soc/interrupt-controller", + "#address-cells", 2); + qemu_fdt_setprop_cell(ms->fdt, "/soc/interrupt-controller", + "#interrupt-cells", 2); + qemu_fdt_setprop_string(ms->fdt, "/soc/interrupt-controller", "compati= ble", + "qcom,h2-pic,hvm-pic"); + qemu_fdt_setprop(ms->fdt, "/soc/interrupt-controller", + "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, "/soc/interrupt-controller", "phandle", + irq_phandle); + + sysbus_mmio_map(SYS_BUS_DEVICE(vms->l2vic), 1, + m_cfg->cfgtable.fastl2vic_base << 16); + + return irq_phandle; +} + + +static void fdt_add_gpt_node(HexagonVirtMachineState *vms) +{ + g_autofree char *name =3D NULL; + MachineState *ms =3D MACHINE(vms); + + name =3D g_strdup_printf("/soc/gpt@%" PRIx64, + (int64_t)base_memmap[VIRT_GPT].base); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", + "qcom,h2-timer,hvm-timer"); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", irqmap[VIRT_GPT], = 0); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, + base_memmap[VIRT_GPT].base, + base_memmap[VIRT_GPT].size); +} + +static int32_t fdt_add_clocks(const HexagonVirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + int32_t clk_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + + qemu_fdt_add_subnode(ms->fdt, "/apb-pclk"); + qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "compatible", "fixed-clo= ck"); + qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "#clock-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "clock-frequency", 2400000= 0); + qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "clock-output-names", + "clk24mhz"); + qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "phandle", clk_phandle); + + return clk_phandle; +} + +static void fdt_add_uart(const HexagonVirtMachineState *vms, int uart, + int32_t irq_phandle, int32_t clk_phandle) +{ + char *nodename; + hwaddr base =3D base_memmap[uart].base; + hwaddr size =3D base_memmap[uart].size; + assert(uart =3D=3D 0); + int irq =3D irqmap[VIRT_UART0 + uart]; + const char compat[] =3D "arm,pl011\0arm,primecell"; + const char clocknames[] =3D "uartclk\0apb_pclk"; + MachineState *ms =3D MACHINE(vms); + DeviceState *dev; + SysBusDevice *s; + + dev =3D qdev_new(TYPE_PL011); + s =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + qdev_connect_clock_in(dev, "clk", vms->apb_clk); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, base); + if (vms->l2vic) { + sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->l2vic, irq)); + } + + nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, nodename); + + /* Note that we can't use setprop_string because of the embedded NUL */ + qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compa= t)); + qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, size); + if (vms->l2vic) { + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", + 32 + irq, 0); + qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", + irq_phandle); + } + qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", clk_phandle, + clk_phandle); + qemu_fdt_setprop(ms->fdt, nodename, "clock-names", clocknames, + sizeof(clocknames)); + + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); + qemu_fdt_add_subnode(ms->fdt, "/aliases"); + qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); + + g_free(nodename); +} + +static void fdt_add_cpu_nodes(const HexagonVirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + + /* cpu nodes */ + for (int num =3D ms->smp.cpus - 1; num >=3D 0; num--) { + char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(ms->fdt)); + g_free(nodename); + } +} + + +static void fdt_add_virtio_devices(const HexagonVirtMachineState *vms, + int32_t irq_phandle) +{ + MachineState *ms =3D MACHINE(vms); + /* VirtIO MMIO devices */ + for (int i =3D 0; i < VIRTIO_DEV_COUNT; i++) { + char *nodename; + int irq =3D irqmap[VIRT_MMIO] + i; + size_t size =3D base_memmap[VIRT_MMIO].size; + hwaddr base =3D base_memmap[VIRT_MMIO].base + i * size; + + nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "virtio,m= mio"); + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 1, + size); + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0); + qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", + irq_phandle); + + sysbus_create_simple( + "virtio-mmio", base, + qdev_get_gpio_in(vms->l2vic, irqmap[VIRT_MMIO] + i)); + + g_free(nodename); + } +} + +static void virt_instance_init(Object *obj) +{ + HexagonVirtMachineState *vms =3D HEXAGON_VIRT_MACHINE(obj); + + create_fdt(vms); +} + +void hexagon_load_fdt(const HexagonVirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + hwaddr fdt_addr =3D base_memmap[VIRT_FDT].base; + uint32_t fdtsize =3D vms->fdt_size; + + g_assert(fdtsize <=3D base_memmap[VIRT_FDT].size); + /* copy in the device tree */ + rom_add_blob_fixed_as("fdt", ms->fdt, fdtsize, fdt_addr, + &address_space_memory); + qemu_register_reset_nosnapshotload( + qemu_fdt_randomize_seeds, + rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); +} + +static uint64_t load_kernel(const HexagonVirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + uint64_t entry =3D 0; + if (load_elf_ram_sym(ms->kernel_filename, NULL, NULL, NULL, &entry, NU= LL, + NULL, NULL, 0, EM_HEXAGON, 0, 0, &address_space_m= emory, + false, NULL) > 0) { + return entry; + } + error_report("error loading '%s'", ms->kernel_filename); + exit(1); +} + +static uint64_t load_bios(HexagonVirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + uint64_t bios_addr =3D 0x0; /* Load BIOS at reset vector address 0x0 = */ + int bios_size; + + bios_size =3D load_image_targphys(ms->firmware ?: "", + bios_addr, 64 * 1024, NULL); + if (bios_size < 0) { + error_report("Could not load BIOS '%s'", ms->firmware ?: ""); + exit(1); + } + + return bios_addr; /* Return entry point at address 0x0 */ +} + +static void do_cpu_reset(void *opaque) +{ + HexagonCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + cpu_reset(cs); +} + +static void virt_init(MachineState *ms) +{ + HexagonVirtMachineState *vms =3D HEXAGON_VIRT_MACHINE(ms); + const struct hexagon_machine_config *m_cfg =3D &v68n_1024; + DeviceState *gsregs_dev; + DeviceState *tlb_dev; + DeviceState *cpu0; + int32_t irq_phandle =3D -1; + int32_t clk_phandle; + + qemu_fdt_setprop_string(ms->fdt, "/chosen", "bootargs", ms->kernel_cmd= line); + + vms->sys =3D get_system_memory(); + + /* Create APB clock for peripherals */ + vms->apb_clk =3D clock_new(OBJECT(ms), "apb-pclk"); + clock_set_hz(vms->apb_clk, 24000000); + + memory_region_init_ram(&vms->parent_obj.ram, NULL, "ddr.ram", + ms->ram_size, &error_fatal); + memory_region_add_subregion(vms->sys, 0x0, &vms->parent_obj.ram); + + if (m_cfg->l2tcm_size) { + memory_region_init_ram(&vms->tcm, NULL, "tcm.ram", m_cfg->l2tcm_si= ze, + &error_fatal); + memory_region_add_subregion(vms->sys, m_cfg->cfgtable.l2tcm_base <= < 16, + &vms->tcm); + } + + memory_region_init_rom(&vms->parent_obj.cfgtable_rom, NULL, + "config_table.rom", sizeof(m_cfg->cfgtable), + &error_fatal); + memory_region_add_subregion(vms->sys, m_cfg->cfgbase, + &vms->parent_obj.cfgtable_rom); + fdt_add_hvx(vms, m_cfg); + + gsregs_dev =3D qdev_new(TYPE_HEXAGON_GLOBALREG); + object_property_add_child(OBJECT(ms), "global-regs", OBJECT(gsregs_dev= )); + qdev_prop_set_uint64(gsregs_dev, "config-table-addr", m_cfg->cfgbase); + qdev_prop_set_uint32(gsregs_dev, "dsp-rev", v68_rev); + sysbus_realize_and_unref(SYS_BUS_DEVICE(gsregs_dev), &error_fatal); + + tlb_dev =3D qdev_new(TYPE_HEXAGON_TLB); + object_property_add_child(OBJECT(ms), "tlb", OBJECT(tlb_dev)); + qdev_prop_set_uint32(tlb_dev, "num-entries", + m_cfg->cfgtable.jtlb_size_entries); + sysbus_realize_and_unref(SYS_BUS_DEVICE(tlb_dev), &error_fatal); + + cpu0 =3D NULL; + for (int i =3D 0; i < ms->smp.cpus; i++) { + HexagonCPU *cpu =3D HEXAGON_CPU(object_new(ms->cpu_type)); + qemu_register_reset(do_cpu_reset, cpu); + + if (i =3D=3D 0) { + cpu0 =3D DEVICE(cpu); + if (ms->kernel_filename) { + uint64_t entry =3D load_kernel(vms); + qdev_prop_set_uint32(cpu0, "exec-start-addr", entry); + } else if (ms->firmware) { + uint64_t entry =3D load_bios(vms); + qdev_prop_set_uint32(cpu0, "exec-start-addr", entry); + } + } + qdev_prop_set_uint32(DEVICE(cpu), "htid", i); + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i !=3D 0)); + object_property_set_link(OBJECT(cpu), "global-regs", + OBJECT(gsregs_dev), &error_fatal); + object_property_set_link(OBJECT(cpu), "tlb", + OBJECT(tlb_dev), &error_fatal); + + qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); + } + /* TODO: enable l2vic when l2vic device arrives */ + if (object_class_by_name("l2vic")) { + vms->l2vic =3D sysbus_create_varargs( + "l2vic", m_cfg->l2vic_base, + qdev_get_gpio_in(cpu0, 0), + qdev_get_gpio_in(cpu0, 1), + qdev_get_gpio_in(cpu0, 2), + qdev_get_gpio_in(cpu0, 3), + qdev_get_gpio_in(cpu0, 4), + qdev_get_gpio_in(cpu0, 5), + qdev_get_gpio_in(cpu0, 6), + qdev_get_gpio_in(cpu0, 7), NULL); + + irq_phandle =3D fdt_add_hvm_pic_node(vms, m_cfg); + fdt_add_virtio_devices(vms, irq_phandle); + fdt_add_gpt_node(vms); + } + + fdt_add_cpu_nodes(vms); + clk_phandle =3D fdt_add_clocks(vms); + fdt_add_uart(vms, VIRT_UART0, irq_phandle, clk_phandle); + + rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable, + sizeof(m_cfg->cfgtable), m_cfg->cfgbase, + &address_space_memory); + + hexagon_load_fdt(vms); +} + + +static void virt_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon Virtual Machine"; + mc->init =3D virt_init; + mc->default_cpu_type =3D HEXAGON_CPU_TYPE_NAME("v68"); + mc->default_ram_size =3D 4 * GiB; + mc->max_cpus =3D 8; + mc->default_cpus =3D 8; + mc->is_default =3D false; + mc->default_kernel_irqchip_split =3D false; + mc->block_default_type =3D IF_VIRTIO; + mc->default_boot_order =3D NULL; + mc->no_cdrom =3D 1; + mc->numa_mem_supported =3D false; + mc->default_nic =3D "virtio-mmio-bus"; +} + + +static const TypeInfo virt_machine_types[] =3D { { + .name =3D TYPE_HEXAGON_VIRT_MACHINE, + .parent =3D TYPE_HEXAGON_COMMON_MACHINE, + .instance_size =3D sizeof(HexagonVirtMachineState), + .class_init =3D virt_class_init, + .instance_init =3D virt_instance_init, +} }; + +DEFINE_TYPES(virt_machine_types) diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index cdf7770a305..52065ab3b22 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -2,3 +2,13 @@ config HEX_DSP bool default y depends on HEXAGON + +config HEX_VIRT + bool + default y + depends on HEX_DSP && FDT + select DEVICE_TREE + select VIRTIO_MMIO + select PL011 + select VIRTIO_BLK + select VIRTIO_SCSI diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index f528d2bc4ab..bade3a32921 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -2,5 +2,6 @@ hexagon_ss =3D ss.source_set() hexagon_ss.add(files('hexagon_tlb.c')) hexagon_ss.add(files('hexagon_globalreg.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c')) +hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c')) =20 hw_arch +=3D {'hexagon': hexagon_ss} diff --git a/tests/qemu-iotests/testenv.py b/tests/qemu-iotests/testenv.py index c357e6ebf50..86bcdf7cfad 100644 --- a/tests/qemu-iotests/testenv.py +++ b/tests/qemu-iotests/testenv.py @@ -259,6 +259,7 @@ def __init__(self, source_dir: str, build_dir: str, ('arm', 'virt'), ('aarch64', 'virt'), ('avr', 'mega2560'), + ('hexagon', 'virt'), ('m68k', 'virt'), ('or1k', 'virt'), ('riscv32', 'virt'), --=20 2.34.1 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1780092022387154100 Content-Type: text/plain; charset="utf-8" Add boot-serial-test support for Hexagon architecture using the virt machine. Reviewed-by: Fabiano Rosas Acked-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/qtest/boot-serial-test.c | 8 ++++++++ tests/qtest/meson.build | 2 ++ 2 files changed, 10 insertions(+) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index bcd0a9c50e7..37fee7a91c4 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -142,6 +142,13 @@ static const uint8_t kernel_stm32vldiscovery[] =3D { 0x04, 0x38, 0x01, 0x40 /* 0x40013804 =3D USART1 TXD */ }; =20 +static const uint8_t bios_hexagon[] =3D { + 0x00, 0x40, 0x00, 0x01, /* immext(#0x10000000) */ + 0x00, 0xc0, 0x00, 0x78, /* r0 =3D ##0x10000000 */ + 0x54, 0xc0, 0x00, 0x3c, /* memb(r0+#0) =3D #0x54 Write= 'T' */ + 0xf8, 0xff, 0xff, 0x59 /* jump 0x0 ; Loop back to sta= rt */ +}; + typedef struct testdef { const char *arch; /* Target architecture */ const char *machine; /* Name of the machine */ @@ -194,6 +201,7 @@ static const testdef_t tests[] =3D { { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 }, { "arm", "stm32vldiscovery", "", "T", sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery }, + { "hexagon", "virt", "", "TT", sizeof(bios_hexagon), NULL, bios_hexago= n }, =20 { NULL } }; diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 728dde54b3f..b6d5113b8af 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -293,6 +293,8 @@ qtests_riscv64 =3D ['riscv-csr-test'] + \ config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? ['iommu-riscv-test'] : []) =20 +qtests_hexagon =3D ['boot-serial-test'] + qos_test_ss =3D ss.source_set() qos_test_ss.add( 'ac97-test.c', --=20 2.34.1