From nobody Sat May 30 17:45:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1780076877; cv=none; d=zohomail.com; s=zohoarc; b=GedXPTNy7BHXhQWRS2dwuHzjhKWNrKF1eaDI7Gh7QXN4Eh1tq5A5sYFHy1s9lSRgRMs+I1sAn9h4LEGyUjUABJtI2gW3+l2mCeRl6kqH4HIZsxmXFeF8IDdzyR19yT/66wy12jVbqd7ZZpSAmn8h86Yi5ubhiX/QwYCCrGvmiCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780076877; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3X3Rfvki5PesEhINGZZ1XM7VNTVNvNKE6bftLN8VM48=; b=dNMBN/kwJaDhJ+lZt6MtzkIVZ8TzOy+pjxffkxW7IiUQFduraomfiT6efr+zRjTzQ47YdfVnpG97WBm0hFP4p2eKIgppTvGu2uUGB7A5Mwb55g4WBpRQ7khw7GeHTDez7eYabcYEErUmSi8eSKPyzN1z06K2Chv/A568KmTyuwk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780076877926714.8692738541575; Fri, 29 May 2026 10:47:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wT1IW-00037p-9s; Fri, 29 May 2026 13:47:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wT1IJ-00035r-9F for qemu-devel@nongnu.org; Fri, 29 May 2026 13:46:51 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wT1IE-0001bH-4f for qemu-devel@nongnu.org; Fri, 29 May 2026 13:46:50 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4905529b933so58228445e9.0 for ; Fri, 29 May 2026 10:46:44 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4909c0aa24bsm18668895e9.9.2026.05.29.10.46.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 May 2026 10:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1780076804; x=1780681604; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3X3Rfvki5PesEhINGZZ1XM7VNTVNvNKE6bftLN8VM48=; b=XFMr6yWT1dMaHFtpvflj7bAsJ3DHV0cWkmJEaOHCAVx8e8l+qxq8hWZGZYYXNKpmx1 bksMn09fUQtYilcdWeALeXLjIAUpBKAss96toLqcu87CX7vekkS7Me1h87gppg+UUZ1W /4P1/qGD2uhmtdKqnRwaXse9C5B6iEgVh5oPkFqD/ksSq2tSwyRrA3mFcoR2wp8g03z9 LTHBlp83dQNC2/yREPydIMGZnb7DknS6YoauhKFcFV3FoAjzrnVyrF8XOOnf3e+7rcKK 47A/BowWBih2ni4DNK/h7+qAFstHz3HAYWw66tcV3Bjjse6dB360KypUcJxHUFHrFBZI 6xow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780076804; x=1780681604; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=3X3Rfvki5PesEhINGZZ1XM7VNTVNvNKE6bftLN8VM48=; b=LhmZlUFdfGfFOUGlJ0ouoZUvYk7x9ao7BG2HsykU28Pi2J9CwzPEQaSKqniFfM6kI2 PjgxE9xgP+wbQov9tJJBYjtyvD3s0fcwUnedNiV5QuzB/NAtq6oLtiwG0nwobZIVOOp/ OOse+85kc14oyztecfci9ql0hOYdcnCGx7k9qiXA/EPzZrXztsTClD1r6my4aEycEYKg ddNVESKuNqd8Sl/itrgBEoJEfv9uXm0o/4mmHX/wst3wQen59PvcdJh7TGrQnFjLNiL8 FHPQ0AUhfkoBlluf9BDPdQNnyms2V13IYy4Wfn/kjY7dTaeWxfp5gEUi1h3hBWaXkhJD V5fQ== X-Gm-Message-State: AOJu0YxF1+js+BO/7HKAYB5hr6ctcDqvOpr9Zq6ZSD8GJFZX/gWXpJhC aY3Vwx/dvMGbWt6sLaRBpjD3zBiAm13il34bqdI1aEyeKx6cj+U9vyiFwhLKXwnt1TdAanAjqz8 isvLj X-Gm-Gg: Acq92OHlL9eHjGqONbRROZiDKZjPMBAYpT+C5povONXBOISR+/r3s+KAOHhOW8K9FAZ 2l23d06m9xVA9+l1YsqVrqRvaWDd9XQfs6iX5v1MnbAGP9FUt4hpmSdHP8CyFDTwbrrGzMqYSuU DSpf4FAiAbXSytA+DYgrVMZM1g/Ka6nXMXYMZWBtyNcZUw4k6pwwaV9XDz7IuZ+a0KRx0B33I2X p/0vPKQAmP1ETd0Qz7axUcMM5RDRzmViFQfGyMWXBiNyu0AA5p0o6NAfR5GW3BX21KKgcFAqcaw zk9E74OYErGQq6jUgMeC7uEikhpkbUhI9Juysg0zfRTj1xXmMdXuLcC+55oDmAHpMggS5kgKu4A 6ynhujr/4S+XLU+Vet46B38P1Id6GRGyRrOxWhwVqVIjiBCZpy33ff6ufDMkOJe/YlJiuIaf25r 0Bbvs6fVTVOmCKsrhLgoG0Z6zO0mEwXOWtFSYB1EqN6WvzBdSqzqJ0ZBDGyqq15CXtPN8k6epiA KLmIlJ4ROjqJd6/kAuNnbmPxANzRCtzH4Riw0yGMbY= X-Received: by 2002:a7b:c854:0:b0:490:9699:4428 with SMTP id 5b1f17b1804b1-490a2964057mr6020575e9.26.1780076803783; Fri, 29 May 2026 10:46:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , Pierrick Bouvier , Paolo Bonzini , "Michael S. Tsirkin" , Sergio Lopez , Song Gao , Bibo Mao , Jiaxun Yang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [PATCH 1/5] docs/specs/fw_cfg: Document all architecture register layouts Date: Fri, 29 May 2026 18:46:35 +0100 Message-ID: <20260529174639.451353-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529174639.451353-1-peter.maydell@linaro.org> References: <20260529174639.451353-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1780076879357158500 Content-Type: text/plain; charset="utf-8" We implement the fw_cfg device for more architectures and machines that we let on about in our documentation. Luckily most of the new ones (notably riscv and loongarch) have followed the straightforward layout that the Arm virt board picked. Restructure the documentation to present this as the "standard" layout, followed by the other layouts used by various other boards for historical reasons. This adds PA-RISC, SPARC, PPC and MIPS. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/specs/fw_cfg.rst | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/docs/specs/fw_cfg.rst b/docs/specs/fw_cfg.rst index 31ae31576b..7e2fe0851d 100644 --- a/docs/specs/fw_cfg.rst +++ b/docs/specs/fw_cfg.rst @@ -84,15 +84,35 @@ increasing address order, similar to memcpy(). Register Locations ------------------ =20 +For a memory-mapped fw_cfg device, the standard register layout is: + + * base address : Data Register (64 bit) + * base address + 8 : Selector Register (16 bit) + * base address + 16 : DMA Address Register (64 bit) + +Some architectures or machines have a different layout for historical reas= ons: + x86, x86_64 * Selector Register IOport: 0x510 * Data Register IOport: 0x511 * DMA Address IOport: 0x514 =20 -Arm - * Selector Register address: Base + 8 (2 bytes) - * Data Register address: Base + 0 (8 bytes) - * DMA Address address: Base + 16 (8 bytes) +PA-RISC: + * base address : Selector Register (16 bit) + * base address + 4 : Data Register (8 bit) + +32-bit SPARC, PPC ``g3beige``, ``mac99``, ``prep``: + * base address : Selector Register (16 bit) + * base address + 2 : Data Register (8 bit) + +64-bit SPARC: + * base address : Selector Register (16 bit) + * base address + 1 : Data Register (8 bit) + +MIPS ``loongson3-virt`` machine: + * base address : Selector Register (16 bit) + * base address + 8 : Data Register (64 bit) + =20 ACPI Interface -------------- --=20 2.43.0 From nobody Sat May 30 17:45:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1780076877; cv=none; d=zohomail.com; s=zohoarc; b=MB7oI8vJmlHZc0IE2/yp+PrL20riwZrTLpTTCv0LMd/iPjaonRTyp+l2bmA0woNsq0r+ncCWOhj08Wjk4muO961qeN2HJTG+BeHrDyR2ttUHVKzWYr2RUy++07zRJDK8iO/5CKG2/WvjEmfHonRkhPXgBNVb40f6ycr84U4JUi4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780076877; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ot3n2Oo9vnyF+OptGzLoEZCf8T45qVznpIm4PeIK0AU=; b=MskUw8pSQSqE40Cqe/8pp2M5uWPZXpO/6n0UuzkYbwmIJO2nvyrhdFunEzsMdGhpbUnBN/qd60HSz7RqyVkmtlKmZF0KmVD1t9AsdtXxO8iYCkUHbUHa5EcOkL5M9c3HcIuIbO52s8p4XTXmYIbpabZMVYBSUQH54rEj6UJmfr8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780076877330748.6132271558707; Fri, 29 May 2026 10:47:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wT1IO-000379-G9; Fri, 29 May 2026 13:46:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wT1IJ-000365-Tz for qemu-devel@nongnu.org; Fri, 29 May 2026 13:46:52 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wT1IG-0001bj-79 for qemu-devel@nongnu.org; Fri, 29 May 2026 13:46:51 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4904c1ce4c1so84627225e9.3 for ; Fri, 29 May 2026 10:46:47 -0700 (PDT) Received: from lanath.. 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Tsirkin" , Sergio Lopez , Song Gao , Bibo Mao , Jiaxun Yang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [PATCH 2/5] hw/nvram/fw_cfg: Enforce standard layout for fw_cfg_init_mem_dma() Date: Fri, 29 May 2026 18:46:36 +0100 Message-ID: <20260529174639.451353-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529174639.451353-1-peter.maydell@linaro.org> References: <20260529174639.451353-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1780076879838154100 Content-Type: text/plain; charset="utf-8" Currently fw_cfg_init_mem_dma() allows the caller to customize the register layout, by specifying separately the offsets for control, data and DMA registers, plus the width of the data register. In practice, all the boards using this function specify the same standard layout: "base + 8, base, 8, base + 16", meaning that the data register is 8 bytes and the registers are data at offset 0, control/selector at offset 8, and DMA at offset 16. Allowing every board to be different is gratuitous and useless variation which leads to code in guest OSes having architecture ifdeffery to cope with it. Avoid potentially introducing any more of this by removing all the arguments from fw_cfg_init_mem_dma(), so that the callers only specify the base address. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/virt.c | 2 +- hw/loongarch/fw_cfg.c | 3 +-- hw/nvram/fw_cfg.c | 10 ++++------ hw/riscv/virt.c | 3 +-- include/hw/nvram/fw_cfg.h | 23 ++++++++++++++++++++--- 5 files changed, 27 insertions(+), 14 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b090233893..2cd1c639f5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1941,7 +1941,7 @@ static FWCfgState *create_fw_cfg(const VirtMachineSta= te *vms, AddressSpace *as) FWCfgState *fw_cfg; char *nodename; =20 - fw_cfg =3D fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, as); + fw_cfg =3D fw_cfg_init_mem_dma(base, as); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); =20 nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base); diff --git a/hw/loongarch/fw_cfg.c b/hw/loongarch/fw_cfg.c index d2a79efbf7..4c976ce1e5 100644 --- a/hw/loongarch/fw_cfg.c +++ b/hw/loongarch/fw_cfg.c @@ -23,8 +23,7 @@ FWCfgState *virt_fw_cfg_init(ram_addr_t ram_size, Machine= State *ms) int max_cpus =3D ms->smp.max_cpus; int smp_cpus =3D ms->smp.cpus; =20 - fw_cfg =3D fw_cfg_init_mem_dma(VIRT_FWCFG_BASE + 8, VIRT_FWCFG_BASE, 8, - VIRT_FWCFG_BASE + 16, &address_space_memo= ry); + fw_cfg =3D fw_cfg_init_mem_dma(VIRT_FWCFG_BASE, &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 1d7d835421..59cf92293c 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1088,13 +1088,11 @@ static FWCfgState *fw_cfg_init_mem_internal(hwaddr = ctl_addr, return s; } =20 -FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as) +FWCfgState *fw_cfg_init_mem_dma(hwaddr base_addr, AddressSpace *dma_as) { - assert(dma_addr && dma_as); - return fw_cfg_init_mem_internal(ctl_addr, data_addr, data_width, - dma_addr, dma_as); + assert(dma_as); + return fw_cfg_init_mem_internal(base_addr + 8, base_addr, 8, + base_addr + 16, dma_as); } =20 FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ce64eaaef7..a10840a81d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1266,8 +1266,7 @@ static FWCfgState *create_fw_cfg(const MachineState *= ms, hwaddr base) { FWCfgState *fw_cfg; =20 - fw_cfg =3D fw_cfg_init_mem_dma(base + 8, base, 8, base + 16, - &address_space_memory); + fw_cfg =3D fw_cfg_init_mem_dma(base, &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); =20 return fw_cfg; diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index 56f17a0bdc..45a3747908 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -309,9 +309,26 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32= _t dma_iobase, AddressSpace *dma_as); FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, unsigned data_width); -FWCfgState *fw_cfg_init_mem_dma(hwaddr ctl_addr, - hwaddr data_addr, uint32_t data_width, - hwaddr dma_addr, AddressSpace *dma_as); +/** + * fw_cfg_init_mem_dma: + * @base_addr: address to map the device at + * @as: the device will do DMA to/from this AddressSpace + * + * Create and map a fw_cfg device at the specified base address. + * + * This always creates a device with DMA support, and the "standard" + * register layout: + * - offset 0 : data, 64 bits + * - offset 8 : selector, 16 bits + * - offset 16 : DMA address, 64 bits + * + * The device will be created, configured and realized, and its + * memory regions for the registers will be mapped at the specified + * address. + * + * Returns the device object. + */ +FWCfgState *fw_cfg_init_mem_dma(hwaddr base_addr, AddressSpace *dma_as); =20 FWCfgState *fw_cfg_find(void); bool fw_cfg_dma_enabled(void *opaque); --=20 2.43.0 From nobody Sat May 30 17:45:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Sergio Lopez , Song Gao , Bibo Mao , Jiaxun Yang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [PATCH 3/5] hw/nvram/fw_cfg: Enforce standard layout for x86 fw_cfg I/O ports Date: Fri, 29 May 2026 18:46:37 +0100 Message-ID: <20260529174639.451353-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529174639.451353-1-peter.maydell@linaro.org> References: <20260529174639.451353-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1780076879403158500 Content-Type: text/plain; charset="utf-8" The fw_cfg_init_io_dma() function allows the caller to specify the base port number of the selector/data register and the base port number of the DMA address register separately. No caller actually uses this: they all pass in base + 4 for the dma_iobase. To reduce the risk of unnecessary variation in what different x86 machine types use as their fw_cfg register layout, remove the dma_iobase argument from fw_cfg_init_io_dma(), and have the function always use the same "DMA port is base port + 4" layout. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/i386/fw_cfg.c | 3 +-- hw/i386/microvm.c | 3 +-- hw/i386/pc.c | 3 +-- hw/nvram/fw_cfg.c | 8 ++++---- include/hw/nvram/fw_cfg.h | 17 +++++++++++++++-- 5 files changed, 22 insertions(+), 12 deletions(-) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index 2876490f06..d422302c1c 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -127,8 +127,7 @@ FWCfgState *fw_cfg_arch_create(MachineState *ms, const CPUArchIdList *cpus =3D mc->possible_cpu_arch_ids(ms); int nb_numa_nodes =3D ms->numa_state->num_nodes; =20 - fw_cfg =3D fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, - &address_space_memory); + fw_cfg =3D fw_cfg_init_io_dma(FW_CFG_IO_BASE, &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus); =20 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 779741ec76..e7adab7d2e 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -320,8 +320,7 @@ static void microvm_memory_init(MicrovmMachineState *mm= s) e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); } =20 - fw_cfg =3D fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, - &address_space_memory); + fw_cfg =3D fw_cfg_init_io_dma(FW_CFG_IO_BASE, &address_space_memory); =20 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, machine->smp.cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, machine->smp.max_cpus); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2ecad3c503..f9d8990d1d 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -568,8 +568,7 @@ void xen_load_linux(PCMachineState *pcms) =20 assert(MACHINE(pcms)->kernel_filename !=3D NULL); =20 - fw_cfg =3D fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, - &address_space_memory); + fw_cfg =3D fw_cfg_init_io_dma(FW_CFG_IO_BASE, &address_space_memory); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); rom_set_fw(fw_cfg); =20 diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 59cf92293c..f68191553b 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1019,15 +1019,14 @@ static void fw_cfg_common_realize(DeviceState *dev,= Error **errp) qemu_add_machine_init_done_notifier(&s->machine_ready); } =20 -FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, - AddressSpace *dma_as) +FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, AddressSpace *dma_as) { DeviceState *dev; SysBusDevice *sbd; FWCfgIoState *ios; FWCfgState *s; MemoryRegion *iomem =3D get_system_io(); - bool dma_requested =3D dma_iobase && dma_as; + bool dma_requested =3D dma_as; =20 dev =3D qdev_new(TYPE_FW_CFG_IO); if (!dma_requested) { @@ -1048,7 +1047,8 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint3= 2_t dma_iobase, /* 64 bits for the address field */ s->dma_as =3D dma_as; s->dma_addr =3D 0; - memory_region_add_subregion(iomem, dma_iobase, &s->dma_iomem); + /* DMA register ioport is always at base + 4 */ + memory_region_add_subregion(iomem, iobase + 4, &s->dma_iomem); } =20 return s; diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index 45a3747908..be3fb5f8aa 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -305,8 +305,21 @@ bool fw_cfg_add_file_from_generator(FWCfgState *s, Object *parent, const char *part, const char *filename, Error **errp); =20 -FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, - AddressSpace *dma_as); +/** + * fw_cfg_init_io_dma: + * @iobase: x86 port number which is the base of the fw_cfg port range + * @dma_as: the device will do DMA to/from this AddressSpace + * + * Create a fw_cfg device and map it into the specified I/O port range. + * + * This creates a device with the x86 PC standard port I/O layout: + * - Selector Register IOport: @iobase + * - Data Register IOport: @iobase + 1 + * - DMA Address IOport: @iobase + 4 + * + * Returns the device object. + */ +FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, AddressSpace *dma_as); FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, unsigned data_width); /** --=20 2.43.0 From nobody Sat May 30 17:45:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Sergio Lopez , Song Gao , Bibo Mao , Jiaxun Yang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [PATCH 4/5] hw/nvram/fw_cfg: Remove support for I/O port fw_cfg without DMA Date: Fri, 29 May 2026 18:46:38 +0100 Message-ID: <20260529174639.451353-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529174639.451353-1-peter.maydell@linaro.org> References: <20260529174639.451353-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1780076879350158500 Content-Type: text/plain; charset="utf-8" Currently fw_cfg_init_io_dma() allows the caller to pass a NULL dma_as argument, which causes it to create a fw_cfg without the DMA port or DMA support. None of the callers use this capability: they all pass &address_space_memory. We don't really want to leave the door open for some future x86 machine type which doesn't support DMA for the fw_cfg device, so remove this, and instead make the function assert that it has a non-NULL dma_as argument, like fw_cfg_init_mem_dma(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/nvram/fw_cfg.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index f68191553b..a9d45adb2d 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1026,12 +1026,10 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, Add= ressSpace *dma_as) FWCfgIoState *ios; FWCfgState *s; MemoryRegion *iomem =3D get_system_io(); - bool dma_requested =3D dma_as; + + assert(dma_as); =20 dev =3D qdev_new(TYPE_FW_CFG_IO); - if (!dma_requested) { - qdev_prop_set_bit(dev, "dma_enabled", false); - } =20 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, OBJECT(dev)); --=20 2.43.0 From nobody Sat May 30 17:45:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1780076877; cv=none; d=zohomail.com; s=zohoarc; b=PE/ciUMlh7FKAZF44zcB8NYM8JYuC2X92N8uyUZQa1cpKj4ARgcynbiO2oNzdLay5zPFQeNtO9WF4m9JP34d0dlBYV2qxkyuzE043rXGpmV3bVJnQV9a285GhLd5JeD0AVZugYYCFqpsv6eNw6HEPUSrLS3bynU6xIwXvmnJ6b0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780076877; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3AhGMFct1diYo4gUZrT3/29poPBrHO01q91DGFEApbU=; b=TUUnOkuv1uFczzf6QY/D9KeFaL+DXW8wHX8r9mafw2PL5ybmWJhMkgOq4nwm0KY8uvWBN4Zm9IV1qAc69oFS9t4q46PYSFsodjo4HmwrpOr0ps5FgWwViXhzLhBVj/jJHLE0+QTsUmaZ9u8bjnjDKMMMpblH9Ac5b17WDu6IA+4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780076877306603.4991261001212; Fri, 29 May 2026 10:47:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wT1IS-00037S-5t; Fri, 29 May 2026 13:47:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wT1IN-00036i-Mc for qemu-devel@nongnu.org; Fri, 29 May 2026 13:46:56 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wT1IM-0001fr-6p for qemu-devel@nongnu.org; Fri, 29 May 2026 13:46:55 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-48a3e9862f0so75296375e9.1 for ; Fri, 29 May 2026 10:46:53 -0700 (PDT) Received: from lanath.. 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Tsirkin" , Sergio Lopez , Song Gao , Bibo Mao , Jiaxun Yang , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Subject: [PATCH 5/5] hw/nvram/fw_cfg: Document fw_cfg_init_mem_nodma() Date: Fri, 29 May 2026 18:46:39 +0100 Message-ID: <20260529174639.451353-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260529174639.451353-1-peter.maydell@linaro.org> References: <20260529174639.451353-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1780076879786154100 Content-Type: text/plain; charset="utf-8" The last few commits have added doc comments for all the fw_cfg_init* functions except for fw_cfg_init_mem_nodma(). Fill in the gap by adding a doc comment for it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/nvram/fw_cfg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index be3fb5f8aa..b75858025f 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -320,6 +320,24 @@ bool fw_cfg_add_file_from_generator(FWCfgState *s, * Returns the device object. */ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, AddressSpace *dma_as); + +/** + * fw_cfg_init_mem_nodma: + * + * @ctl_addr: address of the selector register + * @data_addr: address of the data address + * @data_width: width of the data register in bytes + * + * Create a fw_cfg device without DMA support, and map its + * registers at the specified addresses. + * + * Do not use this function in code for a board type that didn't + * already support the fw_cfg device. All new board types should + * include DMA support and use the standard register layout -- use + * fw_cfg_init_mem_dma() instead. + * + * Returns the device object. + */ FWCfgState *fw_cfg_init_mem_nodma(hwaddr ctl_addr, hwaddr data_addr, unsigned data_width); /** --=20 2.43.0