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Thu, 28 May 2026 14:12:13 -0700 (PDT) From: Wadim Mueller To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Peter Maydell , Paolo Bonzini Subject: [RFC PATCH v0 1/2] hw/arm: Add minimal TI K3 AM64x SoC model Date: Thu, 28 May 2026 23:12:09 +0200 Message-ID: <20260528211210.74266-2-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260528211210.74266-1-wafgo01@gmail.com> References: <20260528211210.74266-1-wafgo01@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=wafgo01@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 28 May 2026 18:32:56 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1780007592895154100 Content-Type: text/plain; charset="utf-8" Add an initial model of the TI K3 AM64x SoC family. This first patch covers the bare minimum needed to bring up a Linux kernel on the Cortex-A53 cluster: - Up to two Cortex-A53 CPUs - ARM GIC at the GICSS0 base address - Two MAIN-domain 16550-style UARTs at their real-hardware addresses, backed by the existing TYPE_SERIAL_MM model The CPU count is read directly from the machine's smp.cpus, matching the pattern in hw/arm/fsl-imx8mp.c. EL2/EL3 are only enabled under TCG. Note: real AM64x hardware uses a GIC-500 (GICv3). This initial drop uses the GICv2 model (arm_gic, revision 2) to keep the bring-up mechanically simple; moving to GICv3 is on the follow-up roadmap. Additional SoC blocks (Cortex-M4F MCU, Cortex-R5F cores, mailbox, secure proxy, DMSC/TISCI service, RAT) are intentionally not modelled here and will be added in subsequent patches. Signed-off-by: Wadim Mueller --- MAINTAINERS | 8 ++ hw/arm/Kconfig | 5 + hw/arm/meson.build | 1 + hw/arm/ti-am64x.c | 212 ++++++++++++++++++++++++++++++++++++++ include/hw/arm/ti-am64x.h | 36 +++++++ 5 files changed, 262 insertions(+) create mode 100644 hw/arm/ti-am64x.c create mode 100644 include/hw/arm/ti-am64x.h diff --git a/MAINTAINERS b/MAINTAINERS index 63e9ba521b..95cadde5dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1186,6 +1186,14 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/olimex-stm32-h405.c =20 +TI K3 AM64x +M: Wadim Mueller +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/am64-virt.c +F: hw/arm/ti-am64x.c +F: include/hw/arm/ti-am64x.h + SmartFusion2 M: Subbaraya Sundeep M: Peter Maydell diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7877506384..96cb0f5185 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -626,6 +626,11 @@ config FSL_IMX8MP_EVK depends on TCG select FSL_IMX8MP =20 +config TI_AM64X + bool + select ARM_GIC + select SERIAL_MM + config ARM_SMMUV3 bool =20 diff --git a/hw/arm/meson.build b/hw/arm/meson.build index aeaf654790..89fad790f5 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -84,6 +84,7 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('= armsse.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) +arm_common_ss.add(when: 'CONFIG_TI_AM64X', if_true: files('ti-am64x.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) diff --git a/hw/arm/ti-am64x.c b/hw/arm/ti-am64x.c new file mode 100644 index 0000000000..4026fe23e8 --- /dev/null +++ b/hw/arm/ti-am64x.c @@ -0,0 +1,212 @@ +/* + * TI K3 AM64x SoC + * + * Copyright (c) 2026 CMBlu + * Written by Wadim Mueller + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/arm/bsa.h" +#include "hw/arm/ti-am64x.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "system/kvm.h" +#include "system/system.h" + +#define TI_AM64X_GIC_DIST_ADDR 0x01800000 +#define TI_AM64X_GIC_CPU_ADDR 0x01810000 +#define TI_AM64X_MAIN_UART0_ADDR 0x02800000 +#define TI_AM64X_MAIN_UART1_ADDR 0x02810000 +#define TI_AM64X_MAIN_UART_SIZE 0x100 +#define TI_AM64X_MAIN_UART_REGSHIFT 2 + +/* SPI =3D AM64x TRM GIC INTID - GIC_INTERNAL. */ +#define TI_AM64X_MAIN_UART0_SPI 146 /* MAIN_UART0_USART_IRQ */ +#define TI_AM64X_MAIN_UART1_SPI 147 /* MAIN_UART1_USART_IRQ */ + +static const struct { + hwaddr addr; + unsigned int spi; +} ti_am64x_main_uart_table[TI_AM64X_NUM_MAIN_UARTS] =3D { + { TI_AM64X_MAIN_UART0_ADDR, TI_AM64X_MAIN_UART0_SPI }, + { TI_AM64X_MAIN_UART1_ADDR, TI_AM64X_MAIN_UART1_SPI }, +}; + +static void ti_am64x_init(Object *obj) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + TIAM64xState *s =3D TI_AM64X(obj); + unsigned int num_cpus =3D MIN(ms->smp.cpus, TI_AM64X_NUM_A53_CPUS); + unsigned int i; + + for (i =3D 0; i < num_cpus; i++) { + object_initialize_child(obj, "a53[*]", &s->a53[i], + ARM_CPU_TYPE_NAME("cortex-a53")); + } + + object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); + + for (i =3D 0; i < TI_AM64X_NUM_MAIN_UARTS; i++) { + object_initialize_child(obj, "main-uart[*]", &s->main_uart[i], + TYPE_SERIAL_MM); + } +} + +static bool ti_am64x_realize_cpus(TIAM64xState *s, unsigned int num_cpus, + Error **errp) +{ + unsigned int i; + + for (i =3D 0; i < num_cpus; i++) { + Object *cpuobj =3D OBJECT(&s->a53[i]); + + if (!object_property_set_int(cpuobj, "mp-affinity", i, errp)) { + return false; + } + + if (object_property_find(cpuobj, "has_el3")) { + object_property_set_bool(cpuobj, "has_el3", !kvm_enabled(), + &error_abort); + } + if (object_property_find(cpuobj, "has_el2")) { + object_property_set_bool(cpuobj, "has_el2", !kvm_enabled(), + &error_abort); + } + object_property_set_bool(cpuobj, "start-powered-off", i !=3D 0, + &error_abort); + + if (!qdev_realize(DEVICE(cpuobj), NULL, errp)) { + return false; + } + } + + return true; +} + +static bool ti_am64x_realize_gic(TIAM64xState *s, unsigned int num_cpus, + Error **errp) +{ + DeviceState *gicdev =3D DEVICE(&s->gic); + SysBusDevice *gicsbd =3D SYS_BUS_DEVICE(&s->gic); + unsigned int i; + + qdev_prop_set_uint32(gicdev, "revision", 2); + qdev_prop_set_uint32(gicdev, "num-cpu", num_cpus); + qdev_prop_set_uint32(gicdev, "num-irq", + TI_AM64X_NUM_SPIS + GIC_INTERNAL); + + if (!sysbus_realize(gicsbd, errp)) { + return false; + } + + sysbus_mmio_map(gicsbd, 0, TI_AM64X_GIC_DIST_ADDR); + sysbus_mmio_map(gicsbd, 1, TI_AM64X_GIC_CPU_ADDR); + + for (i =3D 0; i < num_cpus; i++) { + DeviceState *cpudev =3D DEVICE(&s->a53[i]); + int ppi_base =3D TI_AM64X_NUM_SPIS + i * GIC_INTERNAL; + static const int timer_irqs[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + }; + int j; + + for (j =3D 0; j < ARRAY_SIZE(timer_irqs); j++) { + qdev_connect_gpio_out(cpudev, j, + qdev_get_gpio_in(gicdev, + ppi_base + timer_irqs[j= ])); + } + + sysbus_connect_irq(gicsbd, i, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(gicsbd, i + num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicsbd, i + 2 * num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicsbd, i + 3 * num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + } + + return true; +} + +static bool ti_am64x_realize_uarts(TIAM64xState *s, Error **errp) +{ + DeviceState *gicdev =3D DEVICE(&s->gic); + int i; + + for (i =3D 0; i < TI_AM64X_NUM_MAIN_UARTS; i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->main_uart[i]); + + qdev_prop_set_uint8(DEVICE(sbd), "regshift", + TI_AM64X_MAIN_UART_REGSHIFT); + qdev_prop_set_uint32(DEVICE(sbd), "baudbase", 48000000); + qdev_prop_set_chr(DEVICE(sbd), "chardev", serial_hd(i)); + + if (!sysbus_realize(sbd, errp)) { + return false; + } + + sysbus_mmio_map(sbd, 0, ti_am64x_main_uart_table[i].addr); + sysbus_connect_irq(sbd, 0, + qdev_get_gpio_in(gicdev, + ti_am64x_main_uart_table[i].sp= i)); + } + + return true; +} + +static void ti_am64x_realize(DeviceState *dev, Error **errp) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + TIAM64xState *s =3D TI_AM64X(dev); + unsigned int num_cpus =3D ms->smp.cpus; + + if (num_cpus < 1 || num_cpus > TI_AM64X_NUM_A53_CPUS) { + error_setg(errp, + "%s: only between 1 and %u Cortex-A53 CPUs are supporte= d " + "(%u requested)", + TYPE_TI_AM64X, TI_AM64X_NUM_A53_CPUS, num_cpus); + return; + } + + if (!ti_am64x_realize_cpus(s, num_cpus, errp)) { + return; + } + + if (!ti_am64x_realize_gic(s, num_cpus, errp)) { + return; + } + + if (!ti_am64x_realize_uarts(s, errp)) { + return; + } +} + +static void ti_am64x_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ti_am64x_realize; + /* Mapped at fixed locations on the system bus by board code. */ + dc->user_creatable =3D false; + dc->desc =3D "TI K3 AM64x SoC"; +} + +static const TypeInfo ti_am64x_types[] =3D { + { + .name =3D TYPE_TI_AM64X, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TIAM64xState), + .instance_init =3D ti_am64x_init, + .class_init =3D ti_am64x_class_init, + }, +}; + +DEFINE_TYPES(ti_am64x_types) diff --git a/include/hw/arm/ti-am64x.h b/include/hw/arm/ti-am64x.h new file mode 100644 index 0000000000..73f56c3b2a --- /dev/null +++ b/include/hw/arm/ti-am64x.h @@ -0,0 +1,36 @@ +/* + * TI K3 AM64x SoC + * + * Copyright (c) 2026 CMBlu + * Written by Wadim Mueller + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_TI_AM64X_H +#define HW_ARM_TI_AM64X_H + +#include "hw/sysbus.h" +#include "hw/intc/arm_gic.h" +#include "hw/char/serial-mm.h" +#include "qom/object.h" +#include "target/arm/cpu.h" + +#define TYPE_TI_AM64X "ti-am64x" +OBJECT_DECLARE_SIMPLE_TYPE(TIAM64xState, TI_AM64X) + +#define TI_AM64X_NUM_A53_CPUS 2 +#define TI_AM64X_NUM_MAIN_UARTS 2 +#define TI_AM64X_NUM_SPIS 256 /* AM64x GICSS0 supports up to 992 SPIs */ + +struct TIAM64xState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + ARMCPU a53[TI_AM64X_NUM_A53_CPUS]; + GICState gic; + SerialMM main_uart[TI_AM64X_NUM_MAIN_UARTS]; +}; + +#endif /* HW_ARM_TI_AM64X_H */ --=20 2.52.0 From nobody Sat May 30 17:44:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1780007600; cv=none; d=zohomail.com; s=zohoarc; b=WXJY/YHhihjUJM+zo+TzeNcEgkxgbn2a7u1x12V2K4Spz8P1w1NN3Ypd4RShTJ2uODsw+2FsjEmi0B+V/UHQCxJxGnL0S8hOedkII8ZVtLkPQHNGnhKTSNXvCMH6RAG4E95PxV2nLit+IKADkIZEbpwXcqjl8HPhD9Z728yyh4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780007600; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 28 May 2026 14:12:13 -0700 (PDT) From: Wadim Mueller To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Peter Maydell , Paolo Bonzini Subject: [RFC PATCH v0 2/2] hw/arm: Add AM64-virt machine Date: Thu, 28 May 2026 23:12:10 +0200 Message-ID: <20260528211210.74266-3-wafgo01@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260528211210.74266-1-wafgo01@gmail.com> References: <20260528211210.74266-1-wafgo01@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=wafgo01@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 28 May 2026 18:32:56 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1780007602974154100 Content-Type: text/plain; charset="utf-8" Add an "am64-virt" machine that instantiates the TI AM64x SoC model and prepares it to boot a Linux kernel on the Cortex-A53 cluster. The machine wires up DDR at 0x80000000 and uses the standard ARM PSCI SMC conduit for SMP bring-up. It is intentionally minimal: - No built-in device tree; users supply one via -dtb. - No flash, no PCIe, no MCU/R5F cores. The intent is to provide a starting point on top of which the full AM64x platform (mailbox, secure proxy, DMSC/TISCI service, M4F core, R5F cores, dynamic DT generation, ...) can be added in subsequent patches. Signed-off-by: Wadim Mueller --- hw/arm/Kconfig | 7 ++++ hw/arm/am64-virt.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 88 insertions(+) create mode 100644 hw/arm/am64-virt.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 96cb0f5185..e0884a806e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -631,6 +631,13 @@ config TI_AM64X select ARM_GIC select SERIAL_MM =20 +config AM64_VIRT + bool + default y + depends on AARCH64 + depends on TCG + select TI_AM64X + config ARM_SMMUV3 bool =20 diff --git a/hw/arm/am64-virt.c b/hw/arm/am64-virt.c new file mode 100644 index 0000000000..3018773045 --- /dev/null +++ b/hw/arm/am64-virt.c @@ -0,0 +1,80 @@ +/* + * TI K3 AM64-virt machine + * + * Copyright (c) 2026 CMBlu + * Written by Wadim Mueller + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/units.h" +#include "hw/arm/boot.h" +#include "hw/arm/machines-qom.h" +#include "hw/arm/ti-am64x.h" +#include "hw/boards.h" +#include "qemu/error-report.h" +#include "system/address-spaces.h" + +#define AM64_VIRT_DRAM_BASE 0x80000000ULL + +typedef struct AM64VirtMachineState { + MachineState parent_obj; + TIAM64xState soc; + struct arm_boot_info bootinfo; +} AM64VirtMachineState; + +#define TYPE_AM64_VIRT_MACHINE MACHINE_TYPE_NAME("am64-virt") +OBJECT_DECLARE_SIMPLE_TYPE(AM64VirtMachineState, AM64_VIRT_MACHINE) + +static void am64_virt_init(MachineState *machine) +{ + AM64VirtMachineState *ams =3D AM64_VIRT_MACHINE(machine); + MemoryRegion *sysmem =3D get_system_memory(); + + if (machine->ram_size > 2 * GiB) { + error_report("am64-virt: maximum supported RAM size is 2 GiB"); + exit(1); + } + + object_initialize_child(OBJECT(machine), "soc", &ams->soc, TYPE_TI_AM6= 4X); + sysbus_realize_and_unref(SYS_BUS_DEVICE(&ams->soc), &error_fatal); + + memory_region_add_subregion(sysmem, AM64_VIRT_DRAM_BASE, machine->ram); + + ams->bootinfo.ram_size =3D machine->ram_size; + ams->bootinfo.loader_start =3D AM64_VIRT_DRAM_BASE; + ams->bootinfo.psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + ams->bootinfo.board_id =3D -1; + arm_load_kernel(&ams->soc.a53[0], machine, &ams->bootinfo); +} + +static void am64_virt_machine_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "TI K3 AM64x virt machine"; + mc->init =3D am64_virt_init; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"); + mc->default_ram_id =3D "am64-virt.ram"; + mc->default_ram_size =3D 1 * GiB; + mc->default_cpus =3D TI_AM64X_NUM_A53_CPUS; + mc->max_cpus =3D TI_AM64X_NUM_A53_CPUS; + mc->min_cpus =3D 1; +} + +static const TypeInfo am64_virt_machine_info =3D { + .name =3D TYPE_AM64_VIRT_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(AM64VirtMachineState), + .class_init =3D am64_virt_machine_class_init, + .interfaces =3D arm_aarch64_machine_interfaces, +}; + +static void am64_virt_machine_register_types(void) +{ + type_register_static(&am64_virt_machine_info); +} + +type_init(am64_virt_machine_register_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 89fad790f5..faa00741c3 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -85,6 +85,7 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files= ('fsl-imx7.c', 'mcimx7d arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) arm_common_ss.add(when: 'CONFIG_TI_AM64X', if_true: files('ti-am64x.c')) +arm_common_ss.add(when: 'CONFIG_AM64_VIRT', if_true: files('am64-virt.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) --=20 2.52.0