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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/3] target/microblaze: Convert to translate_for_debug Date: Thu, 28 May 2026 17:14:48 +0100 Message-ID: <20260528161450.3564396-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528161450.3564396-1-peter.maydell@linaro.org> References: <20260528161450.3564396-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779984952783154100 Content-Type: text/plain; charset="utf-8" The get_phys_addr_attrs_debug method of SysemuCPUOps is used only by x86 and microblaze. Convert microblaze to the newer translate_for_debug method, as a step towards being able to remove get_phys_addr_attrs_debug. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 2 +- target/microblaze/cpu.h | 4 ++-- target/microblaze/helper.c | 16 +++++++++------- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c6a456dd5e..a97c92a7b6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -428,7 +428,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 static const struct SysemuCPUOps mb_sysemu_ops =3D { .has_work =3D mb_cpu_has_work, - .get_phys_addr_attrs_debug =3D mb_cpu_get_phys_addr_attrs_debug, + .translate_for_debug =3D mb_cpu_translate_for_debug, }; #endif =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 068da60529..b9602f72b9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -369,8 +369,8 @@ struct MicroBlazeCPUClass { #ifndef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); -hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); +bool mb_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result); #endif /* !CONFIG_USER_ONLY */ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index f81c4f625b..676f9de8f6 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -280,8 +280,8 @@ void mb_cpu_do_interrupt(CPUState *cs) } } =20 -hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr, - MemTxAttrs *attrs) +bool mb_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); hwaddr paddr =3D 0; @@ -289,10 +289,6 @@ hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, int mmu_idx =3D cpu_mmu_index(cs, false); unsigned int hit; =20 - /* Caller doesn't initialize */ - *attrs =3D (MemTxAttrs) {}; - attrs->secure =3D mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); - if (mmu_idx !=3D MMU_NOMMU_IDX) { hit =3D mmu_translate(cpu, &lu, addr, 0, 0); if (hit) { @@ -303,7 +299,13 @@ hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, paddr =3D addr; } =20 - return paddr; + *result =3D (TranslateForDebugResult) { + .physaddr =3D paddr, + .lg_page_size =3D TARGET_PAGE_BITS, + .attrs.secure =3D mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD), + .attrs.debug =3D 1, + }; + return true; } =20 bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) --=20 2.43.0 From nobody Sat May 30 17:35:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/3] target/i386: Convert to translate_for_debug Date: Thu, 28 May 2026 17:14:49 +0100 Message-ID: <20260528161450.3564396-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528161450.3564396-1-peter.maydell@linaro.org> References: <20260528161450.3564396-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779984954678154100 The get_phys_addr_attrs_debug method of SysemuCPUOps is used only by x86 and microblaze. Convert x86 to the newer translate_for_debug method, as a step towards being able to remove get_phys_addr_attrs_debug. The new API allows us to tell the caller the actual size of the mapping via lg_page_size, so we do that, although no caller will care since it's always at least TARGET_PAGE_BITS. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 4 ++-- target/i386/helper.c | 31 +++++++++++++++++-------------- target/i386/whpx/whpx-all.c | 2 +- 4 files changed, 21 insertions(+), 18 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7248720a0e..8929a75c7c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10877,7 +10877,7 @@ static const struct SysemuCPUOps i386_sysemu_ops = =3D { .has_work =3D x86_cpu_has_work, .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_paging_enabled =3D x86_cpu_get_paging_enabled, - .get_phys_addr_attrs_debug =3D x86_cpu_get_phys_addr_attrs_debug, + .translate_for_debug =3D x86_cpu_translate_for_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index bdd4fff89d..67e2ecf325 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2581,8 +2581,8 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env); #ifndef CONFIG_USER_ONLY int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); =20 -hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); +bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr, + TranslateForDebugResult *result); int cpu_get_pic_interrupt(CPUX86State *s); =20 /* MS-DOS compatibility mode FPU exception support */ diff --git a/target/i386/helper.c b/target/i386/helper.c index 8cc73f619a..30f1fa41b3 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -252,8 +252,8 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_= cr4) } =20 #if !defined(CONFIG_USER_ONLY) -hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr, - MemTxAttrs *attrs) +bool x86_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; @@ -263,8 +263,6 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, uint32_t page_offset; int page_size; =20 - *attrs =3D cpu_get_mem_attrs(env); - a20_mask =3D x86_get_a20_mask(env); if (!(env->cr[0] & CR0_PG_MASK)) { pte =3D addr & a20_mask; @@ -283,7 +281,7 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, /* test virtual address sign extension */ sext =3D la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47; if (sext !=3D 0 && sext !=3D -1) { - return -1; + return false; } =20 if (la57) { @@ -291,7 +289,7 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, (((addr >> 48) & 0x1ff) << 3)) & a20_mask; pml5e =3D x86_ldq_phys(cs, pml5e_addr); if (!(pml5e & PG_PRESENT_MASK)) { - return -1; + return false; } } else { pml5e =3D env->cr[3]; @@ -301,13 +299,13 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs= , vaddr addr, (((addr >> 39) & 0x1ff) << 3)) & a20_mask; pml4e =3D x86_ldq_phys(cs, pml4e_addr); if (!(pml4e & PG_PRESENT_MASK)) { - return -1; + return false; } pdpe_addr =3D ((pml4e & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff) << 3)) & a20_mask; pdpe =3D x86_ldq_phys(cs, pdpe_addr); if (!(pdpe & PG_PRESENT_MASK)) { - return -1; + return false; } if (pdpe & PG_PSE_MASK) { page_size =3D 1024 * 1024 * 1024; @@ -322,14 +320,14 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs= , vaddr addr, a20_mask; pdpe =3D x86_ldq_phys(cs, pdpe_addr); if (!(pdpe & PG_PRESENT_MASK)) - return -1; + return false; } =20 pde_addr =3D ((pdpe & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << 3)) & a20_mask; pde =3D x86_ldq_phys(cs, pde_addr); if (!(pde & PG_PRESENT_MASK)) { - return -1; + return false; } if (pde & PG_PSE_MASK) { /* 2 MB page */ @@ -343,7 +341,7 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, pte =3D x86_ldq_phys(cs, pte_addr); } if (!(pte & PG_PRESENT_MASK)) { - return -1; + return false; } } else { uint32_t pde; @@ -352,7 +350,7 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, pde_addr =3D ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a2= 0_mask; pde =3D x86_ldl_phys(cs, pde_addr); if (!(pde & PG_PRESENT_MASK)) - return -1; + return false; if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { pte =3D pde | ((pde & 0x1fe000LL) << (32 - 13)); page_size =3D 4096 * 1024; @@ -361,7 +359,7 @@ hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, = vaddr addr, pte_addr =3D ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_m= ask; pte =3D x86_ldl_phys(cs, pte_addr); if (!(pte & PG_PRESENT_MASK)) { - return -1; + return false; } page_size =3D 4096; } @@ -373,7 +371,12 @@ out: #endif pte &=3D PG_ADDRESS_MASK & ~(page_size - 1); page_offset =3D addr & (page_size - 1); - return pte | page_offset; + + result->attrs =3D cpu_get_mem_attrs(env); + result->attrs.debug =3D 1; + result->physaddr =3D pte | page_offset; + result->lg_page_size =3D ctz64(page_size); + return true; } =20 typedef struct MCEInjectionParams { diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 7943adb93f..e626acef2f 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -247,7 +247,7 @@ struct whpx_register_set { * e. Let the affected CPU run in the exclusive mode. * f. Restore the original handler and the exception exit bitmap. * Note that handling all corner cases related to IDT/GDT is harder - * than it may seem. See x86_cpu_get_phys_addr_attrs_debug() for a + * than it may seem. See x86_cpu_translate_for_debug() for a * rough idea. * * 3. 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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/3] hw/core: Remove SysemuCPUOps::get_phys_addr_attrs_debug Date: Thu, 28 May 2026 17:14:50 +0100 Message-ID: <20260528161450.3564396-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260528161450.3564396-1-peter.maydell@linaro.org> References: <20260528161450.3564396-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779984954621154100 No targets use the SysemuCPUOps::get_phys_addr_attrs_debug method any more, so we can remove it, together with the handling of it in cpu_translate_for_debug(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-system.c | 11 ++--------- include/hw/core/sysemu-cpu-ops.h | 14 -------------- 2 files changed, 2 insertions(+), 23 deletions(-) diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 16f048c956..14eb4ed87f 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -63,15 +63,8 @@ bool cpu_translate_for_debug(CPUState *cpu, vaddr addr, return cpu->cc->sysemu_ops->translate_for_debug(cpu, addr, result); } else { /* Fallbacks for CPUs which don't implement translate_for_debug */ - if (cpu->cc->sysemu_ops->get_phys_addr_attrs_debug) { - result->physaddr =3D - cpu->cc->sysemu_ops->get_phys_addr_attrs_debug(cpu, addr, - &result->at= trs); - } else { - result->physaddr - =3D cpu->cc->sysemu_ops->get_phys_addr_debug(cpu, addr); - result->attrs =3D MEMTXATTRS_UNSPECIFIED; - } + result->physaddr =3D cpu->cc->sysemu_ops->get_phys_addr_debug(cpu,= addr); + result->attrs =3D MEMTXATTRS_UNSPECIFIED; if (result->physaddr =3D=3D -1) { return false; } diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 441901fae8..8be6a84bd5 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -39,20 +39,6 @@ typedef struct SysemuCPUOps { * for a complete target page or they use memory attributes). */ hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr); - /** - * @get_phys_addr_attrs_debug: Callback for obtaining a physical addre= ss - * and the associated memory transaction attributes to use for t= he - * access. - * - * This must be able to handle a non-page-aligned address, and will - * return the physical address corresponding to that address. - * - * CPUs should prefer to implement translate_for_debug instead of - * this (and must do so if their translations are not always valid - * for a complete target page). - */ - hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); /** * @translate_for_debug: Callback for translating a virtual address in= to * a physical address for debug purposes. --=20 2.43.0