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Thu, 28 May 2026 08:34:55 -0700 (PDT) From: Jim MacArthur Date: Thu, 28 May 2026 16:34:36 +0100 Subject: [PATCH 1/5] target/arm/cpu-features.h: x-rme now means GPC3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-jmac-gpc3b-v1-1-d34c46c5069f@linaro.org> References: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> In-Reply-To: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779982543279158500 Signed-off-by: Jim MacArthur --- target/arm/cpu-features.h | 5 +++++ target/arm/tcg/cpu64.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index f9c979d20b..6819d5f6a7 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1138,6 +1138,11 @@ static inline bool isar_feature_aa64_rme_gpc2(const = ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >=3D 2; } =20 +static inline bool isar_feature_aa64_rme_gpc3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) >=3D 3; +} + static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) !=3D 0; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index a377f67b9c..53f0ea0404 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -159,8 +159,8 @@ static void cpu_arm_set_rme(Object *obj, bool value, Er= ror **errp) { ARMCPU *cpu =3D ARM_CPU(obj); =20 - /* Enable FEAT_RME_GPC2 */ - FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value ? 2 : 0); + /* Enable FEAT_RME_GPC3 */ + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value ? 3 : 0); } =20 static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, --=20 2.43.0 From nobody Sat May 30 17:33:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 28 May 2026 08:34:56 -0700 (PDT) From: Jim MacArthur Date: Thu, 28 May 2026 16:34:37 +0100 Subject: [PATCH 2/5] target/arm: Setup new registers for GPC3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-jmac-gpc3b-v1-2-d34c46c5069f@linaro.org> References: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> In-Reply-To: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779982530505154100 Adds GPCBW_EL3. A custom write function is necessary to flush TLBs when this register is written. Also allows write to the GPCBW bit of GPCCR_EL3. Signed-off-by: Jim MacArthur --- target/arm/cpu.h | 7 +++++++ target/arm/helper.c | 19 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 85552b573c..9944dc9727 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -546,6 +546,7 @@ typedef struct CPUArchState { /* RME registers */ uint64_t gpccr_el3; uint64_t gptbr_el3; + uint64_t gpcbw_el3; uint64_t mfar_el3; =20 /* NV2 register */ @@ -1228,6 +1229,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu); typedef struct ARMGranuleProtectionConfig { /* GPCCR_EL3 */ uint64_t gpccr; + /* GPCBW_EL3 */ + uint64_t gpcbw; /* GPTBR_EL3 */ uint64_t gptbr; /* ID_AA64MMFR0_EL1.PARange */ @@ -2098,6 +2101,10 @@ FIELD(GPCCR, NA6, 27, 1) FIELD(GPCCR, NA7, 28, 1) FIELD(GPCCR, GPCBW, 29, 1) =20 +FIELD(GPCBW, BWSIZE, 37, 2) +FIELD(GPCBW, BWSTRIDE, 32, 5) +FIELD(GPCBW, BWADDR, 0, 25) + FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) diff --git a/target/arm/helper.c b/target/arm/helper.c index 34487eeaa3..12453fe39f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4990,6 +4990,10 @@ static void gpccr_write(CPUARMState *env, const ARMC= PRegInfo *ri, R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | R_GPCCR_RLPAD_= MASK; } =20 + if (cpu_isar_feature(aa64_rme_gpc3 , env_archcpu(env))) { + rw_mask |=3D R_GPCCR_GPCBW_MASK; + } + env->cp15.gpccr_el3 =3D (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw= _mask); } =20 @@ -4999,11 +5003,26 @@ static void gpccr_reset(CPUARMState *env, const ARM= CPRegInfo *ri) env_archcpu(env)->reset_l0gptsz); } =20 +static void gpcbw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t rw_mask =3D R_GPCBW_BWADDR_MASK | R_GPCBW_BWSTRIDE_MASK | + R_GPCBW_BWSIZE_MASK; + ARMCPU *cpu =3D env_archcpu(env); + tlb_flush_by_mmuidx(CPU(cpu), alle1_tlbmask(env)); + + env->cp15.gpcbw_el3 =3D (value & rw_mask) | (env->cp15.gpcbw_el3 & ~rw= _mask); +} + static const ARMCPRegInfo rme_reginfo[] =3D { { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name =3D "GPCBW_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 5, + .access =3D PL3_RW, .writefn =3D gpcbw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gpcbw_el3) }, { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, --=20 2.43.0 From nobody Sat May 30 17:33:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 28 May 2026 08:34:56 -0700 (PDT) From: Jim MacArthur Date: Thu, 28 May 2026 16:34:38 +0100 Subject: [PATCH 3/5] target/arm/ptw.c: Add Granule Bypass Windows MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-jmac-gpc3b-v1-3-d34c46c5069f@linaro.org> References: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> In-Reply-To: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779982551243158500 Signed-off-by: Jim MacArthur --- target/arm/ptw.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0a5201763a..46568cc5cb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -341,11 +341,21 @@ bool arm_granule_protection_check(ARMGranuleProtectio= nConfig config, .space =3D ARMSS_Root, }; const uint64_t gpccr =3D config.gpccr; + const uint64_t gpcbw =3D config.gpcbw; unsigned pps, pgs, l0gptsz, level =3D 0; uint64_t tableaddr, pps_mask, align, entry, index; MemTxResult result; int gpi; =20 + const uint64_t BW_ADDR_SHIFT =3D 30; + const uint64_t BW_SIZE_SHIFT =3D 30; + const uint64_t BW_STRIDE_SHIFT =3D 40; + + uint64_t bw_start =3D FIELD_EX64(gpcbw, GPCBW, BWADDR) << BW_ADDR_SHIF= T; + uint64_t bw_size_field =3D FIELD_EX64(gpcbw, GPCBW, BWSIZE); + uint64_t bw_stride_mask =3D -1L << (FIELD_EX64(gpcbw, GPCBW, BWSTRIDE)= + + BW_STRIDE_SHIFT + 1); + /* * We assume Granule Protection Check is enabled when * calling this function (GPCCR.GPC =3D=3D 1). @@ -383,6 +393,28 @@ bool arm_granule_protection_check(ARMGranuleProtection= Config config, goto fault_walk; } =20 + /* At this point, GPCCR_EL3 is valid */ + + /* + * GPC Priority 1 (R_GMGRR): + * If GPCCR_EL3.GPCBW is 1 and the configuration GPCBW + * is invalid, the access fails as GPT walk fault at level 0. + */ + if (FIELD_EX64(gpccr, GPCCR, GPCBW)) { + /* + * GPCBW is invalid if the base address is: + * not aligned to the size programmed in BWSIZE, or + * greater than or equal to the stride value configured by BWSTRID= E. + */ + uint64_t bw_size_mask =3D -1L << (bw_size_field + 31); + if (bw_start & bw_size_mask) { + goto fault_walk; + } + if (bw_start & bw_stride_mask) { + goto fault_walk; + } + } + switch (FIELD_EX64(gpccr, GPCCR, PGS)) { case 0b00: /* 4KB */ pgs =3D 12; @@ -431,6 +463,23 @@ bool arm_granule_protection_check(ARMGranuleProtection= Config config, goto fault_fail; } =20 + /* + * Bypass window check. + * I_JJLRM: Granule Protection Table (GPT) lookups can be skipped + * in portions of the memory map by using GPC bypass windows. + * I_XNHTX: The GPC bypass window check (...) is performed + * immediately after priority 3. + */ + if (FIELD_EX64(gpccr, GPCCR, GPCBW)) { + uint64_t bw_size =3D 1 << (bw_size_field + BW_SIZE_SHIFT); + uint64_t effective_address =3D paddress & bw_stride_mask; + + if (effective_address >=3D bw_start && + effective_address < (bw_start + bw_size)) { + return true; + } + } + /* GPC Priority 4: the base address of GPTBR_EL3 exceeds PPS. */ tableaddr =3D config.gptbr << 12; if (tableaddr & ~pps_mask) { @@ -3817,6 +3866,7 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Tra= nslate *ptw, }; struct ARMGranuleProtectionConfig config =3D { .gpccr =3D env->cp15.gpccr_el3, + .gpcbw =3D env->cp15.gpcbw_el3, .gptbr =3D env->cp15.gptbr_el3, .parange =3D FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANG= E), .support_sel2 =3D cpu_isar_feature(aa64_sel2, cpu), --=20 2.43.0 From nobody Sat May 30 17:33:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779982560; cv=none; d=zohomail.com; s=zohoarc; b=G0f8yU1qiCwgRYxXdCVqHinzBgRbGEH6WH2aBwyHk2DOWIA1Qh8yesP35VSHho5vH6LmEN4ywOO57kHUQlcMJHqpMPfa6S5XDR06m/m2WZHIxJG3DpFqFU/six/25Ygy71sOD8kUWeh2x7xQBbWbdURUqxb2KU+dw9Vppcirbwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779982560; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 28 May 2026 08:34:56 -0700 (PDT) From: Jim MacArthur Date: Thu, 28 May 2026 16:34:39 +0100 Subject: [PATCH 4/5] tests/tcg/aarch64/system: Alternative boot object for exception logging MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-jmac-gpc3b-v1-4-d34c46c5069f@linaro.org> References: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> In-Reply-To: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779982563092154100 This allows us to record information about exceptions using a small area of memory, and continue with the test so it can verify exceptions have been taken where expected. ALT_VECTOR_TABLE is added to switch this on, and altboot.o is built from boot.S with this flag. Since boot.o is created for multiple test targets, we have to build a separate object and selectively link this new altboot.o into particular test binaries. Signed-off-by: Jim MacArthur --- tests/tcg/aarch64/Makefile.softmmu-target | 11 ++++-- tests/tcg/aarch64/system/boot.S | 62 +++++++++++++++++++++++++++= ++++ tests/tcg/aarch64/system/boot.h | 14 +++++++ 3 files changed, 83 insertions(+), 4 deletions(-) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index f7a7d2b800..47b32968fb 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -25,7 +25,7 @@ LDFLAGS=3D-Wl,-T$(LINK_SCRIPT) TESTS+=3D$(AARCH64_TESTS) $(MULTIARCH_TESTS) EXTRA_RUNS+=3D$(MULTIARCH_RUNS) CFLAGS+=3D-nostdlib -ggdb -O0 $(MINILIB_INC) -LDFLAGS+=3D-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc +LDFLAGS+=3D-static -nostdlib $(MINILIB_OBJS) -lgcc =20 config-cc.mak: Makefile $(quiet-@)( \ @@ -36,17 +36,20 @@ config-cc.mak: Makefile # building head blobs .PRECIOUS: $(CRT_OBJS) =20 +altboot.o: $(CRT_PATH)/boot.S + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -DALT_VECTOR_TABLE -x assembler-with-cpp = -Wa,--noexecstack -c $< -o $@ + %.o: $(CRT_PATH)/%.S $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -Wa,--noexecstack -= c $< -o $@ =20 # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o =20 memory: CFLAGS+=3D-DCHECK_UNALIGNED=3D1 =20 memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o =20 memory-sve: CFLAGS+=3D-DCHECK_UNALIGNED=3D1 -march=3Darmv8.1-a+sve -O3 =20 @@ -107,7 +110,7 @@ QEMU_MTE_ENABLED_MACHINE=3D-M virt,mte=3Don -cpu max -d= isplay none QEMU_OPTS_WITH_MTE_ON =3D $(QEMU_MTE_ENABLED_MACHINE) $(QEMU_BASE_ARGS) -k= ernel mte: CFLAGS+=3D-march=3Darmv8.5-a+memtag mte: mte.S $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o =20 run-mte: QEMU_OPTS=3D$(QEMU_OPTS_WITH_MTE_ON) run-mte: mte diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boo= t.S index 8bfa4e4efc..225ae76388 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -60,6 +60,40 @@ curr_sp0_irq: curr_sp0_fiq: curr_sp0_serror: curr_spx_sync: +#ifdef ALT_VECTOR_TABLE + sub sp, sp, #16 + stp x0, x1, [sp, #0] + mrs x0, ESR_EL3 + lsr x0, x0, #26 + and x0, x0, #0x3f + cmp x0, #37 + beq data_fault + cmp x0, #30 + beq gpc_fault + b generic_exception + +data_fault: + mrs x0, FAR_EL3 + adrp x1, exception_log + str x0, [x1] + ldr x0, =3D0x1001 + str x0, [x1, #8] + b skip_return +gpc_fault: + mrs x0, FAR_EL3 + adrp x1, exception_log + str x0, [x1] + ldr x0, =3D0x1002 + str x0, [x1, #8] + /* Fall through */ +skip_return: + mrs x0, ELR_EL3 + add x0, x0, #4 /* Skip faulting instruction */ + msr ELR_EL3, x0 + ldp x0, x1, [sp, #0] + add sp, sp, #16 + eret +#endif curr_spx_irq: curr_spx_fiq: curr_spx_serror: @@ -71,6 +105,7 @@ lower_a32_sync: lower_a32_irq: lower_a32_fiq: lower_a32_serror: +generic_exception: adr x1, .unexp_excp exit_msg: mov x0, SYS_WRITE0 @@ -404,6 +439,33 @@ ttb_stage2: .space 4096, 0 =20 .align 12 + .global realms_gpt0 + /* GPT stage 0 table */ +realms_gpt0: + .space 4096, 0 + .align 17 + .global realms_gpt1 + /* GPT stage 1 table, initialised to all 0xFF (full access) */ +realms_gpt1: + .space 524288, 0xFF +#ifdef ALT_VECTOR_TABLE + .align 8 + .global exception_log + .global exception_fault_address + .global exception_type_code +exception_log: + /* + *These fields record details of the last exception, if ALT_VECTOR_TABLE + * is defined. + */ +exception_fault_address: + /* The contents of FAR_EL3 when an exception is taken. */ + .space 8, 0 +exception_type_code: + /* A generic code indicating what type of exception occurred. */ + .space 8, 0 +#endif + .align 12 system_stack: .space 4096, 0 system_stack_end: diff --git a/tests/tcg/aarch64/system/boot.h b/tests/tcg/aarch64/system/boo= t.h new file mode 100644 index 0000000000..cb9ab6c1b9 --- /dev/null +++ b/tests/tcg/aarch64/system/boot.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * + * + * Copyright (c) 2026 Linaro Ltd + * + */ + + +/* Global variables exported in boot.S */ +extern volatile uint64_t exception_fault_address; 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Thu, 28 May 2026 08:34:57 -0700 (PDT) From: Jim MacArthur Date: Thu, 28 May 2026 16:34:40 +0100 Subject: [PATCH 5/5] tests/tcg/aarch64/system/gpc-test.c: Basic test for granule protection check MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260528-jmac-gpc3b-v1-5-d34c46c5069f@linaro.org> References: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> In-Reply-To: <20260528-jmac-gpc3b-v1-0-d34c46c5069f@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779982554893154100 * Sets up granule protection tables * Enables GPC and bypass windows * Performs memory accesses in the protected region to check for allowed and disallowed reads. Signed-off-by: Jim MacArthur --- tests/tcg/aarch64/Makefile.softmmu-target | 11 +- tests/tcg/aarch64/system/gpc-test.c | 160 ++++++++++++++++++++++++++= ++++ 2 files changed, 170 insertions(+), 1 deletion(-) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index 47b32968fb..d76ca52e63 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -53,7 +53,10 @@ memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILI= B_OBJS) =20 memory-sve: CFLAGS+=3D-DCHECK_UNALIGNED=3D1 -march=3Darmv8.1-a+sve -O3 =20 -TESTS+=3Dmemory-sve +gpc-test: gpc-test.c $(LINK_SCRIPT) altboot.o $(MINILIB_OBJS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) altboot.o + +TESTS+=3Dmemory-sve gpc-test =20 # Running QEMU_BASE_MACHINE=3D-M virt -cpu max -display none @@ -74,6 +77,12 @@ QEMU_EL2_MACHINE=3D-machine virt,virtualization=3Don,gic= -version=3D2 -cpu cortex-a57 - QEMU_EL2_BASE_ARGS=3D-semihosting-config enable=3Don,target=3Dnative,chard= ev=3Doutput,arg=3D"2" run-vtimer: QEMU_OPTS=3D$(QEMU_EL2_MACHINE) $(QEMU_EL2_BASE_ARGS) -kernel =20 +# gpc tests need EL3 and RME +QEMU_EL3_MACHINE=3D-machine virt,virtualization=3Don,secure=3Don,gic-versi= on=3D3 -cpu max,x-rme=3Don +QEMU_EL3_BASE_ARGS=3D-semihosting-config enable=3Don,target=3Dnative,chard= ev=3Doutput,arg=3D"3" +run-gpc-test: QEMU_OPTS=3D$(QEMU_EL3_MACHINE) $(QEMU_EL3_BASE_ARGS) -kern= el +run-gpc3-test: QEMU_OPTS=3D$(QEMU_EL3_MACHINE) $(QEMU_EL3_BASE_ARGS) -kern= el + # Simple Record/Replay Test .PHONY: memory-record run-memory-record: memory-record memory diff --git a/tests/tcg/aarch64/system/gpc-test.c b/tests/tcg/aarch64/system= /gpc-test.c new file mode 100644 index 0000000000..06b25d2787 --- /dev/null +++ b/tests/tcg/aarch64/system/gpc-test.c @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * + * + * Copyright (c) 2026 Linaro Ltd + * + */ + +#include +#include +#include +#include "boot.h" + +#define ID_AA64PFR0_EL1 "S3_0_C0_C4_0" + +#define GPTBR_EL3 "S3_6_C2_C1_4" +#define GPCBW_EL3 "S3_6_C2_C1_5" +#define GPCCR_EL3 "S3_6_C2_C1_6" +#define VBAR_EL3 "S3_6_C12_C0_0" + +#define get_sys_reg(register_name, dest) \ + asm("mrs %[reg], " register_name "\n\t" : [reg] "=3Dr" (dest)) +#define set_sys_reg(register_name, value) \ + asm("msr " register_name ", %[reg]\n\r" : : [reg] "r" (value)) + +const uint32_t gpc_granule_size =3D 4096; +const uint32_t gpis_per_64_bits =3D 16; + +int main(uint64_t sp) +{ + uint64_t out; + uint64_t pfr0; + uint64_t gpt_base; + uint64_t rme_status; + uint64_t currentel_raw; + uint64_t currentel; + uint64_t gpcbw; + uint64_t gpt_table0_addr =3D (uint64_t) realms_gpt0; + uint64_t gpt_table1_addr =3D (uint64_t) realms_gpt1; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask =3D (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in =3D feature_mask; + + get_sys_reg("CurrentEL", currentel_raw); + currentel =3D (currentel_raw >> 2) & 0x3; + + if (currentel < 3) { + ml_printf("FAIL: Test must be run at EL3 (it is %d)\n", currentel); + return 1; + } + + get_sys_reg(ID_AA64PFR0_EL1, pfr0); + + /* rme_status is 1 for RME, 2 for RME + GPC2, 3 for RME+GPC3 */ + rme_status =3D (pfr0 >> 52) & 0xF; + ml_printf("RME is %ld\n", rme_status); + if (rme_status < 1) { + ml_printf("SKIP: System does not support GPC (RME=3D%ld)\n", rme_s= tatus); + return 0; + } + + /* Configure the level 0 table for the first 4GB of memory */ + realms_gpt0[0] =3D gpt_table1_addr | 0x3; /* Covers GB 0; table descri= ptor */ + realms_gpt0[1] =3D 0xf1; /* Covers GB 1; full access */ + realms_gpt0[2] =3D 0xf1; /* Covers GB 2; full access */ + realms_gpt0[3] =3D 0xf1; /* Covers GB 3; full access */ + + /* Pick a random location to read inside the first 1GB. */ + uint64_t fault_location =3D 0x10202008; + uint32_t gpi_index =3D fault_location / gpc_granule_size; + realms_gpt1[gpi_index / gpis_per_64_bits] =3D 0; + + gpt_base =3D gpt_table0_addr >> 12; + set_sys_reg(GPTBR_EL3, gpt_base); + + /* + * Default values: + * PPS=3D0: GPC table 0 protects 4GB. + * RLPAD=3D0: Realm physical address spaces are normal + * NSPAD=3D0: Non-secure physical address spaces are normal + * SPAD=3D0: Secure physical address spaces are normal + * IRGN=3D0: Inner non-cacheable + * ORGN=3D0: Outer non-cacheable + * PGS=3D0: Physical granule size is 4KB. + * GPCP=3D0: All GPC faults reported + * TBGPCP=3D0: Trace buffer rejects trace + * L0GPTSZ=3D0: Each entry in table 0 protects 1GB. + * APPSAA=3D0: Accesses above 4GB must be to Non-secure PAs + * GPCBW=3D0: Bypass windows disabled. + * NA6, NA7, NSP, SA, NSO are all reserved values for GPI. + */ + uint64_t gpccr =3D 0; + + /* Switch on granule protection check */ + gpccr |=3D 1 << 16; /* GPC enabled. */ + gpccr |=3D 0b10 << 12; /* SH =3D Outer shareable */ + set_sys_reg(GPCCR_EL3, gpccr); + + /* Access some memory outside the GPC forbidden region */ + uint64_t x =3D *(unsigned int *) (fault_location + 4096 * 16); + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D 0) { + ml_printf("FAIL: Memory access was blocked by GPC, " + "and should not have been\n"); + return 1; + } + + /* Access the GPC forbidden region */ + x =3D *(unsigned int *) fault_location; + + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D fault_location) { + ml_printf("FAIL: Memory access was not blocked by GPC, " + "and should have been\n"); + return 1; + } + + /* Clear the exception record */ + exception_fault_address =3D 0; + + /* Enable bypass windows */ + gpccr |=3D 1 << 29; /* GPC Bypass windows enabled */ + set_sys_reg(GPCCR_EL3, gpccr); + + gpcbw =3D 0; /* Base 0GB, Size 1GB, Stride 1TB */ + set_sys_reg(GPCBW_EL3, gpcbw); + ml_printf("GPCBW configured\n"); + + /* Access the GPC forbidden region again */ + x =3D *(unsigned int *) fault_location; + + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D 0) { + ml_printf("FAIL: [3] Memory access was blocked by GPC, " + "and should have been allowed by bypass window. code=3D%= lx\n", + exception_type_code); + return 1; + } + + /* Clear the exception record */ + exception_fault_address =3D 0; + /* Reconfigure GPCBW to 1GB start */ + gpcbw =3D 1; /* Base 1GB, Size 1GB, Stride 1TB */ + set_sys_reg(GPCBW_EL3, gpcbw); + ml_printf("GPCBW reconfigured for 1GB start\n"); + + /* Access the GPC forbidden region again */ + x =3D *(unsigned int *) fault_location; + + ml_printf("Fault address: %lx\n", exception_fault_address); + if (exception_fault_address !=3D fault_location) { + ml_printf("FAIL: [4] Memory access was allowed by GPC, " + "and should not have been allowed by bypass window. log= =3D%lx\n", + exception_type_code); + return 1; + } + + return 0; +} --=20 2.43.0