From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912942; cv=none; d=zohomail.com; s=zohoarc; b=UdLPq8pYxNt19NFyjK7vp1huO77okgFMxM+K9vEwPoJeTAhhDJ+rM7uxuhcEhI/lxTICqabsRrSPhSy9Sx+IyTtg/mrY0SJJdIUjDdcGtssVhSn+WTJu2HkeeWiXv+4yfAuPjMPfoTJMF416AWF4PgzyabJDWPuTG9tSVKNNi90= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912942; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UbZDU+VsyaWTWWF5avuwtLUIRzR/V2SulJj+2x8w4LM=; b=OEtwHWv34F9XPS4MuE3Wp2eCd3wo+zY35MF5Q8dSWjkkoYQme519F2CC+UnGFV/OUWfcLqbcnnLe0jDMNqTD8mtuTKFVLmz1n49YSU5sJJ/rwxzZcu/YoyoIsmWhVDfmN/ZrfIaL4ewv42wpvpg9ke40IY/zJxQIMsXLd9w6n44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17799129424628.692259310853501; Wed, 27 May 2026 13:15:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKdi-00063j-E6; Wed, 27 May 2026 16:14:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKdg-00062b-2g for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:04 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKdd-00054C-6g for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:03 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4891d7164ddso57742355e9.3 for ; Wed, 27 May 2026 13:14:00 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45edb5a296bsm8008488f8f.21.2026.05.27.13.13.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:13:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912839; x=1780517639; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UbZDU+VsyaWTWWF5avuwtLUIRzR/V2SulJj+2x8w4LM=; b=Dk+OKNuiBItdhnjpiwheaEVeuOlhLNG5HEjdME3vcbJYtqkbnYBaxKN5H3LQtmY8eM F8O/YKBZcGHr+JOwBjCycR+y5+ZWXuZWbrD69/bJT4W/K2ddjzKbvPSTAEdM6X3//cjg ExwDUvSxJhPsTyHHseJA9V+kZU6+xuXk+iscIND3eeSoejL2Ad/rGd63Is/mLHOeqIzf aV64BgAG+L79T+3K0okrzILvZ/CAljtt/Wv1a2VMJhemIeX/SR4ipqf2zYxTUssUyNTf k4x5VGnNocsEtua1ceIHWgQmxFqpItVAMyG8ul5pF+wZzngMcZEodE3JWknANfrZDSYz xpjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912839; x=1780517639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=UbZDU+VsyaWTWWF5avuwtLUIRzR/V2SulJj+2x8w4LM=; b=af+qWlSMAiRFXWz/mEYhrURNZEThwMrhJldlXIXp2QTN71KULkG3XcdW2AxAuZeu+N enY4h+TYhmEcLmdhlHPcoXuJoXiOgQslN49WBpdExLlm02uBU5qnseUh6vzzu8aYeYE4 RrHtaN+VppZ8Bp2waa2W3pjJKR2UXlwDfSggBF7kvWqHvbVL2yaCRNX7iD/PFkPQPOyg qmoHYkISfPg8JKLiNnThddqOMj/3kZISG3I1moGJFxSGfQWk5dMhVN6aI8sjI6fiAdl3 UNjXloyV+pKHf4Y7o5MsTc7ggPR3t0dUN33DHTru5jDfKaYL+X/grJS+J7Hc1YBg6i76 +vBQ== X-Gm-Message-State: AOJu0YxsyPHhAu5b1to8xVziQNdZOX6uiZ+SoPF2n0lokUgZoZgF+Bnf PQe+wdwRTfPPEBdhzKb07GMqkOAS9vrRXpjRhB0H4lY+Yr9y+XzOp0bm9u7kD+Q6WW4TqgRawJN x8cekH94Q7g== X-Gm-Gg: Acq92OHJmPoh3gWY5Tx1Fe2pnTVA3Z2Y68kG1tPwYSOiOyStNj2be5ePJ6GfmSdc+i/ z9RJX/6MSWEkUYG2xK2L4Lh4nct8fybVjWyYsDjLrP3DQyi50lt19YEKzJMEn2xmnCZtcAOjNNo EfDdHZi3N+e9iR+V1Jnfvv0UpLAHwp25cOrmtNywi4O3QM9xbwv9Wmio88GZ9Jb1zTKz1VQA3qo qQOg1S+SkmVUr95tPO5SENIv5QKzeFIbFFOleb32FXIJhHdorpXJ4LeMWaHsL3y7JDZ6sMchYxZ CD4YVVP8tQSZXa6wGJScez9H0ooBtfExGNBixVs/U4cKXM3/UErFRdMTZe/WeMVmaCJxzlDO105 S+hESiq5A/LTZp8/EVZhFTqRG6XNVyvvcArok19RJE4MZEG5u+N6svCaHehtJ9OQiyyExI99nIj qaefAe7T8E1gdYuwqDK8GdD5sE/QsAba1kMg7h/wr+x2Us9ZFaghcBCdrfLQ+vPzgI3Q== X-Received: by 2002:a05:600c:4e4b:b0:489:1ba8:5bf0 with SMTP id 5b1f17b1804b1-49069da61c3mr211843245e9.21.1779912838916; Wed, 27 May 2026 13:13:58 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Djordje Todorovic Subject: [PATCH v11 01/12] target/riscv: Initialize DisasContext::mo_endian once Date: Wed, 27 May 2026 22:13:37 +0200 Message-ID: <20260527201348.29511-2-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912945981154100 The data access endianness is constant during a translation block; rather than calling the mo_endian() method each time, initialize the DisasContext::mo_endianness field once in TranslatorOps::init_disas_context(). Signed-off-by: Djordje Todorovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/translate.c | 9 ++++++--- target/riscv/insn_trans/trans_rva.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++---- target/riscv/insn_trans/trans_rvzacas.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzce.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 ++-- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 ++-- target/riscv/insn_trans/trans_xmips.c.inc | 8 ++++---- target/riscv/insn_trans/trans_xthead.c.inc | 16 ++++++++-------- target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++-- 13 files changed, 40 insertions(+), 37 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1e4f3402569..9367f159f90 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -120,6 +120,8 @@ typedef struct DisasContext { bool fcfi_lp_expected; /* zicfiss extension, if shadow stack was enabled during TB gen */ bool bcfi_enabled; + /* Data endianness from MSTATUS UBE/SBE/MBE */ + MemOp mo_endianness; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -155,7 +157,7 @@ static inline MemOp mo_endian(DisasContext *ctx) #define get_address_xl(ctx) ((ctx)->address_xl) #endif =20 -#define mxl_memop(ctx) ((get_xl(ctx) + 1) | mo_endian(ctx)) +#define mxl_memop(ctx) ((get_xl(ctx) + 1) | (ctx)->mo_endianness) =20 /* The word size for this machine mode. */ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) @@ -1156,7 +1158,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src1, src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); MemOp size =3D mop & MO_SIZE; =20 - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b && size >=3D MO_32) { mop |=3D MO_ATOM_WITHIN16; } else { @@ -1177,7 +1179,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic= *a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); =20 @@ -1360,6 +1362,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; + ctx->mo_endianness =3D mo_endian(ctx); } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 62c0fe673d7..44c1696fe4d 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -35,7 +35,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGv src1; =20 mop |=3D MO_ALIGN; - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); @@ -65,7 +65,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l2 =3D gen_new_label(); =20 mop |=3D MO_ALIGN; - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index ffea0c2a1f9..3b9a745520a 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -60,7 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) } else { memop |=3D MO_ATOM_IFALIGN; } - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); @@ -85,7 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) } else { memop |=3D MO_ATOM_IFALIGN; } - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 89fb0f604ad..e935523c93c 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -71,7 +71,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 2c82ae41a77..2de74fac3a8 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -392,7 +392,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a,= MemOp memop) } } else { tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop); - if (mo_endian(ctx) =3D=3D MO_LE) { + if (ctx->mo_endianness =3D=3D MO_LE) { tcg_gen_extr_i128_i64(tl, th, t16); } else { tcg_gen_extr_i128_i64(th, tl, t16); @@ -409,7 +409,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) { bool out; =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -508,7 +508,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) tcg_gen_ext_tl_i64(tl, src2l); tcg_gen_ext_tl_i64(th, src2h); =20 - if (mo_endian(ctx) =3D=3D MO_LE) { + if (ctx->mo_endianness =3D=3D MO_LE) { tcg_gen_concat_i64_i128(t16, tl, th); } else { tcg_gen_concat_i64_i128(t16, th, tl); @@ -520,7 +520,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc index 8d94b83ce94..79bca1e9572 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *= a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv_i64 src2 =3D get_gpr_pair(ctx, a->rs2); =20 - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop); =20 @@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amoca= s_q *a) TCGv_i64 desth =3D get_gpr(ctx, a->rd =3D=3D 0 ? 0 : a->rd + 1, EXT_NO= NE); MemOp memop =3D MO_ALIGN | MO_UO; =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_concat_i64_i128(src2, src2l, src2h); tcg_gen_concat_i64_i128(dest, destl, desth); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/in= sn_trans/trans_rvzalasr.c.inc index 0f307affecf..79b0b2c63b8 100644 --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc @@ -29,7 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aq= rl *a, MemOp memop) return false; } =20 - memop |=3D MO_ALIGN | mo_endian(ctx); + memop |=3D MO_ALIGN | ctx->mo_endianness; memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); @@ -79,7 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_a= qrl *a, MemOp memop) return false; } =20 - memop |=3D MO_ALIGN | mo_endian(ctx); + memop |=3D MO_ALIGN | ctx->mo_endianness; memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; =20 /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */ diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index 0d3ba40e52a..71b4ca5473c 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -185,7 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, boo= l ret, bool ret_val) =20 tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv dest =3D dest_gpr(ctx, i); @@ -239,7 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_pus= h *a) =20 tcg_gen_subi_tl(addr, sp, reg_size); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv val =3D get_gpr(ctx, i, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 791ee51f652..f36b46c2118 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -49,7 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -74,7 +74,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index 0b6ad57965c..43f586dce97 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -105,7 +105,7 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_am= oswap_w *a) decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; @@ -135,7 +135,7 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_am= oswap_w *a) decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_= trans/trans_xmips.c.inc index c1a30156d36..1b9993a9b07 100644 --- a/target/riscv/insn_trans/trans_xmips.c.inc +++ b/target/riscv/insn_trans/trans_xmips.c.inc @@ -47,7 +47,7 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) /* Load Doubleword Pair. */ static bool trans_ldp(DisasContext *ctx, arg_ldp *a) { - MemOp memop =3D MO_SQ | mo_endian(ctx); + MemOp memop =3D MO_SQ | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); REQUIRE_64_OR_128BIT(ctx); @@ -71,7 +71,7 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a) /* Load Word Pair. */ static bool trans_lwp(DisasContext *ctx, arg_lwp *a) { - MemOp memop =3D MO_SL | mo_endian(ctx); + MemOp memop =3D MO_SL | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); =20 @@ -94,7 +94,7 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a) /* Store Doubleword Pair. */ static bool trans_sdp(DisasContext *ctx, arg_sdp *a) { - MemOp memop =3D MO_UQ | mo_endian(ctx); + MemOp memop =3D MO_UQ | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); REQUIRE_64_OR_128BIT(ctx); @@ -116,7 +116,7 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a) /* Store Word Pair. */ static bool trans_swp(DisasContext *ctx, arg_swp *a) { - MemOp memop =3D MO_SL | mo_endian(ctx); + MemOp memop =3D MO_SL | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index f8b95c6498b..f4e30510007 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -349,7 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); if ((memop & MO_SIZE) =3D=3D MO_32) { gen_nanbox_s(rd, rd); @@ -370,7 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_me= midx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); =20 return true; @@ -570,7 +570,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_memi= nc *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); @@ -591,7 +591,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_mem= inc *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rs1, rs1); @@ -747,7 +747,7 @@ static bool gen_load_idx(DisasContext *ctx, arg_th_memi= dx *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, rd); =20 @@ -765,7 +765,7 @@ static bool gen_store_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); =20 return true; @@ -926,7 +926,7 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_p= air *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd1, t1); @@ -965,7 +965,7 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_= pair *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); return true; diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_= trans/trans_zilsd.c.inc index f50c52f22c9..8068cc1aec4 100644 --- a/target/riscv/insn_trans/trans_zilsd.c.inc +++ b/target/riscv/insn_trans/trans_zilsd.c.inc @@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a) TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx)); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endiannes= s); =20 if (a->rd =3D=3D 0) { return true; @@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a) } else { tcg_gen_concat_tl_i64(tmp, data_low, data_high); } - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx)); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endiannes= s); =20 return true; } --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912916; cv=none; d=zohomail.com; s=zohoarc; b=fnfAnCRLlQeThISZI9FH00yVmlacmgAyc5J9KuBr+zWadx8WsJmfDtMzZY0xmsPtq/bVWTKg6Bmks8/TWtmBURzIPGtJXi470FDLN2tbGqkcF/Sx+apKfHFRN0TcMyCL8ApfnaHx+M7jC+LdORAmeeW9prUuC/pGIvgEutsel6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912916; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bvsndL3uE0tKY0e5Ntpbz61TpwE+wT5Q3inzD1J7b1A=; b=CCicw5II/6i6q3mhrNXP8EzoKpBh8f+QQHhVtGDKsW+ILfODxpj/vYy67IgBnTpiw9kh3Ql6bTRqmsU1a44rQQmt1oyF1spHpO3cZaDGCY+OS3QmovRZqcWlb5QFEZRzAuWunGTq2FsAlG184MPtSFsWu6MeZqFMTLDaEi0lJgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912916605252.51780837980857; Wed, 27 May 2026 13:15:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKdn-00064S-Lp; Wed, 27 May 2026 16:14:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKdm-000649-34 for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:10 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKdk-00056L-A3 for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:09 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-48d146705b4so127858995e9.3 for ; Wed, 27 May 2026 13:14:07 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454ea134sm461258225e9.8.2026.05.27.13.14.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:14:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912846; x=1780517646; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bvsndL3uE0tKY0e5Ntpbz61TpwE+wT5Q3inzD1J7b1A=; b=rG/doMNgF7Jm7XQGlB3x8BYLhBCLp7MegKcV2eSX+qrSJEMr/njkUOpA07CatzIwth uyLIASval1lEnmVABU9jqgSv/cMZ4X+vzCX5cW3HbxowTB8Sn4jV3cMr0YdieAIWpgf4 WAO4ZMRvWxC3s6ZdC78L0hMCyBvjO4McQsL8UVu2/3GvRKizEHW9bAMuhPbC3vM1plqO NUKGHUCn/u/O+rBqjBu3/GoyMs+japLxiVssLsjxkZoECoWL/b8diUd+ln/Q4CkXcgCL TVvcT1y7jvZ0dV7LIqYDmUUGJmZ7xR3q4zkURHuZAFOnAHiKfAxe1bdpKRGbRCCQgGxK FmqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912846; x=1780517646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=bvsndL3uE0tKY0e5Ntpbz61TpwE+wT5Q3inzD1J7b1A=; b=OOqwRtC6JSEj9BioHASYE3EPHdxmND6BfELH0Xi3iW9h1KyMdhO+jwepfHgS2g2eEH sAdKeQ/I6yjKAiKmmMKUuE5dBUy+rcTI/U4IlGhBJkyryFOI46jVGNKd2/18HJVuX/8k RSbOd0+uSQ441NyiNrehuoT+Z5jcPJ+0vAtsJvb5pwPax2kGMAw20Xs+oNSOLW9Hn3A9 HYfMTdmCxo8TyPHQx4+u9KJxEvi0FNYH1LFRrtjnSb8aBqddcx+64hEK4388CYaQN/xA FZpttrdga3Nsk5EaydXqv9KAE6UCkLpfcRcaGGKmevGxZoMye+qoYwB65Z8DcbxU9LAX A3mg== X-Gm-Message-State: AOJu0Yx3Ng2ue4RkMvciJIxin/7ipmlimyJfjGPBQUcBuqR6tqa91ZXY r7p5ZLPEoRTnMvZ4iSWrs0Xn0h1USzVeckJTURMt9B90r5svlz2vn2y7yFeEKQbirFBDyQgYeVy diIQc4Zuqrw== X-Gm-Gg: Acq92OGAOUGvoBerskvO3+k8iX+AUteJMQJwmVIeiHa7lmFUHD0JWnmf2GHVEomrQav fff45V4aCPT4DC+5geBAW1Fp+Hm6x78ZDNCW0T5dUmNKmQqhIuBjogXqSn1Z1TFzrHNkamZBRPT 0GSWL9b8yiM2O5SgN5xC1f1LvZquzyx54qNP4fXhZ0OMvSasurfafxbJ4Dch99zm8Wjx+MQow7v OqPl04KdcbYQwMqn6izcOK0Hxyyo/DOBpu2Y/EJARXjV4G/6j8XTEjLCgSoZLWy9jMWu09vB+6R pWB1Uva8ERDUhrn2GU32byQ3ny7A3rhgHn+Cl3UxOuIV2cXLZOrpO2er7Eq40VdaeEw4IMzmoj/ SO+fwUI4tVci3hUkPwGUc0guYcwUv0+m4Rkl1tScZwaZ+2X1fh6thrwW7Vx29/GAIvxT/AprQTL N6q4fo/sgJzDMcxzlbR4wZZizKorLElBVeNxc2Z/PGewJaQZja6fFaGscTEhglHKkLhw== X-Received: by 2002:a05:600c:3b0a:b0:490:60cb:560b with SMTP id 5b1f17b1804b1-49060cb57b1mr282702815e9.28.1779912846279; Wed, 27 May 2026 13:14:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , Djordje Todorovic , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 02/12] target/riscv: Implement runtime data endianness via MSTATUS bits Date: Wed, 27 May 2026 22:13:38 +0200 Message-ID: <20260527201348.29511-3-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912919734154100 From: Djordje Todorovic Make data accesses honour the MSTATUS MBE/SBE/UBE endianness bits instead of being hardcoded to little-endian. Update mo_endian_env() to pick the bit corresponding to the current privilege level (MBE for M, SBE for S, UBE for U). Remove the now unused mo_endian() helper. Note, TB_FLAGS has no free bits, so the data endianness is carried in the extended RISC-V TB flags stored in cs_base. It uses EXT_TB_FLAGS.BIG_ENDIAN at bit 33, leaving bit 32 for EXT_TB_FLAGS.ALTFMT. This keys TBs correctly on the current data endianness. Instruction fetches remain MO_LE unconditionally; RISC-V instructions are always little-endian per the ISA specification. Update the disassembler comment to clarify that BFD_ENDIAN_LITTLE is correct. Signed-off-by: Djordje Todorovic Co-developed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 1 + target/riscv/internals.h | 29 +++++++++++++++++++++-------- target/riscv/cpu.c | 7 ++----- target/riscv/tcg/tcg-cpu.c | 2 ++ target/riscv/translate.c | 15 ++------------- 5 files changed, 28 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d79c7a5a7e..1f3cbbf823f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -706,6 +706,7 @@ FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) +FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 8c24af0d855..2b3bdbbf30a 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -62,16 +62,29 @@ static inline bool mmuidx_2stage(int mmu_idx) return mmu_idx & MMU_2STAGE_BIT; } =20 +/* + * Return the endianness for the current privilege + * level, based on the MSTATUS MBE/SBE/UBE bits. + */ static inline MemOp mo_endian_env(CPURISCVState *env) { - /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. - */ - return MO_LE; + bool be =3D false; +#if !defined(CONFIG_USER_ONLY) + switch (env->priv) { + case PRV_M: + be =3D env->mstatus & MSTATUS_MBE; + break; + case PRV_S: + be =3D env->mstatus & MSTATUS_SBE; + break; + case PRV_U: + be =3D env->mstatus & MSTATUS_UBE; + break; + default: + g_assert_not_reached(); + } +#endif + return be ? MO_BE : MO_LE; } =20 /* share data between vector helpers and decode code */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 862834b4809..52f143f1cd4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -830,11 +830,8 @@ static void riscv_cpu_disas_set_info(const CPUState *s= , disassemble_info *info) info->target_info =3D &cpu->cfg; =20 /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. + * RISC-V instructions are always little-endian, regardless of the + * data endianness configured via MSTATUS UBE/SBE/MBE bits. */ info->endian =3D BFD_ENDIAN_LITTLE; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 3e22e7ed53d..45bbf658cad 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -193,6 +193,8 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_= ext); + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, BIG_ENDIAN, + mo_endian_env(env) =3D=3D MO_BE); =20 return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9367f159f90..35c6b37c0b6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -129,18 +129,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t= ext) return ctx->misa_ext & ext; } =20 -static inline MemOp mo_endian(DisasContext *ctx) -{ - /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. - */ - return MO_LE; -} - #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -1362,7 +1350,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; - ctx->mo_endianness =3D mo_endian(ctx); + ctx->mo_endianness =3D FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, BIG_ENDI= AN) + ? MO_BE : MO_LE; } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912916; cv=none; d=zohomail.com; s=zohoarc; b=N/y5xTSb04LRKC7IAqq7PY4oUz1b/jmh/ZXseI4juXTEmTqJBw7HqfzABfXEv4zTlxXJADgmyNpxllAKQ8/rytEUTh5Nb7QHVZtw7xVu9NeZiN2uWaX7Zhh+SB1zdNUVIt+DQnSu0fngPtOxyvjCuvv0wypHqLIGgPJkRiL3eEg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912916; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fcS3pGu767DyDfpU/yLApw18aqoV6ysV4gLdhBJ6clc=; b=EtDQ9rVPBhi8pfgou1GxulIxhshxvue4KxukPnTi1AhGK+hdKVEVWg9QVCWqx/auQNn0ZE/ZvEhz3JvDj78eJ0HjzcKy6J+rNvzyKZEn+Q56CVD3XZpOK9WA/CoiVe6QINzGxItvplbrDCY3si/YebJnEcD67xN2PIXQC5dTxmM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177991291606086.77588013884304; Wed, 27 May 2026 13:15:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKdw-00065t-H2; Wed, 27 May 2026 16:14:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKds-00065P-Rh for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:17 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKdr-000577-9P for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:16 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-48fde648a71so80271075e9.0 for ; Wed, 27 May 2026 13:14:14 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4904561a33dsm385306125e9.11.2026.05.27.13.14.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:14:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912854; x=1780517654; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fcS3pGu767DyDfpU/yLApw18aqoV6ysV4gLdhBJ6clc=; b=vHBQ0aZEiJvZkgi2YtrA9uih9g8Ou7mfZPVwe6gxYyx2cHKtrkkuqwsJE9POlEqpYf YNFj+hqfRMrZP2o7y2VitUXu6Fx/FEYTrHdE3/4H2dRmslpZs7/CzGtKobWjCy9KKcG9 M6acgmup1/ZO/wJ3pCTxvIGoysbkWnaIfPXEvGeVTv+UdsjHCn/cGmHkkIeVnQ49bVsI qVM/KqPvfX8LDhiZCffLDQLOhDS7uL0iPlvZwqNhaP58MfVrCu15635+vn3sgfkirCIP 73Y7nII0bJn4Jl/L8M1H9bP1szqYGl0rop3Tlg03nhFhdv0iU/Vu5fWkq140C2r+jZ2k DzYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912854; x=1780517654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fcS3pGu767DyDfpU/yLApw18aqoV6ysV4gLdhBJ6clc=; b=tV01RyEXvSvvMGbwvUln7qQjFM3EG20Lxv48+rksUvylz6igeHLbfcq+Hr0GbqlFRa WYTh03yBcSSvqhbHptnRNpO1/Yx70WLZMN7cDRpoI2SVAe+lkxmU/cDVv6pct6YaCkUw RNjFWzBc55+rwNjVolJMGGfKpv0g6/HECGLz+R2jzh7M3ac5HKU1IuKTX6sFjWqMtenE iaBlkfCIO6uV8Ftk1uH8fJdnvFqwyA6dl5NNuD6/ezkfHHp/UwJuDSq6KLba6tH6/d4j 2+A63DLtbNotaHW5vKT52BEggxjydo1VtXIBqY4TKJI4a3wYg1AEDy5C+/SMaUvEfjXr G2gA== X-Gm-Message-State: AOJu0YyCLZZAqJUE0qVD2db9voBzw9S/+GtI/PrmW4inDXVrADxQCvX0 qOjSPWiDxWoPQNnMRvPn3Xt0mBdI07mzF8rxbl8IZypC6BLLxTitQ4v0hSTF5kzlrScg1PHB75Z PYtmNWTh1dA== X-Gm-Gg: Acq92OHZ0FP1LtcqGyRrG1XoXvEPUTe/Ja4dWFtt5rlFiILmw3I/yyAfi+gr5r8Lk9B r1FGRWXALIO/r8QqzEmNsS7GyK1l2ZRgE9Hu5DM0qUoiy28tU8RVSg3K7fzaoYUagYot4b0fevx iPSXcv5oqEnzFNkz/RJHpSYoz4VIkZFlKa5c9dOaVpM4OjfNhdKTa+Tkg3t9rZ6Z208B6JcpFCI ZjzyvM2IeFD0a/PXuVx/MXJj8QqoPEsCoL8KKU2HyqRtu1G674/we6mOwlJDkVP3MRUZjSGn0aY k3I21mGJFQ7agt9aaXuc5W1TN+Ndegk174MTazgu6igKnCcU8/HJj6j94fHGfPXHNeikCyg1Ljr hsJre/MwMt6ySYZJLgvqgr9sSthasW2eivJaX0P3FB437BKQ0oZDTbIeYbpn4QFb+LDHQ20/VcP CbUF0xGa0iGZBQzTbcrE9EDObFuUcyFanlmZXvqTb5Hde34nqqFXdu860QMOvstg040Q== X-Received: by 2002:a05:600c:1c0b:b0:48a:53cb:8604 with SMTP id 5b1f17b1804b1-490426a495amr384507365e9.14.1779912853653; Wed, 27 May 2026 13:14:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 03/12] target/riscv: Assert PTE.N/PBMT bits are not expected on RV32 Date: Wed, 27 May 2026 22:13:39 +0200 Message-ID: <20260527201348.29511-4-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912918837158500 PTE_N and PTE_PBMT are undefined on RV64, assert we are not under RV32. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 17305e1bb75..f86bfdb32e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1490,6 +1490,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, return TRANSLATE_FAIL; } if (!pbmte && (pte & PTE_PBMT)) { + assert(riscv_cpu_sxl(env) !=3D MXL_RV32); /* Reserved without Svpbmt. */ qemu_log_mask(LOG_GUEST_ERROR, "%s: PBMT bits set in PTE, " "and Svpbmt extension is disabled: " @@ -1643,6 +1644,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, target_ulong vpn =3D addr >> PGSHIFT; =20 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + assert(riscv_cpu_sxl(env) !=3D MXL_RV32); napot_bits =3D ctzl(ppn) + 1; if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { return TRANSLATE_FAIL; --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779913000; cv=none; d=zohomail.com; s=zohoarc; b=ZFDJDWlmooH24RgpXvmblWyPrpAkc+9d/5b29g4wfIw9724PYR7eFEXtoSM+7QjGkfHVGNFKtyitJh4bHQhqIGSSk0hfvbrJtOJb3nZqifsI1W51OD9X0F64oShfqMO056tqGyI9XQu4jffMmcYRruFs6hGV6AOjVBfgqP8ZqHI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779913000; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j6KuZbw0iwf/xssJze0f006ceb1iyBQfISlrUwfPrC0=; b=bkU0W2GDjp1goMWlrXXud599qzVtUWJYWAwtmyXB2Y4Ya6+0xEzKeg4OV1PLpH4ewHtCi3+MYhLSPcJUySfPprFymMjuvBChp61Z+7Eg7634FQeNnGxKi70VwJCElZmAFDgWSX+WP48JRGLSARYRPsW3zt1paVcUz9E75di+naU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912999932621.9640024003828; Wed, 27 May 2026 13:16:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKe6-0006Df-AD; Wed, 27 May 2026 16:14:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKe4-0006CN-RN for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:28 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKe3-00058t-5a for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:28 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-490686877a1so25871075e9.0 for ; Wed, 27 May 2026 13:14:26 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4908f0b5c92sm64055e9.35.2026.05.27.13.14.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912865; x=1780517665; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j6KuZbw0iwf/xssJze0f006ceb1iyBQfISlrUwfPrC0=; b=FXM6jnmuQamDZsNy7Y2j6cqr96TEISbRGBcDKSzkCeSoMDECxEX+Mi+pU8Z3qJv+PB VZKuDtgukGNs9CHYN1EXUptteuXpuLmwihanYgAsKymyck5Nx9+/tWxxjISrY3n0j4gZ SuIH03BCbl6sc/O0nISzei9gaIOIJJXnMEaR8YjsTg8zUJkTChOWG1+fOHkxrknASxbA u4dtmrA9r4Vp+b3VwofZIJOolh6B2rej7nBXTuZyk0aMLeYQ2meZmHOffy6Cj3LE2r6j 0Sh/jx2n+/Exo5ACb1Qma7a1rz5n9NB+PDeHG5xbs4Iqu9xjph8orlviy6xspV/L1Lzg BFQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912865; x=1780517665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=j6KuZbw0iwf/xssJze0f006ceb1iyBQfISlrUwfPrC0=; b=eiDptAaivxNGDwsObO38AsmpSwaq0W2Gou4t1z4wb3jER2TmnQIXMTn21kBnJDFAhL xlMMMnmzwXfIjk7cjETLnotey8FNuswJlfMgCrCs9cAhVDRYGUoAivFRB5XNBg3qAnnS /gPQcbpxHWQuYHRLtQSDVQJaoRIZyoStXkYrtHycS4QZQU3wvyXw4014GACEiMQH9iC9 QPW4HU8L5ayydUW1Ju/Qk3eqp7VaXbT4z0BMCcDSTGMwH23fzeztC3wLi4p/6krIrWZL zW1VvWQ38b7LlSI74qQ2Vd/H+dQAZS+vimEwvGwkOmc6ui9C5Du8Zm92BYfBXqdEW6bK jbgg== X-Gm-Message-State: AOJu0YwKITppGttDTt1Zq5COsBB3YWWcSAN5BoWYFGQgBTI+Kzw14c4B ffL4bOJLV24i+lAvELs+c06D1Cw5rmcJgoqN+e4vY28SscgMH6my8ADY0XuS/AFZe1nXDuu7BcY RuAzAWiOPpQ== X-Gm-Gg: Acq92OH34BkYwQtMfTB0cCUk98wVPIglb4pEH46ZOW4QFySyxQwKoRjjEU1NocM3bFz 93MeuynHKwcBnxNvT0rdzZI1p4cvHJAJrTZ0imYnyid22Hbq7axmLQhkW+VCM33CGMvOQ8xDgOJ R7LOUfF+WhcqOBzpfoQxdS9An5VEi/Pp0OnzrOO0qKZ//FCAh73TLrFRmUvQYkgd7Ng1BYtuzWv YVfWSXEIfyZXSP22jtscjoJ04sCwLy0vkPOQNvUVf7/TLlYxaA0oT9VWup4NS0+UvMt2nZixgpp M/bQdSDXRGd0p6gClwtH1lW9GV6PzS22rz2cYv+wg5K5kE1xi+eM/8BKJi96nMo6ShC/lv0vKJf wTpgpN/bJ/qaZlYnGT/d7beYvhmysv7MJ6J7hvBvEGZpqHFqfCeAomRt2ALRM7t378VQqx62gYz wqKMFyt0DU0LmEylrTpYfBFa7AFv/99d2wgBJ8KtahzMIG4+lhENVWh4wjrNLh+3/DS5e57oDeb HUc X-Received: by 2002:a05:600c:a402:b0:48f:e230:29f5 with SMTP id 5b1f17b1804b1-490426b0c92mr289639835e9.16.1779912865477; Wed, 27 May 2026 13:14:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 04/12] target/riscv: De-indent some code in get_physical_address() Date: Wed, 27 May 2026 22:13:40 +0200 Message-ID: <20260527201348.29511-5-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779913001159158500 get_physical_address() is quite complex already. In order to make the two next commits simplers, de-indent one if() ladder. No logical change intended. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu_helper.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f86bfdb32e7..6da67e132eb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1617,27 +1617,30 @@ static int get_physical_address(CPURISCVState *env,= hwaddr *physical, hwaddr l =3D sxlen_bytes, addr1; mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); - if (memory_region_is_ram(mr)) { - target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1= ); - target_ulong old_pte; - if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { - old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le3= 2(pte), cpu_to_le32(updated_pte)); - old_pte =3D le32_to_cpu(old_pte); - } else { - old_pte =3D qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), cpu_= to_le64(updated_pte)); - old_pte =3D le64_to_cpu(old_pte); - } - if (old_pte !=3D pte) { - goto restart; - } - pte =3D updated_pte; - } else { + if (!memory_region_is_ram(mr)) { /* * Misconfigured PTE in ROM (AD bits are not preset) or * PTE is in IO space and can't be updated atomically. */ return TRANSLATE_FAIL; } + + target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); + target_ulong old_pte; + + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { + old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le32(pt= e), + cpu_to_le32(updated_pte)); + old_pte =3D le32_to_cpu(old_pte); + } else { + old_pte =3D qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), + cpu_to_le64(updated_pte)); + old_pte =3D le64_to_cpu(old_pte); + } + if (old_pte !=3D pte) { + goto restart; + } + pte =3D updated_pte; } =20 /* For superpage mappings, make a fake leaf PTE for the TLB's benefit.= */ --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912916; cv=none; d=zohomail.com; s=zohoarc; b=Mn8jhRMp7PupdeUv8CkRKaw2hne0c3wGlfvJugKWf+YBAUCcp4tQLqtlngvAWQTvMj5PgnQAI2aJ3MnI5/FOjTJNbTBMi4DManAMkxt+f3GStonvojdzsUQsX3/0JZe5Nw4AmHuXotbNlGOB8t9mpdBKdpxuda14vDrPUSioOak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912916; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qhljTQ/lMvAqMZBeTUmtazgm5zjo86lQdzWtUmmZ4BA=; b=RlEN5lBj79xXm/t/FOUxPvjBl9o/uKuq6Qh8lL3ZUO7ymPZvNQuLsAFXqfpWGtFajT0I7PncorIZTMtkQukronMPaCgkBuXlWV+illERF6i2Fe4DhAV5sTkpPSmc8cJT7/y5Egq8+JivVCuoWK5WM0+9ln/j8xg9YGI0VEwdzW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177991291611860.46902290775961; Wed, 27 May 2026 13:15:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKeI-0006Fw-Cb; Wed, 27 May 2026 16:14:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKeB-0006FK-Ml for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:37 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKeA-0005Dm-73 for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:35 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-49041fb8c23so45884075e9.0 for ; Wed, 27 May 2026 13:14:33 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45ee5a84e92sm88842f8f.35.2026.05.27.13.14.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912873; x=1780517673; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qhljTQ/lMvAqMZBeTUmtazgm5zjo86lQdzWtUmmZ4BA=; b=YgHtjtJCq2kDMsRk51WLDDb/OsJzziwLFPTYvdFIpCoCedTMHCztTvIpDCp0jEYT2I jl8+3YkgZ+/qBkXkdpLMc8kOT8bMzWmltv/z6qOIwObrCO5QNP3xfgQU+Q5PJg051gyC v4I9EP7GP4iKRoJDn9+nvWQyWX71++vJn1EYo1sTqx6tge24gXioFSXPFe5HSxc/gaAD nbilE7lQk/6JgHh1VjJ56EYWdzfhH9zmHLo/RHCLApQ+wXxwBsV9/VY8lEagz3g8+hgT Z0+pvuNHubQQfiZb80909wPDQjq6y0x2pwO6ZE67LZSl45rAidjOCs3R6k8K6NT94Yy/ pp2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912873; x=1780517673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=qhljTQ/lMvAqMZBeTUmtazgm5zjo86lQdzWtUmmZ4BA=; b=FEPrpGCtMO7pINne/+TPo5+2mHNTT9LqMBg+cBw3z+wANi0wWH40J4i0jXD1oCk+1/ kO2iirzVq/hy3RPcNKB7XdHwbf0jhdTVW8VXTYH5o4dNuZOgVCs2b8p/DIC0Lly7Hj/S i+Uk4PLdultWovKB/DNed64noZWKeAhNFoCZkaMD9pNznzlUmuVT1DUCCgzswcMY4Cas bWXrplU/4fZ+tJTsxNssPYlvrnV5+VwMSKQp181iuoFtg6ZarZIrrxRI/F+eiBTdo78O unh5lQsXdprEbfksuMfTLp7eONink96x84nqH4SC+7V4YojkngRavD5I2qrs41SfOqKz c7wg== X-Gm-Message-State: AOJu0YzgEsncI6PsS9DQchpI514+ykLGDfKR5KB9ig1uvnhbAlQhwhLT da9Wr5MNk0KITK4VCzu0FlLcvgNa9Z1IYpEbzs7Jy7nTispnmCSVDUBxTBfBujVz5WLUbbDFYxo KZKokXVmZzQ== X-Gm-Gg: Acq92OHHgQS098rO4091htZBQyz3hqkPjZ97cAq6yWR5d9gU2nZe3g1tmglPd/uy/cG V8gqcS6ptX940s09GKXpWkkG3Ou+8n4xtfAREbp6bZ3BhvJ9uxXzWSfoTvNhmj22HkhA4KM8ECm HDlQU6L+jc+qa7/V4c8RdXy1Tb38iPWl3DF8Z0/0hDpUcy/FrxDl2vf8WeAJ0kbsU0QMHtHu5r4 UEqcH6j9XQu2qXFx8mk6+KsoDCRDuUxmnmUFkJMEJwjzC07hUHGqVZpCfp+0nb98akh5GLsFMo7 v8sYVS+8/zFhbwr4gYIC+eIYaBb5y5PgzHGCJUQF8Iy98JT0V8KmJ3bG0nTVt1DAYbY2K5B6iqf N9DIw740YzjlY1uGNGO1uUd/fEdCodUvv6PE5yKXNC3dw2qKxoexpKF31sBBXDmUfcRNlWgebO9 SKyrFYN73SoaT10Hw2ElcI6lktyQAYEY/JIBIh6PxBtAyYGZoZOZYlG+Vf7hk9pUbMJA== X-Received: by 2002:a05:600c:8599:b0:48a:525b:e148 with SMTP id 5b1f17b1804b1-490424ac7ccmr302211295e9.4.1779912872781; Wed, 27 May 2026 13:14:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 05/12] target/riscv: Remove target_ulong use in get_physical_address() Date: Wed, 27 May 2026 22:13:41 +0200 Message-ID: <20260527201348.29511-6-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912917439158500 Use uint32_t for RV32, uint64_t otherwise. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu_helper.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6da67e132eb..fd7c6ac1b23 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1625,16 +1625,18 @@ static int get_physical_address(CPURISCVState *env,= hwaddr *physical, return TRANSLATE_FAIL; } =20 - target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); - target_ulong old_pte; + void *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); + uint64_t old_pte; =20 if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { - old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le32(pt= e), - cpu_to_le32(updated_pte)); + uint32_t cmp =3D cpu_to_le32(pte); + uint32_t val =3D cpu_to_le32(updated_pte); + old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, cmp, val); old_pte =3D le32_to_cpu(old_pte); } else { - old_pte =3D qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), - cpu_to_le64(updated_pte)); + uint64_t cmp =3D cpu_to_le64(pte); + uint64_t val =3D cpu_to_le64(updated_pte); + old_pte =3D qatomic_cmpxchg((uint64_t *)pte_pa, cmp, val); old_pte =3D le64_to_cpu(old_pte); } if (old_pte !=3D pte) { --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912949; cv=none; d=zohomail.com; s=zohoarc; b=TFzT3t6JyZ2jvqgjZW4xsBTlt0g7ioCDjzBVqVtYy2YLKULhrMg/bcANbK/FzQeEOh+sUgk3WIK8wJWacbnuCHDGKorysWuqSIIUtqSBOrQGprfvYx9ZvjK7tsvtpsJsitTYpMtviSRWr7wiYjyT6DeTIuXELhhhs/e2dztOuiw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912949; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iH62ufHtz7j9HYbBqPOwH+CwObJzaFz/XebFGOq8UJ4=; b=MBUUj2rcrZP3Pvk/Ga49lfWq/tSvnze+mbUAbmpnlYHStvc5UmFxvR7SQSmE/Wlw0FhxqlkZ/tKtEYEGS9Es3nwg9/qszLpGB3vDfQZQRgrnzqePDUQ8fdLmhhDfulWFmHfwEtiOu+TZrLUXhaxBrf+76cd9dqXTwgajIqyuD30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912949988230.80556866074562; Wed, 27 May 2026 13:15:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKeN-0006NL-Ns; Wed, 27 May 2026 16:14:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKeK-0006I7-Cl for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:44 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKeI-0005Ld-6r for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:44 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-49039a8851fso65535515e9.2 for ; Wed, 27 May 2026 13:14:41 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490452765f5sm435518395e9.5.2026.05.27.13.14.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912880; x=1780517680; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iH62ufHtz7j9HYbBqPOwH+CwObJzaFz/XebFGOq8UJ4=; b=ir3l39y45Tv6OqsbjjsrUCu4EiM0/8ukuJDi5RUKKm+0PiDw3qyAFcuJANf3nrU56s +1JWxIh/bYyL1f/8VTiHigc1F5mYyruWmck6UIiN61AP1q4HyH0PL97tXwBCm1hvZwgT 3yaf7nANnh4W7nU5wMFk4tFKHn6cfOyRWpNe+kjnd0YG+kNXxGg+p7HriNvyAdkdJ5Ce MoNRAhZRElP1OQL08BYdD0HjtCRTUWJsodwTvfMGFT1yKEtQMBO7Ue725IIDChpBjH1k NlJ3zjkf7nhJsxN+A1MZmH0fy5jiVvoZp2u4qxXjoR7eruT5gRZZ5vyIocOM8DS2gLAr bd9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912880; x=1780517680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=iH62ufHtz7j9HYbBqPOwH+CwObJzaFz/XebFGOq8UJ4=; b=SJHioNn+Al6QG5UzLYVHwuLNLrZxvBMl3cNbD58+YZL0v8f9HJ0KYOv3JFORAmhFD8 QMWI7XwGz0MkBtaTIzbwG+OZF2uTKwmlhQ+jVzCZmSJNuTRUNQKKHZkRJbGPesDVcwTo JaJg41shWjkNE7dMrZ68Uz1rF6+CigvYLpUvs3/E1OhDFpcB2DkA7pNd7wPjFvcQg95h tnzH1odg+uhQlzkQBEgGpl8jIS0Vbkj9toYM65mOhKUi/qd+DgJFahqYteVDp1fIUqt4 /HJGoQenT8u7ql1Yl6U9XMnvVlvGcdA94Lw3LyssrqcYr/FGmRsGmTxjcGIKvWPVdD6H Au/w== X-Gm-Message-State: AOJu0Yy1oJ/BrNYKRxfZjVsB4yKYdHvrPQSJ9uMsGdOAR9/37mxL1QBc omDin4ffQKzFScNvCqlw4lSxffE7sRV6sUpV7VlcaUj6WL7NvVJJiA8AjFybPiIpS3oxkuuk/U+ 2HQaxFZo/zA== X-Gm-Gg: Acq92OHo4LQBnyS9R+wzfLIWnDiXBZK2y83Le2cUbkrXqObHmVkEykNiGVDs4OlkKPg pSaHJj189EEqmxPNo9uRKAkPU4yQdV4OsHDNZHxTsmAUAbylbzY6G8BGbebC40xVyEXfOprSJh0 8X/15RY20gfqTV9d40jySG6ymfwDun6RhHdphdWtvC7X33d9ED6a0HBB0NYctqde17+ClWi8loX 1tkb2+22NY8ivjG3sDJnVku1cj3iYIOiGNor3cthziL19kO+uZH3iOJzH7+2tv5e1Oc3+Xd6raC IuOdN3r3sA4JHxXdLKKocndMHU5fCZmWSDy8ChpNPsEzIvszg+vgu6euMOE6B3g15dFXy1aifXn miCw9QCDRlgGm7wfxYr8WlaHOAoY69Xj6CYOydLJh/NtLYYvpQKfAilVhxBjt5xeBGiENWZd0FL Mb3wgu40H0KZ2dhUl/a4b7bUick7OpYylVXs0CByvH7rTg0z9NNj+QincqDcxO21Gglw== X-Received: by 2002:a05:600c:4510:b0:490:3d2e:b67d with SMTP id 5b1f17b1804b1-490428eb9aamr380924625e9.30.1779912880153; Wed, 27 May 2026 13:14:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , Djordje Todorovic , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 06/12] target/riscv: Fix page table walk endianness for big-endian harts Date: Wed, 27 May 2026 22:13:42 +0200 Message-ID: <20260527201348.29511-7-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912950882158500 From: Djordje Todorovic The page table walker reads PTEs using address_space_ldl/ldq which use compile-time native endianness (always LE for RISC-V). However, when a big-endian kernel writes PTEs via normal store instructions, they are stored in big-endian byte order. The walker then misinterprets the PTE values, causing page faults and a hang when the kernel enables the MMU. The RISC-V privileged specification states that implicit data memory accesses to supervisor-level memory management data structures follow the hart's endianness setting (MSTATUS SBE/MBE bits). Fix both PTE reads and atomic A/D bit updates to use the explicit _le or _be memory access variants based on the hart's runtime endianness. Signed-off-by: Djordje Todorovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu_helper.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fd7c6ac1b23..9ec15fdf46f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1370,6 +1370,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, target_ulong pte; hwaddr pte_addr; const hwaddr base_root =3D base; + const bool be =3D mo_endian_env(env) =3D=3D MO_BE; int i; =20 restart: @@ -1418,9 +1419,11 @@ static int get_physical_address(CPURISCVState *env, = hwaddr *physical, } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - pte =3D address_space_ldl_le(cs->as, pte_addr, attrs, &res); + pte =3D be ? address_space_ldl_be(cs->as, pte_addr, attrs, &re= s) + : address_space_ldl_le(cs->as, pte_addr, attrs, &res); } else { - pte =3D address_space_ldq_le(cs->as, pte_addr, attrs, &res); + pte =3D be ? address_space_ldq_be(cs->as, pte_addr, attrs, &re= s) + : address_space_ldq_le(cs->as, pte_addr, attrs, &res); } =20 if (res !=3D MEMTX_OK) { @@ -1629,15 +1632,15 @@ static int get_physical_address(CPURISCVState *env,= hwaddr *physical, uint64_t old_pte; =20 if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { - uint32_t cmp =3D cpu_to_le32(pte); - uint32_t val =3D cpu_to_le32(updated_pte); + uint32_t cmp =3D be ? cpu_to_be32(pte) : cpu_to_le32(pte); + uint32_t val =3D be ? cpu_to_be32(updated_pte) : cpu_to_le32(u= pdated_pte); old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, cmp, val); - old_pte =3D le32_to_cpu(old_pte); + old_pte =3D be ? be32_to_cpu(old_pte) : le32_to_cpu(old_pte); } else { - uint64_t cmp =3D cpu_to_le64(pte); - uint64_t val =3D cpu_to_le64(updated_pte); + uint64_t cmp =3D be ? cpu_to_be64(pte) : cpu_to_le64(pte); + uint64_t val =3D be ? cpu_to_be64(updated_pte) : cpu_to_le64(u= pdated_pte); old_pte =3D qatomic_cmpxchg((uint64_t *)pte_pa, cmp, val); - old_pte =3D le64_to_cpu(old_pte); + old_pte =3D be ? be64_to_cpu(old_pte) : le64_to_cpu(old_pte); } if (old_pte !=3D pte) { goto restart; --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912973; cv=none; d=zohomail.com; s=zohoarc; b=RDdaO9z35B+stB//owWqKgUOYqN98GWIGvo4sFMOLQSyB2GU/urFpI7mIPpS06vJRHb70YPMe5t9bd25QSRCoJgSQxGJtdd9zTPjwZwypQGTOemP6EgrcPCjLmZZjpUxYQYkmIARtJ6JtODNJRTnU0xt/IuHyX8HzasGrVqawN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912973; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g8sLi8TpVj+WiyqU3QlE4wdZYfoI/mwrAP3TeMVzFfg=; b=eM3ZyL89G7vmrGvm9fHW5YAdQfsCsEf3ihmmgAm8ikhV/DZfbOURv3heuqGp5wRJqK20rqZ/DKMaCW6rPnTeBb4mdB8ssUTSj4AOpBCOE0wfV/lVdsx8mMPc8eopHmQPKCWr/vwtJunxEx9/Jpu4CwwjouJZpH2CkXxRLC7R/oo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912973441316.4612555480711; Wed, 27 May 2026 13:16:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKeS-0006Py-Ay; Wed, 27 May 2026 16:14:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKeQ-0006PN-Mw for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:50 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKeP-0005ND-12 for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:50 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-49048e043e5so44524935e9.1 for ; Wed, 27 May 2026 13:14:48 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454ea134sm461293765e9.8.2026.05.27.13.14.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912888; x=1780517688; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g8sLi8TpVj+WiyqU3QlE4wdZYfoI/mwrAP3TeMVzFfg=; b=poRX/UaTOaAnJdZnmJMgpeV+XXzQ5Xh8NXmyP9PBYDWeTAK+GQb0k3yCllRW8kyUI2 Xwo70uQ6p84jlbSM0Muwv3DH4CMHeomEGOb301IYKtOnPT6fVMkS+bB40cxCHLpkpBBO de2XpuKCH4tcn9MY4kVMDwJx8yBs74tEbYIqwjgVGPifsyCLKwjF3i/luPbIWKZhiQRq T6iSI7AE2TggsvE6C0uJ85DD2MAR9QYOu+cbd1tHPXofpqAsADQicP/hKLr4IQSfQg4R EqB6BXgSbDJJ96rm5s5jrbK0pBBAnqi9s714ng5IJ21UGKx4Wgdu2wdwb1k7M532nkRp OcMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912888; x=1780517688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=g8sLi8TpVj+WiyqU3QlE4wdZYfoI/mwrAP3TeMVzFfg=; b=f3z+IpSDfT5FPdNfOpxY35uEDIG/OxoF3rmuQD52DfAIfpQgKr9frHurlV7rk+MLrT AcgTPvgNwCYZa+Z5szLZqE+M23vefO87fdmXbScqSXKo+MvoBYfU8xTKcmwu5+LnFDlJ YRMT/2iQt8Adi7kR/Aep0vIa5g9gMVYoEmxnn62i7B+3+jJKmTMck7dcEf+CIhVXQeYK PkPTMHKW+l9fS74xuwu7oqaQCp4ZYf67mmAYA5AS6hlDPssnVh25zedf4R0LGsEXjHLz Hotqzma9GCPdDUnUbRr6JI45hYkCYqAgbmgNuqQW/hQn5TtWvpxjg4qddSnMj7P8pSTN VrtQ== X-Gm-Message-State: AOJu0YxKTzExP2nZhVwyo+VMSChL3iYD9iORfUhthZijcXCF6/4+3akS bVT8HAqKMXbULtCY1u8DOTeISJVbuY6PQvHpFOG/OR8eeqYlzpdUTaVYSINAel1sDmVazzVe34w V3UnuPzLpxA== X-Gm-Gg: Acq92OGnlHK6y6ii5etbsE7fP8A9VvXeCwpU/s2gWLv3CKPbI5K1oRUi8CVqJ/QarWC 0r+gz6i/AlcVQT2PWgZEW+b1CTYJB7Hxv+yyLeaY7dDZi+5Qe4WserKBbqhX6GIfqyoAp0xs4Ka 1h99X5lc2UJry2flcA9OMM1QsCocEGZ6hOX/zlJS5QMbrJy2KaNjN+UsKfUzjEyFEjFG/Cb6CTB Fn1vGlGaLKebv9v0EFdzc+ELPM8tUkXI6bWhz7rEYc44lac6GimDvDhktNyLVq2y0XKKSQ7KYF4 xcxfbMswUIRnjc1wtVARY9qJoWy81WCWqIWxxrNBz+rqhcsP+erPYBmbzCahQl7r+nHaRafOVPO 1kpbIC/+q8IKgB2XQTuTpfcSvejod7fnmhW3EekANFg4F6FjNUZQl7yeackbA60di+RiboVJWz9 JoYNA70X3UP1qWOJEswIjnqLkqStmiLHiurF8QeZ2cTeVRaHaCEXD/47YZBD6Q5YyEjw== X-Received: by 2002:a05:600c:8484:b0:490:3c94:a3c6 with SMTP id 5b1f17b1804b1-490428e205cmr425199855e9.26.1779912887601; Wed, 27 May 2026 13:14:47 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 07/12] hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API Date: Wed, 27 May 2026 22:13:43 +0200 Message-ID: <20260527201348.29511-8-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912976150154100 In order to make the following commits easier to review, do not pre-initialize the reset_vec[] array, fill each word one by one. Set the start and FDT load addresses using the load/ store APIs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/riscv/boot.c | 53 ++++++++++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ae2f86c7ceb..c6ab1cc8cfb 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bswap.h" #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/error-report.h" @@ -444,6 +445,9 @@ void riscv_rom_copy_firmware_info(MachineState *machine, &address_space_memory); } =20 +#define CODE_WORDS 6 +#define DATA_WORDS 4 + void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr start_addr, hwaddr rom_base, hwaddr rom_size, @@ -451,43 +455,34 @@ void riscv_setup_rom_reset_vec(MachineState *machine,= RISCVHartArrayState *harts uint64_t fdt_load_addr) { int i; - uint32_t start_addr_hi32 =3D 0x00000000; - uint32_t fdt_load_addr_hi32 =3D 0x00000000; + const bool rv32 =3D riscv_is_32bit(harts); + uint32_t reset_vec[CODE_WORDS + DATA_WORDS]; =20 - if (!riscv_is_32bit(harts)) { - start_addr_hi32 =3D start_addr >> 32; - fdt_load_addr_hi32 =3D fdt_load_addr >> 32; - } - /* reset vector */ - uint32_t reset_vec[10] =3D { - 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ - 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ - 0, - 0, - 0x00028067, /* jr t0 */ - start_addr, /* start: .dword */ - start_addr_hi32, - fdt_load_addr, /* fdt_laddr: .dword */ - fdt_load_addr_hi32, - /* fw_dyn: */ - }; - if (riscv_is_32bit(harts)) { - reset_vec[3] =3D 0x0202a583; /* lw a1, 32(t0) */ - reset_vec[4] =3D 0x0182a283; /* lw t0, 24(t0) */ + /* .text */ + reset_vec[0] =3D 0x00000297; /* 1: auipc t0, %pcrel= _hi(fw_dyn) */ + reset_vec[1] =3D 0x02828613; /* addi a2, t0, %p= crel_lo(1b) */ + if (harts->harts[0].cfg.ext_zicsr) { + reset_vec[2] =3D 0xf1402573; /* csrr a0, mharti= d */ } else { - reset_vec[3] =3D 0x0202b583; /* ld a1, 32(t0) */ - reset_vec[4] =3D 0x0182b283; /* ld t0, 24(t0) */ - } - - if (!harts->harts[0].cfg.ext_zicsr) { /* * The Zicsr extension has been disabled, so let's ensure we don't * run the CSR instruction. Let's fill the address with a non * compressed nop. */ - reset_vec[2] =3D 0x00000013; /* addi x0, x0, 0 */ + reset_vec[2] =3D 0x00000013; /* addi x0, x0, 0 = */ } + if (rv32) { + reset_vec[3] =3D 0x0202a583; /* lw a1, 32(t0)= */ + reset_vec[4] =3D 0x0182a283; /* lw t0, 24(t0)= */ + } else { + reset_vec[3] =3D 0x0202b583; /* ld a1, 32(t0)= */ + reset_vec[4] =3D 0x0182b283; /* ld t0, 24(t0)= */ + } + reset_vec[5] =3D 0x00028067; /* jr t0 */ + + /* .data */ + stq_p(&reset_vec[6], start_addr); /* start: .dword */ + stq_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */ =20 /* copy in the reset vector in little_endian byte order */ for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912959; cv=none; d=zohomail.com; s=zohoarc; b=KjeZ+YzeSM5bYvUFbIx91KOSGY0o003OIPIyW8XwFrfSLu7gKFUgzUP9ok28V/GNjEouSTtXCnO9VWUC4W0A16ggxpEEV0YdozAgPB02ePHyilf6mWaF4TLSxPwjaFgPM2riekQdfqbUd/PqVw24h5VqfDX0JBYM2Vg7hJDxans= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912959; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TeblK7/EUpTWApgaalqExSacjBZVjtrb39D4H9GOeNI=; b=NQGBFnC0XBfGHG4aHH/qZQsfygFVEH0+r/rrmLbdeFqVPPBF5DD8X8UX4c6jpGPqwBSSAJGsR4QEihPrDqjKkeW4PkSIoPWhpQqU/K/rBg1WpLDK5A6M6WEcy3jV1XZpfYRAwHqGGU9rhyGJMxhwKoMMAV/eUElfucfcP9VbYyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912959635544.3032229888264; Wed, 27 May 2026 13:15:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKeb-0006xA-HS; Wed, 27 May 2026 16:15:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKeZ-0006s8-QA for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:59 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKeY-0005OU-3f for qemu-devel@nongnu.org; Wed, 27 May 2026 16:14:59 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-452169ae568so7822705f8f.3 for ; Wed, 27 May 2026 13:14:57 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45edb557679sm14753300f8f.10.2026.05.27.13.14.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912895; x=1780517695; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TeblK7/EUpTWApgaalqExSacjBZVjtrb39D4H9GOeNI=; b=LSYyblJyObQ0eaTDCf7C5Q0v0NHMnRvZIwSbw1jPJAmGskcA+jjl0475q1cKi54YTI 05l3p4Hldv+2yPPweCg6mcvuHxEhhg3weYjikkzTfrJePsfh+a2fe1LeQ4wEchrAzIgs 3Py+IosL2p1mmsu4WUuqF8IH2yTwti5kAwv59isPQmlY6f/xLK2HdQHpuQMqS2r4dMi6 8GfrGleb6dOnTyDwvUW3tJAmZyWRpdW7kvzNNbgagav7Kg6VGRjHVeE4A41AyEZMzkNT FSW/FMz6/Uas1QnyEnqVCD0893W5n6oN98dLYVC6QwvmFdSu+9m9PQBjrfotbDrKljVJ 4IHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912895; x=1780517695; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=TeblK7/EUpTWApgaalqExSacjBZVjtrb39D4H9GOeNI=; b=mw94wgAfczQuLHP1D3ZRt4TdxLiu/NcMbE3n8O/m+DfcjVN2Jl76coSAJs0f3EkNPn aEsJa4nBBTwixk61gC4pO9Fyo80A3BfRattrtxx/rlA+4reLEK3BDIMSQuQy379P2rV5 DzsZZNp4aGoqIyftG6DN843lovNash7m3villf5e+rUiqEAy04byBIfd3DGWKikcWWd8 Mm2jKe5wNwh9imIe9XvyUEAl6SoPYxrphaYxd2D4KbpHtuU73W8ZMmivxlIME14eRVrA sC+xUlgvlpN9G40tAfiL7rsoUug5E75DqxMfym96UQcg6RnUUzJusjCeV3use7MgWtCT J9xA== X-Gm-Message-State: AOJu0Yy68Aa0gRr5hLL2J92vL0EqTn87FisjTNcJfZpVY7zauslCq3rL N6W9rv9Zc8XDGDl1GFffTlhB4lAmz3sAj11fL7ZQGdXGfuDC+STDZCinqImd1SwvjyTv1cHfJQi cXifCNd1+UA== X-Gm-Gg: Acq92OF1Kx18e5sX3E3iRji95plNSeK/yBG55ge0g0e5k5v717fhvR76VJOt7m7Iz8h 2oNnkJ8CitxyvM9QxlEGsoKF+yv7H0Sfxwx5whCsIhSwKkd12RSNkisHb4kQb61QLpIfAmJquD+ z2L9/zkEEiHs9XEI3834JOPkrSi/C2aVBH6tEiMl6mA1Kfzoz1QmMj6V/QNte+lAfcPvnccZfyd TcbWNv7otYKY6FGuy7K4RYjiyceIkCxEMO4SIxwJZrB8FizIT9UFRnF2DwNZBWNibwSjjtbAGe8 Uve7xgnfsQYEsJOjJ0WAA95wA9Lto/BkLLX+SZ3a/4njxFdrO8umnGH/qVF5Gi8Jb8qIb4nezy6 m7ZBVf0ZMmHKMf/tH0StnmUoOHo6O82czW6Fzo3eblXAPyC1GG6Ls4jg8xinJkV9shPc1lMlqn9 3nQj8xlZZIo4HeYqwkotZdDt+nHj1tHUuBVvfw2iitlaStsZEF+FyPtROfj03Yyqs3JQ== X-Received: by 2002:a05:6000:2f82:b0:45e:d3d4:c230 with SMTP id ffacd0b85a97d-45ed3d4d1cbmr19415767f8f.38.1779912895146; Wed, 27 May 2026 13:14:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 08/12] hw/riscv/boot: Replace cpu_to_le32() -> const_le32() Date: Wed, 27 May 2026 22:13:44 +0200 Message-ID: <20260527201348.29511-9-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912962000154100 Rather than adapting the array endianness when it it filled, directly initialize the CODE words with the correct endianness. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/riscv/boot.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c6ab1cc8cfb..4297949f6be 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -454,40 +454,36 @@ void riscv_setup_rom_reset_vec(MachineState *machine,= RISCVHartArrayState *harts uint64_t kernel_entry, uint64_t fdt_load_addr) { - int i; const bool rv32 =3D riscv_is_32bit(harts); uint32_t reset_vec[CODE_WORDS + DATA_WORDS]; =20 - /* .text */ - reset_vec[0] =3D 0x00000297; /* 1: auipc t0, %pcrel= _hi(fw_dyn) */ - reset_vec[1] =3D 0x02828613; /* addi a2, t0, %p= crel_lo(1b) */ + /* .text (RISC-V instructions are always little-endian) */ + reset_vec[0] =3D const_le32(0x00000297); /* 1: auipc t0, %pcrel= _hi(fw_dyn) */ + reset_vec[1] =3D const_le32(0x02828613); /* addi a2, t0, %p= crel_lo(1b) */ + reset_vec[2] =3D const_le32(0xf1402573); /* csrr a0, mharti= d */ if (harts->harts[0].cfg.ext_zicsr) { - reset_vec[2] =3D 0xf1402573; /* csrr a0, mharti= d */ + reset_vec[2] =3D const_le32(0xf1402573); /* csrr a0, mharti= d */ } else { /* * The Zicsr extension has been disabled, so let's ensure we don't * run the CSR instruction. Let's fill the address with a non * compressed nop. */ - reset_vec[2] =3D 0x00000013; /* addi x0, x0, 0 = */ + reset_vec[2] =3D const_le32(0x00000013); /* addi x0, x0, 0 = */ } if (rv32) { - reset_vec[3] =3D 0x0202a583; /* lw a1, 32(t0)= */ - reset_vec[4] =3D 0x0182a283; /* lw t0, 24(t0)= */ + reset_vec[3] =3D const_le32(0x0202a583); /* lw a1, 32(t0)= */ + reset_vec[4] =3D const_le32(0x0182a283); /* lw t0, 24(t0)= */ } else { - reset_vec[3] =3D 0x0202b583; /* ld a1, 32(t0)= */ - reset_vec[4] =3D 0x0182b283; /* ld t0, 24(t0)= */ + reset_vec[3] =3D const_le32(0x0202b583); /* ld a1, 32(t0)= */ + reset_vec[4] =3D const_le32(0x0182b283); /* ld t0, 24(t0)= */ } - reset_vec[5] =3D 0x00028067; /* jr t0 */ + reset_vec[5] =3D const_le32(0x00028067); /* jr t0 */ =20 /* .data */ - stq_p(&reset_vec[6], start_addr); /* start: .dword */ - stq_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */ + stq_le_p(&reset_vec[6], start_addr); /* start: .dword */ + stq_le_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */ =20 - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { - reset_vec[i] =3D cpu_to_le32(reset_vec[i]); - } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); riscv_rom_copy_firmware_info(machine, harts, --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912991; cv=none; d=zohomail.com; s=zohoarc; b=e4a7w89ZZlzb3WsDH0XQ54HOe8qOg9onlizPgKZ0eDzNkR/eDwvWgvpBVF83vFy+q7UDzn90xb7fE/DijlIDAn/L/MfDacGSZN34GZFCvx/n4G4R7bmWgAAP47z98X4gznDocjHVuULSAxrGHhZeCsexkCYSJoFYiyqxHxo/N2U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912991; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Hk3lZmLUM148KRJytCSWPjv/9H9/R4UDf3r1IZOQ7wI=; b=Q0bV31/xut9fhduDUoeHjPqK2vcTdpftUnJn7Kql6RR6jmcxBWcwD11zsEGLWvkBIoJ8hFOzLea8LPI1oYFU9PMWNjnEPtErpuWwpzpHX8bN7pO5IM4FXkdv2LT4EF2H2ZdrTreSCKdirSHYyQLQ2Vs0l+R83HX2yZ2l1f40suM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912991371386.43077354595175; Wed, 27 May 2026 13:16:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKei-0007IN-Ko; Wed, 27 May 2026 16:15:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKeh-0007Ds-9M for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:07 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKee-0005UO-96 for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:06 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-48a3e9862f0so63868455e9.1 for ; Wed, 27 May 2026 13:15:03 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4908eab248csm259365e9.14.2026.05.27.13.15.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912903; x=1780517703; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hk3lZmLUM148KRJytCSWPjv/9H9/R4UDf3r1IZOQ7wI=; b=a0QP1rluNDFD3qbiqURROT3IoJLqDDQmDfbHCDUKqtR/uiKcOkM6hNM7cpW1YOgqHC cyfyt71sdTBHh6PsVTfa6n/kMdLYfYP4xqYJmamOUJ+K0zboo/X5NMjXmZV+yT75wrLl PwErSs9h4rq1paHG1u5+BT/h0N/1kN0ntcYK2URINbZQvM1XXOQyy0ZJu85a6w7y6hwL EbOKgbuXTgtolS8Q7Y9BTiXzLc9nKxaDa6hElCUCvXRsanCiaU8z0K+zDx2h0Q4vYVCN zb+9ykGH+MQHFgp8YHLoHNW8DjvGtMHpU5XyfEtpL8sKJYBzJyuli+3oZ6Vm+Mxn0zOg iLmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912903; x=1780517703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Hk3lZmLUM148KRJytCSWPjv/9H9/R4UDf3r1IZOQ7wI=; b=g9F8whbAvXevnY374wLycDH4UlMiA+ZKIFaCwrvn6K2z2dYHuw24H/s4mxY+3gZURk SuFGQDemFlnYiEfzVyKEDM8kNdVvjZ8zjpCdQbpkV+l7Plm/aFNa1hXAyxOuf1la3zvn xmQFZjMqq9rG8Fd7BG45PhwyiDV9L1PW85M8DHqtsQrnxREd7l6dTiekFKaSvQ2zWl7B QlVLF0DxmmyExvyrmk3v/gJBoAM9n2Oy6ziozWZOa/mLv1AjfUGo+lUXwIGwfatvMgYY yk8wReheG5/aBCtq92X/jX3qNZ7gY9nBz5iawgqlctX6L6+4bm+X1LE1rsobyH1Mw9Ry rjxQ== X-Gm-Message-State: AOJu0YwKpWMPz9Reqk11FEIQPem4cFCpsbTMDwNu9UDke/6yXXBgefWi SsqTMErvSqZAIMSVFTbdOA57hrzU8r7UPX72th0AWtbOuFIeD+ftn9aSnDadvCI+Z77TBbrC3Gj SjCCTRZMn+w== X-Gm-Gg: Acq92OERYfBEJS//jsOb/8atnZsLmd6gVnq18vGznSdbCwdIXTBk9TznS+R3uOFoQfk pU7RKeu7qZSO8tCgEk2P9pMofAKYq5zJHtYCC9uYEDNGODQD6LlITUOfZcgpVuAYQjU2ISMlz7i Q04JCZc6rR5hKPu3dGCPP6oZjulkepIdcnwvFKMepMkdK/LR5UsbhUzkico+3n30JQPC2MVZHHh 6zfwGnPZc1YHvcA0CDmKc4O2DYJHI27S5wL2o2NdRzzbZaL38hRrGOIfprSbUdyE9ODXAO2wPo1 hEhWNYucbLI1fVL8QLbqFaNb6+9py9MKt1KANygnYZimU+6B3MNjMukHpRDsBt9IEw0ukHCRZHx OQd5qpQN1Q6PQ7Vu9pDa2bWdtebRtEmvamuxwsu2KxXDi9fi0xCknrREAvRXqTyG/9J/8gXPFL0 /7m5BpqU6mGjX9mFO+QtWBYoolQ7YeWy8f5ZVB9T39yDorbM/iXivykkrzP8UDq87JpjBJL9M1x vzE X-Received: by 2002:a05:600c:1992:b0:48a:79d8:a8d6 with SMTP id 5b1f17b1804b1-4904245f54cmr327778735e9.7.1779912902617; Wed, 27 May 2026 13:15:02 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , Djordje Todorovic , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 09/12] target/riscv: Add big-endian CPU configuration field and reset logic Date: Wed, 27 May 2026 22:13:45 +0200 Message-ID: <20260527201348.29511-10-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912992517154100 From: Djordje Todorovic Add a big_endian field to RISCVCPUConfig and wire it into the CPU reset path. When cfg.big_endian is set, riscv_cpu_reset_hold() writes 1 into the MSTATUS MBE/SBE/UBE fields using set_field(); otherwise it writes 0. This makes the reset value deterministic on both cold and warm reset. This models fixed-endian harts, not mixed-endian implementations where the guest can toggle MBE/SBE/UBE at runtime. The MBE/SBE/UBE bits are not included in the writable mask of any mstatus/mstatush/sstatus CSR write path (unchanged by this series), so the value chosen at reset is effectively hardwired per section 3.1.6.5 of the RISC-V Privileged Specification. The user-facing property and documentation are added in a later patch, once the full endianness support is in place. Signed-off-by: Djordje Todorovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/cpu.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 734fa079f28..9eb47af0a76 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -157,6 +157,7 @@ BOOL_FIELD(ext_xmipscmov) BOOL_FIELD(ext_xmipslsp) BOOL_FIELD(ext_xlrbr) =20 +BOOL_FIELD(big_endian) BOOL_FIELD(mmu) BOOL_FIELD(pmp) BOOL_FIELD(debug) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 52f143f1cd4..fef424f2bf9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -739,6 +739,13 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 1); } } + /* + * Model fixed-endian harts: MBE/SBE/UBE are initialized from the + * CPU configuration and are intentionally not writable via status CSR= s. + */ + env->mstatus =3D set_field(env->mstatus, MSTATUS_MBE, cpu->cfg.big_end= ian); + env->mstatus =3D set_field(env->mstatus, MSTATUS_SBE, cpu->cfg.big_end= ian); + env->mstatus =3D set_field(env->mstatus, MSTATUS_UBE, cpu->cfg.big_end= ian); env->mcause =3D 0; env->miclaim =3D MIP_SGEIP; env->pc =3D env->resetvec; --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912960; cv=none; d=zohomail.com; s=zohoarc; b=WDCNmwo0JQimNT/dKJJVPHc6iBgbBU+M61n5wgl4Yl56Lx6mXONZ8nQsLvNDTJKJy1NWQILPbHE50RgVVHKexOueUG8DS4dtPjA84L03Zsf3BA84yw+YvNQgnjtaVeEXVD6Rt4r7GyKl6ZKyqyiR93lnm9cyINoSbwZWFzfDtMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912960; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Qu8O8rtS738a8Ucf54GvfcNN/jmoBkFJcUUMjuQGH6U=; b=dvP4sxoh5W9y1Az4zx7XAUGYjDnVhsuScoIYbUeppgjQGWYIZwhflKkma/LIXB8jtZJdpWaVuNKuEnSFbfKqvdB8cVlG8y49zd8w/oEg0wVQDfICazEJuEiT4nzH+d6kvuTeMpmkeHFbOkvfxqz19X9BgVeTbtLu4xRhBxxp+9s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912960965120.12378767444739; Wed, 27 May 2026 13:16:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKeq-0007fY-QF; Wed, 27 May 2026 16:15:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKep-0007cM-KZ for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:15 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKen-0005ck-3O for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:15 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-45ee1a56328so230674f8f.3 for ; Wed, 27 May 2026 13:15:12 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45edb54a432sm11756563f8f.3.2026.05.27.13.15.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:15:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912911; x=1780517711; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qu8O8rtS738a8Ucf54GvfcNN/jmoBkFJcUUMjuQGH6U=; b=Pm2GKr2GEscF7enPwXigzaaHHUn3RQyYH4AuN9shWFC7MTdt4JEMSDZPgi3bSay4MY 7wl+LKlyXlMN388BHOnXaurezgeCdA/A7P4h1U+Z56H8gyHky6XiPmDzzqQJzDd23si+ ++y6IR7S9FLTlNmg2s13sdhnX2baoglQNY/iWtiCeSl3ckwLZdAEv0mZSwxHc4bczEm7 dDPg0ryFbL9I4k3aq7tcCCLx6Z3LUQ8YUSfKlQfg+FVWU3ikCKVO+D6y4BeSSQGlrA2R FhEcLvs9AUl7GY3K7XByASUT32E4Gl2g3ZgxfiaT5x+A+Fg6BdwzSduANjFsdFnnQrv8 M0nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912911; x=1780517711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Qu8O8rtS738a8Ucf54GvfcNN/jmoBkFJcUUMjuQGH6U=; b=ituM1S95m35GKtEG5oYtotA7J9IPCDVEhQ/GapooXUQH7CUKiGuI5x8m1we3siAHdE DcrMDyYmwlOG6eCnE3xyNm/QZ+w7UhDiIVAvYBf3fNsq/BJi+kuBuaDHioH+AeLyEVuv cTTOI1CW2ddo4C0LwV7AdDr5VVdW4bjO+Yz/Q/D1S4QAMJ0sHfZTr0hpwwKWDDLzcYYO IoxQv+3m061+sCtuNqVPR/RQkBTsgM2FADgv6x5frxP97RqdTvMlcMa+0L12UnAnx135 5uEX+x5KcxxXCwGy//p3OI+Bi4fBXvmEmpZqiFi746uWNTYyhbsuwZHJSORSYIJWTF8h FQaQ== X-Gm-Message-State: AOJu0Yzp9bYH6R9Rw9xW/EhUI42K20PPNYtu/GbeNgKG/wtytoNCbWv6 YLV2xJmGm972GjHd2Rure8mz0aL67uhJ2x8CptKtouc/JDZZQJ6baR1QLdsdLiPLcC1QTXPrjXy sxLQwhz3IvA== X-Gm-Gg: Acq92OGYza0IMbT/MRTc58viC5SQdkAgEdQKnmlSQfDXrhjTsK01vUekASGEwj0SFBj xQvTjVp7Fmc1NGXM7sYlWsYh4iQgqTibiDvr1l+cDbRQf3KSgaeUc/bn1hHjfktmJVIZP8cHtCh j1bvjhx6hAxuqDoFE1/G1rxTKUT4TSYrQqlZy1WuNSRdzc41uunMSJYxgWfAM6fY30K2KMjeyIq XdPF2LET2sC6eR1+tmIHenM7V8TWIsJmcPLa+MBllCBhQgD7piUaC7BnjQQw5KzRmQrQHBPAdOp ZH2//1r+GnD+jmTim4RNj/vZHzmWlAhpWzcuTv8SW20xbsZWPOWc3x/r1v9X9FInjlN5+fbxham LBxrUhrP26a2tgxi8QEUtFFxUKzf6ddZDzrSnnHS330ACb2N/12GxH8LA3vJ+szTQEE4mvAw3CN KkJcKASdu1pKolKv5LkhdbpYrXemMAU2+pHh5r76EyOJYXDU6Vguyf4ElY4dvgOETX82/XzWZFY qU+ X-Received: by 2002:a05:6000:468c:b0:45e:dabf:a00e with SMTP id ffacd0b85a97d-45edabfa2d2mr5891652f8f.31.1779912910665; Wed, 27 May 2026 13:15:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , Djordje Todorovic , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 10/12] hw/riscv/boot: Honour data endianness Date: Wed, 27 May 2026 22:13:46 +0200 Message-ID: <20260527201348.29511-11-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912963011158500 From: Djordje Todorovic Check the hart endianness property and use it throughout the boot code: - ELF loading: pass ELFDATA2MSB or ELFDATA2LSB based on endianness - Firmware dynamic info - Reset vector: instructions (entries 0-5) remain always little-endian, data words (entries 6-9) use target data endianness. Signed-off-by: Djordje Todorovic Co-developed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/riscv/boot.c | 40 ++++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4297949f6be..7c9cd614681 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -407,21 +407,31 @@ void riscv_rom_copy_firmware_info(MachineState *machi= ne, struct fw_dynamic_info64 dinfo64; void *dinfo_ptr =3D NULL; size_t dinfo_len; + const bool rv32 =3D riscv_is_32bit(harts); + const bool be =3D harts->harts[0].cfg.big_endian; =20 - if (riscv_is_32bit(harts)) { - dinfo32.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo32.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); - dinfo32.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo32.next_addr =3D cpu_to_le32(kernel_entry); + if (rv32) { + dinfo32.magic =3D be ? cpu_to_be32(FW_DYNAMIC_INFO_MAGIC_VALUE) + : cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo32.version =3D be ? cpu_to_be32(FW_DYNAMIC_INFO_VERSION) + : cpu_to_le32(FW_DYNAMIC_INFO_VERSION); + dinfo32.next_mode =3D be ? cpu_to_be32(FW_DYNAMIC_INFO_NEXT_MODE_S) + : cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo32.next_addr =3D be ? cpu_to_be32(kernel_entry) + : cpu_to_le32(kernel_entry); dinfo32.options =3D 0; dinfo32.boot_hart =3D 0; dinfo_ptr =3D &dinfo32; dinfo_len =3D sizeof(dinfo32); } else { - dinfo64.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo64.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); - dinfo64.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo64.next_addr =3D cpu_to_le64(kernel_entry); + dinfo64.magic =3D be ? cpu_to_be64(FW_DYNAMIC_INFO_MAGIC_VALUE) + : cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); + dinfo64.version =3D be ? cpu_to_be64(FW_DYNAMIC_INFO_VERSION) + : cpu_to_le64(FW_DYNAMIC_INFO_VERSION); + dinfo64.next_mode =3D be ? cpu_to_be64(FW_DYNAMIC_INFO_NEXT_MODE_S) + : cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo64.next_addr =3D be ? cpu_to_be64(kernel_entry) + : cpu_to_le64(kernel_entry); dinfo64.options =3D 0; dinfo64.boot_hart =3D 0; dinfo_ptr =3D &dinfo64; @@ -455,6 +465,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, R= ISCVHartArrayState *harts uint64_t fdt_load_addr) { const bool rv32 =3D riscv_is_32bit(harts); + const bool big_endian =3D harts->harts[0].cfg.big_endian; uint32_t reset_vec[CODE_WORDS + DATA_WORDS]; =20 /* .text (RISC-V instructions are always little-endian) */ @@ -480,9 +491,14 @@ void riscv_setup_rom_reset_vec(MachineState *machine, = RISCVHartArrayState *harts } reset_vec[5] =3D const_le32(0x00028067); /* jr t0 */ =20 - /* .data */ - stq_le_p(&reset_vec[6], start_addr); /* start: .dword */ - stq_le_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */ + /* .data (must match the firmware's data endianness) */ + if (big_endian) { + stq_be_p(&reset_vec[6], start_addr); /* start: .dword */ + stq_be_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */ + } else { + stq_le_p(&reset_vec[6], start_addr); + stq_le_p(&reset_vec[8], fdt_load_addr); + } =20 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912993; cv=none; d=zohomail.com; s=zohoarc; b=R7nZZfAclafLxOZ4LO4JCzxgPTd68B/Wr6VMzVW11k3WvPeJVE/XkYREAxh/jLwTmBRpCw6npyEurhofRP1didKUnYZ9RyPG7Ut7b/TTybiyAzAlqEZSQFJ+LoqJszWSaHSCJsaW3BdiBQBBOej3fqGaL65BkT344BM1FK/A03Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912993; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3SwaiZ85vx51Jxqz+Ao7fBPYHCfcHkKwY4wASWC2Ft8=; b=GwhxAaT27sRc2Vqo9HsvCSrEUBcmTTwZZ7L5ixA7U8gx81lvMcQjMvBcHVaskr+6v2p6RLZBrSCFU03P3aLFWMrYkmnwNm5hlWDbkQhWinfh/UV1r46CG7RkqOWbWI4ZqeWA3w9iR8kLxZMUjASEHsPNKwLSSJyVuBQcreisCJ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779912993643116.02086297334836; Wed, 27 May 2026 13:16:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKex-00084h-IE; Wed, 27 May 2026 16:15:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKew-00081g-Gw for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:22 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKeu-0005fj-Hq for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:22 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-45ee1a4cd2dso144972f8f.1 for ; Wed, 27 May 2026 13:15:20 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45edb5a2a73sm8162405f8f.22.2026.05.27.13.15.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:15:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912919; x=1780517719; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3SwaiZ85vx51Jxqz+Ao7fBPYHCfcHkKwY4wASWC2Ft8=; b=Y/cba+Bh6ToeQN4+6iNbKQFXNMaKsFa5csh+qJifwtc7GqThlLY/kbyT9JAcEgFTzb Dp8KGrYx0d4YQQBBJXPfhN/LCU1i/2zf0TMjWvYWpoHeFC4KrJeT+UlhL/x4XS64TC5t g7hlCmpxVjXniOkHPsw1+PMO5Tr79kZYkNs3AGM/XffbzgmfJ5KzpR/ZftLNoM4DTy6A zyby/1M1ZWOhQV/S9n7uNX6fLFTWGI89quIvHGFC8pN1YDG9Iw4rGVw5yPzJ6r56Fdgt XZSMLiZR8Dow/3NK4NC4tEJvOmV+VSQNBmdvS9mRoNp9x20ZD/WAU6ua6ueS7YXz/iCr 6U4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912919; x=1780517719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=3SwaiZ85vx51Jxqz+Ao7fBPYHCfcHkKwY4wASWC2Ft8=; b=HIa7sekEJOBQb43Ago+g5EfWoNbN54CC0bDrlNFcWAWC7H6QGJAoU/TWch2DhB4HD6 rIVrnkhPfFA2LsJ75llo9nUI+4ybIAXjMpeQMoPHcUCcw0fABuzC/+8pwE2vTTw1KHw9 +SsgslE4bKbAOMAUBG6p3dtuM02FBE0hCUxBJpHUDYA+2FRY+umD3uf0KIxtbPyz0uIH iwen6i1siUOHr25syz1YPOuamiFBvrUvE5mJBlq5zoIs5rncIG+MBnaGf8ZPu5Qb1Y9P pjgvOC118q1QLESkTogOxk9mB0nFmT4OuAP7VqeE7LuzRMSZe7Il06psuf0YLIidSccF xVhA== X-Gm-Message-State: AOJu0YzA1BDgtGFmX7VqwTV6gjpV6PNFxAW1jSRDXLQ6M1QGtPmGrMAN c1lDAN/QPRRFdfR2E5OzJiF4Go+TBucSHqIJx5XLVEGo1625aXdW5BUmn2xTeM1nroS6Wj2SSDP zRGSCMvTBqg== X-Gm-Gg: Acq92OFQ/FCZ4jo00R9uvO2aqUipRdzBrRpiSj5Qvy3qAEDMXBNxSHS2azH7BemTd/E ecilu5nKf2Fc2Krins/Lyj7KqprcbaWSQzDx+iAZ7TFFhZm54+1sjX0/aU2zLnZsbkf8GKqmLbw Y6Hk55QCP26K/hQw+q4KLM3bZ5lMlWwvUNRwzHus/OVd5dSd8Yc61CVcP0TEUTeabt3JMBpg7wG tN/jO7JnmMjSCqX6bBjmIP4wSbhyifHCJwwC0O6XWl1Fhr945Iy+qWMvirpJsjGZ9mTMrVjsUaz x3QXz3GqV6VUHTlDgRlHqQJ++G+hUukoLvIf9lV9ng40KRDKc7hPMhuH3F0dK6Reu9HtMvdMaFa BDhvUIRrv+BZUU8jaFQFrYik//U6yNna5aA35L16XZEdIHH7uCmtq1sHqck+WpwIqitDUND0r+a UFxdtFdO7vnjJVnLCyy8jVH76HLbR4YFxWADCnbeFrxcs3md9ziXOOjH168gLRkbi0KQ== X-Received: by 2002:a05:6000:18af:b0:45e:9304:a4c3 with SMTP id ffacd0b85a97d-45eb333aa31mr36621337f8f.19.1779912918629; Wed, 27 May 2026 13:15:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , Djordje Todorovic , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 11/12] target/riscv: Expose and document the CPU 'big-endian' property Date: Wed, 27 May 2026 22:13:47 +0200 Message-ID: <20260527201348.29511-12-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912994633154100 From: Djordje Todorovic Now that the full big-endian data path is in place (runtime MSTATUS bits, boot code, and page-table walks), expose the "big-endian" property to users via DEFINE_PROP_BOOL and document it in docs/system/target-riscv.rst. Document that the property models fixed-endian hardware: it selects harts whose MBE/SBE/UBE fields are fixed to 1, and it does not model a mixed-endian implementation where software can toggle those bits at runtime. The property can be enabled from the command line, e.g.: -cpu ,big-endian=3Don Signed-off-by: Djordje Todorovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- docs/system/target-riscv.rst | 29 +++++++++++++++++++++++++++++ target/riscv/cpu.c | 1 + 2 files changed, 30 insertions(+) diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 3ad5d1ddafb..afd86ca2ba1 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -95,3 +95,32 @@ the images they need. * ``-bios `` =20 Tells QEMU to load the specified file as the firmware. + +RISC-V CPU endianness +--------------------- + +The RISC-V ISA specifies that instruction fetches are always little-endian, +while data accesses can be either little-endian or big-endian under control +of the MSTATUS ``MBE``/``SBE``/``UBE`` bits (see section 3.1.6.5, "Memory +Endianness", in the RISC-V Privileged Specification). + +QEMU implements the full data-endianness behaviour described by those bits. +In addition, the RISC-V CPU object exposes a ``big-endian`` boolean proper= ty +which models a big-endian-only hardware implementation, where the +``MBE``/``SBE``/``UBE`` bits are hardwired to 1. When the property is set, +the CPU is reset with all three bits initialised to 1, so the guest starts +executing in big-endian data mode from the reset vector. The property is a +static, per-CPU hardware configuration option and is not meant to be toggl= ed +at runtime. + +The property does not model a mixed-endian implementation where software c= an +toggle ``MBE``/``SBE``/``UBE`` at runtime. QEMU's RISC-V CPUs treat these +fields as fixed by the CPU configuration: they are reset to 0 by default a= nd +to 1 when ``big-endian`` is enabled. + +The property can be enabled from the command line, for example:: + + -cpu ,big-endian=3Don + +No upstream CPU model currently defaults to big-endian; the property is +provided so that big-endian-only RISC-V CPU variants can be modelled. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fef424f2bf9..c8a41c57a57 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2520,6 +2520,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { =20 static const Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false), =20 {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ --=20 2.53.0 From nobody Sat May 30 17:31:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1779912970; cv=none; d=zohomail.com; s=zohoarc; b=ZNK/fr9JT9um2AYfTRdYIHBHOYW23LVqOatLWGjjT+bjpJbjoPomh0wovwDzLE9DmQS/11hJ7EFr119CW/eUxnSm8ym1fUZUdCht0o+skz2D6WR0KWsPOP8/Y9nTHMN13LQR7Ef2pzMEHmY2lVs+JgSpVunAA3BtEPUNFmFJZcE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779912970; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b8I4Uj8QzoYfgxdM3WVJzGYEDhLFU1gsMiq89h2j04Y=; b=bF/qmulaTxjIC+qDRFf85f70MksJtfQCS3VlRgehmHoAWwMl1xIkC+2cv9Kkq2Lc/EzQYVVQ4taCTlzBEwTdEJBmdk9IOE2vqrNPRaTR2o2WLs06YN6As07VPRsHmiuNvNYjqkTyeo4HtZQdRei07x+O8bQeEChOEGUUkz0O5ek= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17799129703891.1692590712244737; Wed, 27 May 2026 13:16:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wSKfT-0008SS-2P; Wed, 27 May 2026 16:15:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wSKf5-0008Ex-0j for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:32 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wSKf2-0005hi-NW for qemu-devel@nongnu.org; Wed, 27 May 2026 16:15:30 -0400 Received: by mail-wr1-x444.google.com with SMTP id ffacd0b85a97d-43d76dd4ee8so7374427f8f.2 for ; Wed, 27 May 2026 13:15:28 -0700 (PDT) Received: from m17.home (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45edb5c1e59sm7714019f8f.33.2026.05.27.13.15.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 27 May 2026 13:15:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779912927; x=1780517727; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b8I4Uj8QzoYfgxdM3WVJzGYEDhLFU1gsMiq89h2j04Y=; b=XDFwQHo0k2oD+p8403JXgsdeKnR8HsoArOjrehWwUsTfgXu0bcycS2Tn211A22+8a9 jOQWfsisoJ5xuexyAsAJpi3bl44o8DgUnrQ4wpnztMJP9joczWHMXRiFvZ6QWM68nEtg w8DJIEt8L86VkJV06f0L7PeW5n1SP2Tvw2YtAm9N9gkHrTtEPr5vr0eMLXJRl03VTDew joNSc1YWzzY9ACTG6RaR3JKMpK01Xl+HJDhjtcHmQIJbsAqAMvw1+ShsgvKMONiCMphC +fD9ptuR9X2cr0sKgJZ4n/cPByZg8og6zNHkbMV0qT/fPI/4t0Cp+uRhmKvR1x5aMqlS xZaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779912927; x=1780517727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=b8I4Uj8QzoYfgxdM3WVJzGYEDhLFU1gsMiq89h2j04Y=; b=CJg7uYO59W649QcLyNvCMdSj9icnmCesjQkLsTFrwumTJdsMpxHHYkBeZ/nkSi5Tzg X7S2ooT9Emf6fPBzmfcCqsQLrDvxJ+m7Bg3efP73m6BiW7UsVX4M+wLdq2439MSkX4Ax ZNEWZvH01YSspVX9WNkIJfFIAjXI7UlIalrkvdLjXDdzPLJrVDXPOUYAPSg7GKkHi/GR yM1qAUkCaC0wzokQbXVsHyT5BUiToISWOXzTkbyLBtbiNiC4L/1FYYioxN9aQXu7oeSV 5h1/RDryLAYdicEDJ5BwgvDVSGoOa/7OvWqA/GORYIgPpXipOGCLalPPA1dys/wO9NEf 9gxA== X-Gm-Message-State: AOJu0YzK0AWN0fEMR3ssVbrUXXJopS9txwbTyNACOLId6hYXW7heDKdo l4636AhPtchCGUq9FGRQqfVY4YCxE3QMdfD+zA0fYKyXY+WutKxBYDfSeTD7NqNrNdJQynG8W19 6vvv7n6yxCGyv X-Gm-Gg: Acq92OFB2/cJnSwaiBQCDOEFyDlnZl+OWVfDi4DcZ0cI6pmMZrfLgYapl99SZtC0ks0 ei2t0zhIKHzWAPP1wA6dV1Yixq5Epui4dMe4sm93YeFTCmsN+fFVUe2FDveCCCH4rlGO3oW5lth VorBHVHqaAd2WI2nBDtmAIgAEex3A/Skbdh0CY0bpevwI8AmI0ri4GjxayLR8azCYU4AhuRQd59 BBxFvNBX2vIwnTJ8hTpj6aSxLGzynA0Y2fDxjt8gKXJKhqmof4BLiS1r4rMXGCF9vNOFx4oq46k LPl5QY9Zh+t1b5S5yBbieaFwTZOS/QRlRnB+XNDK/A3aFQ+SwnzyS+W6Z6wR5D1APwpnsnTkoGj 2U6/GP8m4DOBWeBKky/+53esNNmsoN3qM3KG7eCrMQqPLtCimdQ2/cEf+fIWYI3fR2lsqeIvWz/ ukUMBdKOF5ByLgKSHkw9J/McEOJ5Wr83F2KeJWzNXDmR5RCdxFDXc6+mCwNdQX33R/zQ== X-Received: by 2002:a05:6000:400d:b0:43d:71b:204b with SMTP id ffacd0b85a97d-45eb38c2367mr43530079f8f.39.1779912927037; Wed, 27 May 2026 13:15:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-riscv@nongnu.org, Djordje Todorovic , Anton Johansson , Weiwei Li , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Christoph Muellner , Djordje Todorovic , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 12/12] tests/functional: Add RISC-V endianness test Date: Wed, 27 May 2026 22:13:48 +0200 Message-ID: <20260527201348.29511-13-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260527201348.29511-1-philmd@linaro.org> References: <20260527201348.29511-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philmd@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779912972202154100 From: Djordje Todorovic Add functional test for the RISC-V 'big-endian' CPU property. Signed-off-by: Djordje Todorovic Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_endianness.py | 57 +++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 tests/functional/riscv64/test_endianness.py diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index b996c89d7df..5871211e899 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -11,6 +11,7 @@ tests_riscv64_system_quick =3D [ ] =20 tests_riscv64_system_thorough =3D [ + 'endianness', 'boston', 'sifive_u', 'tuxrun', diff --git a/tests/functional/riscv64/test_endianness.py b/tests/functional= /riscv64/test_endianness.py new file mode 100644 index 00000000000..9e0b3b7db5c --- /dev/null +++ b/tests/functional/riscv64/test_endianness.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# +# Functional tests for RISC-V big-endian support +# +# Copyright (c) 2026 MIPS +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern + + +class RiscvBigEndian(QemuSystemTest): + """ + Tests for RISC-V runtime big-endian data support. + + Uses a bare-metal RV64 ELF that detects data endianness at runtime + by storing a 32-bit word and reading back byte 0. Prints "ENDIAN: BE" + or "ENDIAN: LE" to the NS16550A UART on the virt machine. + """ + + timeout =3D 10 + + ASSET_BE_TEST =3D Asset( + 'https://github.com/MIPS/linux-test-downloads/raw/main/' + 'riscvbe-baremetal/be-test-bare-metal.elf', + '9ad51b675e101de65908fadbac064ed1d0564c17463715d09dd734db86ea0f58') + + def _run_bare_metal(self, big_endian=3DFalse): + self.set_machine('virt') + kernel =3D self.ASSET_BE_TEST.fetch() + self.vm.add_args('-bios', 'none') + self.vm.add_args('-kernel', kernel) + if big_endian: + self.vm.add_args('-cpu', 'rv64,big-endian=3Don') + self.vm.set_console() + self.vm.launch() + expected =3D 'ENDIAN: BE' if big_endian else 'ENDIAN: LE' + wait_for_console_pattern(self, expected) + + def test_bare_metal_littleendian(self): + """ + Boot bare-metal ELF on virt with default little-endian CPU. + Expects "ENDIAN: LE" on UART. + """ + self._run_bare_metal(big_endian=3DFalse) + + def test_bare_metal_bigendian(self): + """ + Boot bare-metal ELF on virt with big-endian=3Don CPU property. + Expects "ENDIAN: BE" on UART. + """ + self._run_bare_metal(big_endian=3DTrue) + + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.53.0