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a="90988074" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988074" X-CSE-ConnectionGUID: IaNpUcevTnqBqv3/bZhwCw== X-CSE-MsgGUID: b2inOO3vR1+l9Gwcf9GSjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086659" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 01/17] vfio/iommufd: Extend attach/detach_hwpt callback implementations with pasid Date: Wed, 27 May 2026 01:46:39 -0400 Message-ID: <20260527054658.1021096-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860917884158500 For attachment with pasid, pasid together with flag VFIO_DEVICE_ATTACH_PASID should be passed in. Define IOMMU_NO_PASID to represent device attachment without pasid same as in kernel. The implementation is similar for detachment. Suggested-by: Shameer Kolothum Thodi Suggested-by: Nicolin Chen Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Nicolin Chen Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Shameer Kolothum Tested-by: Xudong Hao --- include/hw/core/iommu.h | 3 +++ hw/vfio/iommufd.c | 44 +++++++++++++++++++++++++---------------- hw/vfio/trace-events | 4 ++-- 3 files changed, 32 insertions(+), 19 deletions(-) diff --git a/include/hw/core/iommu.h b/include/hw/core/iommu.h index cd59a367ce..7fb5c81c9f 100644 --- a/include/hw/core/iommu.h +++ b/include/hw/core/iommu.h @@ -30,4 +30,7 @@ enum host_iommu_quirks { HOST_IOMMU_QUIRK_NESTING_PARENT_BYPASS_RO =3D BIT_ULL(0), }; =20 +/* ABI constant: IOMMU_NO_PASID must always be 0 (keep in sync with kernel= ) */ +#define IOMMU_NO_PASID 0 + #endif /* HW_IOMMU_H */ diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index df148a49a7..f86f6f0d7b 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -20,6 +20,7 @@ #include "trace.h" #include "qapi/error.h" #include "system/iommufd.h" +#include "hw/core/iommu.h" #include "hw/core/qdev.h" #include "hw/vfio/vfio-cpr.h" #include "system/reset.h" @@ -305,43 +306,48 @@ out: return ret; } =20 -static int iommufd_cdev_attach_ioas_hwpt(VFIODevice *vbasedev, uint32_t id, - Error **errp) +static int iommufd_cdev_pasid_attach_ioas_hwpt(VFIODevice *vbasedev, + uint32_t pasid, uint32_t id, + Error **errp) { int iommufd =3D vbasedev->iommufd->fd; struct vfio_device_attach_iommufd_pt attach_data =3D { .argsz =3D sizeof(attach_data), - .flags =3D 0, + .flags =3D pasid =3D=3D IOMMU_NO_PASID ? 0 : VFIO_DEVICE_ATTACH_PA= SID, + .pasid =3D pasid, .pt_id =3D id, }; =20 /* Attach device to an IOAS or hwpt within iommufd */ if (ioctl(vbasedev->fd, VFIO_DEVICE_ATTACH_IOMMUFD_PT, &attach_data)) { error_setg_errno(errp, errno, - "[iommufd=3D%d] error attach %s (%d) to id=3D%d", - iommufd, vbasedev->name, vbasedev->fd, id); + "[iommufd=3D%d] error attach %s (%d) pasid %d to = id=3D%d", + iommufd, vbasedev->name, vbasedev->fd, pasid, id); return -errno; } =20 - trace_iommufd_cdev_attach_ioas_hwpt(iommufd, vbasedev->name, - vbasedev->fd, id); + trace_iommufd_cdev_pasid_attach_ioas_hwpt(iommufd, vbasedev->name, + vbasedev->fd, pasid, id); return 0; } =20 -static bool iommufd_cdev_detach_ioas_hwpt(VFIODevice *vbasedev, Error **er= rp) +static bool iommufd_cdev_pasid_detach_ioas_hwpt(VFIODevice *vbasedev, + uint32_t pasid, Error **er= rp) { int iommufd =3D vbasedev->iommufd->fd; struct vfio_device_detach_iommufd_pt detach_data =3D { .argsz =3D sizeof(detach_data), - .flags =3D 0, + .flags =3D pasid =3D=3D IOMMU_NO_PASID ? 0 : VFIO_DEVICE_DETACH_PA= SID, + .pasid =3D pasid, }; =20 if (ioctl(vbasedev->fd, VFIO_DEVICE_DETACH_IOMMUFD_PT, &detach_data)) { - error_setg_errno(errp, errno, "detach %s failed", vbasedev->name); + error_setg_errno(errp, errno, "detach %s pasid %d failed", + vbasedev->name, pasid); return false; } =20 - trace_iommufd_cdev_detach_ioas_hwpt(iommufd, vbasedev->name); + trace_iommufd_cdev_pasid_detach_ioas_hwpt(iommufd, vbasedev->name, pas= id); return true; } =20 @@ -363,7 +369,8 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, /* Try to find a domain */ QLIST_FOREACH(hwpt, &container->hwpt_list, next) { if (!cpr_is_incoming()) { - ret =3D iommufd_cdev_attach_ioas_hwpt(vbasedev, hwpt->hwpt_id,= errp); + ret =3D iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, IOMMU_NO= _PASID, + hwpt->hwpt_id, errp); } else if (vbasedev->cpr.hwpt_id =3D=3D hwpt->hwpt_id) { ret =3D 0; } else { @@ -442,7 +449,8 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, return false; } =20 - ret =3D iommufd_cdev_attach_ioas_hwpt(vbasedev, hwpt_id, errp); + ret =3D iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, IOMMU_NO_PASID, = hwpt_id, + errp); if (ret) { iommufd_backend_free_id(container->be, hwpt_id); return false; @@ -495,7 +503,8 @@ static bool iommufd_cdev_attach_container(VFIODevice *v= basedev, =20 /* If CPR, we are already attached to ioas_id. */ return cpr_is_incoming() || - !iommufd_cdev_attach_ioas_hwpt(vbasedev, container->ioas_id, er= rp); + !iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, IOMMU_NO_PASID, + container->ioas_id, errp); } =20 static void iommufd_cdev_detach_container(VFIODevice *vbasedev, @@ -503,7 +512,7 @@ static void iommufd_cdev_detach_container(VFIODevice *v= basedev, { Error *err =3D NULL; =20 - if (!iommufd_cdev_detach_ioas_hwpt(vbasedev, &err)) { + if (!iommufd_cdev_pasid_detach_ioas_hwpt(vbasedev, IOMMU_NO_PASID, &er= r)) { error_report_err(err); } =20 @@ -929,7 +938,8 @@ host_iommu_device_iommufd_vfio_attach_hwpt(HostIOMMUDev= iceIOMMUFD *hiodi, { VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(hiodi)->agent; =20 - return !iommufd_cdev_attach_ioas_hwpt(vbasedev, hwpt_id, errp); + return !iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, IOMMU_NO_PASID, + hwpt_id, errp); } =20 static bool @@ -938,7 +948,7 @@ host_iommu_device_iommufd_vfio_detach_hwpt(HostIOMMUDev= iceIOMMUFD *hiodi, { VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(hiodi)->agent; =20 - return iommufd_cdev_detach_ioas_hwpt(vbasedev, errp); + return iommufd_cdev_pasid_detach_ioas_hwpt(vbasedev, IOMMU_NO_PASID, e= rrp); } =20 static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *hiod, void *opaque, diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events index 2049159015..8dbb477298 100644 --- a/hw/vfio/trace-events +++ b/hw/vfio/trace-events @@ -183,8 +183,8 @@ vfio_vmstate_change_prepare(const char *name, int runni= ng, const char *reason, c =20 iommufd_cdev_connect_and_bind(int iommufd, const char *name, int devfd, in= t devid) " [iommufd=3D%d] Successfully bound device %s (fd=3D%d): output de= vid=3D%d" iommufd_cdev_getfd(const char *dev, int devfd) " %s (fd=3D%d)" -iommufd_cdev_attach_ioas_hwpt(int iommufd, const char *name, int devfd, in= t id) " [iommufd=3D%d] Successfully attached device %s (%d) to id=3D%d" -iommufd_cdev_detach_ioas_hwpt(int iommufd, const char *name) " [iommufd=3D= %d] Successfully detached %s" +iommufd_cdev_pasid_attach_ioas_hwpt(int iommufd, const char *name, int dev= fd, uint32_t pasid, int id) " [iommufd=3D%d] Successfully attached device %= s (%d) pasid %u to id=3D%d" +iommufd_cdev_pasid_detach_ioas_hwpt(int iommufd, const char *name, uint32_= t pasid) " [iommufd=3D%d] Successfully detached %s pasid %u" iommufd_cdev_fail_attach_existing_container(const char *msg) " %s" iommufd_cdev_alloc_ioas(int iommufd, int ioas_id) " [iommufd=3D%d] new IOM= MUFD container with ioasid=3D%d" iommufd_cdev_device_info(char *name, int devfd, int num_irqs, int num_regi= ons, int flags) " %s (%d) num_irqs=3D%d num_regions=3D%d flags=3D%d" --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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26 May 2026 22:47:42 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2026 22:47:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779860865; x=1811396865; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L5VMZ/d6CxxhM/OTaqjPPPlV7ezMALRx5b07JFpxBlc=; b=WMCwQtiQdD/9lr89Utxvqwj8ptNs7HsPqehio9n593dzr3FJA4H/Usd7 gHS5wVJZTYJw62ebbm7TDebpQfg5xsBby9s/7758QbjVus32+HugwGB9G /TRFYQQnUxHnLRfrmFsZQ2dw7bgfbSLP6rbZiCULybi6rb6QC/Zm+YeOI gZSF2521hW3xKQi+9tKgmBA3bdmItzJF59m3b2l0PIg2LHslcVp0K2pja BIvue44w7EMn3CKhEhN/IJjYb1X1ONvy7fbcbPbDw1SXT8kYZ1VGtagzy YGl1Zur+1sP8BCmCHxfwSpftsa2L55vr6YU4Nt7hI8V8WUYmat4B0bxJz Q==; X-CSE-ConnectionGUID: W+prF7jOT7WORMvddD9/uQ== X-CSE-MsgGUID: W+vsso8kRtmGFbHDprj5BA== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988084" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988084" X-CSE-ConnectionGUID: nTat9gfCTWubBF3aa1pEnw== X-CSE-MsgGUID: Jd7+2GtiTVWo8CIZMh3ntA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086667" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan , qemu-arm@nongnu.org Subject: [PATCH v6 02/17] iommufd: Extend attach/detach_hwpt callbacks to support pasid Date: Wed, 27 May 2026 01:46:40 -0400 Message-ID: <20260527054658.1021096-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860961457154100 Same for the two wrappers and their call sites. Suggested-by: Shameer Kolothum Thodi Suggested-by: Nicolin Chen Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Nicolin Chen Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Shameer Kolothum Tested-by: Xudong Hao --- include/system/iommufd.h | 18 ++++++++++++------ backends/iommufd.c | 9 +++++---- hw/arm/smmuv3-accel.c | 12 ++++++++---- hw/i386/intel_iommu_accel.c | 19 ++++++++++--------- hw/vfio/iommufd.c | 10 +++++----- 5 files changed, 40 insertions(+), 28 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 2925d116ac..4257e50f62 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -138,14 +138,16 @@ struct HostIOMMUDeviceIOMMUFDClass { * * @hiodi: host IOMMU device backed by IOMMUFD backend. * + * @pasid: target pasid of the device to be attached. + * * @hwpt_id: ID of IOMMUFD hardware page table. * * @errp: pass an Error out when attachment fails. * * Returns: true on success, false on failure. */ - bool (*attach_hwpt)(HostIOMMUDeviceIOMMUFD *hiodi, uint32_t hwpt_id, - Error **errp); + bool (*attach_hwpt)(HostIOMMUDeviceIOMMUFD *hiodi, uint32_t pasid, + uint32_t hwpt_id, Error **errp); /** * @detach_hwpt: detach host IOMMU device from IOMMUFD hardware page t= able. * VFIO and VDPA device can have different implementation. @@ -154,15 +156,19 @@ struct HostIOMMUDeviceIOMMUFDClass { * * @hiodi: host IOMMU device backed by IOMMUFD backend. * - * @errp: pass an Error out when attachment fails. + * @pasid: target pasid of the device to be detached. + * + * @errp: pass an Error out when detachment fails. * * Returns: true on success, false on failure. */ - bool (*detach_hwpt)(HostIOMMUDeviceIOMMUFD *hiodi, Error **errp); + bool (*detach_hwpt)(HostIOMMUDeviceIOMMUFD *hiodi, uint32_t pasid, + Error **errp); }; =20 bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, - uint32_t hwpt_id, Error **errp); -bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, + uint32_t pasid, uint32_t hwpt_i= d, Error **errp); +bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, + uint32_t pasid, Error **errp); #endif diff --git a/backends/iommufd.c b/backends/iommufd.c index 410b044370..cfde6f2b2c 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -539,23 +539,24 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be= , uint32_t viommu_id, } =20 bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, - uint32_t hwpt_id, Error **errp) + uint32_t pasid, uint32_t hwpt_i= d, + Error **errp) { HostIOMMUDeviceIOMMUFDClass *hiodic =3D HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(hiodi); =20 g_assert(hiodic->attach_hwpt); - return hiodic->attach_hwpt(hiodi, hwpt_id, errp); + return hiodic->attach_hwpt(hiodi, pasid, hwpt_id, errp); } =20 bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, - Error **errp) + uint32_t pasid, Error **errp) { HostIOMMUDeviceIOMMUFDClass *hiodic =3D HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(hiodi); =20 g_assert(hiodic->detach_hwpt); - return hiodic->detach_hwpt(hiodi, errp); + return hiodic->detach_hwpt(hiodi, pasid, errp); } =20 static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **er= rp) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 862be814a0..2947e2e5dc 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -300,7 +300,8 @@ bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevic= e *sdev, int sid, return false; } =20 - if (!host_iommu_device_iommufd_attach_hwpt(hiodi, hwpt_id, errp)) { + if (!host_iommu_device_iommufd_attach_hwpt(hiodi, IOMMU_NO_PASID, hwpt= _id, + errp)) { if (s1_hwpt) { iommufd_backend_free_id(hiodi->iommufd, s1_hwpt->hwpt_id); g_free(s1_hwpt); @@ -575,7 +576,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *hiodi, =20 /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */ hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); - if (!host_iommu_device_iommufd_attach_hwpt(hiodi, hwpt_id, errp)) { + if (!host_iommu_device_iommufd_attach_hwpt(hiodi, IOMMU_NO_PASID, hwpt= _id, + errp)) { goto free_veventq; } return true; @@ -665,7 +667,8 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus= , void *opaque, hiodi =3D accel_dev->hiodi; accel =3D accel_dev->s_accel; /* Re-attach the default s2 hwpt id */ - if (!host_iommu_device_iommufd_attach_hwpt(hiodi, hiodi->hwpt_id, NULL= )) { + if (!host_iommu_device_iommufd_attach_hwpt(hiodi, IOMMU_NO_PASID, + hiodi->hwpt_id, NULL)) { error_report("Unable to attach the default HW pagetable: hiodi dev= id " "0x%x", hiodi->devid); } @@ -879,7 +882,8 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Erro= r **errp) =20 hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); QLIST_FOREACH(accel_dev, &accel->device_list, next) { - if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->hiodi, hwpt_= id, + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->hiodi, + IOMMU_NO_PASID, hwpt_id, &local_err)) { error_append_hint(&local_err, "Failed to attach GBPA hwpt %u f= or " "hiodi devid %u", hwpt_id, diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index ed3793602b..3217a2afac 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -121,8 +121,9 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDevic= e *vtd_hiod, } } =20 - ret =3D host_iommu_device_iommufd_attach_hwpt(hiodi, hwpt_id, errp); - trace_vtd_device_attach_hwpt(hiodi->devid, vtd_as->pasid, hwpt_id, ret= ); + ret =3D host_iommu_device_iommufd_attach_hwpt(hiodi, IOMMU_NO_PASID, h= wpt_id, + errp); + trace_vtd_device_attach_hwpt(hiodi->devid, IOMMU_NO_PASID, hwpt_id, re= t); if (ret) { /* Destroy old fs_hwpt if it's a replacement */ vtd_destroy_old_fs_hwpt(hiodi, vtd_as); @@ -141,22 +142,22 @@ static bool vtd_device_detach_iommufd(VTDHostIOMMUDev= ice *vtd_hiod, { HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); IntelIOMMUState *s =3D vtd_as->iommu_state; - uint32_t pasid =3D vtd_as->pasid; bool ret; =20 if (s->dmar_enabled && s->root_scalable) { - ret =3D host_iommu_device_iommufd_detach_hwpt(hiodi, errp); - trace_vtd_device_detach_hwpt(hiodi->devid, pasid, ret); + ret =3D host_iommu_device_iommufd_detach_hwpt(hiodi, IOMMU_NO_PASI= D, + errp); + trace_vtd_device_detach_hwpt(hiodi->devid, IOMMU_NO_PASID, ret); } else { /* * If DMAR remapping is disabled or guest switches to legacy mode, * we fallback to the default HWPT which contains shadow page tabl= e. * So guest DMA could still work. */ - ret =3D host_iommu_device_iommufd_attach_hwpt(hiodi, hiodi->hwpt_i= d, - errp); - trace_vtd_device_reattach_def_hwpt(hiodi->devid, pasid, hiodi->hwp= t_id, - ret); + ret =3D host_iommu_device_iommufd_attach_hwpt(hiodi, IOMMU_NO_PASI= D, + hiodi->hwpt_id, errp); + trace_vtd_device_reattach_def_hwpt(hiodi->devid, IOMMU_NO_PASID, + hiodi->hwpt_id, ret); } =20 if (ret) { diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index f86f6f0d7b..78e7b6a045 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -934,21 +934,21 @@ static void vfio_iommu_iommufd_class_init(ObjectClass= *klass, const void *data) =20 static bool host_iommu_device_iommufd_vfio_attach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, - uint32_t hwpt_id, Error **errp) + uint32_t pasid, uint32_t hwpt_i= d, + Error **errp) { VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(hiodi)->agent; =20 - return !iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, IOMMU_NO_PASID, - hwpt_id, errp); + return !iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, pasid, hwpt_id, = errp); } =20 static bool host_iommu_device_iommufd_vfio_detach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, - Error **errp) + uint32_t pasid, Error **errp) { VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(hiodi)->agent; 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X-CSE-ConnectionGUID: 3gnEDpVKRauj5uMapW9ncg== X-CSE-MsgGUID: qHWQp9evQya5LJFzg5Rxbg== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988090" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988090" X-CSE-ConnectionGUID: D0xEKKFwS4G4M0rTUQE2sw== X-CSE-MsgGUID: kptPDHDdSFyZ8orosOjsmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086685" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 03/17] vfio/iommufd: Create nesting parent hwpt with IOMMU_HWPT_ALLOC_PASID flag Date: Wed, 27 May 2026 01:46:41 -0400 Message-ID: <20260527054658.1021096-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860919701158500 Content-Type: text/plain; charset="utf-8" When both device and vIOMMU have PASID enabled, then guest may setup pasid usages such as SVM. VFIO needs to be aware of potential pasid usage and should attach the non-pasid part of pasid-capable device to hwpt flagged with IOMMU_HWPT_ALLOC_PASID. ARM SMMU doesn't support IOMMU_HWPT_ALLOC_PASID, only VTD need it. So we can't check the existing vIOMMU flag VIOMMU_FLAG_PASID_SUPPORTED to determine if set flag IOMMU_HWPT_ALLOC_PASID. Instead, introduce a new flag VIOMMU_FLAG_WANT_PASID_ATTACH which will only be exposed by VTD. Opportunistically add documentation for VIOMMU_FLAG_PASID_SUPPORTED and explain the difference with VIOMMU_FLAG_WANT_PASID_ATTACH. Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Tested-by: Xudong Hao Reviewed-by: Shameer Kolothum --- include/hw/core/iommu.h | 11 +++++++++++ include/hw/vfio/vfio-device.h | 1 + hw/vfio/device.c | 11 +++++++++++ hw/vfio/iommufd.c | 8 +++++++- 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/include/hw/core/iommu.h b/include/hw/core/iommu.h index 7fb5c81c9f..fd513d6472 100644 --- a/include/hw/core/iommu.h +++ b/include/hw/core/iommu.h @@ -20,9 +20,20 @@ enum viommu_flags { /* vIOMMU needs nesting parent HWPT to create nested HWPT */ VIOMMU_FLAG_WANT_NESTING_PARENT =3D BIT_ULL(0), + /* + * vIOMMU supports PASID capability, VFIO checks this flag and synthes= ize + * a PASID capability. + */ VIOMMU_FLAG_PASID_SUPPORTED =3D BIT_ULL(1), /* vIOMMU needs dirty tracking on the nesting parent HWPT for nested u= se */ VIOMMU_FLAG_WANT_NESTING_DIRTY_TRACKING =3D BIT_ULL(2), + /* + * vIOMMU requests other sub-system like VFIO to create a HWPT that ca= n be + * used with PASID attachment. VIOMMU_FLAG_PASID_SUPPORTED can't be us= ed + * for this purpose as PASID attachment is needed by VTD IOMMU but not= ARM + * SMMU. + */ + VIOMMU_FLAG_WANT_PASID_ATTACH =3D BIT_ULL(3), }; =20 /* Host IOMMU quirks. Extracted from host IOMMU capabilities */ diff --git a/include/hw/vfio/vfio-device.h b/include/hw/vfio/vfio-device.h index 380a55d6e5..8472420d3f 100644 --- a/include/hw/vfio/vfio-device.h +++ b/include/hw/vfio/vfio-device.h @@ -282,6 +282,7 @@ void vfio_device_unprepare(VFIODevice *vbasedev); =20 bool vfio_device_get_viommu_flags_want_nesting(VFIODevice *vbasedev); bool vfio_device_get_viommu_flags_want_nesting_dirty(VFIODevice *vbasedev); +bool vfio_device_get_viommu_flags_want_pasid_attach(VFIODevice *vbasedev); bool vfio_device_get_host_iommu_quirk_bypass_ro(VFIODevice *vbasedev, uint32_t type, void *caps, uint32_t size); diff --git a/hw/vfio/device.c b/hw/vfio/device.c index ccf14743e9..1a7f8088aa 100644 --- a/hw/vfio/device.c +++ b/hw/vfio/device.c @@ -543,6 +543,17 @@ bool vfio_device_get_viommu_flags_want_nesting(VFIODev= ice *vbasedev) return false; } =20 +bool vfio_device_get_viommu_flags_want_pasid_attach(VFIODevice *vbasedev) +{ + VFIOPCIDevice *vdev =3D vfio_pci_from_vfio_device(vbasedev); + + if (vdev) { + return !!(pci_device_get_viommu_flags(PCI_DEVICE(vdev)) & + VIOMMU_FLAG_WANT_PASID_ATTACH); + } + return false; +} + bool vfio_device_get_host_iommu_quirk_bypass_ro(VFIODevice *vbasedev, uint32_t type, void *caps, uint32_t size) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 78e7b6a045..0718f029ca 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -364,6 +364,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, VendorCaps caps; VFIOIOASHwpt *hwpt; uint32_t hwpt_id; + uint8_t max_pasid_log2 =3D 0; int ret; =20 /* Try to find a domain */ @@ -409,7 +410,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, */ if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devi= d, &type, &caps, sizeof(caps), &hw_c= aps, - NULL, errp)) { + &max_pasid_log2, errp)) { return false; } =20 @@ -437,6 +438,11 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *v= basedev, } } =20 + if (max_pasid_log2 && + vfio_device_get_viommu_flags_want_pasid_attach(vbasedev)) { + flags |=3D IOMMU_HWPT_ALLOC_PASID; + } + if (cpr_is_incoming()) { hwpt_id =3D vbasedev->cpr.hwpt_id; goto skip_alloc; --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779860934; cv=none; d=zohomail.com; s=zohoarc; b=Ivl8L7kTGuRTfx/75csFlHQEkmGG6fDqbZyW6A/L2iHyNO2AbJrTUqhPp9z4a4UK37fuYGOjD3focAIVtfFSjdt43Sgw5SYqXLSiqfnzAEvVzxFS8qippn/ONmaFM+kIY4d/26AQW61bCM9aDOD+IfKWS5gCbGVK6JA3sWoOSjU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779860934; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: Ysf/ciH/SIu1pfrgil8j7A== X-CSE-MsgGUID: HIYU+KWNTPiii8gfs45QCQ== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988099" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988099" X-CSE-ConnectionGUID: WQXjk8wITHqqLQmMA/VPew== X-CSE-MsgGUID: Za+qQhGnTbC2bHlW68riHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086702" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 04/17] intel_iommu: Create the nested hwpt with IOMMU_HWPT_ALLOC_PASID flag Date: Wed, 27 May 2026 01:46:42 -0400 Message-ID: <20260527054658.1021096-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860936246158500 Content-Type: text/plain; charset="utf-8" When pasid is enabled, any hwpt attached to non-PASID or PASID should be IOMMU_HWPT_ALLOC_PASID flagged, or else attachment fails. Change vtd_destroy_old_fs_hwpt() to pass in 'VTDHostIOMMUDevice *' for naming consistency. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Reviewed-by: Yi Liu Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 3217a2afac..bd1236c070 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -69,11 +69,13 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpa= ce *as) return NULL; } =20 -static bool vtd_create_fs_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, +static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, VTDPASIDEntry *pe, uint32_t *fs_hwpt_id, Error **errp) { + HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); struct iommu_hwpt_vtd_s1 vtd =3D {}; + uint32_t flags =3D vtd_hiod->iommu_state->pasid ? IOMMU_HWPT_ALLOC_PAS= ID : 0; =20 vtd.flags =3D (VTD_SM_PASID_ENTRY_SRE(pe) ? IOMMU_VTD_S1_SRE : 0) | (VTD_SM_PASID_ENTRY_WPE(pe) ? IOMMU_VTD_S1_WPE : 0) | @@ -82,13 +84,16 @@ static bool vtd_create_fs_hwpt(HostIOMMUDeviceIOMMUFD *= hiodi, vtd.pgtbl_addr =3D (uint64_t)vtd_pe_get_fspt_base(pe); =20 return iommufd_backend_alloc_hwpt(hiodi->iommufd, hiodi->devid, - hiodi->hwpt_id, 0, IOMMU_HWPT_DATA_V= TD_S1, - sizeof(vtd), &vtd, fs_hwpt_id, errp); + hiodi->hwpt_id, flags, + IOMMU_HWPT_DATA_VTD_S1, sizeof(vtd),= &vtd, + fs_hwpt_id, errp); } =20 -static void vtd_destroy_old_fs_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, +static void vtd_destroy_old_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, VTDAddressSpace *vtd_as) { + HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); + if (!vtd_as->fs_hwpt_id) { return; } @@ -116,7 +121,7 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDevic= e *vtd_hiod, } =20 if (vtd_pe_pgtt_is_fst(pe)) { - if (!vtd_create_fs_hwpt(hiodi, pe, &hwpt_id, errp)) { + if (!vtd_create_fs_hwpt(vtd_hiod, pe, &hwpt_id, errp)) { return false; } } @@ -126,7 +131,7 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDevic= e *vtd_hiod, trace_vtd_device_attach_hwpt(hiodi->devid, IOMMU_NO_PASID, hwpt_id, re= t); if (ret) { /* Destroy old fs_hwpt if it's a replacement */ - vtd_destroy_old_fs_hwpt(hiodi, vtd_as); + vtd_destroy_old_fs_hwpt(vtd_hiod, vtd_as); if (vtd_pe_pgtt_is_fst(pe)) { vtd_as->fs_hwpt_id =3D hwpt_id; } @@ -161,7 +166,7 @@ static bool vtd_device_detach_iommufd(VTDHostIOMMUDevic= e *vtd_hiod, } =20 if (ret) { - vtd_destroy_old_fs_hwpt(hiodi, vtd_as); + vtd_destroy_old_fs_hwpt(vtd_hiod, vtd_as); } =20 return ret; --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779861094; cv=none; d=zohomail.com; s=zohoarc; b=TySzYKOk7IzxvZIzmibkB4aCN1VKEuS3cg4A1e0dqDA8OZFNIlldatTQHJj2uc3sdvhXySBoKxsdzR3cjCxgVYSabh8Zm2UJuAuuq8lcjO3NwkT3hcMHUXSsT4pwszaHW1pVsNxOejredx6ho9wM08VTv9kA6UYJJJrqMa3aTng= ARC-Message-Signature: i=1; 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bh=gQ25tsLstfEWTYZYQ5LX5DGdCN193noUppCXqpAi0Ls=; b=eEx66tRYoaGnZnS2Vw9bJclwukZWkWtxQm1X8N5fcypNqZOQq/gTN3l9 QQ09gbPykL8beZELwJ5E8uF52xwR5OwdUvCCOMrrJhcPz8VqUhE/5Azcl bmefXJJSdQLD7Ow5hmKHgzOCXWLyHTBE9o8NZUesSPGgO8Y+BJpGsmVzr XRqf1dwpO3J8OICu1Ka7jkyM1jZOv7yKv0GcC7vWJkd3lCZczEbms/VjS TmcWXjnaITCCwwcuWwHMirRSz5TpXLEbXWEtCvblYapZs+1wDkEnZVskE kKheiG3mfQaO8dS8a4D/uPfVy0f5I56WnnqUSqNCWXHFDYQxzYxe8k6s3 w==; X-CSE-ConnectionGUID: uqSXne86T+2g9/pWYN/sgw== X-CSE-MsgGUID: 6pYX2gEoQ1KNGVbnc7RxiA== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988107" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988107" X-CSE-ConnectionGUID: p9qUMuzCQCCx5ZYXIU/R8g== X-CSE-MsgGUID: UcjR0Vh5T5epyr4kGZ2nfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086723" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 05/17] intel_iommu: Rename pasid property to "pasid-bits" and define it as type uint8 Date: Wed, 27 May 2026 01:46:43 -0400 Message-ID: <20260527054658.1021096-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861096427158500 Content-Type: text/plain; charset="utf-8" 'x-pasid-mode' is a bool property, we need an extra 'pss' property to represent PASID size supported. Because there is no any device in QEMU supporting pasid capability yet, no guest could use the pasid feature until now, 'x-pasid-mode' takes no effect. So instead of an extra 'pss' property we can use a single property of uint8 type and named 'pasid-bits' to represent if pasid is supported and the PASID bits size. A value of N > 0 means pasid is supported and N - 1 is the value in PSS field in ECAP register. PASID bits size should also be no more than 20 bits according to PCI spec. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Reviewed-by: Yi Liu Tested-by: Xudong Hao --- hw/i386/intel_iommu_internal.h | 2 +- include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 11 +++++++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 11a53aa369..db4f186a3e 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -195,7 +195,7 @@ #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_NWFS (1ULL << 33) -#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid= */ +#define VTD_ECAP_SET_PSS(x, v) ((x)->ecap =3D deposit64((x)->ecap, 35= , 5, v)) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_PDS (1ULL << 42) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e44ce31841..95c76015e4 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -314,7 +314,7 @@ struct IntelIOMMUState { bool intr_eime; /* Extended interrupt mode enabled */ OnOffAuto intr_eim; /* Toggle for EIM cabability */ uint8_t aw_bits; /* Host/IOVA address width (in bits) */ - bool pasid; /* Whether to support PASID */ + uint8_t pasid; /* PASID supported in bits, 0 if not */ bool fs1gp; /* First Stage 1-GByte Page Support */ =20 /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b784c5f10a..cf275b496e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4203,7 +4203,7 @@ static const Property vtd_properties[] =3D { DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FA= LSE), DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, fsts, FALSE), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), - DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), + DEFINE_PROP_UINT8("pasid-bits", IntelIOMMUState, pasid, 0), DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, false), DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false), DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true), @@ -5045,7 +5045,8 @@ static void vtd_cap_init(IntelIOMMUState *s) } =20 if (s->pasid) { - s->ecap |=3D VTD_ECAP_PASID | VTD_ECAP_PSS; + VTD_ECAP_SET_PSS(s, s->pasid - 1); + s->ecap |=3D VTD_ECAP_PASID; } } =20 @@ -5586,6 +5587,12 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) return false; } =20 + if (s->pasid > PCI_EXT_CAP_PASID_MAX_WIDTH) { + error_setg(errp, "PASID width %d exceeds Max PASID Width %d allowe= d " + "in PCI spec", s->pasid, PCI_EXT_CAP_PASID_MAX_WIDTH); + return false; + } + if (s->svm) { if (!x86_iommu->dt_supported) { error_setg(errp, "Need to set device IOTLB for svm"); --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779861004; cv=none; d=zohomail.com; s=zohoarc; b=G/N1aby7e4y76rhYzPQR0CXfAGRvHLD7FdJPddpD4mDcH9kl6za4nBVCxlhSQbSUtPCNHfO2OdX85V8JOYACkKOjcTADWSd1a3pN51WbOEZ8Ub75GkMI9HiuY/c8N8iD8ccrNFZMMKCOGdqUkpbvqb2UZfNRaOE+V4GTkSyPB0Y= ARC-Message-Signature: i=1; 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Wed, 27 May 2026 01:48:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wS77Z-0006FJ-PT for qemu-devel@nongnu.org; Wed, 27 May 2026 01:48:05 -0400 Received: from mgamail.intel.com ([198.175.65.11]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wS77W-0000cT-KC for qemu-devel@nongnu.org; Wed, 27 May 2026 01:48:00 -0400 Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2026 22:47:58 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2026 22:47:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779860879; x=1811396879; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861005875154100 Content-Type: text/plain; charset="utf-8" Refactor vtd_dev_get_pe_from_pasid() to take individual parameters (IntelIOMMUState, PCIBus, devfn, pasid) instead of VTDAddressSpace. This makes the function more reusable and prepares it for export to be used in the acceleration path. Remove inline qualifier as the function will be exported in a subsequent patch. No functional changes intended. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cf275b496e..aa27187e02 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3113,10 +3113,10 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState= *s, return true; } =20 -static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as, - VTDPASIDEntry *pe) +static int vtd_dev_get_pe_from_pasid(IntelIOMMUState *s, PCIBus *bus, + uint8_t devfn, uint32_t pasid, + VTDPASIDEntry *pe) { - IntelIOMMUState *s =3D vtd_as->iommu_state; VTDContextEntry ce; int ret; =20 @@ -3124,13 +3124,12 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddr= essSpace *vtd_as, return -VTD_FR_RTADDR_INV_TTM; } =20 - ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->= devfn, - &ce); + ret =3D vtd_dev_to_context_entry(s, pci_bus_num(bus), devfn, &ce); if (ret) { return ret; } =20 - return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid); + return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); } =20 static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) @@ -3151,7 +3150,8 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, const char *err_prefix =3D "Attaching to HWPT failed: "; Error *local_err =3D NULL; =20 - if (vtd_dev_get_pe_from_pasid(vtd_as, &pe)) { + if (vtd_dev_get_pe_from_pasid(vtd_as->iommu_state, vtd_as->bus, + vtd_as->devfn, vtd_as->pasid, &pe)) { if (!pc_entry->valid) { return; } --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779860947; cv=none; d=zohomail.com; s=zohoarc; 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a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779860883; x=1811396883; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MGbHt1Emt9ZZ7LpwV+zWEQod/KdJebt796FS1R9uwlg=; b=YOJFVd8P/sYaUEjQlbaMQnFymxqP+jCSMNcD1Qn8mSCml5hSZeg8A5SV sLcKGRpl6/K/gPrzL7EHut3QwB7rPKCeOAcsu2r781ze5Ut1f0wXpunHp YUbcrMEscopUvg1DHcqD/u+od8JRXOGC6sPuIjAIU/oaGoduvJ3SUa/7R RW005EvyRWKKyCOfjKjyrD38rdnTdTzmUX+gueDvBgdBaGZeQrNO54Sve 0d/kDyNubVi2LCCyTTFqY7MUOyo8vPU3Ln3OrDrH05lj+BxmcYSKhm3KK QQwvgpwddBkLuhV5dt6DMV0/uL4xAIaS/PWV02NPhb2Dyu1VqEpPhX4Ep w==; X-CSE-ConnectionGUID: SIJ0F8VGSee0NXu1nQ/1lQ== X-CSE-MsgGUID: A4xgMivsQWS+ruAnpFhElA== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988126" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988126" X-CSE-ConnectionGUID: opT1bIiKTiKoMluxrJ0H9g== X-CSE-MsgGUID: erVMgaicTZGjsfT49qeVuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086764" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan , Clement Mathieu--Drif Subject: [PATCH v6 07/17] intel_iommu: Export some functions Date: Wed, 27 May 2026 01:46:45 -0400 Message-ID: <20260527054658.1021096-8-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860950520154100 Content-Type: text/plain; charset="utf-8" Export some functions for accel code usages. Inline functions and MACROs are moved to internal header files. Then accel code in following patches could access them. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Reviewed-by: Yi Liu Tested-by: Xudong Hao --- hw/i386/intel_iommu_internal.h | 31 ++++++++++++++++++++++++ hw/i386/intel_iommu.c | 43 +++++++--------------------------- 2 files changed, 40 insertions(+), 34 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index db4f186a3e..d738ef1803 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -620,6 +620,12 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL =20 +/* context entry operations */ +#define VTD_CE_GET_PASID_DIR_TABLE(ce) \ + ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) +#define VTD_CE_GET_PRE(ce) \ + ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE) + typedef struct VTDPASIDCacheInfo { uint8_t type; uint16_t did; @@ -746,4 +752,29 @@ static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *p= e) { return (VTD_SM_PASID_ENTRY_PGTT(pe) =3D=3D VTD_SM_PASID_ENTRY_FST); } + +static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) +{ + return pdire->val & 1; +} + +static inline bool vtd_pe_present(VTDPASIDEntry *pe) +{ + return pe->val[0] & VTD_PASID_ENTRY_P; +} + +static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry= *p2) +{ + return memcmp(p1, p2, sizeof(*p1)); +} + +int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, + VTDPASIDDirEntry *pdire); +int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, + dma_addr_t addr, VTDPASIDEntry *pe); +int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, + uint8_t devfn, VTDContextEntry *ce); +VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid); +int vtd_dev_get_pe_from_pasid(IntelIOMMUState *s, PCIBus *bus, uint8_t dev= fn, + uint32_t pasid, VTDPASIDEntry *pe); #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index aa27187e02..24d0211db7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -42,12 +42,6 @@ #include "migration/vmstate.h" #include "trace.h" =20 -/* context entry operations */ -#define VTD_CE_GET_PASID_DIR_TABLE(ce) \ - ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) -#define VTD_CE_GET_PRE(ce) \ - ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE) - /* * Paging mode for first-stage translation (VTD spec Figure 9-6) * 00: 4-level paging, 01: 5-level paging @@ -831,18 +825,12 @@ static inline bool vtd_pe_type_check(IntelIOMMUState = *s, VTDPASIDEntry *pe) } } =20 -static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) -{ - return pdire->val & 1; -} - /** * Caller of this function should check present bit if wants * to use pdir entry for further usage except for fpd bit check. */ -static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, - uint32_t pasid, - VTDPASIDDirEntry *pdire) +int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, + VTDPASIDDirEntry *pdire) { uint32_t index; dma_addr_t addr, entry_size; @@ -860,15 +848,8 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pa= sid_dir_base, return 0; } =20 -static inline bool vtd_pe_present(VTDPASIDEntry *pe) -{ - return pe->val[0] & VTD_PASID_ENTRY_P; -} - -static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, - uint32_t pasid, - dma_addr_t addr, - VTDPASIDEntry *pe) +int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, + dma_addr_t addr, VTDPASIDEntry *pe) { uint8_t pgtt; uint32_t index; @@ -1526,8 +1507,8 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, V= TDContextEntry *ce) } =20 /* Map a device to its corresponding domain (context-entry) */ -static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, - uint8_t devfn, VTDContextEntry *ce) +int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, + uint8_t devfn, VTDContextEntry *ce) { VTDRootEntry re; int ret_fr; @@ -1909,7 +1890,7 @@ static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(I= ntelIOMMUState *s, vtd_find_as_by_sid_and_pasid, &key); } =20 -static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) +VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) { return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID); } @@ -3113,9 +3094,8 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *= s, return true; } =20 -static int vtd_dev_get_pe_from_pasid(IntelIOMMUState *s, PCIBus *bus, - uint8_t devfn, uint32_t pasid, - VTDPASIDEntry *pe) +int vtd_dev_get_pe_from_pasid(IntelIOMMUState *s, PCIBus *bus, uint8_t dev= fn, + uint32_t pasid, VTDPASIDEntry *pe) { VTDContextEntry ce; int ret; @@ -3132,11 +3112,6 @@ static int vtd_dev_get_pe_from_pasid(IntelIOMMUState= *s, PCIBus *bus, return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); } =20 -static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) -{ - return memcmp(p1, p2, sizeof(*p1)); -} - /* Update or invalidate pasid cache based on the pasid entry in guest memo= ry. */ static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value, gpointer user_data) --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 27 May 2026 01:48:08 -0400 Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2026 22:48:06 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2026 22:48:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779860887; x=1811396887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SaYEI5jtpzrHueHXY2JSluk3hjuH9bSiA+4fOkitfk4=; b=ONsPmfnKugQOBaMj/r5vn1WrRKxiJqWxR2PkgMgYvLk48wEzDN7F39Sy EwdsREq79t27FUNB2G0DXEehachYtwktBksPlFdYKNQvENylb57f7qV5q bI0/AtUFmcLVg+Pq35+vG4O2dZ9gg7osI5ng8ykNC2UxKB5/S4TUrWbnl djzry8Yd0vOZSJc/VO+eNDPHv0v5qHHXCwRepdsBBmorZ9zxxnJbGxbtW wVtyiuLMGxTyEifzt0otVXORtZcqaPPwgdCFQGqxjLH1qCJQDxbLtnUhj 0rYClH0v+4Fd+y5PObjg8VC4PVOls/58WggYr5zr/HYtcKs0DVxA+Hh52 Q==; X-CSE-ConnectionGUID: U4c/1AP5QUWZzyqUYcWUJQ== X-CSE-MsgGUID: kXNdoIcySDOm6Wywcf/UPw== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988135" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988135" X-CSE-ConnectionGUID: 84dnTbrLRiS84/XKQvp1NA== X-CSE-MsgGUID: aPUhb616TIquZMdSGhnn6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086781" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 08/17] intel_iommu: Fix PASID validity check in fault reporting Date: Wed, 27 May 2026 01:46:46 -0400 Message-ID: <20260527054658.1021096-9-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860961342154100 Content-Type: text/plain; charset="utf-8" The current code incorrectly uses "pasid !=3D PCI_NO_PASID" to determine if PASID should be reported in fault records. However, this check happens after the code converts PCI_NO_PASID to PASID_0 in scalable mode. This means that for requests that originally had PCI_NO_PASID, the check "pasid !=3D PCI_NO_PASID" will incorrectly return true (since pasid is now PASID_0), causing fault records to incorrectly indicate PASID validity. According to the VT-d specification, the PASID field in fault records is only valid for Requests-with-PASID: "When Set, indicates the faulted request has a PASID TLP Prefix." Fix this by capturing the original PASID state before the PCI_NO_PASID to PASID_0 conversion, ensuring fault records correctly reflect whether the original request had a PASID. Fixes: 1b2b12376c8a ("intel_iommu: process PASID-based iotlb invalidation") Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 24d0211db7..034747b0b4 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2109,6 +2109,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, bool is_fpd_set =3D false; bool reads =3D true; bool writes =3D true; + bool is_pasid =3D pasid !=3D PCI_NO_PASID; uint8_t access_flags, pgtt; VTDIOTLBEntry *iotlb_entry; uint64_t xlat, size; @@ -2235,7 +2236,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, if (ret_fr) { if (!vtd_is_recoverable_fault(-ret_fr, iommu_idx)) { vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, - addr, is_write, pasid !=3D PCI_NO_PASID, pasid= ); + addr, is_write, is_pasid, pasid); } goto error; } --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 27 May 2026 01:48:14 -0400 Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2026 22:48:10 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2026 22:48:07 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779860892; x=1811396892; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vpCtzBja/N+cWRl7NPkpK4OhtwJPx9KPsXNNT4CnjbY=; b=KMzdMi1ZUYZcYWyDa+VtARwLHPUJddn6WnC9N7GQr+ZqMULI8M6XXzaJ CxYxyGCzj3M/5nQxpkDSTyewswp/iwaLrMl2l+D1Hn4Fd0PNiC6TS1iHR ntq7tXZ+PidRSBraQMSeCR1JoTti1fCncKusjNCuAuXpLvJwpsDlRxd01 xCAIRaLfxPBboy7qaMtkJsMYnO/eVwZQlQlcFanL4deYrQ0DVGc7PoBBG EhoKvdafqiMhgoaqJBRCymPBbiCe6vKFAZYySwQQfiFL5FCgR3EuFGqsm NZfv9GUb4b9bmvQjGeVHMLV4Xut8OtgdEQmNj32fABoooODwPCnHnjBNL w==; X-CSE-ConnectionGUID: w91JcT7zSAiGFOXhLcg0fA== X-CSE-MsgGUID: gKb2lAWnTBOs8/tRi3LP3Q== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988144" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988144" X-CSE-ConnectionGUID: z2/p6lxiT86mIDbpnwC1qw== X-CSE-MsgGUID: aizfcCBkQtWAUD/DUHvqDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086795" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 09/17] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0 Date: Wed, 27 May 2026 01:46:47 -0400 Message-ID: <20260527054658.1021096-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860959865158500 Content-Type: text/plain; charset="utf-8" In previous patch we introduced a global macro IOMMU_NO_PASID(0) for the RID attachment, this makes the local macro PASID_0 redundant. Delete it and use IOMMU_NO_PASID instead. No functional changes intended. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Clement Mathieu--Drif Tested-by: Xudong Hao --- hw/i386/intel_iommu_internal.h | 1 - hw/i386/intel_iommu.c | 22 +++++++++++----------- hw/i386/intel_iommu_accel.c | 2 +- 3 files changed, 12 insertions(+), 13 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index d738ef1803..ee59df09f8 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -615,7 +615,6 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 -#define PASID_0 0 #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 034747b0b4..5b362ceaf7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -941,7 +941,7 @@ static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, V= TDContextEntry *ce, dma_addr_t pasid_dir_base; =20 if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D PASID_0; + pasid =3D IOMMU_NO_PASID; } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); return vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); @@ -958,7 +958,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D PASID_0; + pasid =3D IOMMU_NO_PASID; } pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); =20 @@ -1501,9 +1501,9 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, V= TDContextEntry *ce) =20 /* * Make sure in Scalable Mode, a present context entry - * has valid pasid entry setting at PASID_0. + * has valid pasid entry setting at IOMMU_NO_PASID. */ - return vtd_ce_get_pasid_entry(s, ce, &pe, PASID_0); + return vtd_ce_get_pasid_entry(s, ce, &pe, IOMMU_NO_PASID); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1564,7 +1564,7 @@ int vtd_dev_to_context_entry(IntelIOMMUState *s, uint= 8_t bus_num, } } else { /* - * Check if the programming of pasid setting of PASID_0 + * Check if the programming of pasid setting of IOMMU_NO_PASID * is valid, and thus avoids to check pasid entry fetching * result in future helper function calling. */ @@ -2123,7 +2123,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, vtd_iommu_lock(s); =20 if (pasid =3D=3D PCI_NO_PASID && s->root_scalable) { - pasid =3D PASID_0; + pasid =3D IOMMU_NO_PASID; } =20 /* Try to fetch pte from IOTLB */ @@ -2488,7 +2488,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id) } =20 /* - * There is no pasid field in iotlb invalidation descriptor, so PCI_NO_PAS= ID + * There is no pasid field in iotlb invalidation descriptor, so IOMMU_NO_P= ASID * is passed as parameter. Piotlb invalidation supports pasid, pasid in its * descriptor is passed which should not be PCI_NO_PASID. */ @@ -2509,10 +2509,10 @@ static void vtd_iotlb_page_invalidate_notify(IntelI= OMMUState *s, * In legacy mode, vtd_as->pasid =3D=3D pasid is always true. * In scalable mode, for vtd address space backing a PCI * device without pasid, needs to compare pasid with - * PASID_0 of this device. + * IOMMU_NO_PASID of this device. */ if (!(vtd_as->pasid =3D=3D pasid || - (vtd_as->pasid =3D=3D PCI_NO_PASID && pasid =3D=3D PASID= _0))) { + (vtd_as->pasid =3D=3D PCI_NO_PASID && pasid =3D=3D IOMMU= _NO_PASID))) { continue; } =20 @@ -2564,7 +2564,7 @@ static void vtd_iotlb_page_invalidate(IntelIOMMUState= *s, uint16_t domain_id, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info); vtd_iommu_unlock(s); - vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, PCI_NO_PASID); + vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, IOMMU_NO_PASI= D); } =20 /* Flush IOTLB @@ -3023,7 +3023,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce) && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { - if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D PASID_0) && + if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D IOMMU_NO_PA= SID) && vtd_as->pasid !=3D pasid) { continue; } diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index bd1236c070..8940d240a1 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -217,7 +217,7 @@ static void vtd_flush_host_piotlb_locked(gpointer key, = gpointer value, =20 did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); =20 - if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D PAS= ID_0) { + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D IOM= MU_NO_PASID) { HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); uint32_t entry_num =3D 1; /* Only implement one request for simpli= city */ --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="241086808" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v6 10/17] intel_iommu: Refactor PASID processing to use IOMMU_NO_PASID internally Date: Wed, 27 May 2026 01:46:48 -0400 Message-ID: <20260527054658.1021096-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861010113158500 Content-Type: text/plain; charset="utf-8" The PCI subsystem uses PCI_NO_PASID for requests-without-PASID, but VT-d emulation uses IOMMU_NO_PASID internally (ecap.RPS=3D=3D0). This leads to conversion and checking code between PCI_NO_PASID and IOMMU_NO_PASID throughout the implementation. Refactor to use IOMMU PASID consistently within Intel IOMMU by storing IOMMU PASID value in vtd_as->pasid. After this change, PCI_NO_PASID is only used at three boundary points: 1. PCI_NO_PASID -> IOMMU_NO_PASID: Convert PCI PASID to IOMMU PASID in vtd_find_add_as() and cache in vtd_as->pasid. 2. IOMMU_NO_PASID -> PCI_NO_PASID: Convert when notifying UNMAP events via memory_region_notify_iommu() and returning IOMMUTLBEntry in vtd_iommu_translate(). This eliminates conversion/checks in PASID table lookups, simplifies invalidation logic with consistent PASID values, and improves code readability. The PCI subsystem interface remains unchanged to maintain compatibility with other IOMMU implementations that may not use PASID 0 for requests-without-PASID. Suggested-by: Clement Mathieu--Drif Signed-off-by: Zhenzhong Duan --- include/system/memory.h | 2 +- hw/i386/intel_iommu.c | 164 +++++++++++++++++------------------- hw/i386/intel_iommu_accel.c | 2 +- 3 files changed, 80 insertions(+), 88 deletions(-) diff --git a/include/system/memory.h b/include/system/memory.h index 1417132f6d..1edb38b07d 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -150,7 +150,7 @@ struct IOMMUTLBEntry { hwaddr translated_addr; hwaddr addr_mask; /* 0xfff =3D 4k translation */ IOMMUAccessFlags perm; - uint32_t pasid; + uint32_t pasid; /* PCI pasid */ }; =20 /* diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 5b362ceaf7..2deea8fbe2 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -938,12 +938,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState= *s, static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, VTDPASIDEntry *pe, uint32_t pasid) { - dma_addr_t pasid_dir_base; + dma_addr_t pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); =20 - if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D IOMMU_NO_PASID; - } - pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); return vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe); } =20 @@ -953,15 +949,10 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, uint32_t pasid) { int ret; - dma_addr_t pasid_dir_base; + dma_addr_t pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); VTDPASIDDirEntry pdire; VTDPASIDEntry pe; =20 - if (pasid =3D=3D PCI_NO_PASID) { - pasid =3D IOMMU_NO_PASID; - } - pasid_dir_base =3D VTD_CE_GET_PASID_DIR_TABLE(ce); - /* * No present bit check since fpd is meaningful even * if the present bit is clear. @@ -1750,7 +1741,7 @@ static bool vtd_switch_address_space(VTDAddressSpace = *as) * * Need to disable ir for as with PASID. */ - if (as->pasid !=3D PCI_NO_PASID) { + if (as->pasid !=3D IOMMU_NO_PASID) { memory_region_set_enabled(&as->iommu_ir, false); } else { memory_region_set_enabled(&as->iommu_ir, true); @@ -1780,7 +1771,7 @@ static bool vtd_switch_address_space(VTDAddressSpace = *as) * We enable per as memory region (iommu_ir_fault) for catching * the translation for interrupt range through PASID + PT. */ - if (pt && as->pasid !=3D PCI_NO_PASID) { + if (pt && as->pasid !=3D IOMMU_NO_PASID) { memory_region_set_enabled(&as->iommu_ir_fault, true); } else { memory_region_set_enabled(&as->iommu_ir_fault, false); @@ -1892,7 +1883,7 @@ static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(I= ntelIOMMUState *s, =20 VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) { - return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID); + return vtd_get_as_by_sid_and_pasid(s, sid, IOMMU_NO_PASID); } =20 static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) @@ -2109,7 +2100,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, bool is_fpd_set =3D false; bool reads =3D true; bool writes =3D true; - bool is_pasid =3D pasid !=3D PCI_NO_PASID; + bool is_pasid =3D pasid !=3D IOMMU_NO_PASID; uint8_t access_flags, pgtt; VTDIOTLBEntry *iotlb_entry; uint64_t xlat, size; @@ -2122,10 +2113,6 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, =20 vtd_iommu_lock(s); =20 - if (pasid =3D=3D PCI_NO_PASID && s->root_scalable) { - pasid =3D IOMMU_NO_PASID; - } - /* Try to fetch pte from IOTLB */ iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); if (iotlb_entry) { @@ -2490,7 +2477,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id) /* * There is no pasid field in iotlb invalidation descriptor, so IOMMU_NO_P= ASID * is passed as parameter. Piotlb invalidation supports pasid, pasid in its - * descriptor is passed which should not be PCI_NO_PASID. + * descriptor is passed. */ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s, uint16_t domain_id, hwaddr ad= dr, @@ -2504,48 +2491,41 @@ static void vtd_iotlb_page_invalidate_notify(IntelI= OMMUState *s, QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) { ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, &ce); - if (!ret && domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pas= id)) { + if (ret || vtd_as->pasid !=3D pasid || + domain_id !=3D vtd_get_domain_id(s, &ce, pasid)) { + continue; + } + + if (vtd_as_has_map_notifier(vtd_as)) { /* - * In legacy mode, vtd_as->pasid =3D=3D pasid is always true. - * In scalable mode, for vtd address space backing a PCI - * device without pasid, needs to compare pasid with - * IOMMU_NO_PASID of this device. + * When first stage translation is off, as long as we have MAP + * notifications registered in any of our IOMMU notifiers, + * we need to sync the shadow page table. Otherwise VFIO + * device attaches to nested page table instead of shadow + * page table, so no need to sync. */ - if (!(vtd_as->pasid =3D=3D pasid || - (vtd_as->pasid =3D=3D PCI_NO_PASID && pasid =3D=3D IOMMU= _NO_PASID))) { - continue; - } - - if (vtd_as_has_map_notifier(vtd_as)) { - /* - * When first stage translation is off, as long as we have= MAP - * notifications registered in any of our IOMMU notifiers, - * we need to sync the shadow page table. Otherwise VFIO - * device attaches to nested page table instead of shadow - * page table, so no need to sync. - */ - if (!s->fsts || !s->root_scalable) { - vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, si= ze); - } - } else { - /* - * For UNMAP-only notifiers, we don't need to walk the - * page tables. We just deliver the PSI down to - * invalidate caches. - */ - const IOMMUTLBEvent event =3D { - .type =3D IOMMU_NOTIFIER_UNMAP, - .entry =3D { - .target_as =3D &address_space_memory, - .iova =3D addr, - .translated_addr =3D 0, - .addr_mask =3D size - 1, - .perm =3D IOMMU_NONE, - .pasid =3D vtd_as->pasid, - }, - }; - memory_region_notify_iommu(&vtd_as->iommu, 0, event); + if (!s->fsts || !s->root_scalable) { + vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size); } + } else { + /* + * For UNMAP-only notifiers, we don't need to walk the + * page tables. We just deliver the PSI down to + * invalidate caches. + */ + const IOMMUTLBEvent event =3D { + .type =3D IOMMU_NOTIFIER_UNMAP, + .entry =3D { + .target_as =3D &address_space_memory, + .iova =3D addr, + .translated_addr =3D 0, + .addr_mask =3D size - 1, + .perm =3D IOMMU_NONE, + /* Other sub-systems use PCI pasid */ + .pasid =3D pasid =3D=3D IOMMU_NO_PASID ? PCI_NO_PASID = : pasid, + }, + }; + memory_region_notify_iommu(&vtd_as->iommu, 0, event); } } } @@ -3008,6 +2988,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, VTDIOTLBPageInvInfo info; VTDAddressSpace *vtd_as; VTDContextEntry ce; + int ret; =20 info.domain_id =3D domain_id; info.pasid =3D pasid; @@ -3020,17 +3001,15 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUS= tate *s, vtd_iommu_unlock(s); =20 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { - if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), - vtd_as->devfn, &ce) && - domain_id =3D=3D vtd_get_domain_id(s, &ce, vtd_as->pasid)) { - if ((vtd_as->pasid !=3D PCI_NO_PASID || pasid !=3D IOMMU_NO_PA= SID) && - vtd_as->pasid !=3D pasid) { - continue; - } + ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), + vtd_as->devfn, &ce); + if (ret || vtd_as->pasid !=3D pasid || + domain_id !=3D vtd_get_domain_id(s, &ce, pasid)) { + continue; + } =20 - if (!s->fsts || !vtd_as_has_map_notifier(vtd_as)) { - vtd_address_space_sync(vtd_as); - } + if (!s->fsts || !vtd_as_has_map_notifier(vtd_as)) { + vtd_address_space_sync(vtd_as); } } } @@ -3239,7 +3218,7 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s, /* PASID selective implies a DID selective */ trace_vtd_inv_desc_pasid_cache_psi(did, pasid); pc_info.did =3D did; - pc_info.pasid =3D pasid ?: PCI_NO_PASID; + pc_info.pasid =3D pasid; break; =20 case VTD_INV_DESC_PASIDC_G_GLOBAL: @@ -3291,6 +3270,7 @@ static void do_invalidate_device_tlb(VTDAddressSpace = *vtd_dev_as, * ... */ =20 + uint32_t pasid =3D vtd_dev_as->pasid; IOMMUTLBEvent event; uint64_t sz; =20 @@ -3307,7 +3287,8 @@ static void do_invalidate_device_tlb(VTDAddressSpace = *vtd_dev_as, event.entry.iova =3D addr; event.entry.perm =3D IOMMU_NONE; event.entry.translated_addr =3D 0; - event.entry.pasid =3D vtd_dev_as->pasid; + /* Other sub-systems use PCI pasid */ + event.entry.pasid =3D pasid =3D=3D IOMMU_NO_PASID ? PCI_NO_PASID : pas= id; memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event); } =20 @@ -3335,7 +3316,7 @@ static bool vtd_process_device_piotlb_desc(IntelIOMMU= State *s, sid =3D VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(inv_desc->lo); if (global) { QLIST_FOREACH(vtd_dev_as, &s->vtd_as_with_notifiers, next) { - if ((vtd_dev_as->pasid !=3D PCI_NO_PASID) && + if ((vtd_dev_as->pasid !=3D IOMMU_NO_PASID) && (PCI_BUILD_BDF(pci_bus_num(vtd_dev_as->bus), vtd_dev_as->devfn) =3D=3D sid))= { do_invalidate_device_tlb(vtd_dev_as, size, addr); @@ -3983,13 +3964,12 @@ static void vtd_mem_write(void *opaque, hwaddr addr, } =20 static void vtd_prepare_identity_entry(hwaddr addr, IOMMUAccessFlags perm, - uint32_t pasid, IOMMUTLBEntry *io= tlb) + IOMMUTLBEntry *iotlb) { iotlb->iova =3D addr & VTD_PAGE_MASK_4K; iotlb->translated_addr =3D addr & VTD_PAGE_MASK_4K; iotlb->addr_mask =3D ~VTD_PAGE_MASK_4K; iotlb->perm =3D perm; - iotlb->pasid =3D pasid; } =20 static inline void vtd_prepare_error_entry(IOMMUTLBEntry *entry) @@ -4001,6 +3981,10 @@ static inline void vtd_prepare_error_entry(IOMMUTLBE= ntry *entry) entry->pasid =3D PCI_NO_PASID; } =20 +/* + * This function returns translation result to other sub-system such as PC= I, + * so iommu pasid is converted to PCI pasid and returned in IOMMUTLBEntry. + */ static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr = addr, IOMMUAccessFlags flag, int iommu_= idx) { @@ -4009,7 +3993,7 @@ static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryR= egion *iommu, hwaddr addr, IOMMUTLBEntry iotlb =3D { /* We'll fill in the rest later. */ .target_as =3D &address_space_memory, - .pasid =3D vtd_as->pasid, + .pasid =3D vtd_as->pasid =3D=3D IOMMU_NO_PASID ? PCI_NO_PASID : vt= d_as->pasid, }; bool success; bool is_write =3D flag & IOMMU_WO; @@ -4017,9 +4001,8 @@ static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryR= egion *iommu, hwaddr addr, if (likely(s->dmar_enabled)) { /* Only support translated requests in scalable mode */ if (iommu_idx =3D=3D VTD_IDX_TRANSLATED && s->root_scalable) { - if (vtd_as->pasid =3D=3D PCI_NO_PASID) { - vtd_prepare_identity_entry(addr, IOMMU_RW, PCI_NO_PASID, - &iotlb); + if (vtd_as->pasid =3D=3D IOMMU_NO_PASID) { + vtd_prepare_identity_entry(addr, IOMMU_RW, &iotlb); success =3D true; } else { vtd_prepare_error_entry(&iotlb); @@ -4034,7 +4017,7 @@ static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryR= egion *iommu, hwaddr addr, } } else { /* DMAR disabled, passthrough, use 4k-page*/ - vtd_prepare_identity_entry(addr, IOMMU_RW, vtd_as->pasid, &iotlb); + vtd_prepare_identity_entry(addr, IOMMU_RW, &iotlb); success =3D true; } =20 @@ -4460,7 +4443,7 @@ static void vtd_report_sid_ir_illegal_access(IntelIOM= MUState *s, uint16_t sid, } =20 vtd_report_fault(s, VTD_FR_SM_INTERRUPT_ADDR, is_fpd_set, sid, addr, - is_write, pasid !=3D PCI_NO_PASID, pasid); + is_write, pasid !=3D IOMMU_NO_PASID, pasid); } =20 static void vtd_report_ir_illegal_access(VTDAddressSpace *vtd_as, @@ -4488,7 +4471,6 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwa= ddr addr, int ret =3D 0; MSIMessage from =3D {}, to =3D {}; uint16_t sid =3D X86_IOMMU_SID_INVALID; - uint32_t pasid; =20 from.address =3D (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; from.data =3D (uint32_t) value; @@ -4496,11 +4478,11 @@ static MemTxResult vtd_mem_ir_write(void *opaque, h= waddr addr, if (!attrs.unspecified) { /* We have explicit Source ID */ sid =3D attrs.requester_id; - pasid =3D attrs.pid !=3D 0 ? attrs.pid : PCI_NO_PASID; =20 if (attrs.address_type =3D=3D PCI_AT_TRANSLATED && sid !=3D X86_IOMMU_SID_INVALID) { - vtd_report_sid_ir_illegal_access(s, sid, pasid, from.address, = true); + vtd_report_sid_ir_illegal_access(s, sid, attrs.pid, from.addre= ss, + true); return MEMTX_ERROR; } } @@ -4562,9 +4544,19 @@ static const MemoryRegionOps vtd_mem_ir_fault_ops = =3D { }, }; =20 +/* + * This function is called by many PCIIOMMUOps callbacks to get + * VTDAddressSpace or create one if non-exist. Those callbacks are + * used by PCI sub-system and are passed in a PCI pasid value. + * + * VTD honors iommu pasid, so the first thing is to convert PCI + * pasid to iommu pasid. + */ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn, unsigned int pasid) { + pasid =3D pasid =3D=3D PCI_NO_PASID ? IOMMU_NO_PASID : pasid; + /* * We can't simply use sid here since the bus number might not be * initialized by the guest. @@ -4606,7 +4598,7 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, = PCIBus *bus, new_key->devfn =3D devfn; new_key->pasid =3D pasid; =20 - if (pasid =3D=3D PCI_NO_PASID) { + if (pasid =3D=3D IOMMU_NO_PASID) { snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), PCI_FUNC(devfn)); } else { @@ -5290,7 +5282,7 @@ error_get_fpd_and_report: vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, vtd_as->pasid); error_report: vtd_report_fault(s, -ret, is_fpd_set, sid, addr, is_write, - vtd_as->pasid !=3D PCI_NO_PASID, vtd_as->pasid); + vtd_as->pasid !=3D IOMMU_NO_PASID, vtd_as->pasid); return false; } =20 @@ -5381,7 +5373,7 @@ static int vtd_pri_request_page(PCIBus *bus, void *op= aque, int devfn, */ =20 /* We do not support PRI without PASID */ - if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + if (vtd_as->pasid =3D=3D IOMMU_NO_PASID) { return -EPERM; } if (exec_req && !is_read) { diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 8940d240a1..10bdbba632 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -207,7 +207,7 @@ static void vtd_flush_host_piotlb_locked(gpointer key, = gpointer value, return; } =20 - assert(vtd_as->pasid =3D=3D PCI_NO_PASID); + assert(vtd_as->pasid =3D=3D IOMMU_NO_PASID); =20 /* Nothing to do if there is no first stage HWPT attached */ if (!pc_entry->valid || --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779860956; cv=none; d=zohomail.com; s=zohoarc; b=iqps4DoSKqrVic6D2pNeHH0VUvfSxMFWe/LogkC7ZwwBGfx7Mx3dHk1+upTcLJDnFz6qoYD87r/6LvJCOQyl17Zzd4dZ0/PSGLaKg354eqrr5Rd4cZouSECrnVIHsMisxTmLpZTA5p0FjBcSOrJmOh5v9ykY5pdZjvuiJe004tQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779860956; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: tjaPIDNdQ4GpYyCEzEF0+g== X-CSE-MsgGUID: 1owSqVW7QxKZIccSb8L7nA== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988164" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988164" X-CSE-ConnectionGUID: GlR+SUNiTouyAdhhb50Q9w== X-CSE-MsgGUID: Nra2fZtnSVG+QnNT5THzag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086823" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 11/17] intel_iommu_accel: Handle PASID entry addition for pc_inv_dsc request Date: Wed, 27 May 2026 01:46:49 -0400 Message-ID: <20260527054658.1021096-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860958049158500 Content-Type: text/plain; charset="utf-8" Structure VTDAddressSpace includes some elements suitable for emulated device and passthrough device without PASID, e.g., address space, different memory regions, etc, it is also protected by vtd iommu lock, all these are useless and become a burden for passthrough device with PASID. When there are lots of PASIDs used in one device, the AS and MRs are all registered to memory core and impact the whole system performance. So instead of using VTDAddressSpace to cache pasid entry for each pasid of a passthrough device, we define a light weight structure VTDAccelPASIDCacheEntry with only necessary elements for each pasid. We will use this struct as a parameter to conduct binding/unbinding to nested hwpt and to record the current bound nested hwpt. It's also designed to support IOMMU_NO_PASID. VTDAccelPASIDCacheEntry is designed to only be used in intel_iommu_accel.c, similarly VTDPASIDCacheEntry should only be used in hw/i386/intel_iommu.c When guest creates new PASID entries, QEMU will capture the pc_inv_dsc (pasid cache invalidation) request, walk through each pasid in each passthrough device for valid pasid entries, create a new VTDAccelPASIDCacheEntry if not existing yet. IOMMU_NO_PASID of passthrough device still need to register MRs in case guest does not operate in scalable mode. So for IOMMU_NO_PASID, we have both VTDPASIDCacheEntry and VTDAccelPASIDCacheEntry. Co-developed-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 13 +++ hw/i386/intel_iommu_internal.h | 8 ++ hw/i386/intel_iommu.c | 3 + hw/i386/intel_iommu_accel.c | 156 +++++++++++++++++++++++++++++++++ 4 files changed, 180 insertions(+) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index e5f0b077b4..c9b1823745 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -12,6 +12,13 @@ #define HW_I386_INTEL_IOMMU_ACCEL_H #include CONFIG_DEVICES =20 +typedef struct VTDAccelPASIDCacheEntry { + VTDHostIOMMUDevice *vtd_hiod; + VTDPASIDEntry pasid_entry; + uint32_t pasid; + QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; +} VTDAccelPASIDCacheEntry; + #ifdef CONFIG_VTD_ACCEL bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); @@ -20,6 +27,7 @@ bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, E= rror **errp); void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, uint32_t pasid, hwaddr addr, uint64_t npages, bool ih); +void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -49,6 +57,11 @@ static inline void vtd_flush_host_piotlb_all_locked(Inte= lIOMMUState *s, { } =20 +static inline void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index ee59df09f8..9307825017 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -615,6 +615,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 +#define VTD_SM_CONTEXT_ENTRY_PDTS(x) extract64((x)->val[0], 9, 3) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL @@ -645,6 +646,7 @@ typedef struct VTDPIOTLBInvInfo { #define VTD_PASID_DIR_BITS_MASK (0x3fffULL) #define VTD_PASID_DIR_INDEX(pasid) (((pasid) >> 6) & VTD_PASID_DIR_BITS= _MASK) #define VTD_PASID_DIR_FPD (1ULL << 1) /* Fault Processing Disa= ble */ +#define VTD_PASID_TABLE_ENTRY_NUM (1ULL << 6) #define VTD_PASID_TABLE_BITS_MASK (0x3fULL) #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK) #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disa= ble */ @@ -710,6 +712,7 @@ typedef struct VTDHostIOMMUDevice { PCIBus *bus; uint8_t devfn; HostIOMMUDevice *hiod; + QLIST_HEAD(, VTDAccelPASIDCacheEntry) pasid_cache_list; } VTDHostIOMMUDevice; =20 /* @@ -767,6 +770,11 @@ static inline int vtd_pasid_entry_compare(VTDPASIDEntr= y *p1, VTDPASIDEntry *p2) return memcmp(p1, p2, sizeof(*p1)); } =20 +static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce) +{ + return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7); +} + int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, VTDPASIDDirEntry *pdire); int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2deea8fbe2..94a6a740f1 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3181,6 +3181,8 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, = VTDPASIDCacheInfo *pc_info) g_hash_table_foreach(s->vtd_address_spaces, vtd_pasid_cache_sync_locke= d, pc_info); vtd_iommu_unlock(s); + + vtd_accel_pasid_cache_sync(s, pc_info); } =20 static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s) @@ -4751,6 +4753,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->devfn =3D (uint8_t)devfn; vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; + QLIST_INIT(&vtd_hiod->pasid_cache_list); =20 if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 10bdbba632..a66d63b4c8 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -259,6 +259,162 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState= *s, uint16_t domain_id, vtd_flush_host_piotlb_locked, &piotlb_info); } =20 +static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid, + VTDPASIDEntry *pe) +{ + VTDAccelPASIDCacheEntry *vtd_pce; + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + if (vtd_pce->pasid =3D=3D pasid) { + if (vtd_pasid_entry_compare(pe, &vtd_pce->pasid_entry)) { + vtd_pce->pasid_entry =3D *pe; + } + return; + } + } + + vtd_pce =3D g_malloc0(sizeof(VTDAccelPASIDCacheEntry)); + vtd_pce->vtd_hiod =3D vtd_hiod; + vtd_pce->pasid =3D pasid; + vtd_pce->pasid_entry =3D *pe; + QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); +} + +/* + * This function walks over PASID range within [start, end) in a single + * PASID table for entries matching @info type/did, then create + * VTDAccelPASIDCacheEntry if not exist yet. + */ +static void vtd_sm_pasid_table_walk_one(VTDHostIOMMUDevice *vtd_hiod, + dma_addr_t pt_base, int start, int= end, + VTDPASIDCacheInfo *info) +{ + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + VTDPASIDEntry pe; + int pasid; + + for (pasid =3D start; pasid < end; pasid++) { + if (vtd_get_pe_in_pasid_leaf_table(s, pasid, pt_base, &pe) || + !vtd_pe_present(&pe)) { + continue; + } + + if ((info->type =3D=3D VTD_INV_DESC_PASIDC_G_DSI || + info->type =3D=3D VTD_INV_DESC_PASIDC_G_PASID_SI) && + (info->did !=3D VTD_SM_PASID_ENTRY_DID(&pe))) { + /* + * VTD_PASID_CACHE_DOMSI and VTD_PASID_CACHE_PASIDSI + * requires domain id check. If domain id check fail, + * go to next pasid. + */ + continue; + } + + vtd_accel_fill_pc(vtd_hiod, pasid, &pe); + } +} + +/* + * In VT-d scalable mode translation, PASID dir + PASID table is used. + * This function aims at looping over a range of PASIDs in the given + * two level table to identify the pasid config in guest. + */ +static void vtd_sm_pasid_table_walk(VTDHostIOMMUDevice *vtd_hiod, + dma_addr_t pdt_base, int start, int en= d, + VTDPASIDCacheInfo *info) +{ + VTDPASIDDirEntry pdire; + int pasid =3D start; + int pasid_next; + dma_addr_t pt_base; + + while (pasid < end) { + pasid_next =3D (pasid + VTD_PASID_TABLE_ENTRY_NUM) & + ~(VTD_PASID_TABLE_ENTRY_NUM - 1); + pasid_next =3D pasid_next < end ? pasid_next : end; + + if (!vtd_get_pdire_from_pdir_table(pdt_base, pasid, &pdire) + && vtd_pdire_present(&pdire)) { + pt_base =3D pdire.val & VTD_PASID_TABLE_BASE_ADDR_MASK; + vtd_sm_pasid_table_walk_one(vtd_hiod, pt_base, pasid, pasid_ne= xt, + info); + } + pasid =3D pasid_next; + } +} + +static void vtd_accel_replay_pasid_bind_for_dev(VTDHostIOMMUDevice *vtd_hi= od, + int start, int end, + VTDPASIDCacheInfo *pc_info) +{ + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + VTDContextEntry ce; + int dev_max_pasid =3D 1 << vtd_hiod->hiod->caps.max_pasid_log2; + + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_hiod->bus), + vtd_hiod->devfn, &ce)) { + VTDPASIDCacheInfo walk_info =3D *pc_info; + uint32_t ce_max_pasid =3D vtd_sm_ce_get_pdt_entry_num(&ce) * + VTD_PASID_TABLE_ENTRY_NUM; + + end =3D MIN(end, MIN(dev_max_pasid, ce_max_pasid)); + + vtd_sm_pasid_table_walk(vtd_hiod, VTD_CE_GET_PASID_DIR_TABLE(&ce), + start, end, &walk_info); + } +} + +/* + * This function replays the guest pasid bindings by walking the two level + * guest PASID table. For each valid pasid entry, it creates an entry + * VTDAccelPASIDCacheEntry dynamically if not exist yet. This entry holds + * info specific to a pasid + */ +void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info) +{ + int start =3D IOMMU_NO_PASID, end =3D 1 << s->pasid; + VTDHostIOMMUDevice *vtd_hiod; + GHashTableIter hiod_it; + + if (!s->fsts) { + return; + } + + switch (pc_info->type) { + case VTD_INV_DESC_PASIDC_G_PASID_SI: + start =3D pc_info->pasid; + end =3D pc_info->pasid + 1; + /* fall through */ + case VTD_INV_DESC_PASIDC_G_DSI: + /* + * loop all assigned devices, do domain id check in + * vtd_sm_pasid_table_walk_one() after get pasid entry. + */ + break; + case VTD_INV_DESC_PASIDC_G_GLOBAL: + /* loop all assigned devices */ + break; + default: + g_assert_not_reached(); + } + + /* + * Loop all the vtd_hiod instances to sync the "pasid cache" per the + * guest pasid configuration. + * + * VTD translation callback never accesses vtd_hiod and its correspond= ing + * cached pasid entry, so no iommu lock needed here. + */ + g_hash_table_iter_init(&hiod_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&hiod_it, NULL, (void **)&vtd_hiod)) { + if (!object_dynamic_cast(OBJECT(vtd_hiod->hiod), + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { + continue; + } + vtd_accel_replay_pasid_bind_for_dev(vtd_hiod, start, end, pc_info); + } +} + static uint64_t vtd_get_host_iommu_quirks(uint32_t type, void *caps, uint32_t size) { --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779860974; cv=none; d=zohomail.com; s=zohoarc; b=ZBUl3AcuzR1L1lol55AFFOdQTlBzNZu+srJzPtyIR1HxHFmrrVRC9gTzanw0umiu7wegVoDmGi3eiFyPS9T28Ddpxe0/Jk2fngcmtb32ekXtKZ6RZC5551CyvsF/TUnUm7t6eR2VYL9AziN4ANKpz7MN/sA2/IDQ6n/wVphd+jQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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bh=vRgsO4g1d6cBRiuDJ6YltRBCADtcgB3A7zjA+Wnu9dw=; b=NMeAqJLRWiYJJy9Ekk/1EHtILjPHibzw3qel0+HFR6Q91UcfEwuG3Pz3 hrffBWF0hgVD6gOKbKwKJeaul1W/TleuYrDzaKx4WGL2dhXVBsYFhs3cW cWjby97Z9qufFp6BO0QS88W03vqQfpKwcoOHc9IeYYERysf8Wnv2X7AV7 oVxqRUykMm4+Yi5JvXBtTD0DQgGeaITp5cCCYDOgGsJdollVx/UVT1081 tZuEguw62fMxYuIilTLas++drPbdealFDPHS6ebsVTuW+5kT2x0Td+RK8 sIm/kmCNCY2BM4rdrJZmv3maFWrdn1uszm3/Whwye3VnMMiuuIGcuT2Dw w==; X-CSE-ConnectionGUID: 5+16K6IQS6ynsaboTGCJyg== X-CSE-MsgGUID: 3LsaZS8BRVifXPyAKMf1Ww== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988170" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988170" X-CSE-ConnectionGUID: 2BIE0/0kRDOCv3iVELv/ig== X-CSE-MsgGUID: PV14E8J2RPW3vEnzs8QcxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086834" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 12/17] intel_iommu_accel: Handle PASID entry removal for pc_inv_dsc request Date: Wed, 27 May 2026 01:46:50 -0400 Message-ID: <20260527054658.1021096-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779860975904158500 Content-Type: text/plain; charset="utf-8" When guest deletes PASID entries, QEMU will capture the pasid cache invalidation request, walk through pasid_cache_list in each passthrough device to find stale VTDAccelPASIDCacheEntry and delete them. Co-developed-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.c | 61 +++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index a66d63b4c8..b6c560753e 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -280,6 +280,59 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_= hiod, uint32_t pasid, QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); } =20 +static void vtd_accel_delete_pc(VTDAccelPASIDCacheEntry *vtd_pce) +{ + QLIST_REMOVE(vtd_pce, next); + g_free(vtd_pce); +} + +static void +vtd_accel_pasid_cache_invalidate_one(VTDAccelPASIDCacheEntry *vtd_pce, + VTDPASIDCacheInfo *pc_info) +{ + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; + VTDPASIDEntry pe; + uint16_t did; + + /* + * VTD_INV_DESC_PASIDC_G_DSI and VTD_INV_DESC_PASIDC_G_PASID_SI require + * DID check. If DID doesn't match the value in cache or memory, then + * it's not a pasid entry we want to invalidate. + */ + switch (pc_info->type) { + case VTD_INV_DESC_PASIDC_G_PASID_SI: + if (pc_info->pasid !=3D vtd_pce->pasid) { + return; + } + /* Fall through */ + case VTD_INV_DESC_PASIDC_G_DSI: + did =3D VTD_SM_PASID_ENTRY_DID(&vtd_pce->pasid_entry); + if (pc_info->did !=3D did) { + return; + } + } + + if (vtd_dev_get_pe_from_pasid(vtd_hiod->iommu_state, vtd_hiod->bus, + vtd_hiod->devfn, vtd_pce->pasid, &pe)) { + /* + * No valid pasid entry in guest memory. e.g. pasid entry was modi= fied + * to be either all-zero or non-present. Either case means existing + * pasid cache should be invalidated. + */ + vtd_accel_delete_pc(vtd_pce); + } +} + +static void vtd_accel_pasid_cache_invalidate(VTDHostIOMMUDevice *vtd_hiod, + VTDPASIDCacheInfo *pc_info) +{ + VTDAccelPASIDCacheEntry *vtd_pce, *next; + + QLIST_FOREACH_SAFE(vtd_pce, &vtd_hiod->pasid_cache_list, next, next) { + vtd_accel_pasid_cache_invalidate_one(vtd_pce, pc_info); + } +} + /* * This function walks over PASID range within [start, end) in a single * PASID table for entries matching @info type/did, then create @@ -411,6 +464,14 @@ void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VT= DPASIDCacheInfo *pc_info) TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { continue; } + + /* + * The replay path inevitably needs to iterate through existing + * PASID cache entries. Since cached PASID entries that are marked + * for removal don't need to be iterated, we intentionally handle + * removals before additions to optimize the replay process. + */ + vtd_accel_pasid_cache_invalidate(vtd_hiod, pc_info); vtd_accel_replay_pasid_bind_for_dev(vtd_hiod, start, end, pc_info); } } --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779861005; cv=none; d=zohomail.com; s=zohoarc; b=Lz34cKvpO4kQPRlW8D5BHwlTQJhM0QsRx9jswchJygoEgyHUTTr3Tx+yJhbfBqEe1pHXwULTZMVwEKJis7vV6WoExc28fTFHUquaOPOanMY99xKK8SjfLJ0nlNBHxmX1gZAfVav7x0Otar/KXHoilVC6zYY4t34JeG5v6WMcHkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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bh=WmvttA5APZjBvPH3sYtQBL5xVErvKSF69eLmvvUhMAI=; b=F4mwbFtgkPeXrYW8J+vZZrzxyWscPxbeXw7uCbuJ98b7Ywcpo1Z58uzZ l2C+injjES23OAlYoHNZLQUhthCnp4xGPgG3xUXpRRqr4EbjX16VJrP6v hNUoUkHVVBVxVOUhG2uSdguCM1zAL8JOgxdiftCubD3Vdrfk//0IDPznd a7njjJ3a9a62rnEMOTFFDqQGP7YpqJAs/n3G2KpSSUfOGvSRMXkPgIpjW lMdRtKzrwykXtwOZbuFwF3TCsj1w/10g1gVbB1NqXtIxwO462o+Anj0HR vitZFpOoLFl++7yctUZ5qvxLxL2NR4YigKhQRoHUojaow4tKt3AKhle/7 w==; X-CSE-ConnectionGUID: XZ+rTuMwSO+raNATLDrnXg== X-CSE-MsgGUID: WmeGzcT7S/6vxno9qU0d6A== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988178" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988178" X-CSE-ConnectionGUID: /SYnOcaFRPONapNOOASH+g== X-CSE-MsgGUID: J2f8UTSgQeK/0twdRw+EyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086847" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 13/17] intel_iommu_accel: Bypass PASID entry addition for just deleted entry Date: Wed, 27 May 2026 01:46:51 -0400 Message-ID: <20260527054658.1021096-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861006302158500 Content-Type: text/plain; charset="utf-8" For VTD_INV_DESC_PASIDC_G_PASID_SI typed pc_inv_dsc invalidation, if an pasid entry is just removed, it can never be a new entry to add. So calling vtd_replay_pasid_bind_for_dev() is unnecessary. Introduce a new field accel_pce_deleted in VTDPASIDCacheInfo to mark this case and to do the bypassing. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Tested-by: Xudong Hao --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu_accel.c | 16 +++++++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 9307825017..64a38afa85 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -630,6 +630,7 @@ typedef struct VTDPASIDCacheInfo { uint8_t type; uint16_t did; uint32_t pasid; + bool accel_pce_deleted; } VTDPASIDCacheInfo; =20 typedef struct VTDPIOTLBInvInfo { diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index b6c560753e..f5fc6327b6 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -280,10 +280,15 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd= _hiod, uint32_t pasid, QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); } =20 -static void vtd_accel_delete_pc(VTDAccelPASIDCacheEntry *vtd_pce) +static void vtd_accel_delete_pc(VTDAccelPASIDCacheEntry *vtd_pce, + VTDPASIDCacheInfo *pc_info) { QLIST_REMOVE(vtd_pce, next); g_free(vtd_pce); + + if (pc_info->type =3D=3D VTD_INV_DESC_PASIDC_G_PASID_SI) { + pc_info->accel_pce_deleted =3D true; + } } =20 static void @@ -319,7 +324,7 @@ vtd_accel_pasid_cache_invalidate_one(VTDAccelPASIDCache= Entry *vtd_pce, * to be either all-zero or non-present. Either case means existing * pasid cache should be invalidated. */ - vtd_accel_delete_pc(vtd_pce); + vtd_accel_delete_pc(vtd_pce, pc_info); } } =20 @@ -472,7 +477,12 @@ void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VT= DPASIDCacheInfo *pc_info) * removals before additions to optimize the replay process. */ vtd_accel_pasid_cache_invalidate(vtd_hiod, pc_info); - vtd_accel_replay_pasid_bind_for_dev(vtd_hiod, start, end, pc_info); + + if (pc_info->accel_pce_deleted) { + pc_info->accel_pce_deleted =3D false; + } else { + vtd_accel_replay_pasid_bind_for_dev(vtd_hiod, start, end, pc_i= nfo); + } } } =20 --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; 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d="scan'208";a="241086857" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 14/17] intel_iommu_accel: Handle PASID entry removal for system reset Date: Wed, 27 May 2026 01:46:52 -0400 Message-ID: <20260527054658.1021096-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861001840154100 Content-Type: text/plain; charset="utf-8" When system level reset, DMA translation is turned off, all PASID entries become stale and should be deleted. vtd_hiod list is never accessed without BQL, so no need to guard with iommu lock. Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 5 +++++ hw/i386/intel_iommu.c | 2 ++ hw/i386/intel_iommu_accel.c | 13 +++++++++++++ 3 files changed, 20 insertions(+) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index c9b1823745..a2226b28b6 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -28,6 +28,7 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s,= uint16_t domain_id, uint32_t pasid, hwaddr addr, uint64_t npages, bool ih); void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); +void vtd_accel_pasid_cache_reset(IntelIOMMUState *s); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -62,6 +63,10 @@ static inline void vtd_accel_pasid_cache_sync(IntelIOMMU= State *s, { } =20 +static inline void vtd_accel_pasid_cache_reset(IntelIOMMUState *s) +{ +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 94a6a740f1..c6e69c47b3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -391,6 +391,8 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_reset_context_cache_locked(s); vtd_pasid_cache_reset_locked(s); vtd_iommu_unlock(s); + + vtd_accel_pasid_cache_reset(s); } =20 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index f5fc6327b6..a445d6276e 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -486,6 +486,19 @@ void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VT= DPASIDCacheInfo *pc_info) } } =20 +/* Fake a global pasid cache invalidation to remove all pasid cache entrie= s */ +void vtd_accel_pasid_cache_reset(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D { .type =3D VTD_INV_DESC_PASIDC_G_GLOBAL= }; + VTDHostIOMMUDevice *vtd_hiod; + GHashTableIter hiod_it; + + g_hash_table_iter_init(&hiod_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&hiod_it, NULL, (void **)&vtd_hiod)) { + vtd_accel_pasid_cache_invalidate(vtd_hiod, &pc_info); + } +} + static uint64_t vtd_get_host_iommu_quirks(uint32_t type, void *caps, uint32_t size) { --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="90988192" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988192" X-CSE-ConnectionGUID: Svu6OoQ2TeGnFhajezGTOg== X-CSE-MsgGUID: kZ1wfrC0SQ2YGS/wTM3jcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086861" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 15/17] intel_iommu_accel: Switch to VTDAccelPASIDCacheEntry for PASID bind/unbind and PIOTLB invalidation Date: Wed, 27 May 2026 01:46:53 -0400 Message-ID: <20260527054658.1021096-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861030267158500 Content-Type: text/plain; charset="utf-8" This patch switches from VTDAddressSpace to VTDAccelPASIDCacheEntry for handling PASID bind/unbind operations and PIOTLB invalidations in passthrough scenarios. VTDAccelPASIDCacheEntry was introduced to cache PASID entries for passthrough devices and is now ready to propagate PASID bind/unbind operations and PIOTLB invalidations to the host. Unlike the previous approach, VTDAccelPASIDCacheEntry supports both IOMMU_NO_PASID (rid_pasid) and other valid PASIDs, so this switch drops IOMMU_NO_PASID limitations that existed in the prior PASID bind/unbind and PIOTLB invalidation path. For IOMMU_NO_PASID of passthrough devices, VTDAddressSpace continues to handle shadow page modifications to the host, but no longer manages PASID bind/unbind operations or PIOTLB invalidations for passthrough scenarios. Co-developed-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao --- hw/i386/intel_iommu_accel.h | 2 +- include/hw/i386/intel_iommu.h | 2 - hw/i386/intel_iommu.c | 17 +---- hw/i386/intel_iommu_accel.c | 131 +++++++++++++++++----------------- 4 files changed, 68 insertions(+), 84 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index a2226b28b6..4a9003c92d 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -16,6 +16,7 @@ typedef struct VTDAccelPASIDCacheEntry { VTDHostIOMMUDevice *vtd_hiod; VTDPASIDEntry pasid_entry; uint32_t pasid; + uint32_t fs_hwpt_id; QLIST_ENTRY(VTDAccelPASIDCacheEntry) next; } VTDAccelPASIDCacheEntry; =20 @@ -23,7 +24,6 @@ typedef struct VTDAccelPASIDCacheEntry { bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); -bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp); void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, uint32_t pasid, hwaddr addr, uint64_t npages, bool ih); diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 95c76015e4..1842ba5840 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -154,8 +154,6 @@ struct VTDAddressSpace { * with the guest IOMMU pgtables for a device. */ IOVATree *iova_tree; - - uint32_t fs_hwpt_id; }; =20 struct VTDIOTLBEntry { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c6e69c47b3..c0859bafd1 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -86,8 +86,6 @@ static void vtd_pasid_cache_reset_locked(IntelIOMMUState = *s) VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; if (pc_entry->valid) { pc_entry->valid =3D false; - /* It's fatal to get failure during reset */ - vtd_propagate_guest_pasid(vtd_as, &error_fatal); } } } @@ -3104,8 +3102,6 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, VTDPASIDEntry pe; IOMMUNotifier *n; uint16_t did; - const char *err_prefix =3D "Attaching to HWPT failed: "; - Error *local_err =3D NULL; =20 if (vtd_dev_get_pe_from_pasid(vtd_as->iommu_state, vtd_as->bus, vtd_as->devfn, vtd_as->pasid, &pe)) { @@ -3127,9 +3123,6 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, vtd_address_space_unmap(vtd_as, n); } vtd_switch_address_space(vtd_as); - - err_prefix =3D "Detaching from HWPT failed: "; - goto do_bind_unbind; } =20 /* @@ -3157,20 +3150,12 @@ static void vtd_pasid_cache_sync_locked(gpointer ke= y, gpointer value, if (!pc_entry->valid) { pc_entry->pasid_entry =3D pe; pc_entry->valid =3D true; - } else if (vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { - err_prefix =3D "Replacing HWPT attachment failed: "; - } else { + } else if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { return; } =20 vtd_switch_address_space(vtd_as); vtd_address_space_sync(vtd_as); - -do_bind_unbind: - /* TODO: Fault event injection into guest, report error to QEMU for no= w */ - if (!vtd_propagate_guest_pasid(vtd_as, &local_err)) { - error_reportf_err(local_err, "%s", err_prefix); - } } =20 static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index a445d6276e..cb0980d0e9 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -89,24 +89,25 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_= hiod, fs_hwpt_id, errp); } =20 -static void vtd_destroy_old_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, - VTDAddressSpace *vtd_as) +static void vtd_destroy_old_fs_hwpt(VTDAccelPASIDCacheEntry *vtd_pce) { - HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); + HostIOMMUDeviceIOMMUFD *hiodi =3D + HOST_IOMMU_DEVICE_IOMMUFD(vtd_pce->vtd_hiod->hiod); =20 - if (!vtd_as->fs_hwpt_id) { + if (!vtd_pce->fs_hwpt_id) { return; } - iommufd_backend_free_id(hiodi->iommufd, vtd_as->fs_hwpt_id); - vtd_as->fs_hwpt_id =3D 0; + iommufd_backend_free_id(hiodi->iommufd, vtd_pce->fs_hwpt_id); + vtd_pce->fs_hwpt_id =3D 0; } =20 -static bool vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, - VTDAddressSpace *vtd_as, Error **err= p) +static bool vtd_device_attach_iommufd(VTDAccelPASIDCacheEntry *vtd_pce, + Error **errp) { + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); - VTDPASIDEntry *pe =3D &vtd_as->pasid_cache_entry.pasid_entry; - uint32_t hwpt_id =3D hiodi->hwpt_id; + VTDPASIDEntry *pe =3D &vtd_pce->pasid_entry; + uint32_t hwpt_id =3D hiodi->hwpt_id, pasid =3D vtd_pce->pasid; bool ret; =20 /* @@ -126,14 +127,13 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDev= ice *vtd_hiod, } } =20 - ret =3D host_iommu_device_iommufd_attach_hwpt(hiodi, IOMMU_NO_PASID, h= wpt_id, - errp); - trace_vtd_device_attach_hwpt(hiodi->devid, IOMMU_NO_PASID, hwpt_id, re= t); + ret =3D host_iommu_device_iommufd_attach_hwpt(hiodi, pasid, hwpt_id, e= rrp); + trace_vtd_device_attach_hwpt(hiodi->devid, pasid, hwpt_id, ret); if (ret) { /* Destroy old fs_hwpt if it's a replacement */ - vtd_destroy_old_fs_hwpt(vtd_hiod, vtd_as); + vtd_destroy_old_fs_hwpt(vtd_pce); if (vtd_pe_pgtt_is_fst(pe)) { - vtd_as->fs_hwpt_id =3D hwpt_id; + vtd_pce->fs_hwpt_id =3D hwpt_id; } } else if (vtd_pe_pgtt_is_fst(pe)) { iommufd_backend_free_id(hiodi->iommufd, hwpt_id); @@ -142,17 +142,19 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDev= ice *vtd_hiod, return ret; } =20 -static bool vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, - VTDAddressSpace *vtd_as, Error **err= p) +static bool vtd_device_detach_iommufd(VTDAccelPASIDCacheEntry *vtd_pce, + Error **errp) { + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->= hiod); - IntelIOMMUState *s =3D vtd_as->iommu_state; + + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + uint32_t pasid =3D vtd_pce->pasid; bool ret; =20 - if (s->dmar_enabled && s->root_scalable) { - ret =3D host_iommu_device_iommufd_detach_hwpt(hiodi, IOMMU_NO_PASI= D, - errp); - trace_vtd_device_detach_hwpt(hiodi->devid, IOMMU_NO_PASID, ret); + if (pasid !=3D IOMMU_NO_PASID || (s->dmar_enabled && s->root_scalable)= ) { + ret =3D host_iommu_device_iommufd_detach_hwpt(hiodi, pasid, errp); + trace_vtd_device_detach_hwpt(hiodi->devid, pasid, ret); } else { /* * If DMAR remapping is disabled or guest switches to legacy mode, @@ -166,58 +168,32 @@ static bool vtd_device_detach_iommufd(VTDHostIOMMUDev= ice *vtd_hiod, } =20 if (ret) { - vtd_destroy_old_fs_hwpt(vtd_hiod, vtd_as); + vtd_destroy_old_fs_hwpt(vtd_pce); } =20 return ret; } =20 -bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp) -{ - VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; - VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); - - /* Ignore emulated device or legacy VFIO backed device */ - if (!vtd_as->iommu_state->fsts || !vtd_hiod) { - return true; - } - - if (pc_entry->valid) { - return vtd_device_attach_iommufd(vtd_hiod, vtd_as, errp); - } - - return vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); -} - /* - * This function is a loop function for the s->vtd_address_spaces - * list with VTDPIOTLBInvInfo as execution filter. It propagates - * the piotlb invalidation to host. + * This function is a loop function for the s->vtd_host_iommu_dev + * and vtd_hiod->pasid_cache_list lists with VTDPIOTLBInvInfo as + * execution filter. It propagates the piotlb invalidation to host. */ -static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value, - gpointer user_data) +static void vtd_flush_host_piotlb_locked(VTDAccelPASIDCacheEntry *vtd_pce, + VTDPIOTLBInvInfo *piotlb_info) { - VTDPIOTLBInvInfo *piotlb_info =3D user_data; - VTDAddressSpace *vtd_as =3D value; - VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); - VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; + VTDPASIDEntry *pe =3D &vtd_pce->pasid_entry; uint16_t did; =20 - if (!vtd_hiod) { - return; - } - - assert(vtd_as->pasid =3D=3D IOMMU_NO_PASID); - /* Nothing to do if there is no first stage HWPT attached */ - if (!pc_entry->valid || - !vtd_pe_pgtt_is_fst(&pc_entry->pasid_entry)) { + if (!vtd_pe_pgtt_is_fst(pe)) { return; } =20 - did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); + did =3D VTD_SM_PASID_ENTRY_DID(pe); =20 - if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D IOM= MU_NO_PASID) { + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D vtd= _pce->pasid) { HostIOMMUDeviceIOMMUFD *hiodi =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); uint32_t entry_num =3D 1; /* Only implement one request for simpli= city */ @@ -225,7 +201,7 @@ static void vtd_flush_host_piotlb_locked(gpointer key, = gpointer value, struct iommu_hwpt_vtd_s1_invalidate *cache =3D piotlb_info->inv_da= ta; =20 if (!iommufd_backend_invalidate_cache(hiodi->iommufd, - vtd_as->fs_hwpt_id, + vtd_pce->fs_hwpt_id, IOMMU_HWPT_INVALIDATE_DATA_V= TD_S1, sizeof(*cache), &entry_num, = cache, &local_err)) { @@ -241,6 +217,8 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *= s, uint16_t domain_id, { struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; VTDPIOTLBInvInfo piotlb_info; + VTDHostIOMMUDevice *vtd_hiod; + GHashTableIter hiod_it; =20 cache_info.addr =3D addr; cache_info.npages =3D npages; @@ -251,23 +229,36 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState= *s, uint16_t domain_id, piotlb_info.inv_data =3D &cache_info; =20 /* - * Go through each vtd_as instance in s->vtd_address_spaces, find out - * affected host devices which need host piotlb invalidation. Piotlb - * invalidation should check pasid cache per architecture point of vie= w. + * Go through each vtd_pce in vtd_hiod->pasid_cache_list for each host + * device, find out affected host device pasid which need host piotlb + * invalidation. Piotlb invalidation should check pasid cache per + * architecture point of view. */ - g_hash_table_foreach(s->vtd_address_spaces, - vtd_flush_host_piotlb_locked, &piotlb_info); + g_hash_table_iter_init(&hiod_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&hiod_it, NULL, (void **)&vtd_hiod)) { + VTDAccelPASIDCacheEntry *vtd_pce; + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + vtd_flush_host_piotlb_locked(vtd_pce, &piotlb_info); + } + } } =20 static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid, VTDPASIDEntry *pe) { VTDAccelPASIDCacheEntry *vtd_pce; + Error *local_err =3D NULL; =20 QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { if (vtd_pce->pasid =3D=3D pasid) { if (vtd_pasid_entry_compare(pe, &vtd_pce->pasid_entry)) { vtd_pce->pasid_entry =3D *pe; + + if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { + error_reportf_err(local_err, "%s", + "Replacing HWPT attachment failed: "= ); + } } return; } @@ -278,11 +269,21 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd= _hiod, uint32_t pasid, vtd_pce->pasid =3D pasid; vtd_pce->pasid_entry =3D *pe; QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); + + if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { + error_reportf_err(local_err, "%s", "Attaching to HWPT failed: "); + } } =20 static void vtd_accel_delete_pc(VTDAccelPASIDCacheEntry *vtd_pce, VTDPASIDCacheInfo *pc_info) { + Error *local_err =3D NULL; + + if (!vtd_device_detach_iommufd(vtd_pce, &local_err)) { + error_reportf_err(local_err, "%s", "Detaching from HWPT failed: "); + } + QLIST_REMOVE(vtd_pce, next); g_free(vtd_pce); =20 --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1779861004; cv=none; d=zohomail.com; s=zohoarc; b=MaxtI1y3oDcpeYSXvFH+W4zOuvUDuMOv4R0wiErltVteMcAPVZR17XqPLOxYGs0DVg9bN+ZfUk4w0R8wwAiy+b9rLusuJ5Win6cJjm3byDt+q/2/+WH2ySaPMN90Sr3g0cR7OsnXSmxRui8Hzpfbf7zLLndBiBv2Fv8q939FGUE= ARC-Message-Signature: i=1; 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bh=RLswROHfylx/DZL1zYO+CJGvFTfDOm22EO3Fx8+t55U=; b=MIs69Nuqc/iMBriAiE6Wg5XyHkZRZK1rJCngIuTy3d70Wis4tO15XlK9 P7QFoxZU4s7j0dYWFYNz3PUvloKC4qfNFEAZFfEgn/2Uvg368swWYgHmf Rn7eV9YSC/SvhooTIAkwb2rs4S95qtEI5NarBXVYKYo2afm2fblpbOFYE nevgKdUL7gQ6h7FaG8MxL3fmu9gv8BsC5sQeT2BUnW8V/V8tCTZnnJ9Fo 4zYrWSDjsql6hUVuFYaGGnmgE4np8upGUimVj7tv/sfUSfO5EmUTmXDUp pMy8ILpcm0X2KO6Q+Q58NQI7Umk/AQ/bCUGNfqbTRucpEat0Cz6Z92qGR w==; X-CSE-ConnectionGUID: UzUBZWJyQ7anC9agdjAo4Q== X-CSE-MsgGUID: KdsDihd0QOCzuI2pGuzq/g== X-IronPort-AV: E=McAfee;i="6800,10657,11798"; a="90988200" X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="90988200" X-CSE-ConnectionGUID: MdGJ49tTRVGAMEVEOcdFBw== X-CSE-MsgGUID: lRmIEfrcRxeiz11ytymDjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,170,1774335600"; d="scan'208";a="241086866" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 16/17] intel_iommu_accel: Add pasid bits size check Date: Wed, 27 May 2026 01:46:54 -0400 Message-ID: <20260527054658.1021096-17-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861005880154100 Content-Type: text/plain; charset="utf-8" If pasid bits size is bigger than host side, host could fail to emulate all bindings in guest. Add a check to fail device plug early. Signed-off-by: Zhenzhong Duan Tested-by: Xudong Hao Reviewed-by: Clement Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu_accel.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 64a38afa85..924e91cb8a 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -196,6 +196,7 @@ #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_NWFS (1ULL << 33) #define VTD_ECAP_SET_PSS(x, v) ((x)->ecap =3D deposit64((x)->ecap, 35= , 5, v)) +#define VTD_ECAP_GET_PSS(ecap) extract64(ecap, 35, 5) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_PDS (1ULL << 42) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index cb0980d0e9..b19cd56645 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -22,6 +22,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMM= UDevice *vtd_hiod, HostIOMMUDevice *hiod =3D vtd_hiod->hiod; struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + uint8_t hpasid =3D VTD_ECAP_GET_PSS(vtd->ecap_reg) + 1; PCIBus *bus =3D vtd_hiod->bus; PCIDevice *pdev =3D bus->devices[vtd_hiod->devfn]; =20 @@ -42,6 +43,13 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOM= MUDevice *vtd_hiod, return false; } =20 + /* Only do the check when host device support PASIDs */ + if (caps->max_pasid_log2 && s->pasid > hpasid) { + error_setg(errp, "PASID bits size %d > host IOMMU PASID bits size = %d", + s->pasid, hpasid); + return false; + } + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { error_setg(errp, "Host device downstream to a PCI bridge is " "unsupported when x-flts=3Don"); --=20 2.47.3 From nobody Sat May 30 17:44:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="241086872" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v6 17/17] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED and VIOMMU_FLAG_WANT_PASID_ATTACH Date: Wed, 27 May 2026 01:46:55 -0400 Message-ID: <20260527054658.1021096-18-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260527054658.1021096-1-zhenzhong.duan@intel.com> References: <20260527054658.1021096-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=198.175.65.11; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1779861078313158500 Content-Type: text/plain; charset="utf-8" VFIO device will check flag VIOMMU_FLAG_PASID_SUPPORTED and expose PASID capability, also check VIOMMU_FLAG_WANT_PASID_ATTACH to enable pasid attachment, without those guest could not enable PASID of this device even if vIOMMU's pasid is configured. We don't expose the two flags when fist stage translation is not configured as we don't support shadow page table on a PASID. This is the final knob to enable PASID. Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Reviewed-by: Clement Mathieu--Drif Tested-by: Xudong Hao --- hw/i386/intel_iommu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c0859bafd1..572c260726 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4788,6 +4788,11 @@ static uint64_t vtd_get_viommu_flags(void *opaque) if (s->fsts) { flags =3D VIOMMU_FLAG_WANT_NESTING_PARENT | VIOMMU_FLAG_WANT_NESTING_DIRTY_TRACKING; + + if (s->pasid) { + flags |=3D VIOMMU_FLAG_PASID_SUPPORTED | + VIOMMU_FLAG_WANT_PASID_ATTACH; + } } =20 return flags; --=20 2.47.3