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Tue, 26 May 2026 20:03:35 -0700 (PDT) From: stephensportia@gmail.com To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Alistair Francis , Chao Liu , Daniel Henrique Barboza , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , Portia Stephens Subject: [PATCH v2] target/riscv: Add support for a custom CPU arch state Date: Wed, 27 May 2026 13:03:27 +1000 Message-ID: <20260527030327.2289-1-stephensportia@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=stephensportia@gmail.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779851076839154100 Content-Type: text/plain; charset="utf-8" From: Portia Stephens Custom vendor CSR implementations may require custom state information. This adds a custom_arch-state struct to the CPUArchState. It also adds a RISCVCPUDef function pointer for handling allocation and initialization of the custom_arch_state as well as a reset function pointer for setting the custom_arch_state fields to known values on reset. Signed-off-by: Portia Stephens --- target/riscv/cpu.c | 15 +++++++++++++++ target/riscv/cpu.h | 7 +++++++ 2 files changed, 22 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 862834b480..ca557d27b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,6 +819,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } + + if (mcc->def->custom_arch_state_reset) { + mcc->def->custom_arch_state_reset(env); + } #endif } =20 @@ -1167,6 +1171,9 @@ static void riscv_cpu_init(Object *obj) if (mcc->def->custom_csrs) { riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); } + if (mcc->def->custom_arch_state_init) { + mcc->def->custom_arch_state_init(&cpu->env); + } #endif =20 accel_cpu_instance_init(CPU(obj)); @@ -2706,6 +2713,14 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) assert(!mcc->def->custom_csrs); mcc->def->custom_csrs =3D def->custom_csrs; } + if (def->custom_arch_state_init) { + assert(!mcc->def->custom_arch_state_init); + mcc->def->custom_arch_state_init =3D def->custom_arch_state_in= it; + } + if (def->custom_arch_state_reset) { + assert(!mcc->def->custom_arch_state_reset); + mcc->def->custom_arch_state_reset =3D def->custom_arch_state_r= eset; + } } =20 if (!object_class_is_abstract(c)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d79c7a5a7..8132c65012 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -213,6 +213,9 @@ typedef struct PMUFixedCtrState { uint64_t counter_virt_prev[2]; } PMUFixedCtrState; =20 +typedef void (*riscv_csr_custom_init_fn)(CPURISCVState *env); +typedef void (*riscv_csr_custom_reset_fn)(CPURISCVState *env); + struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -509,6 +512,8 @@ struct CPUArchState { uint64_t rnmip; uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; + + const void *custom_arch_state; }; =20 /* @@ -561,6 +566,8 @@ typedef struct RISCVCPUDef { RISCVCPUConfig cfg; bool bare; const RISCVCSR *custom_csrs; + riscv_csr_custom_init_fn custom_arch_state_init; + riscv_csr_custom_reset_fn custom_arch_state_reset; } RISCVCPUDef; =20 /** --=20 2.43.0