From nobody Sat May 30 17:44:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779790756; cv=none; d=zohomail.com; s=zohoarc; b=LVzbo9NucY6Iph/D+6YP8wPhgnTpRam9rwxS9T5g7NBTELKyKXSDpQElgEXyCQoqaNFBu0mF99LbbyWQalTC/ZbRu1P4C8gueV4H0LKZLRFmmbwIzFrhFnbHn+49Y2/AglqCG5jJnMIwvKZUrhGijqawz2Ba4H9L5jL0RuwPm5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779790756; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=i6UQMmjJXOvMiIkOKCXgigHHPVp50+pBNbNSrVzCBeg=; b=RruweNXF41QXfp2yhlkmorVLH10ohE3xX0MYbS4bT9I9Woas36zZaAqLt8IxEJ+5x2T4V+NdUYogA1l2X2k+Z4leAhH6SBvQEt1ESDaUaserpoSOWDAcBst4Hyafe3LvGWxGZrzxrEkjNfVFiuJeUmz6zLMt6jF7VNV6E1RBI94= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779790756716816.518915967601; Tue, 26 May 2026 03:19:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRorL-00062P-4f; Tue, 26 May 2026 06:18:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRor8-00061V-SD for qemu-devel@nongnu.org; Tue, 26 May 2026 06:17:51 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wRor4-0001zl-C3 for qemu-devel@nongnu.org; Tue, 26 May 2026 06:17:49 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2ba856db1c0so76255965ad.3 for ; Tue, 26 May 2026 03:17:41 -0700 (PDT) Received: from lima-default.tail89d63.ts.net ([159.196.41.205]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2beb58b386esm126286435ad.44.2026.05.26.03.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 May 2026 03:17:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779790660; x=1780395460; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=i6UQMmjJXOvMiIkOKCXgigHHPVp50+pBNbNSrVzCBeg=; b=oeLSPmE4nS5/I29R2IHKW2BJMq0nG0bqXc998bcZujzo/6C3gORKWiyjebcuozWTKw 28NimS9hKQ4ubDrX9D8tIwnz/q8A0KV7vqGiVZoo9lviGqyOw5SrBlE6lxixh9O1q+QC cN/fY6gENlW9yacb4Sg6U5sxmETd/oMyOX0yaAksj8V2QKOlXgHbK6Q5BYkgwobk7jwV zAAA5/KoBedSBphQhV7V9BmV8wtOqIWaEz7ea0COwMg+46rVeRzM5JB+n5BnNtKadkop jjQDs4E0ZXuTtoYZ7r9yyKRLHxgCIUHxqIzdFSDT+TPGcMFdoiVfVOLH0mXeVxn04BkM 5JCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779790660; x=1780395460; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=i6UQMmjJXOvMiIkOKCXgigHHPVp50+pBNbNSrVzCBeg=; b=EOwN1VsKQT5vhkiYI2q6Fl4+JjwJTifB7INC+zmG3G2cfqLCKlfkEaaHuYtDpbSfzG p34r983qRScSRIxGGo1kE3SiE7rT6hEdsqRAvoYxC9BtHmuAQ+GNV1GRYhIqc3pzAiXH 3RMaLGxoMEhCbzoImqyroflM7n6SzYT+8Sz6djyJUid5aZ/BBV9IzH1p+/4yoFHnotcG 4hzVHIDD1JUMq1A+oK+VxVntDU8zMPgJHEx0lSM4giorHyjFz6QnL2gABNcW/lSDy7Ou 5nLqSBlUj7n5xqzHPMr5xT8gay6vTTG2oOUW0xgVfHzvu7ohNzWNZkWW32Rft8kmtO4a AgnQ== X-Gm-Message-State: AOJu0YxQHgYxxr0y3XZgbgKiczdD3x8urbnEb67OyOtTkKCXO1m8kUkb WrbMbKayV2mhgunUS6fgetZEDRDiAjmzNO+HIwh7joknAGsRj+wClDGKuMQLKS/M X-Gm-Gg: Acq92OEVpLkUD9Xigush+ivIbR5PdCyZYEgkAk4R1N6/7eVQPEU47lIu89SF1z51S16 gDiJPhILmjFYAY03RGH7/BnQGVnrl5El2F4D5ThMl6L7jSku+c5YZv3OjVI+CCW9V+zIPizKJCs 1RDOC80SESADfsbNjqdMuSwASbF5/lSJVtAIOyN9dfymNzqBD67uquDdfchdY6tFvnTBC7ec0ok p4Kij+PGC/GByGL82ZE6ikzg5se4Zk6LsPsVynOJJaBmN2kRY1yan/2UjODAXy1YqrJ8jojzf9r 7mUoi6UDhj4qjcOTghJkAIeI5L5ghkJGNTegcSJPPCtgBAu34zz2OnRyqWGGfzGjgl+8QaQdUWe cxr8Y4pi5aSEf5g/+uOqvjUZ75wFINE83vbxYi1pTa59INWF1SJXC7SC9xr33yGgwlhzKjCMLlE ZdIDMXCqPOB50IKj0PT+hA35RKMXRSN+lOdJkcd43vxfMMtrNna3vStNsB5b+XEE40uZN+hCowe JXlRNQ= X-Received: by 2002:a17:903:1b46:b0:2b2:81aa:f6c3 with SMTP id d9443c01a7336-2beb07378e7mr207604535ad.29.1779790660339; Tue, 26 May 2026 03:17:40 -0700 (PDT) From: stephensportia@gmail.com To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , qemu-riscv@nongnu.org, Liu Zhiwei , Chao Liu , Weiwei Li , Palmer Dabbelt , Alistair Francis , Portia Stephens Subject: [PATCH] target/riscv: Add support for a custom CPU arch state Date: Tue, 26 May 2026 20:17:32 +1000 Message-ID: <20260526101732.54144-1-stephensportia@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=stephensportia@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779790758804154100 Content-Type: text/plain; charset="utf-8" From: Portia Stephens CPU custom CSR implementations may require custom state information. This adds support for a void struct to be added to CPUArchState to track this state information. Signed-off-by: Portia Stephens --- target/riscv/cpu.c | 18 ++++++++++++++++++ target/riscv/cpu.h | 8 ++++++++ 2 files changed, 26 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 862834b480..2e3acee76f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,6 +819,10 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } + + if (env->custom_arch_state_reset) { + env->custom_arch_state_reset(env); + } #endif } =20 @@ -1167,6 +1171,12 @@ static void riscv_cpu_init(Object *obj) if (mcc->def->custom_csrs) { riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); } + if (mcc->def->custom_arch_state_init) { + mcc->def->custom_arch_state_init(&cpu->env); + } + if (mcc->def->custom_arch_state_reset) { + cpu->env.custom_arch_state_reset =3D mcc->def->custom_arch_state_r= eset; + } #endif =20 accel_cpu_instance_init(CPU(obj)); @@ -2706,6 +2716,14 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) assert(!mcc->def->custom_csrs); mcc->def->custom_csrs =3D def->custom_csrs; } + if (def->custom_arch_state_init) { + assert(!mcc->def->custom_arch_state_init); + mcc->def->custom_arch_state_init =3D def->custom_arch_state_in= it; + } + if (def->custom_arch_state_reset) { + assert(!mcc->def->custom_arch_state_reset); + mcc->def->custom_arch_state_reset =3D def->custom_arch_state_r= eset; + } } =20 if (!object_class_is_abstract(c)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d79c7a5a7..77b513c29a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -213,6 +213,9 @@ typedef struct PMUFixedCtrState { uint64_t counter_virt_prev[2]; } PMUFixedCtrState; =20 +typedef void (*riscv_csr_custom_init_fn)(CPURISCVState *env); +typedef void (*riscv_csr_custom_reset_fn)(CPURISCVState *env); + struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -509,6 +512,9 @@ struct CPUArchState { uint64_t rnmip; uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; + + const void *custom_arch_state; + riscv_csr_custom_init_fn custom_arch_state_reset; }; =20 /* @@ -561,6 +567,8 @@ typedef struct RISCVCPUDef { RISCVCPUConfig cfg; bool bare; const RISCVCSR *custom_csrs; + riscv_csr_custom_init_fn custom_arch_state_init; + riscv_csr_custom_reset_fn custom_arch_state_reset; } RISCVCPUDef; =20 /** --=20 2.43.0