From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778277886560.8329094216859; Mon, 25 May 2026 23:51:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcy-0002JF-Jd; Tue, 26 May 2026 02:51:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlca-0002Fq-Hn for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcV-0000ZA-Kn for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:36 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxQ_CyQhVqT0wNAA--.37994S3; Tue, 26 May 2026 14:50:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx68GwQhVqMF6RAA--.10913S3; Tue, 26 May 2026 14:50:25 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 01/12] target/loongarch: Add new field curState in CPULoongArchState Date: Tue, 26 May 2026 14:50:12 +0800 Message-Id: <20260526065023.1639371-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx68GwQhVqMF6RAA--.10913S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778281090158500 Content-Type: text/plain; charset="utf-8" New field curState is added in structure CPULoongArchState, it points to CPULoongArchState itself now. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 8f277f7696..693ce30b60 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -278,6 +278,7 @@ static void loongarch_la464_initfn(Object *obj) uint32_t data =3D 0, field; int i; =20 + set_current_state(env, env); for (i =3D 0; i < 21; i++) { env->cpucfg[i] =3D 0x0; } @@ -406,6 +407,7 @@ static void loongarch_la132_initfn(Object *obj) uint32_t data =3D 0; int i; =20 + set_current_state(env, env); for (i =3D 0; i < 21; i++) { env->cpucfg[i] =3D 0x0; } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 096d778928..e738923049 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -317,6 +317,8 @@ typedef struct LoongArchBT { #define CPU_VENDOR_LOONGSON "Loongson" #define CPU_MODEL_3A5000 "3A5000" #define CPU_MODEL_1C101 "1C101" +struct CPUArchState; +typedef struct CPUArchState CPUSysState; =20 typedef struct CPUArchState { uint64_t gpr[32]; @@ -415,6 +417,7 @@ typedef struct CPUArchState { AddressSpace *address_space_iocsr; uint32_t mp_state; #endif + CPUSysState *curState; } CPULoongArchState; =20 typedef struct LoongArchCPUTopo { @@ -481,6 +484,16 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 =20 +static inline CPUSysState *get_current_state(CPULoongArchState *env) +{ + return env->curState; +} + +static inline void set_current_state(CPULoongArchState *env, CPUSysState *= cur) +{ + env->curState =3D cur; +} + static inline bool is_la64(CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) =3D=3D CPUCFG1_ARCH_L= A64; --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778277236921.6221217357194; Mon, 25 May 2026 23:51:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcg-0002Gf-B3; Tue, 26 May 2026 02:50:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcb-0002Fv-TC for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcV-0000Z5-I8 for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:37 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxReiyQhVqU0wNAA--.31941S3; Tue, 26 May 2026 14:50:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx68GwQhVqMF6RAA--.10913S4; Tue, 26 May 2026 14:50:25 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 02/12] target/loongarch: Use curState in cpu.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:13 +0800 Message-Id: <20260526065023.1639371-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx68GwQhVqMF6RAA--.10913S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778283045154100 Content-Type: text/plain; charset="utf-8" When accessing CSR register in file cpu.c, use curState rather than env. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 114 ++++++++++++++++++++++------------------- target/loongarch/cpu.h | 5 +- 2 files changed, 63 insertions(+), 56 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 693ce30b60..49bc896d7c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -62,6 +62,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) LoongArchCPU *cpu =3D opaque; CPULoongArchState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); + CPUSysState *cur =3D get_current_state(env); =20 if (irq < 0 || irq >=3D N_IRQS) { return; @@ -70,8 +71,8 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int lev= el) if (kvm_enabled()) { kvm_loongarch_set_interrupt(cpu, irq, level); } else if (tcg_enabled()) { - env->CSR_ESTAT =3D deposit64(env->CSR_ESTAT, irq, 1, level !=3D 0); - if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { + cur->CSR_ESTAT =3D deposit64(cur->CSR_ESTAT, irq, 1, level !=3D 0); + if (FIELD_EX64(cur->CSR_ESTAT, CSR_ESTAT, IS)) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -84,9 +85,10 @@ bool cpu_loongarch_hw_interrupts_pending(CPULoongArchSta= te *env) { uint32_t pending; uint32_t status; + CPUSysState *cur =3D get_current_state(env); =20 - pending =3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); - status =3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); + pending =3D FIELD_EX64(cur->CSR_ESTAT, CSR_ESTAT, IS); + status =3D FIELD_EX64(cur->CSR_ECFG, CSR_ECFG, LIE); =20 return (pending & status) !=3D 0; } @@ -112,11 +114,12 @@ static void loongarch_la464_init_csr(DeviceState *dev) static bool initialized; LoongArchCPU *cpu =3D LOONGARCH_CPU(dev); CPULoongArchState *env =3D &cpu->env; + CPUSysState *cur =3D get_current_state(env); int i, num; =20 if (!initialized) { initialized =3D true; - num =3D FIELD_EX64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); + num =3D FIELD_EX64(cur->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM); for (i =3D num; i < 16; i++) { set_csr_flag(LOONGARCH_CSR_SAVE(i), CSRFL_UNUSED); } @@ -275,6 +278,7 @@ static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; + CPUSysState *cur; uint32_t data =3D 0, field; int i; =20 @@ -382,18 +386,19 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6); env->cpucfg[20] =3D data; =20 - env->CSR_ASID =3D FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); + cur =3D get_current_state(env); + cur->CSR_ASID =3D FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); =20 - env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, = 8); - env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS= , 0x2f); - env->CSR_PRCFG1 =3D FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); + cur->CSR_PRCFG1 =3D FIELD_DP64(cur->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, = 8); + cur->CSR_PRCFG1 =3D FIELD_DP64(cur->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS= , 0x2f); + cur->CSR_PRCFG1 =3D FIELD_DP64(cur->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7); =20 - env->CSR_PRCFG2 =3D 0x3ffff000; + cur->CSR_PRCFG2 =3D 0x3ffff000; =20 - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, = 2); - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY= , 63); - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS,= 7); - env->CSR_PRCFG3 =3D FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); + cur->CSR_PRCFG3 =3D FIELD_DP64(cur->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, = 2); + cur->CSR_PRCFG3 =3D FIELD_DP64(cur->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY= , 63); + cur->CSR_PRCFG3 =3D FIELD_DP64(cur->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS,= 7); + cur->CSR_PRCFG3 =3D FIELD_DP64(cur->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS,= 8); =20 cpu->msgint =3D ON_OFF_AUTO_OFF; cpu->ptw =3D ON_OFF_AUTO_OFF; @@ -595,6 +600,7 @@ static void loongarch_cpu_reset_hold(Object *obj, Reset= Type type) CPUState *cs =3D CPU(obj); LoongArchCPUClass *lacc =3D LOONGARCH_CPU_GET_CLASS(obj); CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); =20 if (lacc->parent_phases.hold) { lacc->parent_phases.hold(obj, type); @@ -618,55 +624,55 @@ static void loongarch_cpu_reset_hold(Object *obj, Res= etType type) =20 int n; /* Set csr registers value after reset, see the manual 6.4. */ - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 0); - - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0); - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0); - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0); - env->CSR_EUEN =3D FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0); - - env->CSR_MISC =3D 0; - - env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0); - env->CSR_ECFG =3D FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0); - - env->CSR_ESTAT =3D env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); - env->CSR_RVACFG =3D FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0); - env->CSR_CPUID =3D cs->cpu_index; - env->CSR_TCFG =3D FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); - env->CSR_LLBCTL =3D FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); - env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); - env->CSR_MERRCTL =3D FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); - env->CSR_TID =3D cs->cpu_index; + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, PLV, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, IE, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, DA, 1); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, PG, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, DATF, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, DATM, 0); + + cur->CSR_EUEN =3D FIELD_DP64(cur->CSR_EUEN, CSR_EUEN, FPE, 0); + cur->CSR_EUEN =3D FIELD_DP64(cur->CSR_EUEN, CSR_EUEN, SXE, 0); + cur->CSR_EUEN =3D FIELD_DP64(cur->CSR_EUEN, CSR_EUEN, ASXE, 0); + cur->CSR_EUEN =3D FIELD_DP64(cur->CSR_EUEN, CSR_EUEN, BTE, 0); + + cur->CSR_MISC =3D 0; + + cur->CSR_ECFG =3D FIELD_DP64(cur->CSR_ECFG, CSR_ECFG, VS, 0); + cur->CSR_ECFG =3D FIELD_DP64(cur->CSR_ECFG, CSR_ECFG, LIE, 0); + + cur->CSR_ESTAT =3D cur->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2)); + cur->CSR_RVACFG =3D FIELD_DP64(cur->CSR_RVACFG, CSR_RVACFG, RBITS, 0); + cur->CSR_CPUID =3D cs->cpu_index; + cur->CSR_TCFG =3D FIELD_DP64(cur->CSR_TCFG, CSR_TCFG, EN, 0); + cur->CSR_LLBCTL =3D FIELD_DP64(cur->CSR_LLBCTL, CSR_LLBCTL, KLO, 0); + cur->CSR_TLBRERA =3D FIELD_DP64(cur->CSR_TLBRERA, CSR_TLBRERA, ISTLBR,= 0); + cur->CSR_MERRCTL =3D FIELD_DP64(cur->CSR_MERRCTL, CSR_MERRCTL, ISMERR,= 0); + cur->CSR_TID =3D cs->cpu_index; /* * Workaround for edk2-stable202408, CSR PGD register is set only if * its value is equal to zero for boot cpu, it causes reboot issue. * * Here clear CSR registers relative with TLB. */ - env->CSR_PGDH =3D 0; - env->CSR_PGDL =3D 0; - env->CSR_PWCH =3D 0; - env->CSR_EENTRY =3D 0; - env->CSR_TLBRENTRY =3D 0; - env->CSR_MERRENTRY =3D 0; + cur->CSR_PGDH =3D 0; + cur->CSR_PGDL =3D 0; + cur->CSR_PWCH =3D 0; + cur->CSR_EENTRY =3D 0; + cur->CSR_TLBRENTRY =3D 0; + cur->CSR_MERRENTRY =3D 0; /* set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits from CSR_PRCFG2 */ - if (env->CSR_PRCFG2 =3D=3D 0) { - env->CSR_PRCFG2 =3D 0x3fffff000; + if (cur->CSR_PRCFG2 =3D=3D 0) { + cur->CSR_PRCFG2 =3D 0x3fffff000; } - tlb_ps =3D ctz32(env->CSR_PRCFG2); - env->CSR_STLBPS =3D FIELD_DP64(env->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps= ); - env->CSR_PWCL =3D FIELD_DP64(env->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); + tlb_ps =3D ctz32(cur->CSR_PRCFG2); + cur->CSR_STLBPS =3D FIELD_DP64(cur->CSR_STLBPS, CSR_STLBPS, PS, tlb_ps= ); + cur->CSR_PWCL =3D FIELD_DP64(cur->CSR_PWCL, CSR_PWCL, PTBASE, tlb_ps); for (n =3D 0; n < 4; n++) { - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0); - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0); - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0); - env->CSR_DMW[n] =3D FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0); + cur->CSR_DMW[n] =3D FIELD_DP64(cur->CSR_DMW[n], CSR_DMW, PLV0, 0); + cur->CSR_DMW[n] =3D FIELD_DP64(cur->CSR_DMW[n], CSR_DMW, PLV1, 0); + cur->CSR_DMW[n] =3D FIELD_DP64(cur->CSR_DMW[n], CSR_DMW, PLV2, 0); + cur->CSR_DMW[n] =3D FIELD_DP64(cur->CSR_DMW[n], CSR_DMW, PLV3, 0); } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index e738923049..dedb3971e5 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -503,8 +503,9 @@ static inline bool is_va32(CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 =3D !is_la64(env); - uint64_t plv =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - if (plv >=3D 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << p= lv))) { + CPUSysState *cur =3D get_current_state(env); + uint64_t plv =3D FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, PLV); + if (plv >=3D 1 && (FIELD_EX64(cur->CSR_MISC, CSR_MISC, VA32) & (1 << p= lv))) { va32 =3D true; } return va32; --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778370368999.2746409861269; Mon, 25 May 2026 23:52:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlct-0002HK-6w; Tue, 26 May 2026 02:50:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlca-0002Fp-HL for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:36 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcV-0000Z7-H5 for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:35 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx13izQhVqV0wNAA--.13347S3; Tue, 26 May 2026 14:50:27 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx68GwQhVqMF6RAA--.10913S5; Tue, 26 May 2026 14:50:26 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 03/12] target/loongarch: Use curState in cpu_helper.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:14 +0800 Message-Id: <20260526065023.1639371-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx68GwQhVqMF6RAA--.10913S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778371336158500 Content-Type: text/plain; charset="utf-8" When accessing CSR register in file cpu_helper.c, use curState rather than env. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 41 +++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index eb9684a4a1..f163f22cfe 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -20,27 +20,29 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, unsigned int level) { + CPUSysState *cur =3D get_current_state(env); + switch (level) { case 1: - *dir_base =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_BASE); - *dir_width =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR1_WIDTH); + *dir_base =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, DIR1_BASE); + *dir_width =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, DIR1_WIDTH); break; case 2: - *dir_base =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_BASE); - *dir_width =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, DIR2_WIDTH); + *dir_base =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, DIR2_BASE); + *dir_width =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, DIR2_WIDTH); break; case 3: - *dir_base =3D FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_BASE); - *dir_width =3D FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR3_WIDTH); + *dir_base =3D FIELD_EX64(cur->CSR_PWCH, CSR_PWCH, DIR3_BASE); + *dir_width =3D FIELD_EX64(cur->CSR_PWCH, CSR_PWCH, DIR3_WIDTH); break; case 4: - *dir_base =3D FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR4_BASE); - *dir_width =3D FIELD_EX64(env->CSR_PWCH, CSR_PWCH, DIR4_WIDTH); + *dir_base =3D FIELD_EX64(cur->CSR_PWCH, CSR_PWCH, DIR4_BASE); + *dir_width =3D FIELD_EX64(cur->CSR_PWCH, CSR_PWCH, DIR4_WIDTH); break; default: /* level may be zero for ldpte */ - *dir_base =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE); - *dir_width =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH); + *dir_base =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, PTBASE); + *dir_width =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, PTWIDTH); break; } } @@ -156,13 +158,13 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUConte= xt *context, vaddr address; TLBRet ret; MemTxResult ret1; - + CPUSysState *cur =3D get_current_state(env); =20 address =3D context->addr; if ((address >> 63) & 0x1) { - base =3D env->CSR_PGDH; + base =3D cur->CSR_PGDH; } else { - base =3D env->CSR_PGDL; + base =3D cur->CSR_PGDL; } base &=3D palen_mask; =20 @@ -315,8 +317,9 @@ TLBRet get_physical_address(CPULoongArchState *env, MMU= Context *context, int kernel_mode =3D mmu_idx =3D=3D MMU_KERNEL_IDX; uint32_t plv, base_c, base_v; int64_t addr_high; - uint8_t da =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); - uint8_t pg =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG); + CPUSysState *cur =3D get_current_state(env); + uint8_t da =3D FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, DA); + uint8_t pg =3D FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, PG); vaddr address; =20 /* Check PG and DA */ @@ -337,12 +340,12 @@ TLBRet get_physical_address(CPULoongArchState *env, M= MUContext *context, /* Check direct map window */ for (int i =3D 0; i < 4; i++) { if (is_la64(env)) { - base_c =3D FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG); + base_c =3D FIELD_EX64(cur->CSR_DMW[i], CSR_DMW_64, VSEG); } else { - base_c =3D FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG); + base_c =3D FIELD_EX64(cur->CSR_DMW[i], CSR_DMW_32, VSEG); } - if ((plv & env->CSR_DMW[i]) && (base_c =3D=3D base_v)) { - context->physical =3D dmw_va2pa(env, address, env->CSR_DMW[i]); + if ((plv & cur->CSR_DMW[i]) && (base_c =3D=3D base_v)) { + context->physical =3D dmw_va2pa(env, address, cur->CSR_DMW[i]); context->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; context->mmu_index =3D MMU_DA_IDX; return TLBRET_MATCH; --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17797782859551001.5856308587137; Mon, 25 May 2026 23:51:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRld6-0002Jl-7x; Tue, 26 May 2026 02:51:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcb-0002Fw-VS for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcY-0000aa-73 for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:37 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxncC4QhVqYkwNAA--.14161S3; Tue, 26 May 2026 14:50:32 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx68GwQhVqMF6RAA--.10913S6; Tue, 26 May 2026 14:50:26 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 04/12] target/loongarch: Use curState in file arch_dump.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:15 +0800 Message-Id: <20260526065023.1639371-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx68GwQhVqMF6RAA--.10913S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778289415158500 Content-Type: text/plain; charset="utf-8" When accessing CSR registers in file arch_dump.c, use curState rather than env. Signed-off-by: Bibo Mao --- hw/intc/loongarch_dintc.c | 4 +++- target/loongarch/arch_dump.c | 5 +++-- target/loongarch/cpu-mmu.h | 4 +++- target/loongarch/gdbstub.c | 3 ++- target/loongarch/tcg/constant_timer.c | 10 ++++++---- 5 files changed, 17 insertions(+), 9 deletions(-) diff --git a/hw/intc/loongarch_dintc.c b/hw/intc/loongarch_dintc.c index c42a919df4..1fa8c12a76 100644 --- a/hw/intc/loongarch_dintc.c +++ b/hw/intc/loongarch_dintc.c @@ -35,10 +35,12 @@ static void do_set_vcpu_dintc_irq(CPUState *cs, run_on_= cpu_data data) { int irq =3D data.host_int; CPULoongArchState *env; + CPUSysState *cur; =20 env =3D &LOONGARCH_CPU(cs)->env; + cur =3D get_current_state(env); cpu_synchronize_state(cs); - set_bit(irq, (unsigned long *)&env->CSR_MSGIS); + set_bit(irq, (unsigned long *)&cur->CSR_MSGIS); } =20 static void loongarch_dintc_mem_write(void *opaque, hwaddr addr, diff --git a/target/loongarch/arch_dump.c b/target/loongarch/arch_dump.c index 2b0955a209..da5605b4e6 100644 --- a/target/loongarch/arch_dump.c +++ b/target/loongarch/arch_dump.c @@ -116,6 +116,7 @@ int loongarch_cpu_write_elf64_note(WriteCoreDumpFunctio= n f, CPUState *cs, { struct loongarch_note note; CPULoongArchState *env =3D &LOONGARCH_CPU(cs)->env; + CPUSysState *cur =3D get_current_state(env); int ret, i; =20 loongarch_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, @@ -126,8 +127,8 @@ int loongarch_cpu_write_elf64_note(WriteCoreDumpFunctio= n f, CPUState *cs, for (i =3D 0; i < 32; ++i) { note.prstatus.pr_reg.gpr[i] =3D cpu_to_dump64(s, env->gpr[i]); } - note.prstatus.pr_reg.csr_era =3D cpu_to_dump64(s, env->CSR_ERA); - note.prstatus.pr_reg.csr_badv =3D cpu_to_dump64(s, env->CSR_BADV); + note.prstatus.pr_reg.csr_era =3D cpu_to_dump64(s, cur->CSR_ERA); + note.prstatus.pr_reg.csr_badv =3D cpu_to_dump64(s, cur->CSR_BADV); ret =3D f(¬e, LOONGARCH_PRSTATUS_NOTE_SIZE, s); if (ret < 0) { return -1; diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 2d7ebb2d72..652c522925 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -32,7 +32,9 @@ typedef struct MMUContext { =20 static inline bool cpu_has_ptw(CPULoongArchState *env) { - return !!FIELD_EX64(env->CSR_PWCH, CSR_PWCH, HPTW_EN); + CPUSysState *cur =3D get_current_state(env); + + return !!FIELD_EX64(cur->CSR_PWCH, CSR_PWCH, HPTW_EN); } =20 static inline bool pte_present(CPULoongArchState *env, uint64_t entry) diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 3e9bdfa8bb..1d6c3d19a2 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -34,6 +34,7 @@ void write_fcc(CPULoongArchState *env, uint64_t val) int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int= n) { CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); =20 if (0 <=3D n && n <=3D 34) { uint64_t val; @@ -46,7 +47,7 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteAr= ray *mem_buf, int n) } else if (n =3D=3D 33) { val =3D env->pc; } else /* if (n =3D=3D 34) */ { - val =3D env->CSR_BADV; + val =3D cur->CSR_BADV; } =20 if (is_la64(env)) { diff --git a/target/loongarch/tcg/constant_timer.c b/target/loongarch/tcg/c= onstant_timer.c index 1851f53fd6..b08c2f6d3b 100644 --- a/target/loongarch/tcg/constant_timer.c +++ b/target/loongarch/tcg/constant_timer.c @@ -34,9 +34,10 @@ void cpu_loongarch_store_constant_timer_config(LoongArch= CPU *cpu, uint64_t value) { CPULoongArchState *env =3D &cpu->env; + CPUSysState *cur =3D get_current_state(env); uint64_t now, next; =20 - env->CSR_TCFG =3D value; + cur->CSR_TCFG =3D value; if (value & CONSTANT_TIMER_ENABLE) { now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); next =3D now + (value & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD; @@ -50,14 +51,15 @@ void loongarch_constant_timer_cb(void *opaque) { LoongArchCPU *cpu =3D opaque; CPULoongArchState *env =3D &cpu->env; + CPUSysState *cur =3D get_current_state(env); uint64_t now, next; =20 - if (FIELD_EX64(env->CSR_TCFG, CSR_TCFG, PERIODIC)) { + if (FIELD_EX64(cur->CSR_TCFG, CSR_TCFG, PERIODIC)) { now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - next =3D now + (env->CSR_TCFG & CONSTANT_TIMER_TICK_MASK) * TIMER_= PERIOD; + next =3D now + (cur->CSR_TCFG & CONSTANT_TIMER_TICK_MASK) * TIMER_= PERIOD; timer_mod(&cpu->timer, next); } else { - env->CSR_TCFG =3D FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0); + cur->CSR_TCFG =3D FIELD_DP64(cur->CSR_TCFG, CSR_TCFG, EN, 0); } =20 loongarch_cpu_set_irq(opaque, IRQ_TIMER, 1); --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17797783270601001.7457007467528; Mon, 25 May 2026 23:52:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRld2-0002JS-9l; Tue, 26 May 2026 02:51:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcc-0002GS-Gx for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:38 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcX-0000aS-PU for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:37 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxnOm2QhVqYUwNAA--.36072S3; Tue, 26 May 2026 14:50:30 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBx68GwQhVqMF6RAA--.10913S7; Tue, 26 May 2026 14:50:29 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 05/12] target/loongarch: Use curState in kvm.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:16 +0800 Message-Id: <20260526065023.1639371-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBx68GwQhVqMF6RAA--.10913S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778329292158500 Content-Type: text/plain; charset="utf-8" When accessing CSR registers in file kvm.c, use curState rather than env. Signed-off-by: Bibo Mao --- target/loongarch/kvm/kvm.c | 228 +++++++++++++++++++------------------ 1 file changed, 116 insertions(+), 112 deletions(-) diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 9d844c4905..1534fcb7c3 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -160,6 +160,7 @@ static int kvm_loongarch_put_pmu(CPUState *cs) int i, ret =3D 0; CPULoongArchState *env =3D cpu_env(cs); LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPUSysState *cur =3D get_current_state(env); =20 if (cpu->pmu !=3D ON_OFF_AUTO_ON) { return 0; @@ -167,9 +168,9 @@ static int kvm_loongarch_put_pmu(CPUState *cs) =20 for (i =3D 0; i < env->perf_event_num; i++) { ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PERFCTRL(= i)), - &env->CSR_PERFCTRL[i]); + &cur->CSR_PERFCTRL[i]); ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PERFCNTR(= i)), - &env->CSR_PERFCNTR[i]); + &cur->CSR_PERFCNTR[i]); } =20 return ret; @@ -180,6 +181,7 @@ static int kvm_loongarch_get_pmu(CPUState *cs) int i, ret =3D 0; CPULoongArchState *env =3D cpu_env(cs); LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPUSysState *cur =3D get_current_state(env); =20 if (cpu->pmu !=3D ON_OFF_AUTO_ON) { return 0; @@ -187,9 +189,9 @@ static int kvm_loongarch_get_pmu(CPUState *cs) =20 for (i =3D 0; i < env->perf_event_num; i++) { ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PERFCTRL(= i)), - &env->CSR_PERFCTRL[i]); + &cur->CSR_PERFCTRL[i]); ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PERFCNTR(= i)), - &env->CSR_PERFCNTR[i]); + &cur->CSR_PERFCNTR[i]); } =20 return ret; @@ -199,170 +201,171 @@ static int kvm_loongarch_get_csr(CPUState *cs) { int ret =3D 0; CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), - &env->CSR_CRMD); + &cur->CSR_CRMD); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRMD), - &env->CSR_PRMD); + &cur->CSR_PRMD); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EUEN), - &env->CSR_EUEN); + &cur->CSR_EUEN); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_MISC), - &env->CSR_MISC); + &cur->CSR_MISC); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ECFG), - &env->CSR_ECFG); + &cur->CSR_ECFG); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ESTAT), - &env->CSR_ESTAT); + &cur->CSR_ESTAT); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ERA), - &env->CSR_ERA); + &cur->CSR_ERA); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADV), - &env->CSR_BADV); + &cur->CSR_BADV); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADI), - &env->CSR_BADI); + &cur->CSR_BADI); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EENTRY), - &env->CSR_EENTRY); + &cur->CSR_EENTRY); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBIDX), - &env->CSR_TLBIDX); + &cur->CSR_TLBIDX); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBEHI), - &env->CSR_TLBEHI); + &cur->CSR_TLBEHI); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO0), - &env->CSR_TLBELO0); + &cur->CSR_TLBELO0); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO1), - &env->CSR_TLBELO1); + &cur->CSR_TLBELO1); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ASID), - &env->CSR_ASID); + &cur->CSR_ASID); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDL), - &env->CSR_PGDL); + &cur->CSR_PGDL); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDH), - &env->CSR_PGDH); + &cur->CSR_PGDH); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGD), - &env->CSR_PGD); + &cur->CSR_PGD); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCL), - &env->CSR_PWCL); + &cur->CSR_PWCL); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCH), - &env->CSR_PWCH); + &cur->CSR_PWCH); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_STLBPS), - &env->CSR_STLBPS); + &cur->CSR_STLBPS); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG), - &env->CSR_RVACFG); + &cur->CSR_RVACFG); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID), - &env->CSR_CPUID); + &cur->CSR_CPUID); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1), - &env->CSR_PRCFG1); + &cur->CSR_PRCFG1); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG2), - &env->CSR_PRCFG2); + &cur->CSR_PRCFG2); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG3), - &env->CSR_PRCFG3); + &cur->CSR_PRCFG3); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(0)), - &env->CSR_SAVE[0]); + &cur->CSR_SAVE[0]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(1)), - &env->CSR_SAVE[1]); + &cur->CSR_SAVE[1]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(2)), - &env->CSR_SAVE[2]); + &cur->CSR_SAVE[2]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(3)), - &env->CSR_SAVE[3]); + &cur->CSR_SAVE[3]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(4)), - &env->CSR_SAVE[4]); + &cur->CSR_SAVE[4]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(5)), - &env->CSR_SAVE[5]); + &cur->CSR_SAVE[5]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(6)), - &env->CSR_SAVE[6]); + &cur->CSR_SAVE[6]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(7)), - &env->CSR_SAVE[7]); + &cur->CSR_SAVE[7]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TID), - &env->CSR_TID); + &cur->CSR_TID); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CNTC), - &env->CSR_CNTC); + &cur->CSR_CNTC); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TICLR), - &env->CSR_TICLR); + &cur->CSR_TICLR); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_LLBCTL), - &env->CSR_LLBCTL); + &cur->CSR_LLBCTL); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL1), - &env->CSR_IMPCTL1); + &cur->CSR_IMPCTL1); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL2), - &env->CSR_IMPCTL2); + &cur->CSR_IMPCTL2); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRENTRY), - &env->CSR_TLBRENTRY); + &cur->CSR_TLBRENTRY); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRBADV), - &env->CSR_TLBRBADV); + &cur->CSR_TLBRBADV); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRERA), - &env->CSR_TLBRERA); + &cur->CSR_TLBRERA); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRSAVE), - &env->CSR_TLBRSAVE); + &cur->CSR_TLBRSAVE); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO0), - &env->CSR_TLBRELO0); + &cur->CSR_TLBRELO0); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO1), - &env->CSR_TLBRELO1); + &cur->CSR_TLBRELO1); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBREHI), - &env->CSR_TLBREHI); + &cur->CSR_TLBREHI); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRPRMD), - &env->CSR_TLBRPRMD); + &cur->CSR_TLBRPRMD); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(0)), - &env->CSR_DMW[0]); + &cur->CSR_DMW[0]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(1)), - &env->CSR_DMW[1]); + &cur->CSR_DMW[1]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(2)), - &env->CSR_DMW[2]); + &cur->CSR_DMW[2]); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(3)), - &env->CSR_DMW[3]); + &cur->CSR_DMW[3]); =20 ret |=3D kvm_loongarch_get_pmu(cs); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TVAL), - &env->CSR_TVAL); + &cur->CSR_TVAL); =20 ret |=3D kvm_get_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TCFG), - &env->CSR_TCFG); + &cur->CSR_TCFG); =20 return ret; } @@ -371,165 +374,166 @@ static int kvm_loongarch_put_csr(CPUState *cs, KvmP= utState level) { int ret =3D 0; CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CRMD), - &env->CSR_CRMD); + &cur->CSR_CRMD); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRMD), - &env->CSR_PRMD); + &cur->CSR_PRMD); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EUEN), - &env->CSR_EUEN); + &cur->CSR_EUEN); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_MISC), - &env->CSR_MISC); + &cur->CSR_MISC); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ECFG), - &env->CSR_ECFG); + &cur->CSR_ECFG); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ESTAT), - &env->CSR_ESTAT); + &cur->CSR_ESTAT); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ERA), - &env->CSR_ERA); + &cur->CSR_ERA); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADV), - &env->CSR_BADV); + &cur->CSR_BADV); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_BADI), - &env->CSR_BADI); + &cur->CSR_BADI); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_EENTRY), - &env->CSR_EENTRY); + &cur->CSR_EENTRY); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBIDX), - &env->CSR_TLBIDX); + &cur->CSR_TLBIDX); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBEHI), - &env->CSR_TLBEHI); + &cur->CSR_TLBEHI); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO0), - &env->CSR_TLBELO0); + &cur->CSR_TLBELO0); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBELO1), - &env->CSR_TLBELO1); + &cur->CSR_TLBELO1); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_ASID), - &env->CSR_ASID); + &cur->CSR_ASID); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDL), - &env->CSR_PGDL); + &cur->CSR_PGDL); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGDH), - &env->CSR_PGDH); + &cur->CSR_PGDH); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PGD), - &env->CSR_PGD); + &cur->CSR_PGD); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCL), - &env->CSR_PWCL); + &cur->CSR_PWCL); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PWCH), - &env->CSR_PWCH); + &cur->CSR_PWCH); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_STLBPS), - &env->CSR_STLBPS); + &cur->CSR_STLBPS); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_RVACFG), - &env->CSR_RVACFG); + &cur->CSR_RVACFG); =20 /* CPUID is constant after poweron, it should be set only once */ if (level >=3D KVM_PUT_FULL_STATE) { ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CPUID), - &env->CSR_CPUID); + &cur->CSR_CPUID); } =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG1), - &env->CSR_PRCFG1); + &cur->CSR_PRCFG1); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG2), - &env->CSR_PRCFG2); + &cur->CSR_PRCFG2); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_PRCFG3), - &env->CSR_PRCFG3); + &cur->CSR_PRCFG3); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(0)), - &env->CSR_SAVE[0]); + &cur->CSR_SAVE[0]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(1)), - &env->CSR_SAVE[1]); + &cur->CSR_SAVE[1]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(2)), - &env->CSR_SAVE[2]); + &cur->CSR_SAVE[2]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(3)), - &env->CSR_SAVE[3]); + &cur->CSR_SAVE[3]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(4)), - &env->CSR_SAVE[4]); + &cur->CSR_SAVE[4]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(5)), - &env->CSR_SAVE[5]); + &cur->CSR_SAVE[5]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(6)), - &env->CSR_SAVE[6]); + &cur->CSR_SAVE[6]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_SAVE(7)), - &env->CSR_SAVE[7]); + &cur->CSR_SAVE[7]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TID), - &env->CSR_TID); + &cur->CSR_TID); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_CNTC), - &env->CSR_CNTC); + &cur->CSR_CNTC); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TICLR), - &env->CSR_TICLR); + &cur->CSR_TICLR); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_LLBCTL), - &env->CSR_LLBCTL); + &cur->CSR_LLBCTL); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL1), - &env->CSR_IMPCTL1); + &cur->CSR_IMPCTL1); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_IMPCTL2), - &env->CSR_IMPCTL2); + &cur->CSR_IMPCTL2); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRENTRY), - &env->CSR_TLBRENTRY); + &cur->CSR_TLBRENTRY); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRBADV), - &env->CSR_TLBRBADV); + &cur->CSR_TLBRBADV); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRERA), - &env->CSR_TLBRERA); + &cur->CSR_TLBRERA); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRSAVE), - &env->CSR_TLBRSAVE); + &cur->CSR_TLBRSAVE); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO0), - &env->CSR_TLBRELO0); + &cur->CSR_TLBRELO0); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRELO1), - &env->CSR_TLBRELO1); + &cur->CSR_TLBRELO1); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBREHI), - &env->CSR_TLBREHI); + &cur->CSR_TLBREHI); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TLBRPRMD), - &env->CSR_TLBRPRMD); + &cur->CSR_TLBRPRMD); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(0)), - &env->CSR_DMW[0]); + &cur->CSR_DMW[0]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(1)), - &env->CSR_DMW[1]); + &cur->CSR_DMW[1]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(2)), - &env->CSR_DMW[2]); + &cur->CSR_DMW[2]); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_DMW(3)), - &env->CSR_DMW[3]); + &cur->CSR_DMW[3]); =20 ret |=3D kvm_loongarch_put_pmu(cs); =20 @@ -538,10 +542,10 @@ static int kvm_loongarch_put_csr(CPUState *cs, KvmPut= State level) * guest timer */ ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TVAL), - &env->CSR_TVAL); + &cur->CSR_TVAL); =20 ret |=3D kvm_set_one_reg(cs, KVM_IOC_CSRID(LOONGARCH_CSR_TCFG), - &env->CSR_TCFG); + &cur->CSR_TCFG); return ret; } =20 --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778371999364.22382755148794; Mon, 25 May 2026 23:52:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRldK-0002Q0-0g; Tue, 26 May 2026 02:51:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcd-0002Gj-Hw for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:41 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlca-0000ag-Fy for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:39 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxVei5QhVqZkwNAA--.32131S3; Tue, 26 May 2026 14:50:33 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxbcK4QhVqM16RAA--.11451S2; Tue, 26 May 2026 14:50:32 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 06/12] target/loongarch: Use curState in tlb_helper.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:17 +0800 Message-Id: <20260526065023.1639371-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxbcK4QhVqM16RAA--.11451S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778374977154100 Content-Type: text/plain; charset="utf-8" When accessing CSR registers in file tlb_helper.c, use curState rather than env. There is no function change. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 137 +++++++++++++++++------------- 1 file changed, 77 insertions(+), 60 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 892e0eb473..69331cb02d 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -36,16 +36,19 @@ static bool tlb_match_asid(bool global, int asid, int t= lb_asid) =20 bool check_ps(CPULoongArchState *env, uint8_t tlb_ps) { + CPUSysState *cur =3D get_current_state(env); + if (tlb_ps >=3D 64) { return false; } - return BIT_ULL(tlb_ps) & (env->CSR_PRCFG2); + return BIT_ULL(tlb_ps) & (cur->CSR_PRCFG2); } =20 static void raise_mmu_exception(CPULoongArchState *env, vaddr address, MMUAccessType access_type, TLBRet tlb_erro= r) { CPUState *cs =3D env_cpu(env); + CPUSysState *cur =3D get_current_state(env); =20 switch (tlb_error) { default: @@ -62,7 +65,7 @@ static void raise_mmu_exception(CPULoongArchState *env, v= addr address, } else if (access_type =3D=3D MMU_INST_FETCH) { cs->exception_index =3D EXCCODE_PIF; } - env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 1); + cur->CSR_TLBRERA =3D FIELD_DP64(cur->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 1); break; case TLBRET_INVALID: /* TLB match with no valid bit */ @@ -93,19 +96,19 @@ static void raise_mmu_exception(CPULoongArchState *env,= vaddr address, } =20 if (tlb_error =3D=3D TLBRET_NOMATCH) { - env->CSR_TLBRBADV =3D address; + cur->CSR_TLBRBADV =3D address; if (is_la64(env)) { - env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_= 64, + cur->CSR_TLBREHI =3D FIELD_DP64(cur->CSR_TLBREHI, CSR_TLBREHI_= 64, VPPN, extract64(address, 13, 35)); } else { - env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_= 32, + cur->CSR_TLBREHI =3D FIELD_DP64(cur->CSR_TLBREHI, CSR_TLBREHI_= 32, VPPN, extract64(address, 13, 19)); } } else { - if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { - env->CSR_BADV =3D address; + if (!FIELD_EX64(cur->CSR_DBG, CSR_DBG, DST)) { + cur->CSR_BADV =3D address; } - env->CSR_TLBEHI =3D address & (TARGET_PAGE_MASK << 1); + cur->CSR_TLBEHI =3D address & (TARGET_PAGE_MASK << 1); } } =20 @@ -142,8 +145,9 @@ static void invalidate_tlb(CPULoongArchState *env, int = index) LoongArchTLB *tlb; uint16_t csr_asid, tlb_asid, tlb_g; uint8_t tlb_e; + CPUSysState *cur =3D get_current_state(env); =20 - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + csr_asid =3D FIELD_EX64(cur->CSR_ASID, CSR_ASID, ASID); tlb =3D &env->tlb[index]; tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); if (!tlb_e) { @@ -165,25 +169,26 @@ static void sptw_prepare_context(CPULoongArchState *e= nv, MMUContext *context) { uint64_t lo0, lo1, csr_vppn; uint8_t csr_ps; + CPUSysState *cur =3D get_current_state(env); =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - csr_ps =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + if (FIELD_EX64(cur->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + csr_ps =3D FIELD_EX64(cur->CSR_TLBREHI, CSR_TLBREHI, PS); if (is_la64(env)) { - csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN= ); + csr_vppn =3D FIELD_EX64(cur->CSR_TLBREHI, CSR_TLBREHI_64, VPPN= ); } else { - csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN= ); + csr_vppn =3D FIELD_EX64(cur->CSR_TLBREHI, CSR_TLBREHI_32, VPPN= ); } - lo0 =3D env->CSR_TLBRELO0; - lo1 =3D env->CSR_TLBRELO1; + lo0 =3D cur->CSR_TLBRELO0; + lo1 =3D cur->CSR_TLBRELO1; } else { - csr_ps =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + csr_ps =3D FIELD_EX64(cur->CSR_TLBIDX, CSR_TLBIDX, PS); if (is_la64(env)) { - csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN); + csr_vppn =3D FIELD_EX64(cur->CSR_TLBEHI, CSR_TLBEHI_64, VPPN); } else { - csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN); + csr_vppn =3D FIELD_EX64(cur->CSR_TLBEHI, CSR_TLBEHI_32, VPPN); } - lo0 =3D env->CSR_TLBELO0; - lo1 =3D env->CSR_TLBELO1; + lo0 =3D cur->CSR_TLBELO0; + lo1 =3D cur->CSR_TLBELO1; } =20 context->ps =3D csr_ps; @@ -198,6 +203,7 @@ static void fill_tlb_entry(CPULoongArchState *env, Loon= gArchTLB *tlb, uint64_t lo0, lo1, csr_vppn; uint16_t csr_asid; uint8_t csr_ps; + CPUSysState *cur =3D get_current_state(env); =20 csr_vppn =3D context->addr >> R_TLB_MISC_VPPN_SHIFT; csr_ps =3D context->ps; @@ -208,7 +214,7 @@ static void fill_tlb_entry(CPULoongArchState *env, Loon= gArchTLB *tlb, tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + csr_asid =3D FIELD_EX64(cur->CSR_ASID, CSR_ASID, ASID); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid); =20 tlb->tlb_entry0 =3D lo0; @@ -241,8 +247,9 @@ static LoongArchTLB *loongarch_tlb_search_cb(CPULoongAr= chState *env, bool tlb_g; int i, compare_shift; uint64_t vpn, tlb_vppn; + CPUSysState *cur =3D get_current_state(env); =20 - stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); + stlb_ps =3D FIELD_EX64(cur->CSR_STLBPS, CSR_STLBPS, PS); vpn =3D (vaddr & TARGET_VIRT_MASK) >> (stlb_ps + 1); stlb_idx =3D vpn & 0xff; /* VA[25:15] <=3D=3D> TLBIDX.index for 16KiB = Page */ compare_shift =3D stlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; @@ -289,9 +296,10 @@ static bool loongarch_tlb_search(CPULoongArchState *en= v, vaddr vaddr, int csr_asid; tlb_match func; LoongArchTLB *tlb; + CPUSysState *cur =3D get_current_state(env); =20 func =3D tlb_match_any; - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + csr_asid =3D FIELD_EX64(cur->CSR_ASID, CSR_ASID, ASID); tlb =3D loongarch_tlb_search_cb(env, vaddr, csr_asid, func); if (tlb) { *index =3D tlb - env->tlb; @@ -304,20 +312,21 @@ static bool loongarch_tlb_search(CPULoongArchState *e= nv, vaddr vaddr, void helper_tlbsrch(CPULoongArchState *env) { int index, match; + CPUSysState *cur =3D get_current_state(env); =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - match =3D loongarch_tlb_search(env, env->CSR_TLBREHI, &index); + if (FIELD_EX64(cur->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + match =3D loongarch_tlb_search(env, cur->CSR_TLBREHI, &index); } else { - match =3D loongarch_tlb_search(env, env->CSR_TLBEHI, &index); + match =3D loongarch_tlb_search(env, cur->CSR_TLBEHI, &index); } =20 if (match) { - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX,= index); - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0); + cur->CSR_TLBIDX =3D FIELD_DP64(cur->CSR_TLBIDX, CSR_TLBIDX, INDEX,= index); + cur->CSR_TLBIDX =3D FIELD_DP64(cur->CSR_TLBIDX, CSR_TLBIDX, NE, 0); return; } =20 - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1); + cur->CSR_TLBIDX =3D FIELD_DP64(cur->CSR_TLBIDX, CSR_TLBIDX, NE, 1); } =20 void helper_tlbrd(CPULoongArchState *env) @@ -325,29 +334,30 @@ void helper_tlbrd(CPULoongArchState *env) LoongArchTLB *tlb; int index; uint8_t tlb_ps, tlb_e; + CPUSysState *cur =3D get_current_state(env); =20 - index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + index =3D FIELD_EX64(cur->CSR_TLBIDX, CSR_TLBIDX, INDEX); tlb =3D &env->tlb[index]; tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); =20 if (!tlb_e) { /* Invalid TLB entry */ - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 1); - env->CSR_ASID =3D FIELD_DP64(env->CSR_ASID, CSR_ASID, ASID, 0); - env->CSR_TLBEHI =3D 0; - env->CSR_TLBELO0 =3D 0; - env->CSR_TLBELO1 =3D 0; - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, PS, 0); + cur->CSR_TLBIDX =3D FIELD_DP64(cur->CSR_TLBIDX, CSR_TLBIDX, NE, 1); + cur->CSR_ASID =3D FIELD_DP64(cur->CSR_ASID, CSR_ASID, ASID, 0); + cur->CSR_TLBEHI =3D 0; + cur->CSR_TLBELO0 =3D 0; + cur->CSR_TLBELO1 =3D 0; + cur->CSR_TLBIDX =3D FIELD_DP64(cur->CSR_TLBIDX, CSR_TLBIDX, PS, 0); } else { /* Valid TLB entry */ - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, NE, 0); - env->CSR_TLBIDX =3D FIELD_DP64(env->CSR_TLBIDX, CSR_TLBIDX, + cur->CSR_TLBIDX =3D FIELD_DP64(cur->CSR_TLBIDX, CSR_TLBIDX, NE, 0); + cur->CSR_TLBIDX =3D FIELD_DP64(cur->CSR_TLBIDX, CSR_TLBIDX, PS, (tlb_ps & 0x3f)); - env->CSR_TLBEHI =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) << + cur->CSR_TLBEHI =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN) << R_TLB_MISC_VPPN_SHIFT; - env->CSR_TLBELO0 =3D tlb->tlb_entry0; - env->CSR_TLBELO1 =3D tlb->tlb_entry1; + cur->CSR_TLBELO0 =3D tlb->tlb_entry0; + cur->CSR_TLBELO1 =3D tlb->tlb_entry1; } } =20 @@ -380,10 +390,11 @@ static void update_tlb_index(CPULoongArchState *env, = MMUContext *context, =20 void helper_tlbwr(CPULoongArchState *env) { - int index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + CPUSysState *cur =3D get_current_state(env); + int index =3D FIELD_EX64(cur->CSR_TLBIDX, CSR_TLBIDX, INDEX); MMUContext context; =20 - if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) { + if (FIELD_EX64(cur->CSR_TLBIDX, CSR_TLBIDX, NE)) { invalidate_tlb(env, index); return; } @@ -400,10 +411,11 @@ static int get_tlb_random_index(CPULoongArchState *en= v, vaddr addr, uint16_t asid, tlb_asid, stlb_ps; LoongArchTLB *tlb; uint8_t tlb_e, tlb_g; + CPUSysState *cur =3D get_current_state(env); =20 /* Validity of stlb_ps is checked in helper_csrwr_stlbps() */ - stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); + stlb_ps =3D FIELD_EX64(cur->CSR_STLBPS, CSR_STLBPS, PS); + asid =3D FIELD_EX64(cur->CSR_ASID, CSR_ASID, ASID); if (pagesize =3D=3D stlb_ps) { /* Only write into STLB bits [47:13] */ address =3D addr & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT); @@ -461,15 +473,16 @@ void helper_tlbfill(CPULoongArchState *env) vaddr entryhi; int index, pagesize; MMUContext context; + CPUSysState *cur =3D get_current_state(env); =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - entryhi =3D env->CSR_TLBREHI; + if (FIELD_EX64(cur->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + entryhi =3D cur->CSR_TLBREHI; /* Validity of pagesize is checked in helper_ldpte() */ - pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + pagesize =3D FIELD_EX64(cur->CSR_TLBREHI, CSR_TLBREHI, PS); } else { - entryhi =3D env->CSR_TLBEHI; + entryhi =3D cur->CSR_TLBEHI; /* Validity of pagesize is checked in helper_tlbrd() */ - pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + pagesize =3D FIELD_EX64(cur->CSR_TLBIDX, CSR_TLBIDX, PS); } =20 sptw_prepare_context(env, &context); @@ -483,9 +496,10 @@ void helper_tlbclr(CPULoongArchState *env) LoongArchTLB *tlb; int i, index; uint16_t csr_asid, tlb_asid, tlb_g; + CPUSysState *cur =3D get_current_state(env); =20 - csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); - index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + csr_asid =3D FIELD_EX64(cur->CSR_ASID, CSR_ASID, ASID); + index =3D FIELD_EX64(cur->CSR_TLBIDX, CSR_TLBIDX, INDEX); =20 if (index < LOONGARCH_STLB) { /* STLB. One line per operation */ @@ -515,8 +529,9 @@ void helper_tlbclr(CPULoongArchState *env) void helper_tlbflush(CPULoongArchState *env) { int i, index; + CPUSysState *cur =3D get_current_state(env); =20 - index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); + index =3D FIELD_EX64(cur->CSR_TLBIDX, CSR_TLBIDX, INDEX); =20 if (index < LOONGARCH_STLB) { /* STLB. One line per operation */ @@ -711,6 +726,7 @@ target_ulong helper_lddir(CPULoongArchState *env, targe= t_ulong base, uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint64_t val; + CPUSysState *cur =3D get_current_state(env); =20 if (unlikely((level =3D=3D 0) || (level > 4))) { qemu_log_mask(LOG_GUEST_ERROR, @@ -732,7 +748,7 @@ target_ulong helper_lddir(CPULoongArchState *env, targe= t_ulong base, } } =20 - badvaddr =3D env->CSR_TLBRBADV; + badvaddr =3D cur->CSR_TLBRBADV; base =3D base & palen_mask; get_dir_base_width(env, &dir_base, &dir_width, level); index =3D (badvaddr >> dir_base) & ((1 << dir_width) - 1); @@ -747,10 +763,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulon= g base, target_ulong odd, { CPUState *cs =3D env_cpu(env); hwaddr phys, tmp0, ptindex, ptoffset0, ptoffset1; + CPUSysState *cur =3D get_current_state(env); uint64_t pte_raw; uint64_t badv; - uint64_t ptbase =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE); - uint64_t ptwidth =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH); + uint64_t ptbase =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, PTBASE); + uint64_t ptwidth =3D FIELD_EX64(cur->CSR_PWCL, CSR_PWCL, PTWIDTH); uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint8_t ps; @@ -796,7 +813,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, return; } } else { - badv =3D env->CSR_TLBRBADV; + badv =3D cur->CSR_TLBRBADV; =20 base =3D base & palen_mask; =20 @@ -812,11 +829,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulon= g base, target_ulong odd, } =20 if (odd) { - env->CSR_TLBRELO1 =3D tmp0; + cur->CSR_TLBRELO1 =3D tmp0; } else { - env->CSR_TLBRELO0 =3D tmp0; + cur->CSR_TLBRELO0 =3D tmp0; } - env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps); + cur->CSR_TLBREHI =3D FIELD_DP64(cur->CSR_TLBREHI, CSR_TLBREHI, PS, ps); } =20 static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778345685489.37739855810753; Mon, 25 May 2026 23:52:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRldC-0002KD-O8; Tue, 26 May 2026 02:51:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcd-0002Gg-9J for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:39 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlca-0000as-GQ for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:38 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bxdni5QhVqbUwNAA--.13466S3; Tue, 26 May 2026 14:50:33 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxbcK4QhVqM16RAA--.11451S3; Tue, 26 May 2026 14:50:32 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 07/12] target/loongarch: Use curState in tcg_cpu.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:18 +0800 Message-Id: <20260526065023.1639371-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxbcK4QhVqM16RAA--.11451S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778349393154100 Content-Type: text/plain; charset="utf-8" When accessing CSR registers in file tcg_cpu.c, use curState rather than env. There is no function change. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tcg_cpu.c | 107 +++++++++++++++++---------------- 1 file changed, 56 insertions(+), 51 deletions(-) diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 31d3db6e8e..43c3c0eddc 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -77,34 +77,35 @@ void G_NORETURN do_raise_exception(CPULoongArchState *e= nv, static void loongarch_cpu_do_interrupt(CPUState *cs) { CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); bool update_badinstr =3D 1; int cause =3D -1; - bool tlbfill =3D FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); - uint32_t vec_size =3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); + bool tlbfill =3D FIELD_EX64(cur->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); + uint32_t vec_size =3D FIELD_EX64(cur->CSR_ECFG, CSR_ECFG, VS); uint64_t last_pc =3D env->pc; =20 if (cs->exception_index !=3D EXCCODE_INT) { qemu_log_mask(CPU_LOG_INT, "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", - __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA, + __func__, env->pc, cur->CSR_ERA, cur->CSR_TLBRERA, cs->exception_index, loongarch_exception_name(cs->exception_index)); } =20 switch (cs->exception_index) { case EXCCODE_DBP: - env->CSR_DBG =3D FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1); - env->CSR_DBG =3D FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC); + cur->CSR_DBG =3D FIELD_DP64(cur->CSR_DBG, CSR_DBG, DCL, 1); + cur->CSR_DBG =3D FIELD_DP64(cur->CSR_DBG, CSR_DBG, ECODE, 0xC); goto set_DERA; set_DERA: - env->CSR_DERA =3D env->pc; - env->CSR_DBG =3D FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); - set_pc(env, env->CSR_EENTRY + 0x480); + cur->CSR_DERA =3D env->pc; + cur->CSR_DBG =3D FIELD_DP64(cur->CSR_DBG, CSR_DBG, DST, 1); + set_pc(env, cur->CSR_EENTRY + 0x480); break; case EXCCODE_INT: - if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { - env->CSR_DBG =3D FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1); + if (FIELD_EX64(cur->CSR_DBG, CSR_DBG, DST)) { + cur->CSR_DBG =3D FIELD_DP64(cur->CSR_DBG, CSR_DBG, DEI, 1); goto set_DERA; } QEMU_FALLTHROUGH; @@ -115,7 +116,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) update_badinstr =3D 0; break; case EXCCODE_BCE: - env->CSR_BADV =3D env->pc; + cur->CSR_BADV =3D env->pc; QEMU_FALLTHROUGH; case EXCCODE_SYS: case EXCCODE_BRK: @@ -142,35 +143,35 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) if (update_badinstr) { MemOpIdx oi =3D make_memop_idx(MO_LEUL, cpu_mmu_index(cs, true)); =20 - env->CSR_BADI =3D cpu_ldl_code_mmu(env, env->pc, oi, 0); + cur->CSR_BADI =3D cpu_ldl_code_mmu(env, env->pc, oi, 0); } =20 /* Save PLV and IE */ if (tlbfill) { - env->CSR_TLBRPRMD =3D FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, = PPLV, - FIELD_EX64(env->CSR_CRMD, + cur->CSR_TLBRPRMD =3D FIELD_DP64(cur->CSR_TLBRPRMD, CSR_TLBRPRMD, = PPLV, + FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, PLV)); - env->CSR_TLBRPRMD =3D FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, = PIE, - FIELD_EX64(env->CSR_CRMD, CSR_CRMD,= IE)); + cur->CSR_TLBRPRMD =3D FIELD_DP64(cur->CSR_TLBRPRMD, CSR_TLBRPRMD, = PIE, + FIELD_EX64(cur->CSR_CRMD, CSR_CRMD,= IE)); /* set the DA mode */ - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0); - env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, DA, 1); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, PG, 0); + cur->CSR_TLBRERA =3D FIELD_DP64(cur->CSR_TLBRERA, CSR_TLBRERA, PC, (env->pc >> 2)); } else { - env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, + cur->CSR_ESTAT =3D FIELD_DP64(cur->CSR_ESTAT, CSR_ESTAT, ECODE, EXCODE_MCODE(cause)); - env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE, + cur->CSR_ESTAT =3D FIELD_DP64(cur->CSR_ESTAT, CSR_ESTAT, ESUBCODE, EXCODE_SUBCODE(cause)); - env->CSR_PRMD =3D FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV, - FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV= )); - env->CSR_PRMD =3D FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE, - FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE)= ); - env->CSR_ERA =3D env->pc; + cur->CSR_PRMD =3D FIELD_DP64(cur->CSR_PRMD, CSR_PRMD, PPLV, + FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, PLV= )); + cur->CSR_PRMD =3D FIELD_DP64(cur->CSR_PRMD, CSR_PRMD, PIE, + FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, IE)= ); + cur->CSR_ERA =3D env->pc; } =20 - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, PLV, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, IE, 0); =20 if (vec_size) { vec_size =3D (1 << vec_size) * 4; @@ -179,27 +180,27 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) if (cs->exception_index =3D=3D EXCCODE_INT) { /* Interrupt */ uint32_t vector =3D 0; - uint32_t pending =3D FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS); - pending &=3D FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE); + uint32_t pending =3D FIELD_EX64(cur->CSR_ESTAT, CSR_ESTAT, IS); + pending &=3D FIELD_EX64(cur->CSR_ECFG, CSR_ECFG, LIE); =20 /* Find the highest-priority interrupt. */ vector =3D 31 - clz32(pending); - set_pc(env, env->CSR_EENTRY + \ + set_pc(env, cur->CSR_EENTRY + \ (EXCCODE_EXTERNAL_INT + vector) * vec_size); qemu_log_mask(CPU_LOG_INT, "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx " cause %d\n" " A " TARGET_FMT_lx " D " TARGET_FMT_lx " vector =3D %d ExC " TARGET_FMT_lx "E= xS" TARGET_FMT_lx "\n", - __func__, env->pc, env->CSR_ERA, - cause, env->CSR_BADV, env->CSR_DERA, vector, - env->CSR_ECFG, env->CSR_ESTAT); + __func__, env->pc, cur->CSR_ERA, + cause, cur->CSR_BADV, cur->CSR_DERA, vector, + cur->CSR_ECFG, cur->CSR_ESTAT); qemu_plugin_vcpu_interrupt_cb(cs, last_pc); } else { if (tlbfill) { - set_pc(env, env->CSR_TLBRENTRY); + set_pc(env, cur->CSR_TLBRENTRY); } else { - set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); + set_pc(env, cur->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); } qemu_log_mask(CPU_LOG_INT, "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx @@ -207,12 +208,12 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu " cpu %d asid " TARGET_FMT_lx "\n", __func__, env->p= c, - tlbfill ? env->CSR_TLBRERA : env->CSR_ERA, - cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT, - env->CSR_ECFG, - tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV, - env->CSR_BADI, env->gpr[11], cs->cpu_index, - env->CSR_ASID); + tlbfill ? cur->CSR_TLBRERA : cur->CSR_ERA, + cause, tlbfill ? "(refill)" : "", cur->CSR_ESTAT, + cur->CSR_ECFG, + tlbfill ? cur->CSR_TLBRBADV : cur->CSR_BADV, + cur->CSR_BADI, env->gpr[11], cs->cpu_index, + cur->CSR_ASID); qemu_plugin_vcpu_exception_cb(cs, last_pc); } cs->exception_index =3D -1; @@ -226,8 +227,9 @@ static void loongarch_cpu_do_transaction_failed(CPUStat= e *cs, hwaddr physaddr, uintptr_t retaddr) { CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); =20 - env->CSR_BADV =3D addr; + cur->CSR_BADV =3D addr; if (access_type =3D=3D MMU_INST_FETCH) { do_raise_exception(env, EXCCODE_ADEF, retaddr); } else { @@ -238,9 +240,10 @@ static void loongarch_cpu_do_transaction_failed(CPUSta= te *cs, hwaddr physaddr, static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *= env) { bool ret =3D 0; + CPUSysState *cur =3D get_current_state(env); =20 - ret =3D (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) && - !(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST))); + ret =3D (FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, IE) && + !(FIELD_EX64(cur->CSR_DBG, CSR_DBG, DST))); =20 return ret; } @@ -271,12 +274,13 @@ static vaddr loongarch_pointer_wrap(CPUState *cs, int= mmu_idx, static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs) { CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); uint32_t flags; =20 - flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FP= E; - flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SX= E; - flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_A= SXE; + flags =3D cur->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + flags |=3D FIELD_EX64(cur->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FP= E; + flags |=3D FIELD_EX64(cur->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SX= E; + flags |=3D FIELD_EX64(cur->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_A= SXE; flags |=3D is_va32(env) * HW_FLAGS_VA32; =20 return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; @@ -299,9 +303,10 @@ static void loongarch_restore_state_to_opc(CPUState *c= s, static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) { CPULoongArchState *env =3D cpu_env(cs); + CPUSysState *cur =3D get_current_state(env); =20 - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + if (FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, PLV); } return MMU_DA_IDX; } --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778321646447.8094963534853; Mon, 25 May 2026 23:52:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRld9-0002K9-NK; Tue, 26 May 2026 02:51:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcd-0002Gi-F5 for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:41 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlca-0000aj-HT for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:39 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxzsC5QhVqbkwNAA--.14357S3; Tue, 26 May 2026 14:50:33 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxbcK4QhVqM16RAA--.11451S4; Tue, 26 May 2026 14:50:33 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 08/12] target/loongarch: Use curState in csr_helper.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:19 +0800 Message-Id: <20260526065023.1639371-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxbcK4QhVqM16RAA--.11451S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778323887154100 Content-Type: text/plain; charset="utf-8" When accessing CSR registers in file csr_helper.c, use curState rather than env. There is no function change. Signed-off-by: Bibo Mao --- target/loongarch/tcg/csr_helper.c | 55 ++++++++++++++++++------------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index cd35ca93c7..5a93727704 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -20,7 +20,8 @@ =20 target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val) { - int64_t old_v =3D env->CSR_STLBPS; + CPUSysState *cur =3D get_current_state(env); + int64_t old_v =3D cur->CSR_STLBPS; =20 /* * The real hardware only supports the min tlb_ps is 12 @@ -33,7 +34,7 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, = target_ulong val) } else { /* Only update PS field, reserved bit keeps zero */ val =3D FIELD_DP64(val, CSR_STLBPS, RESERVE, 0); - env->CSR_STLBPS =3D val; + cur->CSR_STLBPS =3D val; } =20 return old_v; @@ -42,17 +43,18 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env= , target_ulong val) target_ulong helper_csrrd_pgd(CPULoongArchState *env) { int64_t v; + CPUSysState *cur =3D get_current_state(env); =20 - if (env->CSR_TLBRERA & 0x1) { - v =3D env->CSR_TLBRBADV; + if (cur->CSR_TLBRERA & 0x1) { + v =3D cur->CSR_TLBRBADV; } else { - v =3D env->CSR_BADV; + v =3D cur->CSR_BADV; } =20 if ((v >> 63) & 0x1) { - v =3D env->CSR_PGDH; + v =3D cur->CSR_PGDH; } else { - v =3D env->CSR_PGDL; + v =3D cur->CSR_PGDL; } =20 return v; @@ -61,10 +63,11 @@ target_ulong helper_csrrd_pgd(CPULoongArchState *env) target_ulong helper_csrrd_cpuid(CPULoongArchState *env) { LoongArchCPU *lac =3D env_archcpu(env); + CPUSysState *cur =3D get_current_state(env); =20 - env->CSR_CPUID =3D CPU(lac)->cpu_index; + cur->CSR_CPUID =3D CPU(lac)->cpu_index; =20 - return env->CSR_CPUID; + return cur->CSR_CPUID; } =20 target_ulong helper_csrrd_tval(CPULoongArchState *env) @@ -77,16 +80,17 @@ target_ulong helper_csrrd_tval(CPULoongArchState *env) target_ulong helper_csrrd_msgir(CPULoongArchState *env) { int irq, new; + CPUSysState *cur =3D get_current_state(env); =20 - irq =3D find_first_bit((unsigned long *)env->CSR_MSGIS, 256); + irq =3D find_first_bit((unsigned long *)cur->CSR_MSGIS, 256); if (irq < 256) { - clear_bit(irq, (unsigned long *)env->CSR_MSGIS); - new =3D find_first_bit((unsigned long *)env->CSR_MSGIS, 256); + clear_bit(irq, (unsigned long *)cur->CSR_MSGIS); + new =3D find_first_bit((unsigned long *)cur->CSR_MSGIS, 256); if (new < 256) { return irq; } =20 - env->CSR_ESTAT =3D FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, MSGINT, 0= ); + cur->CSR_ESTAT =3D FIELD_DP64(cur->CSR_ESTAT, CSR_ESTAT, MSGINT, 0= ); } else { /* bit 31 set 1 for no invalid irq */ irq =3D BIT(31); @@ -97,21 +101,23 @@ target_ulong helper_csrrd_msgir(CPULoongArchState *env) =20 target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val) { - int64_t old_v =3D env->CSR_ESTAT; + CPUSysState *cur =3D get_current_state(env); + int64_t old_v =3D cur->CSR_ESTAT; =20 /* Only IS[1:0] can be written */ - env->CSR_ESTAT =3D deposit64(env->CSR_ESTAT, 0, 2, val); + cur->CSR_ESTAT =3D deposit64(cur->CSR_ESTAT, 0, 2, val); =20 return old_v; } =20 target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val) { - int64_t old_v =3D env->CSR_ASID; + CPUSysState *cur =3D get_current_state(env); + int64_t old_v =3D cur->CSR_ASID; =20 /* Only ASID filed of CSR_ASID can be written */ - env->CSR_ASID =3D deposit64(env->CSR_ASID, 0, 10, val); - if (old_v !=3D env->CSR_ASID) { + cur->CSR_ASID =3D deposit64(cur->CSR_ASID, 0, 10, val); + if (old_v !=3D cur->CSR_ASID) { tlb_flush(env_cpu(env)); } return old_v; @@ -120,7 +126,8 @@ target_ulong helper_csrwr_asid(CPULoongArchState *env, = target_ulong val) target_ulong helper_csrwr_tcfg(CPULoongArchState *env, target_ulong val) { LoongArchCPU *cpu =3D env_archcpu(env); - int64_t old_v =3D env->CSR_TCFG; + CPUSysState *cur =3D get_current_state(env); + int64_t old_v =3D cur->CSR_TCFG; =20 cpu_loongarch_store_constant_timer_config(cpu, val); =20 @@ -143,7 +150,8 @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env,= target_ulong val) target_ulong helper_csrwr_pwcl(CPULoongArchState *env, target_ulong val) { uint8_t shift, ptbase; - int64_t old_v =3D env->CSR_PWCL; + CPUSysState *cur =3D get_current_state(env); + int64_t old_v =3D cur->CSR_PWCL; =20 /* * The real hardware only supports 64bit PTE width now, 128bit or othe= rs @@ -160,14 +168,15 @@ target_ulong helper_csrwr_pwcl(CPULoongArchState *env= , target_ulong val) qemu_log_mask(LOG_GUEST_ERROR, "Attempted set ptbase 2^%d\n", ptbase); } - env->CSR_PWCL =3D val; + cur->CSR_PWCL =3D val; return old_v; } =20 target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val) { uint8_t has_ptw; - int64_t old_v =3D env->CSR_PWCH; + CPUSysState *cur =3D get_current_state(env); + int64_t old_v =3D cur->CSR_PWCH; =20 val =3D FIELD_DP64(val, CSR_PWCH, RESERVE, 0); has_ptw =3D FIELD_EX32(env->cpucfg[2], CPUCFG2, HPTW); @@ -175,6 +184,6 @@ target_ulong helper_csrwr_pwch(CPULoongArchState *env, = target_ulong val) val =3D FIELD_DP64(val, CSR_PWCH, HPTW_EN, 0); } =20 - env->CSR_PWCH =3D val; + cur->CSR_PWCH =3D val; return old_v; } --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778363064330.1664335194994; Mon, 25 May 2026 23:52:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRleK-0004Pu-V8; Tue, 26 May 2026 02:52:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRleI-00042o-0b for qemu-devel@nongnu.org; Tue, 26 May 2026 02:52:22 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRleF-0000ta-Km for qemu-devel@nongnu.org; Tue, 26 May 2026 02:52:21 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axvem6QhVqd0wNAA--.36295S3; Tue, 26 May 2026 14:50:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxbcK4QhVqM16RAA--.11451S5; Tue, 26 May 2026 14:50:33 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 09/12] target/loongarch: Use curState in op_helper.c when accessing CSR registers Date: Tue, 26 May 2026 14:50:20 +0800 Message-Id: <20260526065023.1639371-10-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxbcK4QhVqM16RAA--.11451S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778366480154100 Content-Type: text/plain; charset="utf-8" When accessing CSR registers in file op_helper.c, use curState rather than env. There is no function change. Signed-off-by: Bibo Mao --- target/loongarch/tcg/op_helper.c | 45 ++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_hel= per.c index 16ac0d43bc..4f12cdb3d3 100644 --- a/target/loongarch/tcg/op_helper.c +++ b/target/loongarch/tcg/op_helper.c @@ -46,16 +46,20 @@ target_ulong helper_bitswap(target_ulong v) /* loongarch assert op */ void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong= rk) { + CPUSysState *cur =3D get_current_state(env); + if (rj > rk) { - env->CSR_BADV =3D rj; + cur->CSR_BADV =3D rj; do_raise_exception(env, EXCCODE_BCE, GETPC()); } } =20 void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong= rk) { + CPUSysState *cur =3D get_current_state(env); + if (rj <=3D rk) { - env->CSR_BADV =3D rj; + cur->CSR_BADV =3D rj; do_raise_exception(env, EXCCODE_BCE, GETPC()); } } @@ -91,9 +95,10 @@ uint64_t helper_rdtime_d(CPULoongArchState *env) #else uint64_t plv; LoongArchCPU *cpu =3D env_archcpu(env); + CPUSysState *cur =3D get_current_state(env); =20 - plv =3D FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - if (extract64(env->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) { + plv =3D FIELD_EX64(cur->CSR_CRMD, CSR_CRMD, PLV); + if (extract64(cur->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) { do_raise_exception(env, EXCCODE_IPE, GETPC()); } =20 @@ -105,26 +110,28 @@ uint64_t helper_rdtime_d(CPULoongArchState *env) void helper_ertn(CPULoongArchState *env) { uint64_t csr_pplv, csr_pie; - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - csr_pplv =3D FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV); - csr_pie =3D FIELD_EX64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE); - - env->CSR_TLBRERA =3D FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1); - set_pc(env, env->CSR_TLBRERA); + CPUSysState *cur =3D get_current_state(env); + + if (FIELD_EX64(cur->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + csr_pplv =3D FIELD_EX64(cur->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV); + csr_pie =3D FIELD_EX64(cur->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE); + + cur->CSR_TLBRERA =3D FIELD_DP64(cur->CSR_TLBRERA, CSR_TLBRERA, IST= LBR, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, DA, 0); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, PG, 1); + set_pc(env, cur->CSR_TLBRERA); qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n", - __func__, env->CSR_TLBRERA); + __func__, cur->CSR_TLBRERA); } else { - csr_pplv =3D FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV); - csr_pie =3D FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE); + csr_pplv =3D FIELD_EX64(cur->CSR_PRMD, CSR_PRMD, PPLV); + csr_pie =3D FIELD_EX64(cur->CSR_PRMD, CSR_PRMD, PIE); =20 - set_pc(env, env->CSR_ERA); + set_pc(env, cur->CSR_ERA); qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n", - __func__, env->CSR_ERA); + __func__, cur->CSR_ERA); } - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, csr_pplv); - env->CSR_CRMD =3D FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, csr_pie); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, PLV, csr_pplv); + cur->CSR_CRMD =3D FIELD_DP64(cur->CSR_CRMD, CSR_CRMD, IE, csr_pie); =20 env->lladdr =3D 1; } --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778331639472.8587267256469; Mon, 25 May 2026 23:52:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRldj-0002pc-H1; Tue, 26 May 2026 02:51:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcw-0002Iu-Dd for qemu-devel@nongnu.org; Tue, 26 May 2026 02:51:00 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcs-0000e4-R8 for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:57 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axvem6QhVqdkwNAA--.36294S3; Tue, 26 May 2026 14:50:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxbcK4QhVqM16RAA--.11451S6; Tue, 26 May 2026 14:50:33 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 10/12] target/loongarch: Add default CSRFL_BASIC info with flags field Date: Tue, 26 May 2026 14:50:21 +0800 Message-Id: <20260526065023.1639371-11-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxbcK4QhVqM16RAA--.11451S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778333972154100 Content-Type: text/plain; charset="utf-8" With CSR array structure, its validility is checked from offset field. Now default CSRFL_BASIC information is added with flags field and its validility can be checked with flags field. Signed-off-by: Bibo Mao --- target/loongarch/csr.c | 6 +++--- target/loongarch/csr.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c index fff2312f87..d759be316b 100644 --- a/target/loongarch/csr.c +++ b/target/loongarch/csr.c @@ -17,11 +17,11 @@ [LOONGARCH_CSR_##NAME(N)] =3D { \ .name =3D (stringify(NAME##N)), \ .offset =3D offsetof(CPULoongArchState, CSR_##NAME[N]), \ - .flags =3D 0, .readfn =3D NULL, .writefn =3D NULL \ + .flags =3D CSRFL_BASIC, .readfn =3D NULL, .writefn =3D NULL = \ } =20 #define CSR_OFF_FLAGS(NAME, FL) CSR_OFF_FUNCS(NAME, FL, NULL, NULL) -#define CSR_OFF(NAME) CSR_OFF_FLAGS(NAME, 0) +#define CSR_OFF(NAME) CSR_OFF_FLAGS(NAME, CSRFL_BASIC) =20 static CSRInfo csr_info[] =3D { CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB), @@ -144,7 +144,7 @@ CSRInfo *get_csr(unsigned int csr_num) } =20 csr =3D &csr_info[csr_num]; - if (csr->offset =3D=3D 0) { + if (csr->flags =3D=3D 0) { return NULL; } =20 diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h index 81a656baae..508a3214fc 100644 --- a/target/loongarch/csr.h +++ b/target/loongarch/csr.h @@ -14,6 +14,7 @@ enum { CSRFL_EXITTB =3D (1 << 1), CSRFL_IO =3D (1 << 2), CSRFL_UNUSED =3D (1 << 3), + CSRFL_BASIC =3D (1 << 4), }; =20 typedef struct { --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778296681578.3779545216545; Mon, 25 May 2026 23:51:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRldN-0002Sy-64; Tue, 26 May 2026 02:51:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlcd-0002Gh-EU for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:41 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcb-0000b7-7T for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:39 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxRXi7QhVqfUwNAA--.13629S3; Tue, 26 May 2026 14:50:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxbcK4QhVqM16RAA--.11451S7; Tue, 26 May 2026 14:50:33 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 11/12] target/loongarch: Add wrapper function get_csr_offset() Date: Tue, 26 May 2026 14:50:22 +0800 Message-Id: <20260526065023.1639371-12-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxbcK4QhVqM16RAA--.11451S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778301589154100 Content-Type: text/plain; charset="utf-8" Add wrapper function get_csr_offset(), it is to get offset from structure CPULoongArchState. There is no function change, and it is used for future LVZ feature. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 4 ++-- target/loongarch/csr.h | 4 ++++ .../loongarch/tcg/insn_trans/trans_extra.c.inc | 11 ++++++++++- .../tcg/insn_trans/trans_privileged.c.inc | 16 +++++++++++----- 4 files changed, 27 insertions(+), 8 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 49bc896d7c..a036355e0c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -761,7 +761,7 @@ static void loongarch_cpu_dump_csr(CPUState *cs, FILE *= f) { #ifndef CONFIG_USER_ONLY CPULoongArchState *env =3D cpu_env(cs); - CSRInfo *csr_info; + const CSRInfo *csr_info; int64_t *addr; int i, j, len, col =3D 0; =20 @@ -783,7 +783,7 @@ static void loongarch_cpu_dump_csr(CPUState *cs, FILE *= f) qemu_fprintf(f, " CSR%03d:", col); } =20 - addr =3D (void *)env + csr_info->offset; + addr =3D (void *)env + get_csr_offset(csr_info, 0); qemu_fprintf(f, " %s ", csr_info->name); len =3D strlen(csr_info->name); for (; len < 6; len++) { diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h index 508a3214fc..ed7c603a0b 100644 --- a/target/loongarch/csr.h +++ b/target/loongarch/csr.h @@ -27,4 +27,8 @@ typedef struct { =20 CSRInfo *get_csr(unsigned int csr_num); bool set_csr_flag(unsigned int csr_num, int flag); +static inline int get_csr_offset(const CSRInfo *csr, int vm_level) +{ + return csr->offset; +} #endif /* TARGET_LOONGARCH_CSR_H */ diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc b/target/loo= ngarch/tcg/insn_trans/trans_extra.c.inc index 298a80cff5..fdff09efd4 100644 --- a/target/loongarch/tcg/insn_trans/trans_extra.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_extra.c.inc @@ -3,6 +3,7 @@ * Copyright (c) 2021 Loongson Technology Corporation Limited */ =20 +#include "csr.h" static bool trans_break(DisasContext *ctx, arg_break *a) { generate_exception(ctx, EXCCODE_BRK); @@ -46,13 +47,21 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a, { TCGv dst1 =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv dst2 =3D gpr_dst(ctx, a->rj, EXT_NONE); + tcg_target_long offset; + const CSRInfo *csr; =20 translator_io_start(&ctx->base); gen_helper_rdtime_d(dst1, tcg_env); if (word) { tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32); } - tcg_gen_ld_i64(dst2, tcg_env, offsetof(CPULoongArchState, CSR_TID)); + csr =3D get_csr(LOONGARCH_CSR_TID); + if (!csr) { + return false; + } + + offset =3D get_csr_offset(csr, 0); + tcg_gen_ld_i64(dst2, tcg_env, offset); =20 return true; } diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index 2094d182ac..6728ce5ec9 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -106,6 +106,7 @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a) TCGv dest; const CSRInfo *csr; GenCSRRead readfn; + tcg_target_long offset; =20 if (check_plv(ctx)) { return false; @@ -121,7 +122,8 @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a) if (readfn) { readfn(dest, tcg_env); } else { - tcg_gen_ld_tl(dest, tcg_env, csr->offset); + offset =3D get_csr_offset(csr, 0); + tcg_gen_ld_tl(dest, tcg_env, offset); } } gen_set_gpr(a->rd, dest, EXT_NONE); @@ -133,6 +135,7 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a) TCGv dest, src1; const CSRInfo *csr; GenCSRWrite writefn; + tcg_target_long offset; =20 if (check_plv(ctx)) { return false; @@ -154,8 +157,9 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a) writefn(dest, tcg_env, src1); } else { dest =3D tcg_temp_new(); - tcg_gen_ld_tl(dest, tcg_env, csr->offset); - tcg_gen_st_tl(src1, tcg_env, csr->offset); + offset =3D get_csr_offset(csr, 0); + tcg_gen_ld_tl(dest, tcg_env, offset); + tcg_gen_st_tl(src1, tcg_env, offset); } gen_set_gpr(a->rd, dest, EXT_NONE); return true; @@ -166,6 +170,7 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxch= g *a) TCGv src1, mask, oldv, newv, temp; const CSRInfo *csr; GenCSRWrite writefn; + tcg_target_long offset; =20 if (check_plv(ctx)) { return false; @@ -191,7 +196,8 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxch= g *a) newv =3D tcg_temp_new(); temp =3D tcg_temp_new(); =20 - tcg_gen_ld_tl(oldv, tcg_env, csr->offset); + offset =3D get_csr_offset(csr, 0); + tcg_gen_ld_tl(oldv, tcg_env, offset); tcg_gen_and_tl(newv, src1, mask); tcg_gen_andc_tl(temp, oldv, mask); tcg_gen_or_tl(newv, newv, temp); @@ -200,7 +206,7 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxch= g *a) if (writefn) { writefn(oldv, tcg_env, newv); } else { - tcg_gen_st_tl(newv, tcg_env, csr->offset); + tcg_gen_st_tl(newv, tcg_env, offset); } gen_set_gpr(a->rd, oldv, EXT_NONE); return true; --=20 2.39.3 From nobody Sat May 30 17:46:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779778320051436.78131215178223; Mon, 25 May 2026 23:52:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRldW-0002XA-3T; Tue, 26 May 2026 02:51:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wRlci-0002HL-Qx for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:50 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wRlcf-0000cT-8d for qemu-devel@nongnu.org; Tue, 26 May 2026 02:50:44 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx8eq9QhVqg0wNAA--.38074S3; Tue, 26 May 2026 14:50:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCx98C8QhVqNF6RAA--.64567S2; Tue, 26 May 2026 14:50:36 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: qemu-devel@nongnu.org, SignKirigami , Hengyu Yu Subject: [PATCH 12/12] target/loongarch: Add new structure CPUSysState Date: Tue, 26 May 2026 14:50:23 +0800 Message-Id: <20260526065023.1639371-13-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260526065023.1639371-1-maobibo@loongson.cn> References: <20260526065023.1639371-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCx98C8QhVqNF6RAA--.64567S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1779778323073154100 Content-Type: text/plain; charset="utf-8" New structure CPUSysState is added here, it contains CSR registers now, in future TLB and timer can be moved to this structure also. It is only code movement, no function change. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 4 +- target/loongarch/cpu.h | 35 +++++------ target/loongarch/csr.c | 4 +- target/loongarch/csr.h | 2 +- target/loongarch/machine.c | 116 ++++++++++++++++++------------------- 5 files changed, 81 insertions(+), 80 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index a036355e0c..f918fd94b8 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -282,7 +282,7 @@ static void loongarch_la464_initfn(Object *obj) uint32_t data =3D 0, field; int i; =20 - set_current_state(env, env); + set_current_state(env, &env->sys_env[0]); for (i =3D 0; i < 21; i++) { env->cpucfg[i] =3D 0x0; } @@ -412,7 +412,7 @@ static void loongarch_la132_initfn(Object *obj) uint32_t data =3D 0; int i; =20 - set_current_state(env, env); + set_current_state(env, &env->sys_env[0]); for (i =3D 0; i < 21; i++) { env->cpucfg[i] =3D 0x0; } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index dedb3971e5..9787ad2ec6 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -317,23 +317,7 @@ typedef struct LoongArchBT { #define CPU_VENDOR_LOONGSON "Loongson" #define CPU_MODEL_3A5000 "3A5000" #define CPU_MODEL_1C101 "1C101" -struct CPUArchState; -typedef struct CPUArchState CPUSysState; - -typedef struct CPUArchState { - uint64_t gpr[32]; - uint64_t pc; - - fpr_t fpr[32]; - bool cf[8]; - uint32_t fcsr0; - lbt_t lbt; - - uint32_t cpucfg[21]; - uint32_t pv_features; - uint64_t vendor_id; - uint64_t cpu_id; - +typedef struct CPUSysState { /* LoongArch CSRs */ uint64_t CSR_CRMD; uint64_t CSR_PRMD; @@ -395,6 +379,23 @@ typedef struct CPUArchState { uint64_t CSR_MSGIS[N_MSGIS]; uint64_t CSR_MSGIR; uint64_t CSR_MSGIE; +} CPUSysState; + +typedef struct CPUArchState { + uint64_t gpr[32]; + uint64_t pc; + + fpr_t fpr[32]; + bool cf[8]; + uint32_t fcsr0; + lbt_t lbt; + + uint32_t cpucfg[21]; + uint32_t pv_features; + uint64_t vendor_id; + uint64_t cpu_id; + CPUSysState sys_env[1]; + struct { uint64_t guest_addr; } stealtime; diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c index d759be316b..9678948c45 100644 --- a/target/loongarch/csr.c +++ b/target/loongarch/csr.c @@ -9,14 +9,14 @@ #define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ [LOONGARCH_CSR_##NAME] =3D { \ .name =3D (stringify(NAME)), \ - .offset =3D offsetof(CPULoongArchState, CSR_##NAME), \ + .offset =3D offsetof(CPUSysState, CSR_##NAME), \ .flags =3D FL, .readfn =3D RD, .writefn =3D WR \ } =20 #define CSR_OFF_ARRAY(NAME, N) \ [LOONGARCH_CSR_##NAME(N)] =3D { \ .name =3D (stringify(NAME##N)), \ - .offset =3D offsetof(CPULoongArchState, CSR_##NAME[N]), \ + .offset =3D offsetof(CPUSysState, CSR_##NAME[N]), \ .flags =3D CSRFL_BASIC, .readfn =3D NULL, .writefn =3D NULL = \ } =20 diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h index ed7c603a0b..6841968b80 100644 --- a/target/loongarch/csr.h +++ b/target/loongarch/csr.h @@ -29,6 +29,6 @@ CSRInfo *get_csr(unsigned int csr_num); bool set_csr_flag(unsigned int csr_num, int flag); static inline int get_csr_offset(const CSRInfo *csr, int vm_level) { - return csr->offset; + return csr->offset + offsetof(CPULoongArchState, sys_env[vm_level]); } #endif /* TARGET_LOONGARCH_CSR_H */ diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index 4db53fec26..a54c5d18a4 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -58,9 +58,9 @@ static const VMStateDescription vmstate_msgint =3D { .minimum_version_id =3D 1, .needed =3D msgint_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, N_MSGIS), - VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_MSGIS, LoongArchCPU, N_MSG= IS), + VMSTATE_UINT64(env.sys_env[0].CSR_MSGIR, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MSGIE, LoongArchCPU), VMSTATE_END_OF_LIST() }, }; @@ -167,8 +167,8 @@ static const VMStateDescription vmstate_pmu =3D { .needed =3D pmu_needed, .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.perf_event_num, LoongArchCPU), - VMSTATE_UINT64_ARRAY(env.CSR_PERFCTRL, LoongArchCPU, MAX_PERF_EVEN= TS), - VMSTATE_UINT64_ARRAY(env.CSR_PERFCNTR, LoongArchCPU, MAX_PERF_EVEN= TS), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_PERFCTRL, LoongArchCPU, MA= X_PERF_EVENTS), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_PERFCNTR, LoongArchCPU, MA= X_PERF_EVENTS), VMSTATE_END_OF_LIST() }, }; @@ -215,61 +215,61 @@ const VMStateDescription vmstate_loongarch_cpu =3D { VMSTATE_UINT64(env.pc, LoongArchCPU), =20 /* Remaining CSRs */ - VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU), - VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU), - VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU), - VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU), - VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU), - VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16), - VMSTATE_UINT64(env.CSR_TID, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU), - VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU), - VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU), - VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4), + VMSTATE_UINT64(env.sys_env[0].CSR_CRMD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRMD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_EUEN, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MISC, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ECFG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ESTAT, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_BADV, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_BADI, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_EENTRY, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBIDX, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBEHI, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBELO0, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBELO1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ASID, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PGDL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PGDH, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PGD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PWCL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PWCH, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_STLBPS, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_RVACFG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRCFG1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRCFG2, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRCFG3, LoongArchCPU), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_SAVE, LoongArchCPU, 16), + VMSTATE_UINT64(env.sys_env[0].CSR_TID, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TCFG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TVAL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_CNTC, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TICLR, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_LLBCTL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_IMPCTL1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_IMPCTL2, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRENTRY, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRBADV, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRSAVE, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRELO0, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRELO1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBREHI, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRPRMD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRCTL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRINFO1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRINFO2, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRENTRY, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRSAVE, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_CTAG, LoongArchCPU), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_DMW, LoongArchCPU, 4), =20 /* Debug CSRs */ - VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_DBG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_DERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_DSAVE, LoongArchCPU), =20 VMSTATE_UINT64(kvm_state_counter, LoongArchCPU), /* PV steal time */ --=20 2.39.3