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[107.220.129.194]) by smtp.gmail.com with ESMTPSA id 00721157ae682-7d38be313c9sm47545467b3.30.2026.05.25.08.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 May 2026 08:24:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779722671; x=1780327471; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ksOvl/ewr6dXPnhJyxWvDLQ6m0eOKL1ME5QF1eL20+A=; b=Vq2n1ih/IJhLUvOpJAKWTIM5fr2ZlPMNqIGzRetO/SGhGfJGF4/Xlh+xysm4S49sCl sHx1FoDLNenNki1Eq/VqWKXnwc8wfC60zRco1jkRL5LS7Y8WR3yO5a/K7zOX9qDAatjU ORmfTHPyY2XvqZalSuZRTHK3YkvQJVhliyH7bYzni8NsJPV/6Y2wjjhs3DFaQ6t1bVcf DNP/HFdHIz+cITJ7CWtQj1AuQqujkirDeCvwhFitOO+isN/yNePCerHdHeJU39B5bcD4 EQHjw+/Wv8p0XxDmtm+6comGrPCqI0K0pcYnB+sZ3hXQHssT1hNn6SYYyeXk4RQqhz1h ovwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779722671; x=1780327471; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=ksOvl/ewr6dXPnhJyxWvDLQ6m0eOKL1ME5QF1eL20+A=; b=SQ+8fy8cnfK6Q/lNhwkWjJ+3x9rHU8VRMMnKnkQi1hN/5FAcy9tvwpKcqbexv+6EoM 4qECCSE+L7o8a6vJ3vzJhI7HDhnZqffVnzxNTxLg4Bfio68fvP7glKeMknH42xOIaFrG M0KXluXyw5LACKawgMnLJq+0uuVIIXKaPALXMCxxNTmcSp7BELq1eavDv2JiAKtPycz8 kZWIFqAIkO27Xpbte+IhDeTWgjrz3aM9S7qrb+Ty8bKPKmhNN286H3MEaJBFfYKJRxBq 6OG3CoC71Ppv8st4hn0E8A9FNCMvXF54M/TfY2KvxLkGHVE+09g0PPi/T0qslUEqm5XS F5ag== X-Gm-Message-State: AOJu0Ywo8r2JBzFjbsZf3bC09KCKqSVTTlRfos6NcDNH623jE2yHBeqL WR1vPE/Jo50hIRbhHDv6dFtTRcoyNLX7AR0Ldr1gQpEa1TU3Cj35/ssMLhkrla9w X-Gm-Gg: Acq92OElgZd8L/k2mHNiOl9FQvaOhLq5pSNX2xE90QGypkU1lYOdvXOn+4uZ1m/rjPh GFkrqtNPTgCNHrSVCFwNgkpoeSwD6/JiJJHshO1qXwEX32E/8sQ7wR5WOMm0qs/YHvEPrxD1nRz JNGBEUePo7X0pwtjG53pMgEjanF2m+HlBYH43kCWYg1dL4hNTsYxwTOLMP0v40L4CT5x2Wwq1Wa 961daL2ktJ2I/HYDkrzF2H3w1GsknY/Yfc5ougtgeOvuPt2dqNdHNMpiFWPJRi3gt/r7SzNUJJs mwf8itDGlVus82MMxHuPbJn16EfaTtwuWxfmDo5/x7cW4QJc56CnSuFU2jN0vwjd8Li/SAoyFKq t+qmnRJ5LaWcghXNSjpVjd5G82tgpms1z3PP+B/SFhFImnr9LWllXrbVPr6SGOTKAAKyaXYxcZQ WSXSvMaHYVMGGYy9GGL5debJMFyzzxDfy1ZJZFfw9WA9X1ulqttlRs/X3F9JdHpYB+4rnwXMHx3 CU= X-Received: by 2002:a05:690c:c22e:b0:7bd:a50c:454d with SMTP id 00721157ae682-7d33868107fmr171135817b3.13.1779722671502; Mon, 25 May 2026 08:24:31 -0700 (PDT) From: Matt Turner To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Matt Turner , qemu-stable@nongnu.org Subject: [PATCH] linux-user/mips: save/restore FCSR across signal delivery Date: Mon, 25 May 2026 11:24:27 -0400 Message-ID: <20260525152427.4120785-1-mattst88@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1130; envelope-from=mattst88@gmail.com; helo=mail-yw1-x1130.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779722680545158500 Content-Type: text/plain; charset="utf-8" QEMU keeps the MIPS FPU control/status register (FCSR, fcr31) in env->active_fpu.fcr31. The rounding mode, flush-to-zero (FS), and NaN-2008 mode bits in fcr31 are reflected into the derived env->active_fpu.fp_status via set_float_rounding_mode() and friends; every architectural write to FCSR goes through helper_ctc1() which calls restore_fp_status() to keep the two in sync. Both target_sigcontext variants (O32 and N32/N64) have an sc_fpc_csr field that holds FCSR, but setup_sigcontext() never wrote it and restore_sigcontext() never read it. As a result: - The signal frame always delivered sc_fpc_csr =3D=3D 0 to the handler, so sigaction(SA_SIGINFO) handlers that inspect the interrupted context see the wrong FCSR. - On sigreturn, active_fpu.fcr31 retained whatever value the signal handler last installed (if any), and active_fpu.fp_status was never resynced. Interrupted code resumed with the wrong rounding mode, FS flag, and NaN-2008 semantics. Fix setup_sigcontext() to save fcr31 into sc_fpc_csr. Fix restore_sigcontext() to read it back (masked to fcr31_rw_bitmask as the kernel does) and call cpu_mips_restore_fp_status() to resync fp_status from the restored fcr31. Add cpu_mips_restore_fp_status() in target/mips/fpu.c (which already defines ieee_rm and includes fpu_helper.h), and declare it in cpu.h. Fixes: 084d0497a0 ("mips-linux-user: Save and restore fpu and dsp from sigc= ontext") Cc: qemu-stable@nongnu.org --- linux-user/mips/signal.c | 7 +++++++ target/mips/cpu.h | 3 +++ target/mips/fpu.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git ./linux-user/mips/signal.c ./linux-user/mips/signal.c index d69a5d73dd..1b10012726 100644 --- ./linux-user/mips/signal.c +++ ./linux-user/mips/signal.c @@ -134,6 +134,7 @@ static inline void setup_sigcontext(CPUMIPSState *regs, for (i =3D 0; i < 32; ++i) { __put_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]); } + __put_user(regs->active_fpu.fcr31, &sc->sc_fpc_csr); } =20 static inline void @@ -165,6 +166,12 @@ restore_sigcontext(CPUMIPSState *regs, struct target_s= igcontext *sc) for (i =3D 0; i < 32; ++i) { __get_user(regs->active_fpu.fpr[i].d, &sc->sc_fpregs[i]); } + { + uint32_t fcr31; + __get_user(fcr31, &sc->sc_fpc_csr); + regs->active_fpu.fcr31 =3D fcr31 & regs->active_fpu.fcr31_rw_bitma= sk; + cpu_mips_restore_fp_status(regs); + } } =20 /* diff --git ./target/mips/cpu.h ./target/mips/cpu.h index 346713705a..392406aff8 100644 --- ./target/mips/cpu.h +++ ./target/mips/cpu.h @@ -1384,6 +1384,9 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 +/* fpu.c */ +void cpu_mips_restore_fp_status(CPUMIPSState *env); + /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git ./target/mips/fpu.c ./target/mips/fpu.c index c7c487c1f9..8b661865ca 100644 --- ./target/mips/fpu.c +++ ./target/mips/fpu.c @@ -17,6 +17,11 @@ const FloatRoundMode ieee_rm[4] =3D { float_round_down }; =20 +void cpu_mips_restore_fp_status(CPUMIPSState *env) +{ + restore_fp_status(env); +} + const char fregnames[32][4] =3D { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", --=20 2.53.0