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Sun, 24 May 2026 20:26:42 -0700 (PDT) From: Nicholas Righi To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Righi Subject: [PATCH] hw/arm/bcm2838: Route I2C interrupts to GIC Date: Sun, 24 May 2026 20:26:34 -0700 Message-ID: <20260525032634.7754-1-nicholasrighi@gmail.com> X-Mailer: git-send-email 2.51.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=nicholasrighi@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 May 2026 01:08:36 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779685759818154100 Content-Type: text/plain; charset="utf-8" The I2C interrupts are only routed to the legacy interrupt controller. This= means that for modern device trees that use the GIC, the interrupts don't work. T= his patch re-routes the I2C OR'd interrupt from the legacy interrupt controller to th= e GIC so I2C emulation works out of the box with current kernels. Testing Add these lines to QEMU invocation -drive if=3Dnone,id=3Di2c_storage,format=3Draw,file=3Deeprom.bin \ -device at24c-eeprom,bus=3Di2c-bus.1,address=3D0x50,drive=3Di2c_storage,rom= -size=3D4096 \ note: eeprom.bin is all zeros Before this change, running i2c get to read from EEPROM would result in this i2cget -y 1 0x50 Error: Read failed After this change, running i2c to read from EEPROM results in this i2cget -y 1 0x50 0x00 The eeprom can now also be enabled in the device tree. Before the eeprom driver load would fail due to the read failing ls -l /sys/bus/i2c/devices/i2c-1/1-0050/ | grep -i eeprom -rw------- 1 root root 4096 May 17 16:57 eeprom Signed-off-by: Nicholas Righi Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/bcm2838.c | 3 +++ include/hw/arm/bcm2838_peripherals.h | 1 + 2 files changed, 4 insertions(+) diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c index c14a854046..6895f70385 100644 --- a/hw/arm/bcm2838.c +++ b/hw/arm/bcm2838.c @@ -184,6 +184,9 @@ static void bcm2838_realize(DeviceState *dev, Error **e= rrp) sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->aux), 0, qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_AUX_UART= 1)); =20 + qdev_connect_gpio_out(DEVICE(&ps_base->orgated_i2c_irq), 0, + qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_I2C)); + /* Connect VC mailbox to the interrupt controller */ sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->mboxes), 0, qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_MBOX)); diff --git a/include/hw/arm/bcm2838_peripherals.h b/include/hw/arm/bcm2838_= peripherals.h index 7ee1bd066f..0be97e67c7 100644 --- a/include/hw/arm/bcm2838_peripherals.h +++ b/include/hw/arm/bcm2838_peripherals.h @@ -22,6 +22,7 @@ #define GIC_SPI_INTERRUPT_DMA_7_8 87 #define GIC_SPI_INTERRUPT_DMA_9_10 88 #define GIC_SPI_INTERRUPT_AUX_UART1 93 +#define GIC_SPI_INTERRUPT_I2C 117 #define GIC_SPI_INTERRUPT_SDHOST 120 #define GIC_SPI_INTERRUPT_UART0 121 #define GIC_SPI_INTERRUPT_RNG200 125 --=20 2.51.2