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Thu, 21 May 2026 17:04:53 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Chengbo Gao , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 24/48] hw/riscv/riscv-iommu: Avoid caching PCI device IDs Date: Fri, 22 May 2026 10:03:00 +1000 Message-ID: <20260522000324.23255-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260522000324.23255-1-alistair.francis@wdc.com> References: <20260522000324.23255-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779408571128154100 Content-Type: text/plain; charset="utf-8" From: Chengbo Gao PCI bus numbers may still be unassigned when QEMU initializes a PCI device's bus-master address space. For devices behind bridges, pci_bus_num() can return 0 at that point because the guest has not yet programmed the bridge Secondary Bus Number register. The RISC-V IOMMU currently stores a fixed device_id in RISCVIOMMUSpace when the address space is created. If the guest later enumerates the device on a non-zero bus, DMA translation still uses the stale device_id and may look up the wrong device context in the DDT. Store the stable PCIBus pointer and devfn in RISCVIOMMUSpace instead, and compute the device_id from the current bus number when it is needed. This keeps DMA translation and ATS invalidation in sync with guest PCI bus enumeration. Signed-off-by: Chengbo Gao Reviewed-by: Daniel Henrique Barboza Message-ID: <20260514020637.2819308-1-gaochengbo@bosc.ac.cn> Signed-off-by: Alistair Francis --- hw/riscv/riscv-iommu.c | 40 +++++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index c9c64be24f..5bc2472a83 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -49,7 +49,8 @@ struct RISCVIOMMUSpace { IOMMUMemoryRegion iova_mr; /* IOVA memory region for attached device = */ AddressSpace iova_as; /* IOVA address space for attached device = */ RISCVIOMMUState *iommu; /* Managing IOMMU device state */ - uint32_t devid; /* Requester identifier, AKA device_id */ + PCIBus *bus; /* PCI bus of the requester */ + uint8_t devfn; /* Requester identifier, AKA device_id */ bool notifier; /* IOMMU unmap notifier enabled */ QLIST_ENTRY(RISCVIOMMUSpace) list; }; @@ -74,6 +75,15 @@ struct RISCVIOMMUEntry { /* IOMMU index for transactions without process_id specified. */ #define RISCV_IOMMU_NOPROCID 0 =20 +static uint32_t riscv_iommu_space_devid(RISCVIOMMUSpace *as) +{ + uint32_t devid =3D PCI_BUILD_BDF(pci_bus_num(as->bus), as->devfn); + + /* FIXME: PCIe bus remapping for attached endpoints. */ + devid |=3D as->iommu->bus << 8; + return devid; +} + static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t vec_t= ype) { switch (vec_type) { @@ -1379,15 +1389,13 @@ static void riscv_iommu_ctx_put(RISCVIOMMUState *s,= void *ref) } =20 /* Find or allocate address space for a given device */ -static AddressSpace *riscv_iommu_space(RISCVIOMMUState *s, uint32_t devid) +static AddressSpace *riscv_iommu_space(RISCVIOMMUState *s, PCIBus *bus, + int devfn) { RISCVIOMMUSpace *as; =20 - /* FIXME: PCIe bus remapping for attached endpoints. */ - devid |=3D s->bus << 8; - QLIST_FOREACH(as, &s->spaces, list) { - if (as->devid =3D=3D devid) { + if (as->bus =3D=3D bus && as->devfn =3D=3D devfn) { break; } } @@ -1397,10 +1405,11 @@ static AddressSpace *riscv_iommu_space(RISCVIOMMUSt= ate *s, uint32_t devid) as =3D g_new0(RISCVIOMMUSpace, 1); =20 as->iommu =3D s; - as->devid =3D devid; + as->bus =3D bus; + as->devfn =3D devfn; =20 snprintf(name, sizeof(name), "riscv-iommu-%04x:%02x.%d-iova", - PCI_BUS_NUM(as->devid), PCI_SLOT(as->devid), PCI_FUNC(as->devi= d)); + pci_bus_num(bus), PCI_SLOT(devfn), PCI_FUNC(devfn)); =20 /* IOVA address space, untranslated addresses */ memory_region_init_iommu(&as->iova_mr, sizeof(as->iova_mr), @@ -1410,8 +1419,8 @@ static AddressSpace *riscv_iommu_space(RISCVIOMMUStat= e *s, uint32_t devid) =20 QLIST_INSERT_HEAD(&s->spaces, as, list); =20 - trace_riscv_iommu_new(s->parent_obj.id, PCI_BUS_NUM(as->devid), - PCI_SLOT(as->devid), PCI_FUNC(as->devid)); + trace_riscv_iommu_new(s->parent_obj.id, pci_bus_num(bus), + PCI_SLOT(devfn), PCI_FUNC(devfn)); } return &as->iova_as; } @@ -1732,7 +1741,7 @@ static void riscv_iommu_ats(RISCVIOMMUState *s, pid =3D get_field(cmd->dword0, RISCV_IOMMU_CMD_ATS_PID); =20 QLIST_FOREACH(as, &s->spaces, list) { - if (as->devid =3D=3D devid) { + if (riscv_iommu_space_devid(as) =3D=3D devid) { break; } } @@ -2745,8 +2754,9 @@ static IOMMUTLBEntry riscv_iommu_memory_region_transl= ate( .addr_mask =3D ~0ULL, .perm =3D flag, }; + uint32_t devid =3D riscv_iommu_space_devid(as); =20 - ctx =3D riscv_iommu_ctx(as->iommu, as->devid, iommu_idx, &ref); + ctx =3D riscv_iommu_ctx(as->iommu, devid, iommu_idx, &ref); if (ctx =3D=3D NULL) { /* Translation disabled or invalid. */ iotlb.addr_mask =3D 0; @@ -2758,8 +2768,8 @@ static IOMMUTLBEntry riscv_iommu_memory_region_transl= ate( } =20 /* Trace all dma translations with original access flags. */ - trace_riscv_iommu_dma(as->iommu->parent_obj.id, PCI_BUS_NUM(as->devid), - PCI_SLOT(as->devid), PCI_FUNC(as->devid), iommu_= idx, + trace_riscv_iommu_dma(as->iommu->parent_obj.id, PCI_BUS_NUM(devid), + PCI_SLOT(devid), PCI_FUNC(devid), iommu_idx, IOMMU_FLAG_STR[flag & IOMMU_RW], iotlb.iova, iotlb.translated_addr); =20 @@ -2807,7 +2817,7 @@ static AddressSpace *riscv_iommu_find_as(PCIBus *bus,= void *opaque, int devfn) =20 /* Find first matching IOMMU */ while (s !=3D NULL && as =3D=3D NULL) { - as =3D riscv_iommu_space(s, PCI_BUILD_BDF(pci_bus_num(bus), devfn)= ); + as =3D riscv_iommu_space(s, bus, devfn); s =3D s->iommus.le_next; } =20 --=20 2.53.0