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[184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427217; x=1780032017; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=99YbXwU+QZjVpPSGzU0gdv9rBjyJynqi/nBLawDCdQk=; b=DtOAaxCtIXRjfR1T/L/p1sPoDzVn1P477aRC+oJ+DcIqjh+OyxDYnQ4amK5YGyK0yz OsuVnY2yKuq+mwMXo0XNlwTG3yELEaTfvOWr07VBB0Y5nehQ51b0oh2N/vBr5TA9MbmO 6TYZzOmqlT8R0I0swIK3ZsCCgMeXwMY+HI93oRSFGoZU71Dv5d6JA5WuGGW3iV2ffBIg 7ZGkPbPNZKpZWPsYWl6QS8dLTM5V6Vko2ljemv6ludiuD3gGo0wz5iO6HqQyR133wUTD tbfUODY3pySEoSIJth0tIUjtNavVU/mm08y2r6Oefm54xU24fSG11ffrdca8QcLDznAF v20g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427217; x=1780032017; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=99YbXwU+QZjVpPSGzU0gdv9rBjyJynqi/nBLawDCdQk=; b=EnBu7+3pFeIIZPnzUd6qMGJu9fpke+9XIqhHceqd//N5u0znS3r6wrIE/2hz3Lc8rF IPzPweIt+hldFZnmika8nDFwoj+FrEwmxHs01lMW//1qUuJXErz6NpuafIl/m4ON05ft nFdWYhmK/2ukCA/l/FyfXSZL+kr8kxbo9uhxzUmWTcj7/uf9x4+G4pmvF/QI4PiCZd3m 7675Bx8m2sst0zLbhFKOI/hAPRSF9Sv2JBw2cggCjP8DXb1cFcEkS0xBWNe7hyha1UWG xU65dSoE92hiVilJi3yfxlKvLJxANvP/FofWRuk0LxH7KWWi4PFHcRTOxsmKwSyHQXba OSRA== X-Gm-Message-State: AOJu0YxIF0mmv4mNUmYHjyUOsmYENYyP86s72jOwK6orIxHOHXaXeVmq N6KwVPsC37CHXWEgH+/vTQKEIiWWGXQ1xzm1vlBP8jXlIb4gPJ/qnuJl X-Gm-Gg: Acq92OF37AStpx67VUrm2+Szv8MS9UBpTVfIbB4kLHKu6DN+GhU4jMj2qXD4u76vvfU 2qGQj1Fcoi61CcuFuKLwXzxtd89jbG2y/dsWNdGx2zLBCJhCWt65s5y8lTxpIJupd3eEB5EgPze oUxWw/UCj1MpYCHjiQ0ziIAXx4hgoGigyf05ugA7IxlPZFLDg0zfU+jQITj1ni4snv2QP1D3vvp kgt1jAsjTmSL0M7pFCHfbbvLN19g1bs0g3k945iYQq81DG4xhHa/nqc3GEQ5ViBZlT/HsnXJr7r +ua63fsJhy87Wyv+1SqPPIS3q4CnQgqTVXDGBmTcdanSQUErxr/BCCKP9qOgYfeHTglSj6/AB3D clQWNODbT+hZebEiNfNPzJlvNJt5GGuKSWP5zKciiA9sOEBnC7EEtVnE40+iUj78tQPvtoq0zqv QIYdqNA1gaj96fuRR+Wovt2AO9L823WPpDBbfV3z3mEuUMNTLUKe2Dj1nMj3OeD3rAZ+phyl6A4 4G3knI8xhrRgRkuO1oRG95i8wOBxVebpS2XRwpWW2+Py9z8+4yIF92qQA1LZj4b70ktfXtfxApb DVw= X-Received: by 2002:a05:6808:6786:b0:463:a42c:503a with SMTP id 5614622812f47-4854ae802demr969507b6e.14.1779427217241; Thu, 21 May 2026 22:20:17 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:46 -0600 Subject: [PATCH v14 04/22] target/mips: add Octeon CRC COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-4-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427309227154100 Add helper support for the Octeon COP2 CRC register interface. This covers normal and reflected CRC state handling, byte/halfword/word/ doubleword/variable-width update selectors, and the reflected IV readback operation. Register moves that can be represented as direct TCG loads/stores do not need helpers. Add only the side-effecting CRC helper implementation here. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v9 -> v10: - Mask variable-length CRC writes to CRCLEN<3:0>. - Add Richard's Reviewed-by tag. Changes v8 -> v9: - Split CRC selector operations into their own COP2 helper patch. - Expose per-operation helpers instead of a generic selector helper. - Add matching helper.h declarations with the helper implementation. --- target/mips/helper.h | 14 +++++ target/mips/tcg/octeon_crypto.c | 131 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 145 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index e2b83a1d19..e802f50fd6 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -25,6 +25,20 @@ DEF_HELPER_3(crc32, tl, tl, tl, i32) DEF_HELPER_3(crc32c, tl, tl, tl, i32) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 +/* Octeon COP2 selector operation helpers. */ +DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env) +DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_half, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_word, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_byte_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_half_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_word_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_dword, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_var, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_dword_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_var_reflect, void, env, i64) + /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) DEF_HELPER_4(swm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index df5b0449ae..811f36f46a 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -14,3 +14,134 @@ #include "crypto/sm4.h" #include "qemu/bitops.h" #include "qemu/host-utils.h" + +static inline uint32_t octeon_crc_reflect32_by_byte(uint32_t v) +{ + return bswap32(revbit32(v)); +} + +static uint32_t octeon_crc_state_reflect(const MIPSOcteonCryptoState *cryp= to) +{ + return octeon_crc_reflect32_by_byte(crypto->crc_iv); +} + +static void octeon_crc_set_state_reflect(MIPSOcteonCryptoState *crypto, + uint32_t state) +{ + crypto->crc_iv =3D octeon_crc_reflect32_by_byte(state); +} + +static void octeon_crc_update_normal(MIPSOcteonCryptoState *crypto, + uint64_t value, unsigned int bytes) +{ + uint32_t crc =3D crypto->crc_iv; + uint32_t poly =3D crypto->crc_poly; + + for (unsigned int i =3D 0; i < bytes; i++) { + uint8_t byte =3D value >> ((bytes - 1 - i) * 8); + + crc ^=3D (uint32_t)byte << 24; + for (int bit =3D 0; bit < 8; bit++) { + if (crc & 0x80000000U) { + crc =3D (crc << 1) ^ poly; + } else { + crc <<=3D 1; + } + } + } + + crypto->crc_iv =3D crc; +} + +static void octeon_crc_update_reflect(MIPSOcteonCryptoState *crypto, + uint64_t value, unsigned int bytes) +{ + uint32_t crc =3D octeon_crc_state_reflect(crypto); + uint32_t poly =3D bswap32(crypto->crc_poly); + + for (unsigned int i =3D 0; i < bytes; i++) { + uint8_t byte =3D value >> ((bytes - 1 - i) * 8); + + crc ^=3D byte; + for (int bit =3D 0; bit < 8; bit++) { + if (crc & 1U) { + crc =3D (crc >> 1) ^ poly; + } else { + crc >>=3D 1; + } + } + } + + octeon_crc_set_state_reflect(crypto, crc); +} + +uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env) +{ + return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv); +} + +void helper_octeon_cp2_mt_crc_write_iv_reflect(CPUMIPSState *env, + uint64_t value) +{ + env->octeon_crypto.crc_iv =3D + octeon_crc_reflect32_by_byte((uint32_t)value); +} + +void helper_octeon_cp2_mt_crc_write_byte(CPUMIPSState *env, uint64_t value) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 1); +} + +void helper_octeon_cp2_mt_crc_write_half(CPUMIPSState *env, uint64_t value) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 2); +} + +void helper_octeon_cp2_mt_crc_write_word(CPUMIPSState *env, uint64_t value) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 4); +} + +void helper_octeon_cp2_mt_crc_write_dword(CPUMIPSState *env, uint64_t valu= e) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 8); +} + +void helper_octeon_cp2_mt_crc_write_var(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + octeon_crc_update_normal(crypto, value, MIN(8U, crypto->crc_len & 0xf)= ); +} + +void helper_octeon_cp2_mt_crc_write_byte_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 1); +} + +void helper_octeon_cp2_mt_crc_write_half_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 2); +} + +void helper_octeon_cp2_mt_crc_write_word_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 4); +} + +void helper_octeon_cp2_mt_crc_write_dword_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 8); +} + +void helper_octeon_cp2_mt_crc_write_var_reflect(CPUMIPSState *env, + uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + octeon_crc_update_reflect(crypto, value, MIN(8U, crypto->crc_len & 0xf= )); +} --=20 2.54.0