From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427424; cv=none; d=zohomail.com; s=zohoarc; b=NQWerES/IhL9HTN7xl5IVzKHnnq91Mm0peGhnQG3osoTx+RCrJ7VxHoIIs5ydT46j1lBP9gewUzfKf1nYO8O4UsXznLnlEQlJ0PG7IP9tYpBLuAC6wfMqANQZCZ/OPSIac2BwVkHBeyiMKkzHH4Qgmu/BDLuuHdb476y7dvdauU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427424; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JKF4Q/fd29mnWV/NByXIaIABCsq7UsmokkILVWMv7cY=; b=PXRrMGrKeYkxMUD6UE96c4jClFJ4v5+rBcmjuRPtM3Es/vO2LHmiLsTwraABbfYPxrTMSatmzTlSAEfrF1PmNX4fyL1csEdPhZgCCzYjP3d6L6yVhNXBwQge9+pBW9HrbO9LahzzIIrzl5PglRvBAm2CiWTPwkLhkPmpd3FoJ38= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427424014158.1835279878777; Thu, 21 May 2026 22:23:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJ5-0002SJ-J5; Fri, 22 May 2026 01:20:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ0-0002PP-7R for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:19 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIIx-0001mB-0t for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:16 -0400 Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-484d3c0855aso2756215b6e.3 for ; Thu, 21 May 2026 22:20:14 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427214; x=1780032014; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JKF4Q/fd29mnWV/NByXIaIABCsq7UsmokkILVWMv7cY=; b=qu4K8T4UJUX7S5pmE6iCMWveT2hzCDifbUUyCA/e9jh7gow/8PtF+McCOsxeFam946 leWGQTK4F4OgVXSbC9Hw6PUqAnFL5+Bk9A3YZgc44it5kNK7lgm4x+etLXYkjco9LJbk jJ+4plplVBzyAVHlV7jmG5mDVBWddw6dYOmxS75LuPGVJHmqL/DpaWn4AlVkohVJk3+C CmuspGnKQXo7sXC8jQde+W2vrChmecBMSElsqEfhxqtLmhHi8aHp0qSFWtfZzFtmG3Ab QBcDz7kTUhSWV3eg3L2XxI1uk+9hXM+JjfPJvFSgSNqJkwbAtwpRgQtsnwAs8DaeNngx X3dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427214; x=1780032014; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=JKF4Q/fd29mnWV/NByXIaIABCsq7UsmokkILVWMv7cY=; b=kSroQBAU5PZaAjb/JrHJHKWRmKFLhTnr+x+iQwnC09MLvc+1o4OEKhasTa/4jXek8g wNc60BO6FW0gWJ7CrePnVswZXrdlEs7jKwdfrJ3ZuuvOw1B3KEeAIpqsFO2WmAI6YcbZ NsuoirjjPZ8LPYGf3Q6MZ2V9teHw3u2VWbDASvSKOiQHxuk2dPUbMDUejm9o8PRtC7qs MzvmnAoKpIEQlJ6A+Fu7+gLlrLPDMyzA+wTKrhCBMfiROhjGQajcBN/hQdLCKlakDEMu +olS4bdgnCV6nvOJVejSUbCFcWy7MBRTbFf97kUNaM4MGNOBt4/lRB7+Eql3zgOeurML rF5g== X-Gm-Message-State: AOJu0YyNF+RPV/NA6wcSS7O+UECkBsloGWp7oz+TwsU9IbqhR1vRN9Cl gUaquhE21ZjhrJLYqWcxan30B76l+RASyUtPVXo85wiJIoWXWcJ7431u X-Gm-Gg: Acq92OGX0AVJFfzjJV+KhVMP0qXRvN6hwZLSyX3SHLWEwwLKAX/Z0jiW/O4MaYQVE95 ISH316gRgJpE+lmSV4gx2HtSeOyGpHSu1145vrDNFjXMvvmLXCb6V/IJp2n5BhOiLIqAK7bC/IM nPPAPjB3zNeR4cyAy1ONa3rw3QBk+SfKnDvhS36L6wcKl7VW9KHa6GfCno7OfEyrGlV6k9EPBb4 B2MUfL9W3Rdi7qErLjsXY4eryjMIN67NUZxoY1OkNgre2vPc7DE9TbAkOGZIiPDjn8IDg4XM1QZ SkGHjeQ9Q1C3Olx8yZdx3FxVPmaLRvAHejNGow7tELJh1zu7XhXSWREfJKarqPVU2dKVjoPM33f OpcCfFEfddF0QX5Nlx1VFxKgzAz9jO2XtF7/ZHbdO9HAgxoGjVhUVGXZZf4Tugf2tRVb8fO7htP nn8WZp55Jm3vFi4SUfkwt6guZTtUUbuDDy+Db3PBfr+GpCQzf+E/Bw/tnHwBJXrKPHwEty03SZA w/yp41Wkw8cAOF1eehIqDlRdGP2/2C86cWiPuUu7uyAs5d601jgiggKHJHFoXDT+kXZfGVu1RVB ZJOMs6RwbF1UKA== X-Received: by 2002:a05:6808:23c2:b0:482:6b8a:33a6 with SMTP id 5614622812f47-4854a279b51mr1462253b6e.23.1779427213687; Thu, 21 May 2026 22:20:13 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:43 -0600 Subject: [PATCH v14 01/22] tcg: Optimize INDEX_op_mul[us]2 for 0 and 1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-1-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427426413154100 From: Richard Henderson Zero operands produce a zero high and low product. One operands produce a copy of the other operand and a zero or sign extension in the high half. Fold those cases during TCG optimization so wide-multiply idioms used by target translators can collapse before code generation. Signed-off-by: Richard Henderson --- Changes v9 -> v10: - Restore the original constant-fold output ordering. Changes v7 -> v8: - New patch from Richard Henderson's v7.5 multiplier rework. --- tcg/optimize.c | 92 ++++++++++++++++++++++++++++++++++++++----------------= ---- 1 file changed, 60 insertions(+), 32 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index b1abec69a5..fcdef25bee 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2173,45 +2173,73 @@ static bool fold_multiply2(OptContext *ctx, TCGOp *= op) { swap_commutative(op->args[0], &op->args[2], &op->args[3]); =20 - if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) { - uint64_t a =3D arg_const_val(op->args[2]); + if (arg_is_const(op->args[3])) { uint64_t b =3D arg_const_val(op->args[3]); - uint64_t h, l; - TCGArg rl, rh; + TCGArg rl =3D op->args[0]; + TCGArg rh =3D op->args[1]; TCGOp *op2; =20 - switch (op->opc) { - case INDEX_op_mulu2: - if (ctx->type =3D=3D TCG_TYPE_I32) { - l =3D (uint64_t)(uint32_t)a * (uint32_t)b; - h =3D (int32_t)(l >> 32); - l =3D (int32_t)l; - } else { - mulu64(&l, &h, a, b); - } - break; - case INDEX_op_muls2: - if (ctx->type =3D=3D TCG_TYPE_I32) { - l =3D (int64_t)(int32_t)a * (int32_t)b; - h =3D l >> 32; - l =3D (int32_t)l; - } else { - muls64(&l, &h, a, b); + if (arg_is_const(op->args[2])) { + uint64_t a =3D arg_const_val(op->args[2]); + uint64_t h, l; + + switch (op->opc) { + case INDEX_op_mulu2: + if (ctx->type =3D=3D TCG_TYPE_I32) { + l =3D (uint64_t)(uint32_t)a * (uint32_t)b; + h =3D (int32_t)(l >> 32); + l =3D (int32_t)l; + } else { + mulu64(&l, &h, a, b); + } + break; + case INDEX_op_muls2: + if (ctx->type =3D=3D TCG_TYPE_I32) { + l =3D (int64_t)(int32_t)a * (int32_t)b; + h =3D l >> 32; + l =3D (int32_t)l; + } else { + muls64(&l, &h, a, b); + } + break; + default: + g_assert_not_reached(); } - break; - default: - g_assert_not_reached(); - } =20 - rl =3D op->args[0]; - rh =3D op->args[1]; + /* The proper opcode is supplied by tcg_opt_gen_mov. */ + op2 =3D opt_insert_before(ctx, op, 0, 2); + tcg_opt_gen_movi(ctx, op, rl, l); + tcg_opt_gen_movi(ctx, op2, rh, h); + return true; + } =20 - /* The proper opcode is supplied by tcg_opt_gen_mov. */ - op2 =3D opt_insert_before(ctx, op, 0, 2); + if (b =3D=3D 0) { + op2 =3D opt_insert_before(ctx, op, 0, 2); + tcg_opt_gen_movi(ctx, op2, rl, 0); + tcg_opt_gen_movi(ctx, op, rh, 0); + return true; + } + if (b =3D=3D 1) { + op2 =3D opt_insert_before(ctx, op, 0, 2); + tcg_opt_gen_mov(ctx, op2, rl, op->args[2]); + + switch (op->opc) { + case INDEX_op_mulu2: + tcg_opt_gen_movi(ctx, op, rh, 0); + break; + case INDEX_op_muls2: + op->opc =3D INDEX_op_sar; + op->args[0] =3D rh; + op->args[1] =3D rl; + op->args[2] =3D + arg_new_constant(ctx, tcg_type_size(ctx->type) * 8 - 1= ); + break; + default: + g_assert_not_reached(); + } =20 - tcg_opt_gen_movi(ctx, op, rl, l); - tcg_opt_gen_movi(ctx, op2, rh, h); - return true; + return true; + } } return finish_folding(ctx, op); } --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427237; cv=none; d=zohomail.com; s=zohoarc; b=m9Qg48MeMn730BPOUofbhEsUFYskHCWXpeMISku6HU5Xo42/QHvl5/YeNuEkZlnOsottVxZlS+vNr0ZyNIMu3IyMimygjEmZYZ/1scNvP+L6Ib3z9a6Hht+BQAKc5MZH2Lrr32NxDYKYdMJ5iK0yopwfPYFxDRVyTsySzXYJCSw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427237; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=x0NUdarwlNBIbAV+0BMqGTTe4aMVplAxOCrABMuHx4A=; b=mBwZUz43I7BTeEJ9tDjzDDfJ1Gtx5ic7fEz7gkJaiNAjg+k47bKk9+3BJp2jzeV1KFMElgSRs7i4aZ2DTdTZxvf9hOG67jb6f0jje9W9WCPZOshyyZUL0yWeuzSjANR28bBJvyXQLaoduFZsPueKxwoWOZokWdOJzM6/FTGEDus= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427237562365.3350395694947; Thu, 21 May 2026 22:20:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJ4-0002RB-Sy; Fri, 22 May 2026 01:20:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ1-0002Q7-To for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:19 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIIz-0001mu-PA for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:19 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-7dbca22dbfeso3699622a34.1 for ; Thu, 21 May 2026 22:20:16 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427215; x=1780032015; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=x0NUdarwlNBIbAV+0BMqGTTe4aMVplAxOCrABMuHx4A=; b=lX9Z8iNByPq0Yh8tfbU10h2htdmV/cV1issCjF6FySZbqChYUbGqnAv7ztzn7g3wOz qX8o+bMTT71Fj4k/9a9ZsWiqeC/OcxpY1uci9zej5FaPkPwSRZcATPHMzDWAAV72FoGh eWfuohD6MG39iW4sdncDJk6LJglWnldTswW1ewvXh7z7wX/SMJgoIMN1d60fP5eP9Mp7 BJPsprR9Z2RpzffzKmhwLCUSf9ef7Kr5+F9DEMwPGgdqxXfQTG/iqGUCKQHxBxmW/AyG NAamiaMCrASsMPZHG99wCrh01573X37Q6nKsnKs4zF/XOUBQCSpXksZ3ooc2tCed1c1O W3zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427215; x=1780032015; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=x0NUdarwlNBIbAV+0BMqGTTe4aMVplAxOCrABMuHx4A=; b=Ui0wY4PoL8IThUPdUZq8u/phwe+L+iRYfqxxYDiErrdZV0MrNw+X6gADrMj7rTyjuq Ym9ukD2LYe6+VxsytIz1PUNyMHBi3hBYY6Iidln3t2mhAWcKzRikJyZajycWZ2vlQtvu fCDc3nfX7b0VjIFc5Qk28TjZRakcl/qP+WMamwbhughjjW2Z1+GdxMPFxeY/JNl+LNW0 tEE1xlpPlj+xHSMDMRquk+klfKilzTsoeHRrRmNqAlMaTuGcF4+0Leto8Wj77StMyPiV /KgjDAOEOM1fSnuVj1L94uqlt/l/cCOignD9lzf2gCGCCFbpawbGS6+EX57jTwbbUp6d rGxw== X-Gm-Message-State: AOJu0YyPhAPNTf0Yjayq1f37GbXhsEJAo1bOOTGgdJ8OU2k+uKHer6U5 XDV4k4yeyQIBmuCTVg8OcmtSm5O0BuYyptSWGCS9BVtR7OsGdikmeHoB X-Gm-Gg: Acq92OECC683osn6ZajxsSTzgLSMbhMlWXfvHkEe6R7u0hvIo5xvsVu8Sdhlr+NmJeN Hc604aCoiYESa+awYakcfD+zOeDWm293Ce1zquK0RzJbF7DgTsQST0/QEqkrwqSZndgquMgy0GE +7tm0Y5jwx5nZ6M/xJ9rnbcmZyTEX8TaFJUBDHZUf5wRZe/R0zfKlhW5dGX0aL/cZKyiHpmfJl7 eKSkFs8YE1mQMSv2o3514KVjg/oCHSGkNNYUeN2mSvxwp/65GtzHi5ZMpCuJTKVA4n+ApA2tb6q Yl7hPp+olTxeU5nm2ygzfoV6v0x2k1cKcZc8yYY5nox/Q4j5JiGbo6DAi3iBhHYazpteyYPAG/R DylMS1EjA+SY6h8grwNNmX16ZnfjHtYQJog7h3tL7qnGPfHQR9qRYCi7JIhFRqDwkDKsnMYKKSU eCqKQaVunEpSFCdKAvx/1Tbx6sJNLmuOkFJ71I2INzcIDdO68g1dwts7vCgZe/aQu7fQH+h8586 LFcsDtY5zujCTX/F/eUAGmiOJbcAGggd7sBQoZdTCQp3N9wuSyGB8hr+vl87ZNAlgtD X-Received: by 2002:a05:6808:23d2:b0:467:819:dc61 with SMTP id 5614622812f47-4854a29f503mr1222801b6e.23.1779427215037; Thu, 21 May 2026 22:20:15 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:44 -0600 Subject: [PATCH v14 02/22] target/mips: add Octeon COP2 crypto state MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-2-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=james.hilliard1@gmail.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427240018154100 Add the common architectural state needed by Octeon's selector-driven COP2 crypto interfaces. This includes storage for the base hash, AES, CRC, GFM, 3DES, KASUMI, and overlapping HSH/SHA512/SHA3/SNOW3G/ZUC selector windows. Keep selector values and helper-local aliasing logic out of the CPU state header so the state definition remains limited to architectural storage. Helper code uses the same register banks instead of adding non-architectural shadow state. Migrate the state in an Octeon-only subsection so non-Octeon CPU models do not grow migration data. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v10 -> v13: - Keep reflected GFM selectors mapped onto the architectural GFM state from the start instead of adding temporary reflected shadow fields. Changes v9 -> v10: - Drop non-architectural shared-mode, AES input/result split, GFM XOR, and ZUC/SNOW3G shadow state. - Model HSH/SHA512/SHA3/SNOW3G/ZUC overlap with the architectural HSH DAT/IV register banks. - Store CRCLEN as the architectural 4-bit state. Changes v8 -> v9: - Remove the MIPSOcteonCop2Sel enum; selector values are decoded by decodetree or kept local to helper plumbing. - Leave only COP2 state and migration data in this patch. Changes v7 -> v8: - Split COP2 crypto state and migration coverage out of the combined COP2 crypto core patch. --- target/mips/cpu.h | 21 +++++++++++++++++++++ target/mips/system/machine.c | 27 +++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 346713705a..2dad7f538f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -537,6 +537,25 @@ struct TCState { }; =20 struct MIPSITUState; +typedef struct MIPSOcteonCryptoState { + uint64_t hsh_dat[16]; + uint64_t hsh_iv[8]; + uint64_t sha3_dat24; + uint64_t des3_key[3]; + uint64_t des3_iv; + uint64_t des3_result; + uint64_t aes_resinp[2]; + uint64_t aes_iv[2]; + uint64_t aes_key[4]; + uint32_t crc_poly; + uint32_t crc_iv; + uint64_t gfm_mul[2]; + uint64_t gfm_resinp[2]; + uint16_t gfm_poly; + uint8_t aes_keylen; + uint8_t crc_len; +} MIPSOcteonCryptoState; + typedef struct CPUArchState { TCState active_tc; CPUMIPSFPUContext active_fpu; @@ -558,6 +577,8 @@ typedef struct CPUArchState { #define MSAIR_ProcID 8 #define MSAIR_Rev 0 =20 + MIPSOcteonCryptoState octeon_crypto; + /* * CP0 Register 0 */ diff --git a/target/mips/system/machine.c b/target/mips/system/machine.c index f988b3695b..77f576a25b 100644 --- a/target/mips/system/machine.c +++ b/target/mips/system/machine.c @@ -279,6 +279,32 @@ static const VMStateDescription mips_vmstate_octeon_mu= ltiplier =3D { } }; =20 +static const VMStateDescription mips_vmstate_octeon_crypto =3D { + .name =3D "cpu/octeon_crypto", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D mips_octeon_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_dat, MIPSCPU, 16), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_iv, MIPSCPU, 8), + VMSTATE_UINT64(env.octeon_crypto.sha3_dat24, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.des3_key, MIPSCPU, 3), + VMSTATE_UINT64(env.octeon_crypto.des3_iv, MIPSCPU), + VMSTATE_UINT64(env.octeon_crypto.des3_result, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_resinp, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_iv, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_key, MIPSCPU, 4), + VMSTATE_UINT32(env.octeon_crypto.crc_poly, MIPSCPU), + VMSTATE_UINT32(env.octeon_crypto.crc_iv, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_mul, MIPSCPU, 2), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_resinp, MIPSCPU, 2), + VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU), + VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU), + VMSTATE_UINT8(env.octeon_crypto.crc_len, MIPSCPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_mips_cpu =3D { .name =3D "cpu", .version_id =3D 21, @@ -396,6 +422,7 @@ const VMStateDescription vmstate_mips_cpu =3D { .subsections =3D (const VMStateDescription * const []) { &mips_vmstate_timer, &mips_vmstate_octeon_multiplier, + &mips_vmstate_octeon_crypto, NULL } }; --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427257; cv=none; d=zohomail.com; s=zohoarc; b=L6RugWSvkNOpwNLj+BJTCk2K5OtIhhgJdNqadAEDHeoYPsBIaxLBkYiADggmu53bxX5vwzh4jKIfE11GjfPuAyZYhjmTqVnCSXIs3soVIH3djCAZLyC8FHTNop+nqlJKG35jDve9YD9y5Yfr70ptMN+EG35+65JO6zKM3j4ZHSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427257; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=48Ai9CIUSaGzXZYONL1dAcOkXHUHQVK32aP2mmtN5aU=; b=VLNMnuWtanjAu5gIq0WBhqh5Vjaz6TlE6AOBIJQgO4nAM+iWMI8uway+5owuqvjBtMxcJpGKVeb0Lp3vZUvQwB4APtJ5oUQ+9qAttXJuvQTsP25pgiCW+q3/3GGoSYW9HgDwKS/Rd2IvlLiadTXnWWfjPuu9rGT+oVa6TJEMliY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427257845640.0494422767446; Thu, 21 May 2026 22:20:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJ6-0002Sx-1x; Fri, 22 May 2026 01:20:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ1-0002Pm-Pn for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:19 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIIz-0001nI-W8 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:19 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-485462d9290so549084b6e.1 for ; Thu, 21 May 2026 22:20:16 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427216; x=1780032016; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=48Ai9CIUSaGzXZYONL1dAcOkXHUHQVK32aP2mmtN5aU=; b=HWW4cmVkiVT3NdJ5JlU2oT8clQFy2tILz8DnM0rQr50D2AbewaRcOXJmZbvVlPexog o5e9V9a5qhNbYX/OcTl6RjYEotlAk5WddRsJNeBhSx591VNct/pOvP1b7jIZq8HDK0yO 8t7FRe8UMzWZcA2CjxsJ9oy+ySUHWDzOGsSYl+iUsiRikaJVPA9J/FaTXdX6daUpOSQ7 GdnBTieGJlBva+IZB6fSD/jowgpC1lhPcmfrPKYJ/nm2stiBhjRv1lvRiQU9bzwmJ+Ln He32x50OD9Sx0ArWl4z662IwRzv6+/ZuZr5u6TQF1I3BLGZjjt8uh4y1RUUWgB3iJJbo 4JvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427216; x=1780032016; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=48Ai9CIUSaGzXZYONL1dAcOkXHUHQVK32aP2mmtN5aU=; b=muMPYevn/GMLkaffmSD4aLCsSmXw5soHNuhJQt03Y1IwUmzICEbtnYHrUonUa3QyDr QnL5aFItFOjZZ7El9QsTZ8/CuOw7ouZITONeiYUAiFcAXxNbsvNTYIYCTHudHP5/CUEc JK7zQprmWN/atf6keY1N0/rLaKq//FthMksth8UJxwxkWJLVfVgUGmZ+eAzRdmzdMGxG QIkARplH+TEfiCImojG1RjCIc7QMBi1ugPRlZgnY9nq+7yKQFjx7NV4oC4p/ofQGpdj8 uPJWr9TlUubbJqqdcKcOEIJ6dcxUiNJYvS2NpGTw0kSsBb1JwCVfMrCIcEDCLGB+qxjl CTCw== X-Gm-Message-State: AOJu0Yw+1Gn8O5zh+KiN2gzvsQZ8W4/Npxa3pxcWau6zN/vXaihwhq/e 3gmdA2WSglQibRpMKNSJnzg0mLYowl4ZVOjsO2MI9j9vKRCBe/nCSBsb X-Gm-Gg: Acq92OEhqQfNFXOGE/7HWo47LG5fN+2NTJlleHi0gEAO26ulOKY6aJtoGk+LR3j+jIW CVoypgG2zFyJSjY2t3v1uu8ywoLrFTBGfUzgkjaVgey+srEEx+buxw8Z4f3dZKCE/UmlOyHdHnb Alg1/fvu8w9TwIPfWULvg2gI3y1yeSXM7NloNSfbXTsgWXLrUIl8RFBS42hgE4J+xzUX+GPDvig OzDPxu9SbUJMXprVLfRtyW2I/BEo/d2qSvOoJh8VJUiSOyAlCe4BHNSScJLf1XQF2HtB3dTZNOG s0U7gbhZOCz4SZOU2PI0rb3Czn99iFD5CvLejl7tb3Qw48tQxWADv5kdfcNu7SROwZRAHVIthyk 6/kWaMDo3eI71ZXeLGnXBdi8cl2imVR7U3rZlJ1dqeM832ODAvHFNGSmeOGajg0C3RiTuF55auH fcD3vixDQ+I2C4W5OcYe1OPIvjr6PM9YGsAGifhwsy2FL/Ya+nzbtkhHRQ6nK0AJWsBh21LptLk IqL0y1ncxv3S9HeayrMmP1pxTDIJsh2c1EA3XGtRIPokPnTeICcM0kJ62g6IhPkwhKx X-Received: by 2002:a05:6808:1520:b0:479:e826:ccdd with SMTP id 5614622812f47-4854aace3cemr964900b6e.5.1779427216016; Thu, 21 May 2026 22:20:16 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:45 -0600 Subject: [PATCH v14 03/22] target/mips: add Octeon COP2 crypto helper plumbing MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-3-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427260247158500 Add the Octeon COP2 crypto helper source file and build it with the MIPS TCG target. This provides the common compilation unit for the COP2 engine helpers. The instruction dispatch itself remains fully decoded by decodetree, and operation selectors call per-operation helpers rather than a common selector-dispatch helper. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v9 -> v10: - Remove shared-window selector constants and the shared-mode setter. Changes v8 -> v9: - Split helper plumbing out of the former monolithic COP2 helper patch. - Keep shared-window selector arithmetic local to octeon_crypto.c. --- target/mips/tcg/meson.build | 1 + target/mips/tcg/octeon_crypto.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index fff9cd6c7f..4ee359874a 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -18,6 +18,7 @@ mips_ss.add(files( 'lmmi_helper.c', 'msa_helper.c', 'msa_translate.c', + 'octeon_crypto.c', 'op_helper.c', 'rel6_translate.c', 'translate.c', diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c new file mode 100644 index 0000000000..df5b0449ae --- /dev/null +++ b/target/mips/tcg/octeon_crypto.c @@ -0,0 +1,16 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * MIPS Octeon crypto emulation helpers. + * + * Copyright (c) 2026 James Hilliard + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "crypto/aes.h" +#include "crypto/sm4.h" +#include "qemu/bitops.h" +#include "qemu/host-utils.h" --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427307; cv=none; d=zohomail.com; s=zohoarc; b=gpoDl+9UyYw058YTXvRs22pX8lZ6nWBsB90bxac9rssUdazILS6jGFjfhkrpcPU0+2EtyU+qmzcqVN0vREBYSIA/A4xcC1HEdc+jD4R6MNMAwxB149H0w44TtwsZdnwSICspOXkl9zkyUvlZ/vz0flgeHjTQ+q1vHFeC4fnHSHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427307; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=99YbXwU+QZjVpPSGzU0gdv9rBjyJynqi/nBLawDCdQk=; b=YDkBTTApILJF5fPvc2x3EFZ2PkZJmnYxBHvitdytbFtoOnk91TKfiyTO2Yw/SoXDp/gHqbwtCR3St6qpv+XWf8PVgWDv51dU2r4zm7Kbw81U78hMLCCWuAUgPfj7CbMLBxSttVoE5dHsu2Q3a9u1BPR43hLtvCb4hvv4pxTXSj0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427307362281.7325918850754; Thu, 21 May 2026 22:21:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJ7-0002T7-NL; Fri, 22 May 2026 01:20:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ4-0002RL-JK for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:22 -0400 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJ0-0001nO-GW for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:21 -0400 Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-482de4ef03aso4878695b6e.1 for ; Thu, 21 May 2026 22:20:18 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427217; x=1780032017; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=99YbXwU+QZjVpPSGzU0gdv9rBjyJynqi/nBLawDCdQk=; b=DtOAaxCtIXRjfR1T/L/p1sPoDzVn1P477aRC+oJ+DcIqjh+OyxDYnQ4amK5YGyK0yz OsuVnY2yKuq+mwMXo0XNlwTG3yELEaTfvOWr07VBB0Y5nehQ51b0oh2N/vBr5TA9MbmO 6TYZzOmqlT8R0I0swIK3ZsCCgMeXwMY+HI93oRSFGoZU71Dv5d6JA5WuGGW3iV2ffBIg 7ZGkPbPNZKpZWPsYWl6QS8dLTM5V6Vko2ljemv6ludiuD3gGo0wz5iO6HqQyR133wUTD tbfUODY3pySEoSIJth0tIUjtNavVU/mm08y2r6Oefm54xU24fSG11ffrdca8QcLDznAF v20g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427217; x=1780032017; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=99YbXwU+QZjVpPSGzU0gdv9rBjyJynqi/nBLawDCdQk=; b=EnBu7+3pFeIIZPnzUd6qMGJu9fpke+9XIqhHceqd//N5u0znS3r6wrIE/2hz3Lc8rF IPzPweIt+hldFZnmika8nDFwoj+FrEwmxHs01lMW//1qUuJXErz6NpuafIl/m4ON05ft nFdWYhmK/2ukCA/l/FyfXSZL+kr8kxbo9uhxzUmWTcj7/uf9x4+G4pmvF/QI4PiCZd3m 7675Bx8m2sst0zLbhFKOI/hAPRSF9Sv2JBw2cggCjP8DXb1cFcEkS0xBWNe7hyha1UWG xU65dSoE92hiVilJi3yfxlKvLJxANvP/FofWRuk0LxH7KWWi4PFHcRTOxsmKwSyHQXba OSRA== X-Gm-Message-State: AOJu0YxIF0mmv4mNUmYHjyUOsmYENYyP86s72jOwK6orIxHOHXaXeVmq N6KwVPsC37CHXWEgH+/vTQKEIiWWGXQ1xzm1vlBP8jXlIb4gPJ/qnuJl X-Gm-Gg: Acq92OF37AStpx67VUrm2+Szv8MS9UBpTVfIbB4kLHKu6DN+GhU4jMj2qXD4u76vvfU 2qGQj1Fcoi61CcuFuKLwXzxtd89jbG2y/dsWNdGx2zLBCJhCWt65s5y8lTxpIJupd3eEB5EgPze oUxWw/UCj1MpYCHjiQ0ziIAXx4hgoGigyf05ugA7IxlPZFLDg0zfU+jQITj1ni4snv2QP1D3vvp kgt1jAsjTmSL0M7pFCHfbbvLN19g1bs0g3k945iYQq81DG4xhHa/nqc3GEQ5ViBZlT/HsnXJr7r +ua63fsJhy87Wyv+1SqPPIS3q4CnQgqTVXDGBmTcdanSQUErxr/BCCKP9qOgYfeHTglSj6/AB3D clQWNODbT+hZebEiNfNPzJlvNJt5GGuKSWP5zKciiA9sOEBnC7EEtVnE40+iUj78tQPvtoq0zqv QIYdqNA1gaj96fuRR+Wovt2AO9L823WPpDBbfV3z3mEuUMNTLUKe2Dj1nMj3OeD3rAZ+phyl6A4 4G3knI8xhrRgRkuO1oRG95i8wOBxVebpS2XRwpWW2+Py9z8+4yIF92qQA1LZj4b70ktfXtfxApb DVw= X-Received: by 2002:a05:6808:6786:b0:463:a42c:503a with SMTP id 5614622812f47-4854ae802demr969507b6e.14.1779427217241; Thu, 21 May 2026 22:20:17 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:46 -0600 Subject: [PATCH v14 04/22] target/mips: add Octeon CRC COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-4-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427309227154100 Add helper support for the Octeon COP2 CRC register interface. This covers normal and reflected CRC state handling, byte/halfword/word/ doubleword/variable-width update selectors, and the reflected IV readback operation. Register moves that can be represented as direct TCG loads/stores do not need helpers. Add only the side-effecting CRC helper implementation here. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v9 -> v10: - Mask variable-length CRC writes to CRCLEN<3:0>. - Add Richard's Reviewed-by tag. Changes v8 -> v9: - Split CRC selector operations into their own COP2 helper patch. - Expose per-operation helpers instead of a generic selector helper. - Add matching helper.h declarations with the helper implementation. --- target/mips/helper.h | 14 +++++ target/mips/tcg/octeon_crypto.c | 131 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 145 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index e2b83a1d19..e802f50fd6 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -25,6 +25,20 @@ DEF_HELPER_3(crc32, tl, tl, tl, i32) DEF_HELPER_3(crc32c, tl, tl, tl, i32) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 +/* Octeon COP2 selector operation helpers. */ +DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env) +DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_half, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_word, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_byte_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_half_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_word_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_dword, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_var, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_dword_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_var_reflect, void, env, i64) + /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) DEF_HELPER_4(swm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index df5b0449ae..811f36f46a 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -14,3 +14,134 @@ #include "crypto/sm4.h" #include "qemu/bitops.h" #include "qemu/host-utils.h" + +static inline uint32_t octeon_crc_reflect32_by_byte(uint32_t v) +{ + return bswap32(revbit32(v)); +} + +static uint32_t octeon_crc_state_reflect(const MIPSOcteonCryptoState *cryp= to) +{ + return octeon_crc_reflect32_by_byte(crypto->crc_iv); +} + +static void octeon_crc_set_state_reflect(MIPSOcteonCryptoState *crypto, + uint32_t state) +{ + crypto->crc_iv =3D octeon_crc_reflect32_by_byte(state); +} + +static void octeon_crc_update_normal(MIPSOcteonCryptoState *crypto, + uint64_t value, unsigned int bytes) +{ + uint32_t crc =3D crypto->crc_iv; + uint32_t poly =3D crypto->crc_poly; + + for (unsigned int i =3D 0; i < bytes; i++) { + uint8_t byte =3D value >> ((bytes - 1 - i) * 8); + + crc ^=3D (uint32_t)byte << 24; + for (int bit =3D 0; bit < 8; bit++) { + if (crc & 0x80000000U) { + crc =3D (crc << 1) ^ poly; + } else { + crc <<=3D 1; + } + } + } + + crypto->crc_iv =3D crc; +} + +static void octeon_crc_update_reflect(MIPSOcteonCryptoState *crypto, + uint64_t value, unsigned int bytes) +{ + uint32_t crc =3D octeon_crc_state_reflect(crypto); + uint32_t poly =3D bswap32(crypto->crc_poly); + + for (unsigned int i =3D 0; i < bytes; i++) { + uint8_t byte =3D value >> ((bytes - 1 - i) * 8); + + crc ^=3D byte; + for (int bit =3D 0; bit < 8; bit++) { + if (crc & 1U) { + crc =3D (crc >> 1) ^ poly; + } else { + crc >>=3D 1; + } + } + } + + octeon_crc_set_state_reflect(crypto, crc); +} + +uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env) +{ + return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv); +} + +void helper_octeon_cp2_mt_crc_write_iv_reflect(CPUMIPSState *env, + uint64_t value) +{ + env->octeon_crypto.crc_iv =3D + octeon_crc_reflect32_by_byte((uint32_t)value); +} + +void helper_octeon_cp2_mt_crc_write_byte(CPUMIPSState *env, uint64_t value) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 1); +} + +void helper_octeon_cp2_mt_crc_write_half(CPUMIPSState *env, uint64_t value) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 2); +} + +void helper_octeon_cp2_mt_crc_write_word(CPUMIPSState *env, uint64_t value) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 4); +} + +void helper_octeon_cp2_mt_crc_write_dword(CPUMIPSState *env, uint64_t valu= e) +{ + octeon_crc_update_normal(&env->octeon_crypto, value, 8); +} + +void helper_octeon_cp2_mt_crc_write_var(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + octeon_crc_update_normal(crypto, value, MIN(8U, crypto->crc_len & 0xf)= ); +} + +void helper_octeon_cp2_mt_crc_write_byte_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 1); +} + +void helper_octeon_cp2_mt_crc_write_half_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 2); +} + +void helper_octeon_cp2_mt_crc_write_word_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 4); +} + +void helper_octeon_cp2_mt_crc_write_dword_reflect(CPUMIPSState *env, + uint64_t value) +{ + octeon_crc_update_reflect(&env->octeon_crypto, value, 8); +} + +void helper_octeon_cp2_mt_crc_write_var_reflect(CPUMIPSState *env, + uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + octeon_crc_update_reflect(crypto, value, MIN(8U, crypto->crc_len & 0xf= )); +} --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427418; cv=none; d=zohomail.com; s=zohoarc; b=fOAPDnOh/LcljyTA4Zqbu5nxLMJLHzWg2uW4wFXM+jTZoFcwPR5EXv4rbRhrX2TAasfbb3fN7w9QbxXT+NGlAy9Sm2hfs1+Ex2SG7MjJupzdzXBymeuV5QSnIKcNYx3WJmlKeK7XCHigqHF2Eh73LDZY+qeB4ENXxlvF5bmXZcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427418; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hiKG7vqkKtjgPdKX+1200Dw0BsCoKa6VofI0vBywP+g=; b=E8C+WQyWUczbRBSIAo6YLPM2jBzu48YnVcG7LES8NnRt77EUqu/VUpVKBlRykozczmutRc+rtrCgtL1UXiTQChdHefR2b7PfDQO2tG6ZxlupzPsec3NO/RoO0gKMcRmtif/fm4sJgJ9FoZC6oZg+45qxkHtxQuPd1aGqsqPDDZs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177942741828575.6570901248167; Thu, 21 May 2026 22:23:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJA-0002VQ-6C; Fri, 22 May 2026 01:20:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ6-0002T0-72 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:25 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJ1-0001p4-Pm for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:23 -0400 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-479d85152c9so2652832b6e.2 for ; Thu, 21 May 2026 22:20:19 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427218; x=1780032018; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hiKG7vqkKtjgPdKX+1200Dw0BsCoKa6VofI0vBywP+g=; b=LWWEe/XL8NkwnkJKgX6yvpY9l3Gd9jozPmGnldEHgt44fZpgEJC1MjV1XqRCm1lgIt sfTUsUx4mRj6JorXKv32chu+tEJ9+xas/1J7ymSkqmDNCwK8vNcnVjlEApaJ9t7GeIp8 K+MjNIUprkiCWoBE3RLso00OHDdHr3ggLG0ToyF4vX4ZYuA+VCcN35l52ILNU1pu7nnf gYABjAzTZ8RW7tPrpoubmbDRLTXLkZK8SUTOEi9eC77KocNeMocxrpwtdtiWI+bXocNm xdHzAQ6YQK4ijjX3n7PuO2o8pVec7uyOD1GuqMV8jGvY2fWCIMeN+CRN+SvahHeN9hH5 QO+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427218; x=1780032018; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=hiKG7vqkKtjgPdKX+1200Dw0BsCoKa6VofI0vBywP+g=; b=Kvqk4xqh4td3lXUTZXNrV3A016PjUO8L7+0h24vC0XUXsoiJbwIrDZIXfeRRCQNoUf 6M65fbnJRZ65cE+1VRtD6YUPqeiH28SmRgkxbAN0yan7pLQsrrHz8eJkaJ6F4NYZ0qwV vv9K3f+cYz0szS/xxsYZbqWADpXzhuxlSrDpkcZWE9xKluzSQTzuFPbKqK9KZLiTDKDp bHWq/3SvjNqrnZRNBNNVld0y/HdEBHxIC5SJxKI68Fa7igHvZvwheGp1Fe1kqBYGSO73 AgHqaarlMwZ2iBCWHUUP+jYjzvKowdYHEg2Y59su2M/bHe5IQxPo6h3nq2kgQa7c9Sfy Wa1Q== X-Gm-Message-State: AOJu0YyFYUGUAvUR5fl3XaG9EUX/c18ScHoyXOGkfaVTliHnG/KVY8tr Sg5DgZfhEO6deAPCdWm/al30zXSIyOfK07/XC5CGfX+tlhW02hzYy3UV X-Gm-Gg: Acq92OGWR4U+6WHM76ckKNZGvTCppQ6ejpF8Tl89QrUsXFFmpDV+U1Gm+/0ULvRh2oT mymYUXKHDy60ZJ4F+bZvb9H+z/8MUlV/9pk/A02T/h4oJlp8Nwo8xXhmy74SQATza8TGo918j9Q IdyaDldIvVDhEFd6kRWYTkI9ZzJKX82qbEc+MTAs94tJJYy50aU/BgqJqs4Uk705a+0rLTQ9qEF ygGpQzZqHPUZmgWUIcoaP0uxn0JT9nrT34n5XYNVsM+bm4wf2L5j/Z6wKOdmfVY6vs/WjVcLQ0k 85RnqaaxX3Pyr25mx4h0gRYA5dy17hJ+OrF9gu1CZpOcg8XyhxdRaA/9OihPOqrpNPlwBO7uTqB HFlhZ8Vpy1/3lkMdACbvXqntUEvae7IjgABNcEwY1KloJ4Lw0ScA8UohR/uXjeW0aIvEudO2DhV t+jfNUP+9hPInuC4/FvHCrB3JCY1KGOiK7O2gqCGE3ShBy8Qa+WLOHz2JFCOzxawhknojB93JJq NvZk+qEvxTyo8bPGoe0vahGF8RdTeLc5MzJzJt86+a4VsepnkxMW8LL9T3hP8wRDBYHmcGwaB0c Vdo= X-Received: by 2002:a05:6808:f8f:b0:485:29ad:d1b2 with SMTP id 5614622812f47-4854a3afa53mr1284535b6e.34.1779427218573; Thu, 21 May 2026 22:20:18 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:47 -0600 Subject: [PATCH v14 05/22] target/mips: add Octeon GFM COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-5-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427420362154100 Add helper support for the Octeon GFM carryless multiply selectors. This models the normal and reflected multiplication paths, including the XOR-and-multiply forms that update the result/input state used by Octeon crypto code. Reflected selectors operate on the architectural GFM register bank using bit-reflected register transfers rather than a separate shadow state. Keep the 64-bit UIA2 reduction path used by SNOW3G F9. Signed-off-by: James Hilliard --- Changes v10 -> v13: - Map reflected GFM selectors directly onto the architectural GFM state in this patch instead of adding temporary reflected shadow state. - Preserve the 64-bit UIA2 GFM reduction path used by SNOW3G F9. Changes v8 -> v9: - Split GFM selector operations into their own COP2 helper patch. - Expose per-operation helpers instead of a generic selector helper. - Add matching helper.h declarations with the helper implementation. --- target/mips/helper.h | 10 +++ target/mips/tcg/octeon_crypto.c | 139 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 149 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index e802f50fd6..9a6702ff60 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -27,6 +27,10 @@ DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32= , i32, i32) =20 /* Octeon COP2 selector operation helpers. */ DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env) +DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect0, i64, env) +DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect1, i64, env) +DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect0, i64, env) +DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect1, i64, env) DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_half, void, env, i64) @@ -38,6 +42,12 @@ DEF_HELPER_2(octeon_cp2_mt_crc_write_dword, void, env, i= 64) DEF_HELPER_2(octeon_cp2_mt_crc_write_var, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_dword_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_var_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect0, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_gfm_mul_reflect1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_gfm_xor0_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_gfm_xor0, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 811f36f46a..b22474574c 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -11,6 +11,7 @@ #include "internal.h" #include "exec/helper-proto.h" #include "crypto/aes.h" +#include "crypto/clmul.h" #include "crypto/sm4.h" #include "qemu/bitops.h" #include "qemu/host-utils.h" @@ -75,11 +76,149 @@ static void octeon_crc_update_reflect(MIPSOcteonCrypto= State *crypto, octeon_crc_set_state_reflect(crypto, crc); } =20 +static void octeon_gfm_mul(const uint64_t x[2], const uint64_t y[2], + uint16_t poly, uint64_t out[2]) +{ + uint64_t zh =3D 0, zl =3D 0; + uint64_t vh =3D y[0], vl =3D y[1]; + uint64_t rh =3D (uint64_t)poly << 48; + int i; + + /* + * Keep the reflected-shift formulation used by Octeon software: the + * selector polynomial is pre-positioned at the top of the high word b= efore + * each carry reduction. + */ + for (i =3D 0; i < 128; i++) { + bool bit; + bool lsb; + + if (i < 64) { + bit =3D (x[0] >> (63 - i)) & 1; + } else { + bit =3D (x[1] >> (127 - i)) & 1; + } + if (bit) { + zh ^=3D vh; + zl ^=3D vl; + } + + lsb =3D vl & 1; + vl =3D (vh << 63) | (vl >> 1); + vh >>=3D 1; + if (lsb) { + vh ^=3D rh; + } + } + + out[0] =3D zh; + out[1] =3D zl; +} + +static uint64_t octeon_gfm_reduce64(Int128 product, uint8_t poly) +{ + uint64_t lo =3D int128_getlo(product); + uint64_t hi =3D int128_gethi(product); + + while (hi) { + int bit =3D 63 - clz64(hi); + + hi ^=3D 1ULL << bit; + lo ^=3D (uint64_t)poly << bit; + if (bit > 56) { + hi ^=3D (uint64_t)poly >> (64 - bit); + } + } + + return lo; +} + +static void octeon_gfm_mul64_uia2(const uint64_t x[2], const uint64_t y[2], + uint8_t poly, uint64_t out[2]) +{ + /* + * SNOW3G UIA2 uses the GFM datapath as a reflected 64-bit multiply in + * the low half of the 128-bit register pair. + */ + uint64_t vx =3D revbit64(x[1]); + uint64_t vy =3D revbit64(y[0]); + Int128 product =3D clmul_64(vx, vy); + uint64_t res =3D octeon_gfm_reduce64(product, revbit32(poly) >> 24); + + out[0] =3D 0; + out[1] =3D revbit64(res); +} + uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env) { return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv); } =20 +uint64_t helper_octeon_cp2_mf_gfm_mul_reflect0(CPUMIPSState *env) +{ + return revbit64(env->octeon_crypto.gfm_mul[0]); +} + +uint64_t helper_octeon_cp2_mf_gfm_mul_reflect1(CPUMIPSState *env) +{ + return revbit64(env->octeon_crypto.gfm_mul[1]); +} + +uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect0(CPUMIPSState *env) +{ + return revbit64(env->octeon_crypto.gfm_resinp[0]); +} + +uint64_t helper_octeon_cp2_mf_gfm_resinp_reflect1(CPUMIPSState *env) +{ + return revbit64(env->octeon_crypto.gfm_resinp[1]); +} + +void helper_octeon_cp2_mt_gfm_mul_reflect0(CPUMIPSState *env, uint64_t val= ue) +{ + env->octeon_crypto.gfm_mul[0] =3D revbit64(value); +} + +void helper_octeon_cp2_mt_gfm_mul_reflect1(CPUMIPSState *env, uint64_t val= ue) +{ + env->octeon_crypto.gfm_mul[1] =3D revbit64(value); +} + +void helper_octeon_cp2_mt_gfm_xor0_reflect(CPUMIPSState *env, uint64_t val= ue) +{ + env->octeon_crypto.gfm_resinp[0] ^=3D revbit64(value); +} + +void helper_octeon_cp2_mt_gfm_xor0(CPUMIPSState *env, uint64_t value) +{ + env->octeon_crypto.gfm_resinp[0] ^=3D value; +} + +void helper_octeon_cp2_mt_gfm_xormul1_reflect(CPUMIPSState *env, + uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->gfm_resinp[1] ^=3D revbit64(value); + octeon_gfm_mul(crypto->gfm_resinp, crypto->gfm_mul, crypto->gfm_poly, + crypto->gfm_resinp); +} + +void helper_octeon_cp2_mt_gfm_xormul1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->gfm_resinp[1] ^=3D value; + if (crypto->gfm_poly <=3D 0xff && crypto->gfm_mul[1] =3D=3D 0 && + crypto->gfm_resinp[0] =3D=3D 0) { + octeon_gfm_mul64_uia2(crypto->gfm_resinp, crypto->gfm_mul, + crypto->gfm_poly, crypto->gfm_resinp); + } else { + octeon_gfm_mul(crypto->gfm_resinp, crypto->gfm_mul, crypto->gfm_po= ly, + crypto->gfm_resinp); + } +} + void helper_octeon_cp2_mt_crc_write_iv_reflect(CPUMIPSState *env, uint64_t value) { --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427418; cv=none; d=zohomail.com; s=zohoarc; b=ezKJ8fSLjeSrXRvwcf6WNnjhPIrMmQ6BM3+2WF3ScZy5BKT6qgTM4KJLMSnvd6iNmzl/apzIREicU7zYEUk5d4L6npNhLQGzT76/EcQ4dfjX7mz/Q2qOQyX/hoC1xPoCV+8lraezDp+6UMtLuaAgwt8Mgl1g8z7iZalJsIUJJaE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427418; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qd1JecVeUCnnJeorVMFX3xhJOlLs9zkGyq9ooA19Irc=; b=JfJScAigrESUFnaL+zMt4fkTtVnu5Mbqi53vpVDYgtrdoh0Vj/cOFeWJd0P8QhZ8TRP1T0PaauLcPNFfKEiwM9njOOSJIHagDdL1/IdQiVLEWOaXVqgMt8RFvxZbibefjaRYZHIpr36IpSMA8R/zlBv0FDV/s2Cy9gKtwR/4qNg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177942741810440.55358256511272; Thu, 21 May 2026 22:23:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJA-0002Xf-UU; Fri, 22 May 2026 01:20:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ6-0002T3-AP for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:25 -0400 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJ3-0001r6-FV for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:24 -0400 Received: by mail-oi1-x232.google.com with SMTP id 5614622812f47-4855562f32eso5091b6e.2 for ; Thu, 21 May 2026 22:20:20 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427220; x=1780032020; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qd1JecVeUCnnJeorVMFX3xhJOlLs9zkGyq9ooA19Irc=; b=l98AEtRe1Wqb01YPlOaSgk9HzhbIDn4bczsyKsoqSsI28bD2S98WNqc+0im/yGDHqX 3UUJ5eWgW2zqzjhddcGWZay+Fqi2fp8TYbbBq4ODpvoYUwjib7kYIe0Q0W4vq1FHmtWB I+cEDUnVs+u7EZHFlgStjQJf2lJy+OwcpAbJ4p3Jap97SqhSd5wGfLBDQLV9jS/lG48B Sp6QMoDJVGYhvCqFuWZw2b/MVSYHHFcbAKJkyvNoihXBYvGka31MlCFVC6UE6U7XsGJN G9Cuo6oVohlyhVOKYZEmEVZCD9JWMmw/YJ0OhuW4DzzjeeEYbSaWl+cEAc4UPlnhSYaE xOeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427220; x=1780032020; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qd1JecVeUCnnJeorVMFX3xhJOlLs9zkGyq9ooA19Irc=; b=OY8Eg9Qu83zXTvpA0txIWud+KddcgDfGgn1L5sUc1vNA53muF5bEA/7XheWYAGimHB ydhUK/ExandCWI+xJjiDE/nNamlXnRkfe69ca0eFl+E8GGKSvdUQkeubPrCOyv+76Hlc xEZnK6V7GLMKBA1iDO0VsedfEN0d7/O2gAo5hxKtQj6SKtSWhmdxigiHdhe7rxCtM7Eh LjxH8paAeGrGs1GpiehxlZodx7Eavnw92dOqJ2YU4n3vgkgi9oU+wVddhtu8prfsM4vo tmBrSh6gpwLVGCE3D/VEgy36cyC2cbDXFTfeJKfbiltuTFPGNTW6xN0RH2C3pF+UrKvI 4J1Q== X-Gm-Message-State: AOJu0Yx1fq+sSnspkQ446vrqCN0HBz0c/IgNvX2ZzrmdNYWb+gvui7NE +2H/9sS/hOst8Rk9c6LGMQPDN+iuYaFBI8y8/59Tu5Ui/p0I6qa77WEX X-Gm-Gg: Acq92OFTnTA3DDkNeFexf/yZvo6wRSjxclOM6gRF7BMtSQo56kjWfl5b2rheVAaLL4w pptRGM+Y8o96u+i6LcEYAEIJwMiuuTywHaea+Dg39/l90brrT3o3fXKzejtqK8UWQBNHMY0IbyX B0vIuNXHS6kaRCbD+3yUHKwDPmg7TM1I62n7mfOZdDy2ELTrTcv0oJ7XwdjG8yC+s+pghuTNMtW TqXuBnn8IfmFfiV9i2qh6y6mogd4Ain6ddoIryx6R4uQB3AYeoxLL/9LuQ3nS4JK1MgAw6QOIp9 BgRxTpWujTYg/OZMfdtrnxdt+SZy15EmyOGv/586Lai/n/EKTvvd4CmPGWEL5o3+k+4jn0Z/Ab+ ZGpYy1Gbavxpe/N/sPCT2q1tc6GzYD9oBvgGKtjR3nVxbHv3V8mKJh3bJtBfd9v3rgjht+uib9O qDg7Yl3myEOji4WPjlkYtuszTIeClh7MbammPsrKFjfZOQlTkDCz+r9ARLo5RpaRJoV7CVuU8QB URbP+DPL82E6Q8lLZyxnic4hMA9qOPDJxpqpgdWF3tygYd5TcscgE4SqR38wuxTFHIVaRW6NoXd ZqE+4O6MVzxh2w== X-Received: by 2002:a05:6808:1787:b0:485:542:f905 with SMTP id 5614622812f47-4854a0dfaa5mr1093919b6e.16.1779427219854; Thu, 21 May 2026 22:20:19 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:48 -0600 Subject: [PATCH v14 06/22] target/mips: add Octeon SHA3 COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-6-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427418456158500 Add the Octeon SHA3 register-window state and helper operations. Keep the shared HSH/SHA3/SHA512 write path coherent, model the dedicated 25-lane Keccak state, and implement the Keccak-f[1600] permutation for the STARTOP selector. The shared selector window still uses explicit selector-position arithmetic internally because multiple COP2 engines alias the same numeric window. Individual DMFC2/DMTC2 instruction decode stays outside the helper implementation. Signed-off-by: James Hilliard --- Changes v8 -> v9: - Split SHA3 selector operations into their own COP2 helper patch. - Replace generic selector dispatch with per-operation SHA3 helpers. - Use helper-local selector constants for shared-window position logic. - Add matching helper.h declarations with the helper implementation. Changes v5 -> v6: - Rename SHA3 DAT15 selector aliases with MF/MT direction suffixes. Changes v1 -> v2: - Use switch ranges and g_assert_not_reached() for SHA3 selector position decoding. (suggested by Philippe Mathieu-Daud=C3=A9) - Add selector dispatch updates in octeon_translate.c after moving COP2 decode out of translate.c. (suggested by Philippe Mathieu-Daud=C3=A9) --- target/mips/helper.h | 22 +++++ target/mips/tcg/octeon_crypto.c | 172 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 194 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 9a6702ff60..d1ec75eaff 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -27,6 +27,7 @@ DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32,= i32, i32) =20 /* Octeon COP2 selector operation helpers. */ DEF_HELPER_1(octeon_cp2_mf_crc_iv_reflect, i64, env) +DEF_HELPER_1(octeon_cp2_mf_sha3_dat24, i64, env) DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect0, i64, env) DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect1, i64, env) DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect0, i64, env) @@ -48,6 +49,27 @@ DEF_HELPER_2(octeon_cp2_mt_gfm_xor0_reflect, void, env, = i64) DEF_HELPER_2(octeon_cp2_mt_gfm_xor0, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_gfm_xormul1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_dat24, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_dat15, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat0, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat2, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat3, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat4, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat5, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat6, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat7, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat8, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat9, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat10, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat11, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat12, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat13, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat14, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat15, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat16, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_xordat17, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sha3_startop, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index b22474574c..b3b88ce018 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -16,6 +16,8 @@ #include "qemu/bitops.h" #include "qemu/host-utils.h" =20 +#define OCTEON_SHA3_DAT15 15 + static inline uint32_t octeon_crc_reflect32_by_byte(uint32_t v) { return bswap32(revbit32(v)); @@ -149,11 +151,129 @@ static void octeon_gfm_mul64_uia2(const uint64_t x[2= ], const uint64_t y[2], out[1] =3D revbit64(res); } =20 +static const uint64_t octeon_sha3_round_constants[24] =3D { + 0x0000000000000001ULL, 0x0000000000008082ULL, + 0x800000000000808aULL, 0x8000000080008000ULL, + 0x000000000000808bULL, 0x0000000080000001ULL, + 0x8000000080008081ULL, 0x8000000000008009ULL, + 0x000000000000008aULL, 0x0000000000000088ULL, + 0x0000000080008009ULL, 0x000000008000000aULL, + 0x000000008000808bULL, 0x800000000000008bULL, + 0x8000000000008089ULL, 0x8000000000008003ULL, + 0x8000000000008002ULL, 0x8000000000000080ULL, + 0x000000000000800aULL, 0x800000008000000aULL, + 0x8000000080008081ULL, 0x8000000000008080ULL, + 0x0000000080000001ULL, 0x8000000080008008ULL, +}; + +static const uint8_t octeon_sha3_rotation_constants[24] =3D { + 1, 3, 6, 10, 15, 21, 28, 36, 45, 55, 2, 14, + 27, 41, 56, 8, 25, 43, 62, 18, 39, 61, 20, 44, +}; + +static const uint8_t octeon_sha3_pi_lanes[24] =3D { + 10, 7, 11, 17, 18, 3, 5, 16, 8, 21, 24, 4, + 15, 23, 19, 13, 12, 2, 20, 14, 22, 9, 6, 1, +}; + +static uint64_t octeon_sha3_reg_to_lane(uint64_t value) +{ + /* + * The COP2 register interface is consumed by big-endian MIPS code as + * 64-bit register values, while Keccak lanes are byte-little-endian. + */ + return bswap64(value); +} + +static uint64_t octeon_sha3_lane_to_reg(uint64_t value) +{ + return bswap64(value); +} + +static uint64_t octeon_sha3_get_lane(MIPSOcteonCryptoState *crypto, + unsigned int index) +{ + if (index < 16) { + return octeon_sha3_reg_to_lane(crypto->hsh_dat[index]); + } + if (index < 24) { + return octeon_sha3_reg_to_lane(crypto->hsh_iv[index - 16]); + } + return octeon_sha3_reg_to_lane(crypto->sha3_dat24); +} + +static void octeon_sha3_set_lane(MIPSOcteonCryptoState *crypto, + unsigned int index, uint64_t value) +{ + value =3D octeon_sha3_lane_to_reg(value); + if (index < 16) { + crypto->hsh_dat[index] =3D value; + } else if (index < 24) { + crypto->hsh_iv[index - 16] =3D value; + } else { + crypto->sha3_dat24 =3D value; + } +} + +static void octeon_sha3_permute(MIPSOcteonCryptoState *crypto) +{ + uint64_t state[25]; + + for (int i =3D 0; i < 25; i++) { + state[i] =3D octeon_sha3_get_lane(crypto, i); + } + + for (int round =3D 0; round < 24; round++) { + uint64_t bc[5]; + uint64_t temp; + + for (int x =3D 0; x < 5; x++) { + bc[x] =3D state[x] ^ state[5 + x] ^ state[10 + x] ^ + state[15 + x] ^ state[20 + x]; + } + for (int x =3D 0; x < 5; x++) { + temp =3D bc[(x + 4) % 5] ^ rol64(bc[(x + 1) % 5], 1); + for (int y =3D 0; y < 25; y +=3D 5) { + state[y + x] ^=3D temp; + } + } + + temp =3D state[1]; + for (int i =3D 0; i < 24; i++) { + uint64_t next =3D state[octeon_sha3_pi_lanes[i]]; + + state[octeon_sha3_pi_lanes[i]] =3D + rol64(temp, octeon_sha3_rotation_constants[i]); + temp =3D next; + } + + for (int y =3D 0; y < 25; y +=3D 5) { + for (int x =3D 0; x < 5; x++) { + bc[x] =3D state[y + x]; + } + for (int x =3D 0; x < 5; x++) { + state[y + x] =3D bc[x] ^ ((~bc[(x + 1) % 5]) & bc[(x + 2) = % 5]); + } + } + + state[0] ^=3D octeon_sha3_round_constants[round]; + } + + for (int i =3D 0; i < 25; i++) { + octeon_sha3_set_lane(crypto, i, state[i]); + } +} + uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env) { return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv); } =20 +uint64_t helper_octeon_cp2_mf_sha3_dat24(CPUMIPSState *env) +{ + return env->octeon_crypto.sha3_dat24; +} + uint64_t helper_octeon_cp2_mf_gfm_mul_reflect0(CPUMIPSState *env) { return revbit64(env->octeon_crypto.gfm_mul[0]); @@ -219,6 +339,58 @@ void helper_octeon_cp2_mt_gfm_xormul1(CPUMIPSState *en= v, uint64_t value) } } =20 +void helper_octeon_cp2_mt_sha3_dat24(CPUMIPSState *env, uint64_t value) +{ + env->octeon_crypto.sha3_dat24 =3D value; +} + +void helper_octeon_cp2_mt_sha3_dat15(CPUMIPSState *env, uint64_t value) +{ + env->octeon_crypto.hsh_dat[OCTEON_SHA3_DAT15] =3D value; +} + +static void octeon_sha3_xordat(MIPSOcteonCryptoState *crypto, + unsigned int index, uint64_t value) +{ + uint64_t lane =3D octeon_sha3_get_lane(crypto, index); + + octeon_sha3_set_lane(crypto, index, + lane ^ octeon_sha3_reg_to_lane(value)); +} + +#define OCTEON_SHA3_XORDAT_HELPER(N) \ +void helper_octeon_cp2_mt_sha3_xordat ## N(CPUMIPSState *env, uint64_t val= ue) \ +{ \ + octeon_sha3_xordat(&env->octeon_crypto, N, value); \ +} +OCTEON_SHA3_XORDAT_HELPER(0) +OCTEON_SHA3_XORDAT_HELPER(1) +OCTEON_SHA3_XORDAT_HELPER(2) +OCTEON_SHA3_XORDAT_HELPER(3) +OCTEON_SHA3_XORDAT_HELPER(4) +OCTEON_SHA3_XORDAT_HELPER(5) +OCTEON_SHA3_XORDAT_HELPER(6) +OCTEON_SHA3_XORDAT_HELPER(7) +OCTEON_SHA3_XORDAT_HELPER(8) +OCTEON_SHA3_XORDAT_HELPER(9) +OCTEON_SHA3_XORDAT_HELPER(10) +OCTEON_SHA3_XORDAT_HELPER(11) +OCTEON_SHA3_XORDAT_HELPER(12) +OCTEON_SHA3_XORDAT_HELPER(13) +OCTEON_SHA3_XORDAT_HELPER(14) +OCTEON_SHA3_XORDAT_HELPER(15) +OCTEON_SHA3_XORDAT_HELPER(16) +OCTEON_SHA3_XORDAT_HELPER(17) +#undef OCTEON_SHA3_XORDAT_HELPER + +void helper_octeon_cp2_mt_sha3_startop(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + (void)value; + octeon_sha3_permute(crypto); +} + void helper_octeon_cp2_mt_crc_write_iv_reflect(CPUMIPSState *env, uint64_t value) { --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427338; cv=none; d=zohomail.com; s=zohoarc; b=TmeD6gQsFFwTreEoPc3zJdpYojeqv5up+ENc0+BA0B6bV7R0BprHLO34KuOUrC8QkPScBtBTEBqGpU7HW5aFgKsAvzwSpogJeE9lYkgIQba6ffva4392twg14wn+UpNLpn9mBig2rmtWZaj3mA2CdghMloc1mqMAG+plNDmVsMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427338; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Lb0OvF7hQ6PiNdrSYpxR44n5ZueReZ1PaD49+fWM2z8=; b=XA+od6l8hEmZlUnuNwMEPC2FeZGdkx0SN1bUCqbTvXQDy1LwE0TxTVcklvl+kQjsnephxq5RIr703QRLzoGbkNM6G+yYfG97/6A1Uuc9ROyJi006Ezje8Q37Z1Hv0tvxEo4wVu7n90OiIgZMf1llgSjBDeDSTqh0tYXwHPTAM7E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427338243718.6777566731644; Thu, 21 May 2026 22:22:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJA-0002Xb-Ni; Fri, 22 May 2026 01:20:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ8-0002US-GO for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:26 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJ4-0001rE-Kb for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:26 -0400 Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-4824b15c19eso5791910b6e.2 for ; Thu, 21 May 2026 22:20:22 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427221; x=1780032021; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Lb0OvF7hQ6PiNdrSYpxR44n5ZueReZ1PaD49+fWM2z8=; b=Nf5fKqO3J0rz6uKBLDe/DNPzRZLNiWqbBmINTdrf2VF/kYkX4RYGghNSgZb69jihIQ XhjkK2b2nI5oBiviHkWgg9mTzmLuFcVi9MWlZ1pcP6zT8jRPLQjXWbI8Fk2mFdMBT4Uu QAHCjreIwJuxwfpApF0nKkzvi0oBqarK4EAWt9V48DVYKubmHBX9lAi329BsQCJdOvLw s461i1llf8IShhLqhnaZOjMBKOy8wgguG8kyC7I7R5oNsIt+vw61/+sMT8uMFUnEa8Fd qwmyw6R9e98jugZAhDGHLP9qujAMpGf79p+GbU/e3afX+TQ2YY4GKVmZ2qDGX57aWYhw wNyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427221; x=1780032021; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Lb0OvF7hQ6PiNdrSYpxR44n5ZueReZ1PaD49+fWM2z8=; b=lotUtcVj3DbLFL+TB/U+wUVSa+86xCZix+fQhAmHlVaxg0oRVIKb6YnDnCYWF/aE5j +o4YzJs9yG26qWM1Yo++f6M0sMhDos1niQEfyku6ngB0CsW1T2H8k9TjfNWpEy2FuIv1 RQoiwjqWsDPcBz+E4VXBmAO9KsG6ANprMDV0WNP3TwKuZ2em74NssxWKPA/j+A7pdu0/ K74t1K8iFq5VOmkalKFUWnEPkntg7dXSDNG5koxx8DqoePOUA8TmIOKx0DCMXzZVrpvC 1La5V1EB7kJg3qvPtvD0D/JXLZ47hSPjyPQyAD7O+NXCjcwrT3cndKaIA+0HOM0BU34i knlw== X-Gm-Message-State: AOJu0YyTa2CUpMcbkw1FWlXWqFS5EfJFGZU6Z90cHuw2UZUF3zTT4In8 JESnkKjXJUE2uWTRWnf8q0uzUJA4v3KpwmG3eKncTer941IfeA9txntS X-Gm-Gg: Acq92OG7NhLnAaDHO5l1YaGQikv2A1iWTMXcU1Npc4od8YELUk3ZwnJaaeKg5O0XkvY gC2GNNGL1Ra0DE0B+gAgveSg/7xRWXmrpFaoHLeSj9o8v5gTJloCTuH3ooAI87hB1q5KRFVbIg5 5JGetrHIv0sEnEHAzbWjLb7fKMjXJ62gNjnEsyOHAGFVj/Z99JcrFq5NBSxIxQMQ1TeHiTz5t6+ vn7KuwwYoUJD/A/9qkZ4Y+dpvhlMlpsEVRU/2W8qQlS1UIkEw4zXjufUa7zSuNKp2Zu1ldRA04I g4qWVA5Ooui23GO+PVNnqc1BEq2v0pr0Vu1GnNyoXH4mvB9rryEUkegSMCyAZxmZxv5sGHfYeUr DKZdjKTL4QrMOEcqAci9n6qFx5BYhmoEzuVClY3VhgXxQEfkSPnl5vKE13bzuy62I8weJXu4A3M uN7Vh5aqSWPVD4gyCGDNcGh9Sy7XhO97kBKUVr5diNG4WwOYmxDzRITwDyBHb1Egt9YrJ6sFKCp HO2xghEr2Z76ayWNAgSfAu2vBfGAXClGEysI8/TxJ18XA7JDGBOApP/RnCf7KL16sKyvvoFbgMV PGc= X-Received: by 2002:a05:6808:4fea:b0:484:e5e2:6b99 with SMTP id 5614622812f47-48549ecf994mr1312588b6e.1.1779427221251; Thu, 21 May 2026 22:20:21 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:49 -0600 Subject: [PATCH v14 07/22] target/mips: add Octeon ZUC COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-7-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427341179154100 Add the Octeon ZUC START and MORE helper operations and model the shared state window used by the hardware interface. This covers the keystream and MAC engine state, including the save-and-restore view that overlaps the HSH/SHA3 bank. Shared-window writes also update the SHA512/SHA3 backing state so guests can switch between engines without stale register contents. Signed-off-by: James Hilliard --- Changes v8 -> v9: - Split ZUC selector operations into their own COP2 helper patch. - Replace generic selector dispatch with per-operation ZUC helpers. - Use helper-local selector constants for shared-window position logic. - Add matching helper.h declarations with the helper implementation. Changes v5 -> v6: - Use the manual-aligned HSH_DATW field and shared HSH window helper names introduced by the COP2 crypto core patch. Changes v1 -> v2: - Add shared-window selector predicates and assert on unreachable ZUC selector switches. (suggested by Philippe Mathieu-Daud=C3=A9) - Preserve aliased HSH/SHA3/SHA512 backing state during ZUC shared-window writes. - Add selector dispatch updates in octeon_translate.c after moving COP2 decode out of translate.c. (suggested by Philippe Mathieu-Daud=C3=A9) --- target/mips/helper.h | 2 + target/mips/tcg/octeon_crypto.c | 369 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 371 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index d1ec75eaff..353832748c 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -70,6 +70,8 @@ DEF_HELPER_2(octeon_cp2_mt_sha3_xordat15, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_sha3_xordat16, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_sha3_xordat17, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_sha3_startop, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_zuc_start, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_zuc_more, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index b3b88ce018..28a9fca013 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -264,6 +264,375 @@ static void octeon_sha3_permute(MIPSOcteonCryptoState= *crypto) } } =20 +static inline uint32_t octeon_crypto_hi32(uint64_t value) +{ + return value >> 32; +} + +static inline uint32_t octeon_crypto_lo32(uint64_t value) +{ + return value; +} + +static inline uint64_t octeon_crypto_pack32(uint32_t hi, uint32_t lo) +{ + return ((uint64_t)hi << 32) | lo; +} + +static const uint8_t octeon_zuc_s0[256] =3D { + 0x3e, 0x72, 0x5b, 0x47, 0xca, 0xe0, 0x00, 0x33, + 0x04, 0xd1, 0x54, 0x98, 0x09, 0xb9, 0x6d, 0xcb, + 0x7b, 0x1b, 0xf9, 0x32, 0xaf, 0x9d, 0x6a, 0xa5, + 0xb8, 0x2d, 0xfc, 0x1d, 0x08, 0x53, 0x03, 0x90, + 0x4d, 0x4e, 0x84, 0x99, 0xe4, 0xce, 0xd9, 0x91, + 0xdd, 0xb6, 0x85, 0x48, 0x8b, 0x29, 0x6e, 0xac, + 0xcd, 0xc1, 0xf8, 0x1e, 0x73, 0x43, 0x69, 0xc6, + 0xb5, 0xbd, 0xfd, 0x39, 0x63, 0x20, 0xd4, 0x38, + 0x76, 0x7d, 0xb2, 0xa7, 0xcf, 0xed, 0x57, 0xc5, + 0xf3, 0x2c, 0xbb, 0x14, 0x21, 0x06, 0x55, 0x9b, + 0xe3, 0xef, 0x5e, 0x31, 0x4f, 0x7f, 0x5a, 0xa4, + 0x0d, 0x82, 0x51, 0x49, 0x5f, 0xba, 0x58, 0x1c, + 0x4a, 0x16, 0xd5, 0x17, 0xa8, 0x92, 0x24, 0x1f, + 0x8c, 0xff, 0xd8, 0xae, 0x2e, 0x01, 0xd3, 0xad, + 0x3b, 0x4b, 0xda, 0x46, 0xeb, 0xc9, 0xde, 0x9a, + 0x8f, 0x87, 0xd7, 0x3a, 0x80, 0x6f, 0x2f, 0xc8, + 0xb1, 0xb4, 0x37, 0xf7, 0x0a, 0x22, 0x13, 0x28, + 0x7c, 0xcc, 0x3c, 0x89, 0xc7, 0xc3, 0x96, 0x56, + 0x07, 0xbf, 0x7e, 0xf0, 0x0b, 0x2b, 0x97, 0x52, + 0x35, 0x41, 0x79, 0x61, 0xa6, 0x4c, 0x10, 0xfe, + 0xbc, 0x26, 0x95, 0x88, 0x8a, 0xb0, 0xa3, 0xfb, + 0xc0, 0x18, 0x94, 0xf2, 0xe1, 0xe5, 0xe9, 0x5d, + 0xd0, 0xdc, 0x11, 0x66, 0x64, 0x5c, 0xec, 0x59, + 0x42, 0x75, 0x12, 0xf5, 0x74, 0x9c, 0xaa, 0x23, + 0x0e, 0x86, 0xab, 0xbe, 0x2a, 0x02, 0xe7, 0x67, + 0xe6, 0x44, 0xa2, 0x6c, 0xc2, 0x93, 0x9f, 0xf1, + 0xf6, 0xfa, 0x36, 0xd2, 0x50, 0x68, 0x9e, 0x62, + 0x71, 0x15, 0x3d, 0xd6, 0x40, 0xc4, 0xe2, 0x0f, + 0x8e, 0x83, 0x77, 0x6b, 0x25, 0x05, 0x3f, 0x0c, + 0x30, 0xea, 0x70, 0xb7, 0xa1, 0xe8, 0xa9, 0x65, + 0x8d, 0x27, 0x1a, 0xdb, 0x81, 0xb3, 0xa0, 0xf4, + 0x45, 0x7a, 0x19, 0xdf, 0xee, 0x78, 0x34, 0x60, +}; + +static const uint8_t octeon_zuc_s1[256] =3D { + 0x55, 0xc2, 0x63, 0x71, 0x3b, 0xc8, 0x47, 0x86, + 0x9f, 0x3c, 0xda, 0x5b, 0x29, 0xaa, 0xfd, 0x77, + 0x8c, 0xc5, 0x94, 0x0c, 0xa6, 0x1a, 0x13, 0x00, + 0xe3, 0xa8, 0x16, 0x72, 0x40, 0xf9, 0xf8, 0x42, + 0x44, 0x26, 0x68, 0x96, 0x81, 0xd9, 0x45, 0x3e, + 0x10, 0x76, 0xc6, 0xa7, 0x8b, 0x39, 0x43, 0xe1, + 0x3a, 0xb5, 0x56, 0x2a, 0xc0, 0x6d, 0xb3, 0x05, + 0x22, 0x66, 0xbf, 0xdc, 0x0b, 0xfa, 0x62, 0x48, + 0xdd, 0x20, 0x11, 0x06, 0x36, 0xc9, 0xc1, 0xcf, + 0xf6, 0x27, 0x52, 0xbb, 0x69, 0xf5, 0xd4, 0x87, + 0x7f, 0x84, 0x4c, 0xd2, 0x9c, 0x57, 0xa4, 0xbc, + 0x4f, 0x9a, 0xdf, 0xfe, 0xd6, 0x8d, 0x7a, 0xeb, + 0x2b, 0x53, 0xd8, 0x5c, 0xa1, 0x14, 0x17, 0xfb, + 0x23, 0xd5, 0x7d, 0x30, 0x67, 0x73, 0x08, 0x09, + 0xee, 0xb7, 0x70, 0x3f, 0x61, 0xb2, 0x19, 0x8e, + 0x4e, 0xe5, 0x4b, 0x93, 0x8f, 0x5d, 0xdb, 0xa9, + 0xad, 0xf1, 0xae, 0x2e, 0xcb, 0x0d, 0xfc, 0xf4, + 0x2d, 0x46, 0x6e, 0x1d, 0x97, 0xe8, 0xd1, 0xe9, + 0x4d, 0x37, 0xa5, 0x75, 0x5e, 0x83, 0x9e, 0xab, + 0x82, 0x9d, 0xb9, 0x1c, 0xe0, 0xcd, 0x49, 0x89, + 0x01, 0xb6, 0xbd, 0x58, 0x24, 0xa2, 0x5f, 0x38, + 0x78, 0x99, 0x15, 0x90, 0x50, 0xb8, 0x95, 0xe4, + 0xd0, 0x91, 0xc7, 0xce, 0xed, 0x0f, 0xb4, 0x6f, + 0xa0, 0xcc, 0xf0, 0x02, 0x4a, 0x79, 0xc3, 0xde, + 0xa3, 0xef, 0xea, 0x51, 0xe6, 0x6b, 0x18, 0xec, + 0x1b, 0x2c, 0x80, 0xf7, 0x74, 0xe7, 0xff, 0x21, + 0x5a, 0x6a, 0x54, 0x1e, 0x41, 0x31, 0x92, 0x35, + 0xc4, 0x33, 0x07, 0x0a, 0xba, 0x7e, 0x0e, 0x34, + 0x88, 0xb1, 0x98, 0x7c, 0xf3, 0x3d, 0x60, 0x6c, + 0x7b, 0xca, 0xd3, 0x1f, 0x32, 0x65, 0x04, 0x28, + 0x64, 0xbe, 0x85, 0x9b, 0x2f, 0x59, 0x8a, 0xd7, + 0xb0, 0x25, 0xac, 0xaf, 0x12, 0x03, 0xe2, 0xf2, +}; + +static inline uint32_t octeon_zuc_addm(uint32_t a, uint32_t b) +{ + uint32_t c =3D a + b; + + c =3D (c & 0x7fffffffU) + (c >> 31); + return c ? c : 0x7fffffffU; +} + +static inline uint32_t octeon_zuc_mul_by_pow2(uint32_t v, unsigned int shi= ft) +{ + return ((v << shift) | (v >> (31 - shift))) & 0x7fffffffU; +} + +static inline uint32_t octeon_zuc_make_u32(uint8_t a, uint8_t b, + uint8_t c, uint8_t d) +{ + return ((uint32_t)a << 24) | ((uint32_t)b << 16) | + ((uint32_t)c << 8) | d; +} + +static inline uint64_t octeon_zuc_pack_pair(uint32_t hi, uint32_t lo) +{ + return ((uint64_t)hi << 32) | lo; +} + +static uint32_t octeon_zuc_lfsr(const MIPSOcteonCryptoState *crypto, + unsigned int index) +{ + uint64_t pair =3D crypto->hsh_dat[index / 2]; + + return index & 1 ? octeon_crypto_lo32(pair) : octeon_crypto_hi32(pair); +} + +static void octeon_zuc_set_lfsr(MIPSOcteonCryptoState *crypto, + unsigned int index, uint32_t value) +{ + uint32_t hi =3D octeon_crypto_hi32(crypto->hsh_dat[index / 2]); + uint32_t lo =3D octeon_crypto_lo32(crypto->hsh_dat[index / 2]); + + value &=3D 0x7fffffffU; + if (index & 1) { + lo =3D value; + } else { + hi =3D value; + } + crypto->hsh_dat[index / 2] =3D octeon_zuc_pack_pair(hi, lo); +} + +static uint32_t octeon_zuc_fsm(const MIPSOcteonCryptoState *crypto, + unsigned int index) +{ + uint64_t pair =3D crypto->hsh_dat[8]; + + return index ? octeon_crypto_lo32(pair) : octeon_crypto_hi32(pair); +} + +static void octeon_zuc_set_fsm(MIPSOcteonCryptoState *crypto, + unsigned int index, uint32_t value) +{ + uint32_t hi =3D octeon_crypto_hi32(crypto->hsh_dat[8]); + uint32_t lo =3D octeon_crypto_lo32(crypto->hsh_dat[8]); + + if (index) { + lo =3D value; + crypto->hsh_iv[2] =3D value; + } else { + hi =3D value; + crypto->hsh_iv[1] =3D value; + } + crypto->hsh_dat[8] =3D octeon_zuc_pack_pair(hi, lo); +} + +static uint32_t octeon_zuc_window(const MIPSOcteonCryptoState *crypto, + unsigned int index) +{ + switch (index) { + case 0: + return octeon_crypto_hi32(crypto->hsh_dat[9]); + case 1: + return octeon_crypto_lo32(crypto->hsh_dat[9]); + case 2: + return crypto->hsh_dat[10]; + default: + g_assert_not_reached(); + } +} + +static void octeon_zuc_set_window(MIPSOcteonCryptoState *crypto, + unsigned int index, uint32_t value) +{ + switch (index) { + case 0: + crypto->hsh_dat[9] =3D + octeon_zuc_pack_pair(value, octeon_crypto_lo32(crypto->hsh_dat= [9])); + crypto->hsh_iv[0] =3D crypto->hsh_dat[9]; + return; + case 1: + crypto->hsh_dat[9] =3D + octeon_zuc_pack_pair(octeon_crypto_hi32(crypto->hsh_dat[9]), v= alue); + crypto->hsh_iv[0] =3D crypto->hsh_dat[9]; + return; + case 2: + crypto->hsh_dat[10] =3D value; + return; + default: + g_assert_not_reached(); + } +} + +static uint32_t octeon_zuc_tresult(const MIPSOcteonCryptoState *crypto) +{ + return crypto->hsh_dat[11]; +} + +static void octeon_zuc_set_tresult(MIPSOcteonCryptoState *crypto, + uint32_t value) +{ + crypto->hsh_dat[11] =3D value; + crypto->hsh_iv[3] =3D value; +} + +static void octeon_zuc_bit_reorganization(const MIPSOcteonCryptoState *cry= pto, + uint32_t x[4]) +{ + x[0] =3D ((octeon_zuc_lfsr(crypto, 15) & 0x7fff8000U) << 1) | + (octeon_zuc_lfsr(crypto, 14) & 0xffffU); + x[1] =3D ((octeon_zuc_lfsr(crypto, 11) & 0xffffU) << 16) | + (octeon_zuc_lfsr(crypto, 9) >> 15); + x[2] =3D ((octeon_zuc_lfsr(crypto, 7) & 0xffffU) << 16) | + (octeon_zuc_lfsr(crypto, 5) >> 15); + x[3] =3D ((octeon_zuc_lfsr(crypto, 2) & 0xffffU) << 16) | + (octeon_zuc_lfsr(crypto, 0) >> 15); +} + +static inline uint32_t octeon_zuc_l1(uint32_t x) +{ + return x ^ rol32(x, 2) ^ rol32(x, 10) ^ + rol32(x, 18) ^ rol32(x, 24); +} + +static inline uint32_t octeon_zuc_l2(uint32_t x) +{ + return x ^ rol32(x, 8) ^ rol32(x, 14) ^ + rol32(x, 22) ^ rol32(x, 30); +} + +static uint32_t octeon_zuc_f(MIPSOcteonCryptoState *crypto, const uint32_t= x[4]) +{ + uint32_t fsm0 =3D octeon_zuc_fsm(crypto, 0); + uint32_t fsm1 =3D octeon_zuc_fsm(crypto, 1); + uint32_t w =3D (x[0] ^ fsm0) + fsm1; + uint32_t w1 =3D fsm0 + x[1]; + uint32_t w2 =3D fsm1 ^ x[2]; + uint32_t u =3D octeon_zuc_l1((w1 << 16) | (w2 >> 16)); + uint32_t v =3D octeon_zuc_l2((w2 << 16) | (w1 >> 16)); + + octeon_zuc_set_fsm(crypto, 0, + octeon_zuc_make_u32(octeon_zuc_s0[u >> 24], + octeon_zuc_s1[(uint8_t)(u >> 16= )], + octeon_zuc_s0[(uint8_t)(u >> 8)= ], + octeon_zuc_s1[(uint8_t)u])); + octeon_zuc_set_fsm(crypto, 1, + octeon_zuc_make_u32(octeon_zuc_s0[v >> 24], + octeon_zuc_s1[(uint8_t)(v >> 16= )], + octeon_zuc_s0[(uint8_t)(v >> 8)= ], + octeon_zuc_s1[(uint8_t)v])); + return w; +} + +static void octeon_zuc_lfsr_step(MIPSOcteonCryptoState *crypto, + bool init_mode, uint32_t u) +{ + uint32_t lfsr[16]; + uint32_t f; + + for (int i =3D 0; i < 16; i++) { + lfsr[i] =3D octeon_zuc_lfsr(crypto, i); + } + + f =3D lfsr[0]; + f =3D octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(lfsr[0], 8)); + f =3D octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(lfsr[4], 20)); + f =3D octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(lfsr[10], 21)); + f =3D octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(lfsr[13], 17)); + f =3D octeon_zuc_addm(f, octeon_zuc_mul_by_pow2(lfsr[15], 15)); + if (init_mode) { + f =3D octeon_zuc_addm(f, u); + } + + for (int i =3D 0; i < 15; i++) { + octeon_zuc_set_lfsr(crypto, i, lfsr[i + 1]); + } + octeon_zuc_set_lfsr(crypto, 15, f); +} + +static uint32_t octeon_zuc_generate_word(MIPSOcteonCryptoState *crypto) +{ + uint32_t x[4]; + uint32_t z; + + octeon_zuc_bit_reorganization(crypto, x); + z =3D octeon_zuc_f(crypto, x) ^ x[3]; + octeon_zuc_lfsr_step(crypto, false, 0); + return z; +} + +static void octeon_zuc_fill_window(MIPSOcteonCryptoState *crypto) +{ + octeon_zuc_set_window(crypto, 0, octeon_zuc_generate_word(crypto)); + octeon_zuc_set_window(crypto, 1, octeon_zuc_generate_word(crypto)); + octeon_zuc_set_window(crypto, 2, octeon_zuc_generate_word(crypto)); +} + +static inline uint32_t +octeon_zuc_window_word(const MIPSOcteonCryptoState *crypto, unsigned int b= it) +{ + if (bit =3D=3D 0) { + return octeon_zuc_window(crypto, 0); + } + if (bit < 32) { + return (octeon_zuc_window(crypto, 0) << bit) | + (octeon_zuc_window(crypto, 1) >> (32 - bit)); + } + if (bit =3D=3D 32) { + return octeon_zuc_window(crypto, 1); + } + return (octeon_zuc_window(crypto, 1) << (bit - 32)) | + (octeon_zuc_window(crypto, 2) >> (64 - bit)); +} + +static void octeon_zuc_advance_window(MIPSOcteonCryptoState *crypto) +{ + octeon_zuc_set_window(crypto, 0, octeon_zuc_window(crypto, 2)); + octeon_zuc_set_window(crypto, 1, octeon_zuc_generate_word(crypto)); + octeon_zuc_set_window(crypto, 2, octeon_zuc_generate_word(crypto)); +} + +static void octeon_zuc_start(MIPSOcteonCryptoState *crypto, uint64_t data) +{ + uint32_t x[4]; + + for (int i =3D 0; i < 14; i++) { + octeon_zuc_set_lfsr(crypto, i, octeon_zuc_lfsr(crypto, i)); + } + octeon_zuc_set_lfsr(crypto, 14, data >> 32); + octeon_zuc_set_lfsr(crypto, 15, data); + octeon_zuc_set_fsm(crypto, 0, 0); + octeon_zuc_set_fsm(crypto, 1, 0); + octeon_zuc_set_tresult(crypto, 0); + + for (int i =3D 0; i < 32; i++) { + octeon_zuc_bit_reorganization(crypto, x); + octeon_zuc_lfsr_step(crypto, true, octeon_zuc_f(crypto, x) >> 1); + } + + octeon_zuc_bit_reorganization(crypto, x); + (void)octeon_zuc_f(crypto, x); + octeon_zuc_lfsr_step(crypto, false, 0); + octeon_zuc_fill_window(crypto); +} + +static void octeon_zuc_more(MIPSOcteonCryptoState *crypto, uint64_t data) +{ + uint32_t t =3D octeon_zuc_tresult(crypto); + + for (unsigned int bit =3D 0; bit < 64; bit++) { + if ((data >> (63 - bit)) & 1) { + t ^=3D octeon_zuc_window_word(crypto, bit); + } + } + octeon_zuc_set_tresult(crypto, t); + octeon_zuc_advance_window(crypto); +} + +void helper_octeon_cp2_mt_zuc_start(CPUMIPSState *env, uint64_t value) +{ + octeon_zuc_start(&env->octeon_crypto, value); +} + +void helper_octeon_cp2_mt_zuc_more(CPUMIPSState *env, uint64_t value) +{ + octeon_zuc_more(&env->octeon_crypto, value); +} + uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env) { return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427286; cv=none; d=zohomail.com; s=zohoarc; b=l7d905iZgbxXWmio5tJAzNiJkjzG2scGRm/ZSkLD8Eq3QW6Fums2EseHzFIskJsoV1Qz/YNJ7bIeFWq8OBgst+42Mhkq2DvejQdP+8G1+Zjy23m6iZg0ZjutqhwNu7S0x9fSBxHqzNS6ONFcJBoegRfVFUGMpX55d20BiHJQeAA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427286; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aGJ+lGGsCu0d6uFtqXo0HJGtey3n+HsCJ/BUXG8uA+k=; b=nB6W6/iRDNwM73kltwiJsPiNDfNVCF1VgAOmnmm/RDC0jLE6VHffgIo8S0h2efiyikpWakBqC8nxOa1evm1wOG97tOtNSn1R4g5Q/P1w+ujDMInQDj9SnhQq8WV+orEIUItaVwP+p46fMhv7uA0tqqnN2SBVsmVhjv7cOfgZosI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427286690281.81283840835977; Thu, 21 May 2026 22:21:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJ9-0002VF-O0; Fri, 22 May 2026 01:20:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ8-0002UD-BD for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:26 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJ5-0001rz-Ts for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:25 -0400 Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-47c35be02fdso2533317b6e.3 for ; Thu, 21 May 2026 22:20:23 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427223; x=1780032023; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aGJ+lGGsCu0d6uFtqXo0HJGtey3n+HsCJ/BUXG8uA+k=; b=Q68H5sRPjmUvLo3qiQ/gZEsAy4EJrQtrxyzh4DjRVEAmpRxI685qEr6DZuQzbV9Acz LCXA958At42t0AbLyCKVV6AtOfjtn/PFGrGJYXgozGP10npbwciJoe6KtszUFQfvzEjD oOOKlUJbGuScm9A/3fnFfA6P6RCqjvAG9sVM6lKnVzKp235xzas4KTV/wNvvpnXvpEcK 5XAJewFV7z6W2CUSLwYmA/1SjXxbP1zAJNddgqPExs3Wj3C3SN8d0QD6cNh7FOk4wsqq 8oZBfRMMH0hQ73GEuStIIzPaEjAaorg5KamjcZKFo0YJYrprglVOLU8/nTMPuVKtN222 J/Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427223; x=1780032023; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=aGJ+lGGsCu0d6uFtqXo0HJGtey3n+HsCJ/BUXG8uA+k=; b=fbQDM1sRqizh7l9mqP3la+L13j8rlCfnspTKcmOh+gxedxFzB/75+4snrX+yfva5cs H+IkLcQRNbN82HJ0KF1LdrNEkq94Mj92HN637bMyVj9WfeWfdw8EngULnzl9UJhGXjPe YFLwxsfcubqz6dv+AYTTf8G6gFZzuF/H4NwLrwpj2Eaw27jNjx0zvG124hGi+ksyMcdM rxTOuG8I2maIhtxAtIEmzvnD5avDnt+8La6kEuprkdSAO18JqF43rSgCyEfpvDw1kZJN AsUqi5Tu77XSibyI2VnWd4nh84eT02IXrEGUJtFUKVHreSoQFgCH/swFPgdqPdu5wNvC D+Ew== X-Gm-Message-State: AOJu0YwOK5FABZZ9OHyo4/DhbT2goqwdCO3JN8GfaTF5Yd2KYol6vRgt PwDb1rMzVBPbAbtcCgbxnZuwZA3vqmw8kTi2hUYcM585NwWiIrpRO9un X-Gm-Gg: Acq92OExL+K/x1TNdLp/DR3d0RbSdmma3dQHY23KxkIvUfM6mPfcoXNUXxF0G7QqAoz 3E6MGQd6NVmUAl0buKwidkikpbdqySvabr+K8SmpfeuUHk7cYZYQF0OlCRO17DQdXjbPMzalYWI bUqs/sEoMNfKmajkGfoo+rx0iioEeSwLZp/hmZ3Y2c+DPbd2XdQ28MCfxka665ERkTUMBaD6RlF hm1CDnngemA8F5LWLw3dzG4Dp8tbCIyfmFCwmQnOuo6dlqdAIP56w1/BlACD73IcfiClTZ+FGk6 2cwPcyi2cSPfn2k8Eh9ShfJW9KF/qFDJGnkN4vf9OgzOoz1T6yy0oYX0PzqztTHkK9g8SEfRSuk 4Pp/ZvatYfl4ADpWZJuFaYBwpK4W9eIjvU6r7U9/mEakwqgulMks5hv4JfIikugCkTyKnpLzhSZ 3KH7YCXkjfk696xNh7DeaZv7tbEKchCBJArxbYvIJ0/61+8MZ8f+CUlkr/n90fPqCxx5K0XNL5u HnDWpKvUPIhVz236mB3UtZY6xbl8VtZEhSejSDlA8s52UtNmJ0f5pNP02lmRN2WdvVg X-Received: by 2002:a05:6808:c2fa:b0:47b:c2a2:1c6c with SMTP id 5614622812f47-48549d5e897mr1355118b6e.16.1779427222761; Thu, 21 May 2026 22:20:22 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:50 -0600 Subject: [PATCH v14 08/22] target/mips: add Octeon SNOW3G COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-8-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427288694154100 Add helper support for the Octeon SNOW3G START and MORE selectors. The engine state and result are represented through the architectural HSH IV and DAT register banks that SNOW3G aliases for save and restore. Signed-off-by: James Hilliard --- Changes v9 -> v10: - Drop non-architectural SNOW3G shadow state and shared-mode tracking. - Use the architectural HSH IV/DAT register banks for aliased state. Changes v8 -> v9: - Split SNOW3G selector operations into their own COP2 helper patch. - Replace generic selector dispatch with per-operation SNOW3G helpers. - Add matching helper.h declarations with the helper implementation. --- target/mips/helper.h | 2 + target/mips/tcg/octeon_crypto.c | 275 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 277 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 353832748c..7985083e6f 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -72,6 +72,8 @@ DEF_HELPER_2(octeon_cp2_mt_sha3_xordat17, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_sha3_startop, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_zuc_start, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_zuc_more, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_snow3g_start, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_snow3g_more, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 28a9fca013..2610f7224a 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -623,6 +623,281 @@ static void octeon_zuc_more(MIPSOcteonCryptoState *cr= ypto, uint64_t data) octeon_zuc_advance_window(crypto); } =20 +static const uint8_t octeon_snow3g_sr[256] =3D { + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, + 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, + 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, + 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, + 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, + 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, + 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, + 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, + 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, + 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, + 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, + 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, + 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, + 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, + 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, + 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, + 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, + 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, + 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, + 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, + 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, + 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, + 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, + 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, + 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, + 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16, +}; + +static const uint8_t octeon_snow3g_sq[256] =3D { + 0x25, 0x24, 0x73, 0x67, 0xd7, 0xae, 0x5c, 0x30, + 0xa4, 0xee, 0x6e, 0xcb, 0x7d, 0xb5, 0x82, 0xdb, + 0xe4, 0x8e, 0x48, 0x49, 0x4f, 0x5d, 0x6a, 0x78, + 0x70, 0x88, 0xe8, 0x5f, 0x5e, 0x84, 0x65, 0xe2, + 0xd8, 0xe9, 0xcc, 0xed, 0x40, 0x2f, 0x11, 0x28, + 0x57, 0xd2, 0xac, 0xe3, 0x4a, 0x15, 0x1b, 0xb9, + 0xb2, 0x80, 0x85, 0xa6, 0x2e, 0x02, 0x47, 0x29, + 0x07, 0x4b, 0x0e, 0xc1, 0x51, 0xaa, 0x89, 0xd4, + 0xca, 0x01, 0x46, 0xb3, 0xef, 0xdd, 0x44, 0x7b, + 0xc2, 0x7f, 0xbe, 0xc3, 0x9f, 0x20, 0x4c, 0x64, + 0x83, 0xa2, 0x68, 0x42, 0x13, 0xb4, 0x41, 0xcd, + 0xba, 0xc6, 0xbb, 0x6d, 0x4d, 0x71, 0x21, 0xf4, + 0x8d, 0xb0, 0xe5, 0x93, 0xfe, 0x8f, 0xe6, 0xcf, + 0x43, 0x45, 0x31, 0x22, 0x37, 0x36, 0x96, 0xfa, + 0xbc, 0x0f, 0x08, 0x52, 0x1d, 0x55, 0x1a, 0xc5, + 0x4e, 0x23, 0x69, 0x7a, 0x92, 0xff, 0x5b, 0x5a, + 0xeb, 0x9a, 0x1c, 0xa9, 0xd1, 0x7e, 0x0d, 0xfc, + 0x50, 0x8a, 0xb6, 0x62, 0xf5, 0x0a, 0xf8, 0xdc, + 0x03, 0x3c, 0x0c, 0x39, 0xf1, 0xb8, 0xf3, 0x3d, + 0xf2, 0xd5, 0x97, 0x66, 0x81, 0x32, 0xa0, 0x00, + 0x06, 0xce, 0xf6, 0xea, 0xb7, 0x17, 0xf7, 0x8c, + 0x79, 0xd6, 0xa7, 0xbf, 0x8b, 0x3f, 0x1f, 0x53, + 0x63, 0x75, 0x35, 0x2c, 0x60, 0xfd, 0x27, 0xd3, + 0x94, 0xa5, 0x7c, 0xa1, 0x05, 0x58, 0x2d, 0xbd, + 0xd9, 0xc7, 0xaf, 0x6b, 0x54, 0x0b, 0xe0, 0x38, + 0x04, 0xc8, 0x9d, 0xe7, 0x14, 0xb1, 0x87, 0x9c, + 0xdf, 0x6f, 0xf9, 0xda, 0x2a, 0xc4, 0x59, 0x16, + 0x74, 0x91, 0xab, 0x26, 0x61, 0x76, 0x34, 0x2b, + 0xad, 0x99, 0xfb, 0x72, 0xec, 0x33, 0x12, 0xde, + 0x98, 0x3b, 0xc0, 0x9b, 0x3e, 0x18, 0x10, 0x3a, + 0x56, 0xe1, 0x77, 0xc9, 0x1e, 0x9e, 0x95, 0xa3, + 0x90, 0x19, 0xa8, 0x6c, 0x09, 0xd0, 0xf0, 0x86, +}; + +static inline uint8_t octeon_snow3g_mulx(uint8_t v, uint8_t c) +{ + return (v & 0x80) ? ((v << 1) ^ c) : (v << 1); +} + +static uint8_t octeon_snow3g_mulxpow(uint8_t v, unsigned int n, uint8_t c) +{ + while (n-- > 0) { + v =3D octeon_snow3g_mulx(v, c); + } + return v; +} + +static inline uint32_t octeon_snow3g_pack32(uint8_t b0, uint8_t b1, + uint8_t b2, uint8_t b3) +{ + return ((uint32_t)b0 << 24) | ((uint32_t)b1 << 16) | + ((uint32_t)b2 << 8) | b3; +} + +static uint32_t octeon_snow3g_mulalpha(uint8_t c) +{ + return octeon_snow3g_pack32(octeon_snow3g_mulxpow(c, 23, 0xa9), + octeon_snow3g_mulxpow(c, 245, 0xa9), + octeon_snow3g_mulxpow(c, 48, 0xa9), + octeon_snow3g_mulxpow(c, 239, 0xa9)); +} + +static uint32_t octeon_snow3g_divalpha(uint8_t c) +{ + return octeon_snow3g_pack32(octeon_snow3g_mulxpow(c, 16, 0xa9), + octeon_snow3g_mulxpow(c, 39, 0xa9), + octeon_snow3g_mulxpow(c, 6, 0xa9), + octeon_snow3g_mulxpow(c, 64, 0xa9)); +} + +static uint32_t octeon_snow3g_s1(uint32_t w) +{ + uint8_t x0 =3D octeon_snow3g_sr[w >> 24]; + uint8_t x1 =3D octeon_snow3g_sr[(uint8_t)(w >> 16)]; + uint8_t x2 =3D octeon_snow3g_sr[(uint8_t)(w >> 8)]; + uint8_t x3 =3D octeon_snow3g_sr[(uint8_t)w]; + uint8_t r0 =3D octeon_snow3g_mulx(x0, 0x1b) ^ x1 ^ x2 ^ + octeon_snow3g_mulx(x3, 0x1b) ^ x3; + uint8_t r1 =3D octeon_snow3g_mulx(x0, 0x1b) ^ x0 ^ + octeon_snow3g_mulx(x1, 0x1b) ^ x2 ^ x3; + uint8_t r2 =3D x0 ^ octeon_snow3g_mulx(x1, 0x1b) ^ x1 ^ + octeon_snow3g_mulx(x2, 0x1b) ^ x3; + uint8_t r3 =3D x0 ^ x1 ^ octeon_snow3g_mulx(x2, 0x1b) ^ x2 ^ + octeon_snow3g_mulx(x3, 0x1b); + + return octeon_snow3g_pack32(r0, r1, r2, r3); +} + +static uint32_t octeon_snow3g_s2(uint32_t w) +{ + uint8_t x0 =3D octeon_snow3g_sq[w >> 24]; + uint8_t x1 =3D octeon_snow3g_sq[(uint8_t)(w >> 16)]; + uint8_t x2 =3D octeon_snow3g_sq[(uint8_t)(w >> 8)]; + uint8_t x3 =3D octeon_snow3g_sq[(uint8_t)w]; + uint8_t r0 =3D octeon_snow3g_mulx(x0, 0x69) ^ x1 ^ x2 ^ + octeon_snow3g_mulx(x3, 0x69) ^ x3; + uint8_t r1 =3D octeon_snow3g_mulx(x0, 0x69) ^ x0 ^ + octeon_snow3g_mulx(x1, 0x69) ^ x2 ^ x3; + uint8_t r2 =3D x0 ^ octeon_snow3g_mulx(x1, 0x69) ^ x1 ^ + octeon_snow3g_mulx(x2, 0x69) ^ x3; + uint8_t r3 =3D x0 ^ x1 ^ octeon_snow3g_mulx(x2, 0x69) ^ x2 ^ + octeon_snow3g_mulx(x3, 0x69); + + return octeon_snow3g_pack32(r0, r1, r2, r3); +} + +static uint32_t octeon_snow3g_lfsr(const MIPSOcteonCryptoState *crypto, + unsigned int index) +{ + uint64_t pair =3D crypto->hsh_dat[index / 2]; + + return index & 1 ? octeon_crypto_lo32(pair) : octeon_crypto_hi32(pair); +} + +static void octeon_snow3g_set_lfsr(MIPSOcteonCryptoState *crypto, + unsigned int index, uint32_t value) +{ + uint32_t hi =3D octeon_crypto_hi32(crypto->hsh_dat[index / 2]); + uint32_t lo =3D octeon_crypto_lo32(crypto->hsh_dat[index / 2]); + + if (index & 1) { + lo =3D value; + } else { + hi =3D value; + } + crypto->hsh_dat[index / 2] =3D octeon_crypto_pack32(hi, lo); +} + +static uint32_t octeon_snow3g_fsm(const MIPSOcteonCryptoState *crypto, + unsigned int index) +{ + return crypto->hsh_iv[1 + index]; +} + +static void octeon_snow3g_set_fsm(MIPSOcteonCryptoState *crypto, + unsigned int index, uint32_t value) +{ + crypto->hsh_iv[1 + index] =3D value; +} + +static uint32_t octeon_snow3g_clock_fsm(MIPSOcteonCryptoState *crypto) +{ + uint32_t fsm0 =3D octeon_snow3g_fsm(crypto, 0); + uint32_t fsm1 =3D octeon_snow3g_fsm(crypto, 1); + uint32_t fsm2 =3D octeon_snow3g_fsm(crypto, 2); + uint32_t f =3D (uint32_t)(octeon_snow3g_lfsr(crypto, 15) + fsm0) ^ fsm= 1; + uint32_t r =3D (uint32_t)(fsm1 + (fsm2 ^ octeon_snow3g_lfsr(crypto, 5)= )); + + octeon_snow3g_set_fsm(crypto, 2, octeon_snow3g_s2(fsm1)); + octeon_snow3g_set_fsm(crypto, 1, octeon_snow3g_s1(fsm0)); + octeon_snow3g_set_fsm(crypto, 0, r); + return f; +} + +static void octeon_snow3g_clock_lfsr(MIPSOcteonCryptoState *crypto, + bool init_mode, uint32_t f) +{ + uint32_t lfsr[16]; + uint32_t s0; + uint32_t s11; + uint32_t v; + int i; + + for (i =3D 0; i < 16; i++) { + lfsr[i] =3D octeon_snow3g_lfsr(crypto, i); + } + + s0 =3D lfsr[0]; + s11 =3D lfsr[11]; + v =3D (s0 << 8) ^ octeon_snow3g_mulalpha(s0 >> 24) ^ + lfsr[2] ^ (s11 >> 8) ^ octeon_snow3g_divalpha((uint8_t)s11); + + if (init_mode) { + v ^=3D f; + } + + for (i =3D 0; i < 15; i++) { + octeon_snow3g_set_lfsr(crypto, i, lfsr[i + 1]); + } + octeon_snow3g_set_lfsr(crypto, 15, v); +} + +static uint32_t octeon_snow3g_generate_word(MIPSOcteonCryptoState *crypto) +{ + uint32_t f =3D octeon_snow3g_clock_fsm(crypto); + uint32_t z =3D f ^ octeon_snow3g_lfsr(crypto, 0); + + octeon_snow3g_clock_lfsr(crypto, false, 0); + return z; +} + +static void octeon_snow3g_queue_result(MIPSOcteonCryptoState *crypto) +{ + uint32_t z0 =3D octeon_snow3g_generate_word(crypto); + uint32_t z1 =3D octeon_snow3g_generate_word(crypto); + + crypto->hsh_iv[0] =3D octeon_crypto_pack32(z0, z1); +} + +static void octeon_snow3g_start(MIPSOcteonCryptoState *crypto, uint64_t da= ta) +{ + int i; + + for (i =3D 0; i < 14; i++) { + octeon_snow3g_set_lfsr(crypto, i, octeon_snow3g_lfsr(crypto, i)); + } + octeon_snow3g_set_lfsr(crypto, 14, data >> 32); + octeon_snow3g_set_lfsr(crypto, 15, data); + for (i =3D 0; i < 3; i++) { + octeon_snow3g_set_fsm(crypto, i, 0); + } + + for (i =3D 0; i < 32; i++) { + uint32_t f =3D octeon_snow3g_clock_fsm(crypto); + + octeon_snow3g_clock_lfsr(crypto, true, f); + } + + (void)octeon_snow3g_clock_fsm(crypto); + octeon_snow3g_clock_lfsr(crypto, false, 0); + octeon_snow3g_queue_result(crypto); +} + +static void octeon_snow3g_more(MIPSOcteonCryptoState *crypto) +{ + octeon_snow3g_queue_result(crypto); +} + +void helper_octeon_cp2_mt_snow3g_start(CPUMIPSState *env, uint64_t value) +{ + octeon_snow3g_start(&env->octeon_crypto, value); +} + +void helper_octeon_cp2_mt_snow3g_more(CPUMIPSState *env, uint64_t value) +{ + (void)value; + octeon_snow3g_more(&env->octeon_crypto); +} + void helper_octeon_cp2_mt_zuc_start(CPUMIPSState *env, uint64_t value) { octeon_zuc_start(&env->octeon_crypto, value); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427306; cv=none; d=zohomail.com; s=zohoarc; b=TI4k4V92rP4e054sWPLi2rSxoPntVSqqOmmcMl5gSF/K+8SMio3zDzg2HNNiP0PFhox41+la0LXEzp14CH2eaOEHOoqnz5mEZ7AYNtzqSUQAHLamdbglC/Zg5zzVJnurKWRy1/vWh1WwpKgf+TQ8AnrMQ7KM9ZLFEhGJA6VpLEg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427306; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kquL+4fEmdOa1jgdWKrGP/ZTDBa1OlSfyNf7ARwi0dk=; b=gXFac47Qw3u1hivr2xwOhju1bRo+XTPPRoxc5p3YADZA6Ma7q3EUiZJJkjyBJoAxi94rClDGVf5rIV1yxN6sE/CQYUt574aKR07RriWs28iSA/LIRYa1+QXpOgGbMuQ6j44GfiKwXYPYt+O/lnqcxOmVldoUNgaqXkJ5EPxnK28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427306776645.8599289128496; Thu, 21 May 2026 22:21:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJC-0002Yu-U2; Fri, 22 May 2026 01:20:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJ9-0002VB-If for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:27 -0400 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJ7-0001uS-Hh for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:27 -0400 Received: by mail-oi1-x235.google.com with SMTP id 5614622812f47-479f7e75a6bso2647061b6e.2 for ; Thu, 21 May 2026 22:20:25 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427224; x=1780032024; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kquL+4fEmdOa1jgdWKrGP/ZTDBa1OlSfyNf7ARwi0dk=; b=WmyL18/ul9YCtJVpR1fnkcQJ3w6dNA7zUa1pF/3AC+u8dsRQ2bte6Gll2NT+yZUKAQ l2CYvAiQJ5YarSCGLuxUKyb7Q2dj/q5Km4IT8fsoEZCvCTnqn8ot0rEuaJKJpHd5hrcT t/aBOVPjcaGUqWEHaXvf4ID9UjQlyoR4Fy4S2oyBvaGIKKJon+cMMnTCILs4Cso/hAXK tZ6dx1gQlirPZvwSArRuae4fC3O6QRmyL8nCSdm16EArHnL1YOrhsmkeBFPgzlRaFjbJ 1DU8ck9DH+boIySDUDaTvknbyfxgmP6+n1Jqxx2p6bOEMYzrNzt9w1LB6Mbq4F67l0Wr Ng7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427224; x=1780032024; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kquL+4fEmdOa1jgdWKrGP/ZTDBa1OlSfyNf7ARwi0dk=; b=kdWZ9VH5Jwfmep5OULKmVlPETMriLb+GzgD0SeN3jhwt/hRWncu8805MeYV/WTanFd P9ohTJQ79odYJxhKdeuCjUrF3gDrABXV7pf2U1uSiPOariaKcuXJ4AvzeVX5YyrNags4 WvVkPx+bB805NsKBPXCpK2S9vW9pH5eDywDaiNvhSgc/6SaoAuZz0CCu9T5IGRFR4BBf ZOuEQbqvCZBhK06oDlDYmTwkDAq4hwcu4KKffreMAJ4dTBqHcDpUIIZ/mPWuEgXxzjnz P49X4Iggo+HBKa5UOod2ON1GWlUyfRLZKyku3fRuCKL62/68mF7OSMj+5RLsGmxYCf7M CFWg== X-Gm-Message-State: AOJu0Yyc98YqPI+BsPzZmpaCiAzzzqh/Wyf26tDZ4G1guyPpcr0wqorC kDoSHNMsV1J3szR1IZ55or3jP6hHJteWTCTR+2MikvVNcM5NRoAQL4lp X-Gm-Gg: Acq92OGUpktLnx4csxUJvOvJ4FTQZctVPyGzI0Y1GLZE/2CH5Y2o1DCRf86/Uq35Qlc yn0bE64pnv7WsXa8qGYzrAEX9I1rOfx4kuDEd9LVaBwCerbM+RAyNdMx4pJHQTdAhC1TRSPoONO c6RqtrjC00SASziWhF4jc/Wct9Mwf2F4avx0WOh5iEqU7DTAgRPXZTdXw9PnrRt4uWwdPtw8rKx iV3aRm8jTXTgsit7kbmI0GLcb6/HQ8PAvunv9XKyVGHDBLKve5EGuDXHh0AGISRO2AZdafdnfCf l2B91kQrGvcMECElY4/ZowAZPkTMkkPWl5VgYNYof5exJNlLsyCK2j4PSq9bIdV/LdkY3Zdhex8 l0EFpBRTYbls4SDhqb+0rtZZceln0UQm0KIP4xoMgd/98xuiOJyHVKTklW3Le6uz7/ifWDNk+YY K3/+Gduzxb37KRKzJ9tA3rxHktLtJdhVPJzIrG84wx3lMnwwiKq8CFU+Po6Jf15AY4gntGKLhBr F0wB0I77YLH15PdoiW6jTvMxpJMCT3I4/BuditWGmWfgaxKV1/Iq4hiChM1tfaGuJkE X-Received: by 2002:a05:6808:6f91:b0:482:4741:5f57 with SMTP id 5614622812f47-4854a28a7c1mr1153869b6e.40.1779427224074; Thu, 21 May 2026 22:20:24 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:51 -0600 Subject: [PATCH v14 09/22] target/mips: add Octeon AES COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-9-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427308062158500 Add helper support for the Octeon AES operation selectors. Direct register-transfer selectors do not need helpers; the ECB/CBC encrypt and decrypt operations consume the AES input, key, IV, and key-length state. AESRESINP is modeled as one architectural register bank; operation helpers consume the current AESRESINP block and write the result back to the same bank. Signed-off-by: James Hilliard --- Changes v9 -> v10: - Drop the non-architectural AES input/result split. - Model AESRESINP as a single architectural input/result bank. Changes v8 -> v9: - Split AES operation selectors into their own COP2 helper patch. - Replace generic selector dispatch with per-operation AES helpers. - Add matching helper.h declarations with the helper implementation. --- target/mips/helper.h | 4 ++ target/mips/tcg/octeon_crypto.c | 145 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 149 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 7985083e6f..1ab644bab5 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -74,6 +74,10 @@ DEF_HELPER_2(octeon_cp2_mt_zuc_start, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_zuc_more, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_snow3g_start, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_snow3g_more, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_aes_enc_cbc1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_aes_enc1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_aes_dec_cbc1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_aes_dec1, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 2610f7224a..419f65bd29 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -887,6 +887,151 @@ static void octeon_snow3g_more(MIPSOcteonCryptoState = *crypto) octeon_snow3g_queue_result(crypto); } =20 +static int octeon_aes_key_bits(const MIPSOcteonCryptoState *crypto) +{ + enum { + OCTEON_AES_KEYLEN_128 =3D 1, + OCTEON_AES_KEYLEN_192 =3D 2, + OCTEON_AES_KEYLEN_256 =3D 3, + }; + + switch (crypto->aes_keylen) { + case OCTEON_AES_KEYLEN_128: + return 128; + case OCTEON_AES_KEYLEN_192: + return 192; + case OCTEON_AES_KEYLEN_256: + return 256; + default: + return 0; + } +} + +static void octeon_aes_load_key(const MIPSOcteonCryptoState *crypto, + uint8_t *key, size_t keylen) +{ + stq_be_p(key, crypto->aes_key[0]); + stq_be_p(key + 8, crypto->aes_key[1]); + if (keylen > 16) { + stq_be_p(key + 16, crypto->aes_key[2]); + } + if (keylen > 24) { + stq_be_p(key + 24, crypto->aes_key[3]); + } +} + +static void octeon_aes_load_block(const uint64_t regs[2], uint8_t *block) +{ + stq_be_p(block, regs[0]); + stq_be_p(block + 8, regs[1]); +} + +static void octeon_aes_store_block(uint64_t regs[2], const uint8_t *block) +{ + regs[0] =3D ldq_be_p(block); + regs[1] =3D ldq_be_p(block + 8); +} + +static void octeon_aes_encrypt_common(MIPSOcteonCryptoState *crypto, bool = cbc) +{ + AES_KEY key; + uint8_t in[16]; + uint8_t out[16]; + uint8_t iv[16]; + uint8_t raw_key[32] =3D {}; + int bits =3D octeon_aes_key_bits(crypto); + + if (!bits) { + return; + } + + octeon_aes_load_key(crypto, raw_key, bits / 8); + octeon_aes_load_block(crypto->aes_resinp, in); + if (cbc) { + int i; + + octeon_aes_load_block(crypto->aes_iv, iv); + for (i =3D 0; i < sizeof(in); i++) { + in[i] ^=3D iv[i]; + } + } + + AES_set_encrypt_key(raw_key, bits, &key); + AES_encrypt(in, out, &key); + octeon_aes_store_block(crypto->aes_resinp, out); + if (cbc) { + octeon_aes_store_block(crypto->aes_iv, out); + } +} + +static void octeon_aes_decrypt_common(MIPSOcteonCryptoState *crypto, bool = cbc) +{ + AES_KEY key; + uint8_t in[16]; + uint8_t out[16]; + uint8_t iv[16]; + uint8_t next_iv[16]; + uint8_t raw_key[32] =3D {}; + int bits =3D octeon_aes_key_bits(crypto); + int i; + + if (!bits) { + return; + } + + octeon_aes_load_key(crypto, raw_key, bits / 8); + octeon_aes_load_block(crypto->aes_resinp, in); + if (cbc) { + memcpy(next_iv, in, sizeof(next_iv)); + octeon_aes_load_block(crypto->aes_iv, iv); + } + + AES_set_decrypt_key(raw_key, bits, &key); + AES_decrypt(in, out, &key); + if (cbc) { + for (i =3D 0; i < sizeof(out); i++) { + out[i] ^=3D iv[i]; + } + } + + octeon_aes_store_block(crypto->aes_resinp, out); + if (cbc) { + octeon_aes_store_block(crypto->aes_iv, next_iv); + } +} + +void helper_octeon_cp2_mt_aes_enc_cbc1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_aes_encrypt_common(crypto, true); +} + +void helper_octeon_cp2_mt_aes_enc1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_aes_encrypt_common(crypto, false); +} + +void helper_octeon_cp2_mt_aes_dec_cbc1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_aes_decrypt_common(crypto, true); +} + +void helper_octeon_cp2_mt_aes_dec1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_aes_decrypt_common(crypto, false); +} + void helper_octeon_cp2_mt_snow3g_start(CPUMIPSState *env, uint64_t value) { octeon_snow3g_start(&env->octeon_crypto, value); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427260; cv=none; d=zohomail.com; s=zohoarc; b=DKjCg5RoctFSu1C3fibWpS+zIeqAhH33jwsLkogFZltzB4zFkl3v/gHSXm0kspXMf/eN6qiow1+idFnvBLQx5MJBWjMvVdjp57ykOVqgcBEzqkTGU766SbmYKTEgz/V7H6udAUuoaifBbH8UVnVJ4Hc5QT1KOWuWX1dC8H3OB1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427260; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W92ESlapdyO9qH3x4Uam7jTzjBzkYRQhK1ViYpc9r4U=; b=MmnNl/deAeeL1cgrmx6WbZlglRgpFl3qwGo94mgpei9nJKluZlV/5SRwgllM94+4HfufHIv8YQjIYnIODTEtrZTPoKn0XPOLcNzmXfXp6QjoUC7Kjz9iSD162FVbMUgCerGhSvT5nLmLZ4m+6aEBJYzCwEtG5CFMSvhW2o1vMeA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427260060343.00241712178297; Thu, 21 May 2026 22:21:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJC-0002YX-69; Fri, 22 May 2026 01:20:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJA-0002WU-Di for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:28 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJ8-0001wY-Gx for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:28 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-485433a6889so377142b6e.0 for ; Thu, 21 May 2026 22:20:26 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427225; x=1780032025; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=W92ESlapdyO9qH3x4Uam7jTzjBzkYRQhK1ViYpc9r4U=; b=g0kFnEtICc68hndhfnAOTp76m+as6uNmiIA3puVLLgLgAOmAQhqHxjXvOeJJZaDea2 WF96R7hn9t+pisfpucAIue9eZ4PyVGtUByOp8IE/IXYMcUtwv1pbE+KsbDn7J/M3MIEC YiYQ+jhhtiylIUuNnzjPRWuaTeEG03w/etg/Y8TttrdIA/nNgbR8fTwBWwE+zP2UCk14 MVvzxrs6eEc9WOMG54t08XhLIShb+w7a+OIBngt8R0r+ThbV6m5Hb0NrrrrAIY5mXv+T v71poduD466wfg5XqRy1FDvsKv0gik/3ihPlY+oC1QJp70Dwmkp8InoNc18Jy1RpsWaz h3YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427225; x=1780032025; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=W92ESlapdyO9qH3x4Uam7jTzjBzkYRQhK1ViYpc9r4U=; b=rsLXYH1NqG4+EXbnROF2tdoUhLp9qN1N40Rj46Ud/z+pMKNhTMAaliYz3VB4Mebg0B BC8hIsgw4lSUpVUubfHYwGOKmL9ZXsqSI9KOmh35DtmqmnBVKljFPHZ+/BYp0Jp/0LC1 l3mxkT3zlP2jyt6BRxHloMkK1/sPyC054o8fiDZukCC9jPDFEQfY1DNkOZFp1KzAMpRo eU0sjjLr6e3seXQnbBR8KGm9Fg+S7Vk+Mdd5lKPwU3t1jOW0/f3MAvoLIFGd5AW5P9UZ /tX86dG4LBxhkKP7Y/MfR3kpQwD/FKNZfMETmwViCHsXZi2dkhsFs4WYdWwjENAifgPW lD5Q== X-Gm-Message-State: AOJu0YzW8kItxx4hUEcp+xRLewIPyCgQhCOqQS1b7CALK35y7O9yT3C6 riGc5mJeru87/RNFC0sgxJZklt/avXNsxn0beubA8Ot9JUN4GIJzMFc6 X-Gm-Gg: Acq92OEYNdCAZJxo4o4TF6IAsBz3fDK35vKjeY2+HjDEYF5mlHBWzyEGzfA/JU0UDWx ngGsn6SSKiW5b67Pd/VqStd0SNbtVPmWfq+qcq5X9fhCZJsp4oXlixx6X0fwfhnKRTit5ydeYqV X6TmmB2+IPC9JNTSa1u+k56g1JoxsLOx3DWNQB7GEpM5qb7Iy86Fq4JUn5kevdwVS7NaZ+gjHVo H11qSb0Ym4bKOvj2Rw7JOqwde0WFO0IyRAcgKQnBH54bTwoR+t0DWVJ0aKu0vjujfIp95anflUk PMurDkkJIz4GN4kq0xaisWjZbYQ3fTvVgZG8oNnkO7Jy8IqpM9uWwqrT41csGTsxNNgmGqMg3NB qS2uDGAIPoTrNGiUBVX5ha5iHBsC6U258y/Cb6bosPy1yTBUpFVEhGPn30A5hq/GQcydr5yu7R6 mFDfjlIK50G8UUhussQDO+D+xx9T2BHWm+99LgsB/zDzrVNbuaKIE0QUdWbB60SeV9ecFqfNT4a w34FCiCm4Gay/rkFLW9sEHtRbxioXpXLwgd8o3uPRe5FpSyTBqp6MhRiq6Xr5wyv1E6 X-Received: by 2002:a05:6808:30a6:b0:479:dcb1:dce3 with SMTP id 5614622812f47-4854994df1emr1133049b6e.0.1779427225327; Thu, 21 May 2026 22:20:25 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:52 -0600 Subject: [PATCH v14 10/22] target/mips: add Octeon SMS4 COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-10-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427261876158500 Add helper support for the Octeon SMS4 operation selectors. SMS4 reuses the AES RESINP, IV, and key banks, so the helpers share the existing AES state while implementing the SMS4 ECB/CBC encrypt and decrypt operations. Signed-off-by: James Hilliard --- Changes v8 -> v9: - Split SMS4 operation selectors into their own COP2 helper patch. - Replace generic selector dispatch with per-operation SMS4 helpers. - Add matching helper.h declarations with the helper implementation. Changes v5 -> v6: - Use RESINP wording for the SMS4 shared selector aliases. Changes v1 -> v2: - Add selector dispatch updates in octeon_translate.c after moving COP2 decode out of translate.c. (suggested by Philippe Mathieu-Daud=C3=A9) --- target/mips/helper.h | 4 ++ target/mips/tcg/octeon_crypto.c | 124 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 128 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 1ab644bab5..64bb3ff8a5 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -78,6 +78,10 @@ DEF_HELPER_2(octeon_cp2_mt_aes_enc_cbc1, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_aes_enc1, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_aes_dec_cbc1, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_aes_dec1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sms4_enc_cbc1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sms4_enc1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sms4_dec_cbc1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_sms4_dec1, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 419f65bd29..64b553392a 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -1032,6 +1032,130 @@ void helper_octeon_cp2_mt_aes_dec1(CPUMIPSState *en= v, uint64_t value) octeon_aes_decrypt_common(crypto, false); } =20 +static inline uint32_t octeon_sms4_t(uint32_t x) +{ + x =3D sm4_subword(x); + return x ^ rol32(x, 2) ^ rol32(x, 10) ^ + rol32(x, 18) ^ rol32(x, 24); +} + +static inline uint32_t octeon_sms4_t_key(uint32_t x) +{ + x =3D sm4_subword(x); + return x ^ rol32(x, 13) ^ rol32(x, 23); +} + +static void octeon_sms4_expand_key(const uint8_t *key, uint32_t round_keys= [32]) +{ + static const uint32_t fk[4] =3D { + 0xa3b1bac6U, 0x56aa3350U, 0x677d9197U, 0xb27022dcU, + }; + uint32_t k[36]; + + for (int i =3D 0; i < 4; i++) { + k[i] =3D ldl_be_p(key + i * 4) ^ fk[i]; + } + for (int i =3D 0; i < 32; i++) { + k[i + 4] =3D k[i] ^ octeon_sms4_t_key(k[i + 1] ^ k[i + 2] ^ + k[i + 3] ^ sm4_ck[i]); + round_keys[i] =3D k[i + 4]; + } +} + +static void octeon_sms4_crypt_block(const uint8_t *in, uint8_t *out, + const uint32_t round_keys[32], + bool encrypt) +{ + uint32_t x[36]; + + for (int i =3D 0; i < 4; i++) { + x[i] =3D ldl_be_p(in + i * 4); + } + for (int i =3D 0; i < 32; i++) { + uint32_t rk =3D round_keys[encrypt ? i : 31 - i]; + + x[i + 4] =3D x[i] ^ octeon_sms4_t(x[i + 1] ^ x[i + 2] ^ + x[i + 3] ^ rk); + } + stl_be_p(out, x[35]); + stl_be_p(out + 4, x[34]); + stl_be_p(out + 8, x[33]); + stl_be_p(out + 12, x[32]); +} + +static void octeon_sms4_crypt_common(MIPSOcteonCryptoState *crypto, + bool encrypt, bool cbc) +{ + uint8_t key[16]; + uint8_t in[16]; + uint8_t out[16]; + uint8_t iv[16]; + uint8_t next_iv[16]; + uint32_t round_keys[32]; + + /* + * SMS4 aliases the AES state onto the RESINP, IV, and KEY banks, + * with only the operation selectors remaining distinct. + */ + octeon_aes_load_key(crypto, key, sizeof(key)); + octeon_aes_load_block(crypto->aes_resinp, in); + if (cbc) { + octeon_aes_load_block(crypto->aes_iv, iv); + if (encrypt) { + for (int i =3D 0; i < sizeof(in); i++) { + in[i] ^=3D iv[i]; + } + } else { + memcpy(next_iv, in, sizeof(next_iv)); + } + } + + octeon_sms4_expand_key(key, round_keys); + octeon_sms4_crypt_block(in, out, round_keys, encrypt); + if (cbc && !encrypt) { + for (int i =3D 0; i < sizeof(out); i++) { + out[i] ^=3D iv[i]; + } + } + + octeon_aes_store_block(crypto->aes_resinp, out); + if (cbc) { + octeon_aes_store_block(crypto->aes_iv, encrypt ? out : next_iv); + } +} + +void helper_octeon_cp2_mt_sms4_enc_cbc1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_sms4_crypt_common(crypto, true, true); +} + +void helper_octeon_cp2_mt_sms4_enc1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_sms4_crypt_common(crypto, true, false); +} + +void helper_octeon_cp2_mt_sms4_dec_cbc1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_sms4_crypt_common(crypto, false, true); +} + +void helper_octeon_cp2_mt_sms4_dec1(CPUMIPSState *env, uint64_t value) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->aes_resinp[1] =3D value; + octeon_sms4_crypt_common(crypto, false, false); +} + void helper_octeon_cp2_mt_snow3g_start(CPUMIPSState *env, uint64_t value) { octeon_snow3g_start(&env->octeon_crypto, value); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427417; cv=none; d=zohomail.com; s=zohoarc; b=iI6QLPhFwj8oV40xnsvl0JrYgw4bHYNpZB/aCJDixMEi24F97UAaCxrLzt/PwqjsQgc7maB8O7ZYBnY4PH/6yVO7tfRcZ9BCpwIT8/7b9NbHEiGfXVuhoMXYA9hcSHcunOPWQoiB+CVqcQmf8XnHawxWTLEXbgxZOtSq5uFvq+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427417; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KCMCwSrvPApDaTT/eK8226LssVWE0QxPTwRU0tAy9hs=; b=Y9RU9q+dWAfC+hj7gVNRheNypUPXWdKfpAhT97uc0Sm4LxfEHClwh2VQIlhoRhyL/t1ge8izpIGUEsIF5lHP/g47Vf2bTksHJ347nRD9MsG3Pvew7gEyCWGNLRKI3NcvGcUlRa3S29GWd1Sgryi7dEOn5IrML2r0FXtK+7oLrCs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427417007476.3775184326988; Thu, 21 May 2026 22:23:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJE-0002b1-DO; Fri, 22 May 2026 01:20:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJC-0002Yr-RQ for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:30 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJA-00020c-11 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:30 -0400 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-47c7b282e21so2866517b6e.1 for ; Thu, 21 May 2026 22:20:27 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427227; x=1780032027; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KCMCwSrvPApDaTT/eK8226LssVWE0QxPTwRU0tAy9hs=; b=BzLCD5DcnTTYQD7/NMoFqTKuVj6Sz+B2NMJTvTDfrneapYXjf2IJBeV37lXPQAp8dl 9JzEJW2eIyzuQ36gSd8jdxFwe6aTQj9JgKTu7Nj0Mtzr6mrgN4eY7X0kpwg9GNqAgEPV /yaINoPT5odi+mFPovkQ5R8ROfRYhnYGkWCw5XegLF2Mp8ZrZgllHIPZOrMehaEtzhbJ EuXKllwmhFZXTmUeTMBcwLSfAWidyyockHNkDRXlDauEmpj7VwO7ueUFQY+5aD1F6WIG oKCQQy1U7pejvxwDtMidYOEtcxlPBNsX8O56sN+2tnWsKYCrdpz19f2EAdr7dtI5wgXN HUNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427227; x=1780032027; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=KCMCwSrvPApDaTT/eK8226LssVWE0QxPTwRU0tAy9hs=; b=JkPCOn8iEbnPPnlUgSLhb4jJKUUmdlwFYuCkRd3CL1Dr5JpoATIHJinuc3f7L30fxk s6cvXqShNyQZUPLSuVV2uwQ0tOfDV+NbKATPHkC/CIzuzaRddtc1wNFRDRqDsJncLxuu fWnmjKzlxrBfcqWfcAj8dcd8R8Pio41RGrOphy40kC4p2jE8/2FiaYjOq9rznLFsNQRj aavD38Spnmy1X+r/VwiYlssgh9FIJXpRIE6I2SHJqiBHl5Zx+QdxYFWWjMrifHWWJ0lr U6bhXS4U7NjN//9xcMeOMU8Di2Rqn4QQyZLB8uKRYwqVoBHLqGVwp8nzIXUg8Zk3k/zF RpdA== X-Gm-Message-State: AOJu0YzxVCNnWQEYSwR/SOGeIr/g7FHndRZr04sQOGaKv9Ob24O5QETG JeVfuykifEOm8cWNwAHdhCzeeXXPVWVamXZxnPm5AuK3BeenoB9Ati42 X-Gm-Gg: Acq92OE/52m0U3ZIZcEmr8E+h2g5v1QGQrrLvVU+l8jBa6YUruOlVnP9t5f9TzI/4XJ 4Nk00P1PmNC6XHCVGsIhvEPDsFBFR4clooH7do9G5x2dVDbHMVpGNO7gjIDbwaUQjmDLqJreMe+ Tw+rpnDWmScPG4Sg0wJj48hKJSBzenFjVnGgmbkOs0t6Mubc3Gcc8BeVULjgz5RF+osQJRDSKxT wQhOoxQYBikBeb155BPwSXJj/Eh58jA/DlYRyx4gPpamV8d3HlncaHkLZRnuorN7/5iqBX4zCqN zUsOkOaPQbcuZXV8KaHrHxMpE+9ASK1OnwBtNzhXN+/flWHuk8PF23qOu9fAYoL5OW1eIrjL36O 6tc1v44toH3k0DwlRcKFfAhGZhwDJbBhbfcnG/kT7Qt0wdWK/tSvRohRaJDXfOGi+p/aTTDAtmG 1u8wRtwEqrwe4KdcWUbIigPYjNF6gYUT2SkiMsc7FaCUB0Q5sz0CJeONJYW8H/gdvDXhYdrCpZM AIQp8wC3UUv24yI8jatQhgu81pxrah/RbSUkMAK3d2NCjaJxbD3p+AnbdxU4dwXBZMcZ7yPX1FF zBY= X-Received: by 2002:a05:6808:1b10:b0:479:dc28:b71f with SMTP id 5614622812f47-4854a3f312dmr1134796b6e.40.1779427226674; Thu, 21 May 2026 22:20:26 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:53 -0600 Subject: [PATCH v14 11/22] target/mips: add Octeon 3DES and KASUMI COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-11-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427418457158500 Add helper support for the Octeon 3DES and KASUMI operation selectors. The 3DES helpers implement ECB and CBC encrypt/decrypt over the shared 3DES key, IV, and result bank. KASUMI reuses the same register bank and adds its own encrypt selectors. Only the operation selectors require helper code. Simple key, IV, and result register transfers are handled by direct selector decode. Signed-off-by: James Hilliard --- Changes v8 -> v9: - Split 3DES/KASUMI operation selectors into their own COP2 helper patch. - Replace generic selector dispatch with per-operation 3DES/KASUMI helpers. - Add matching helper.h declarations with the helper implementation. --- target/mips/helper.h | 6 + target/mips/tcg/octeon_crypto.c | 458 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 464 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 64bb3ff8a5..444eeeb3ec 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -82,6 +82,12 @@ DEF_HELPER_2(octeon_cp2_mt_sms4_enc_cbc1, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_sms4_enc1, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_sms4_dec_cbc1, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_sms4_dec1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_des3_enc_cbc, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_kas_enc_cbc, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_des3_enc, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_kas_enc, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_des3_dec_cbc, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_des3_dec, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 64b553392a..893f55d1e5 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -1156,6 +1156,464 @@ void helper_octeon_cp2_mt_sms4_dec1(CPUMIPSState *e= nv, uint64_t value) octeon_sms4_crypt_common(crypto, false, false); } =20 +static const uint8_t octeon_des_ip[64] =3D { + 58, 50, 42, 34, 26, 18, 10, 2, + 60, 52, 44, 36, 28, 20, 12, 4, + 62, 54, 46, 38, 30, 22, 14, 6, + 64, 56, 48, 40, 32, 24, 16, 8, + 57, 49, 41, 33, 25, 17, 9, 1, + 59, 51, 43, 35, 27, 19, 11, 3, + 61, 53, 45, 37, 29, 21, 13, 5, + 63, 55, 47, 39, 31, 23, 15, 7, +}; + +static const uint8_t octeon_des_fp[64] =3D { + 40, 8, 48, 16, 56, 24, 64, 32, + 39, 7, 47, 15, 55, 23, 63, 31, + 38, 6, 46, 14, 54, 22, 62, 30, + 37, 5, 45, 13, 53, 21, 61, 29, + 36, 4, 44, 12, 52, 20, 60, 28, + 35, 3, 43, 11, 51, 19, 59, 27, + 34, 2, 42, 10, 50, 18, 58, 26, + 33, 1, 41, 9, 49, 17, 57, 25, +}; + +static const uint8_t octeon_des_e[48] =3D { + 32, 1, 2, 3, 4, 5, + 4, 5, 6, 7, 8, 9, + 8, 9, 10, 11, 12, 13, + 12, 13, 14, 15, 16, 17, + 16, 17, 18, 19, 20, 21, + 20, 21, 22, 23, 24, 25, + 24, 25, 26, 27, 28, 29, + 28, 29, 30, 31, 32, 1, +}; + +static const uint8_t octeon_des_p[32] =3D { + 16, 7, 20, 21, 29, 12, 28, 17, + 1, 15, 23, 26, 5, 18, 31, 10, + 2, 8, 24, 14, 32, 27, 3, 9, + 19, 13, 30, 6, 22, 11, 4, 25, +}; + +static const uint8_t octeon_des_pc1[56] =3D { + 57, 49, 41, 33, 25, 17, 9, + 1, 58, 50, 42, 34, 26, 18, + 10, 2, 59, 51, 43, 35, 27, + 19, 11, 3, 60, 52, 44, 36, + 63, 55, 47, 39, 31, 23, 15, + 7, 62, 54, 46, 38, 30, 22, + 14, 6, 61, 53, 45, 37, 29, + 21, 13, 5, 28, 20, 12, 4, +}; + +static const uint8_t octeon_des_pc2[48] =3D { + 14, 17, 11, 24, 1, 5, + 3, 28, 15, 6, 21, 10, + 23, 19, 12, 4, 26, 8, + 16, 7, 27, 20, 13, 2, + 41, 52, 31, 37, 47, 55, + 30, 40, 51, 45, 33, 48, + 44, 49, 39, 56, 34, 53, + 46, 42, 50, 36, 29, 32, +}; + +static const uint8_t octeon_des_rotations[16] =3D { + 1, 1, 2, 2, 2, 2, 2, 2, + 1, 2, 2, 2, 2, 2, 2, 1, +}; + +static const uint8_t octeon_des_sboxes[8][64] =3D { + { + 14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7, + 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8, + 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0, + 15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13, + }, + { + 15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10, + 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5, + 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15, + 13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9, + }, + { + 10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8, + 13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1, + 13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7, + 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12, + }, + { + 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15, + 13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9, + 10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4, + 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14, + }, + { + 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9, + 14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6, + 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14, + 11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3, + }, + { + 12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11, + 10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8, + 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6, + 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13, + }, + { + 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1, + 13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6, + 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2, + 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12, + }, + { + 13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7, + 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2, + 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8, + 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11, + }, +}; + +static const uint8_t octeon_kasumi_s7[128] =3D { + 54, 50, 62, 56, 22, 34, 94, 96, 38, 6, 63, 93, 2, 18, + 123, 33, 55, 113, 39, 114, 21, 67, 65, 12, 47, 73, 46, 27, + 25, 111, 124, 81, 53, 9, 121, 79, 52, 60, 58, 48, 101, 127, + 40, 120, 104, 70, 71, 43, 20, 122, 72, 61, 23, 109, 13, 100, + 77, 1, 16, 7, 82, 10, 105, 98, 117, 116, 76, 11, 89, 106, + 0, 125, 118, 99, 86, 69, 30, 57, 126, 87, 112, 51, 17, 5, + 95, 14, 90, 84, 91, 8, 35, 103, 32, 97, 28, 66, 102, 31, + 26, 45, 75, 4, 85, 92, 37, 74, 80, 49, 68, 29, 115, 44, + 64, 107, 108, 24, 110, 83, 36, 78, 42, 19, 15, 41, 88, 119, + 59, 3, +}; + +static const uint16_t octeon_kasumi_s9[512] =3D { + 167, 239, 161, 379, 391, 334, 9, 338, 38, 226, 48, 358, 452, 385, + 90, 397, 183, 253, 147, 331, 415, 340, 51, 362, 306, 500, 262, 82, + 216, 159, 356, 177, 175, 241, 489, 37, 206, 17, 0, 333, 44, 254, + 378, 58, 143, 220, 81, 400, 95, 3, 315, 245, 54, 235, 218, 405, + 472, 264, 172, 494, 371, 290, 399, 76, 165, 197, 395, 121, 257, 480, + 423, 212, 240, 28, 462, 176, 406, 507, 288, 223, 501, 407, 249, 265, + 89, 186, 221, 428, 164, 74, 440, 196, 458, 421, 350, 163, 232, 158, + 134, 354, 13, 250, 491, 142, 191, 69, 193, 425, 152, 227, 366, 135, + 344, 300, 276, 242, 437, 320, 113, 278, 11, 243, 87, 317, 36, 93, + 496, 27, 487, 446, 482, 41, 68, 156, 457, 131, 326, 403, 339, 20, + 39, 115, 442, 124, 475, 384, 508, 53, 112, 170, 479, 151, 126, 169, + 73, 268, 279, 321, 168, 364, 363, 292, 46, 499, 393, 327, 324, 24, + 456, 267, 157, 460, 488, 426, 309, 229, 439, 506, 208, 271, 349, 401, + 434, 236, 16, 209, 359, 52, 56, 120, 199, 277, 465, 416, 252, 287, + 246, 6, 83, 305, 420, 345, 153, 502, 65, 61, 244, 282, 173, 222, + 418, 67, 386, 368, 261, 101, 476, 291, 195, 430, 49, 79, 166, 330, + 280, 383, 373, 128, 382, 408, 155, 495, 367, 388, 274, 107, 459, 417, + 62, 454, 132, 225, 203, 316, 234, 14, 301, 91, 503, 286, 424, 211, + 347, 307, 140, 374, 35, 103, 125, 427, 19, 214, 453, 146, 498, 314, + 444, 230, 256, 329, 198, 285, 50, 116, 78, 410, 10, 205, 510, 171, + 231, 45, 139, 467, 29, 86, 505, 32, 72, 26, 342, 150, 313, 490, + 431, 238, 411, 325, 149, 473, 40, 119, 174, 355, 185, 233, 389, 71, + 448, 273, 372, 55, 110, 178, 322, 12, 469, 392, 369, 190, 1, 109, + 375, 137, 181, 88, 75, 308, 260, 484, 98, 272, 370, 275, 412, 111, + 336, 318, 4, 504, 492, 259, 304, 77, 337, 435, 21, 357, 303, 332, + 483, 18, 47, 85, 25, 497, 474, 289, 100, 269, 296, 478, 270, 106, + 31, 104, 433, 84, 414, 486, 394, 96, 99, 154, 511, 148, 413, 361, + 409, 255, 162, 215, 302, 201, 266, 351, 343, 144, 441, 365, 108, 298, + 251, 34, 182, 509, 138, 210, 335, 133, 311, 352, 328, 141, 396, 346, + 123, 319, 450, 281, 429, 228, 443, 481, 92, 404, 485, 422, 248, 297, + 23, 213, 130, 466, 22, 217, 283, 70, 294, 360, 419, 127, 312, 377, + 7, 468, 194, 2, 117, 295, 463, 258, 224, 447, 247, 187, 80, 398, + 284, 353, 105, 390, 299, 471, 470, 184, 57, 200, 348, 63, 204, 188, + 33, 451, 97, 30, 310, 219, 94, 160, 129, 493, 64, 179, 263, 102, + 189, 207, 114, 402, 438, 477, 387, 122, 192, 42, 381, 5, 145, 118, + 180, 449, 293, 323, 136, 380, 43, 66, 60, 455, 341, 445, 202, 432, + 8, 237, 15, 376, 436, 464, 59, 461, +}; + +static const uint16_t octeon_kasumi_constants[8] =3D { + 0x0123, 0x4567, 0x89ab, 0xcdef, 0xfedc, 0xba98, 0x7654, 0x3210, +}; + +typedef struct OcteonKasumiSubkeys { + uint16_t kli1[8]; + uint16_t kli2[8]; + uint16_t koi1[8]; + uint16_t koi2[8]; + uint16_t koi3[8]; + uint16_t kii1[8]; + uint16_t kii2[8]; + uint16_t kii3[8]; +} OcteonKasumiSubkeys; + +static uint64_t octeon_des_permute(uint64_t input, const uint8_t *table, + size_t output_bits, size_t input_bits) +{ + uint64_t out =3D 0; + + for (size_t i =3D 0; i < output_bits; i++) { + unsigned src =3D table[i] - 1; + + out =3D (out << 1) | ((input >> (input_bits - 1 - src)) & 1); + } + return out; +} + +static uint32_t octeon_des_rotate28(uint32_t v, unsigned shift) +{ + return ((v << shift) | (v >> (28 - shift))) & 0x0fffffffU; +} + +static void octeon_des_expand_subkeys(uint64_t key, uint64_t subkeys[16]) +{ + uint64_t permuted =3D octeon_des_permute(key, octeon_des_pc1, + ARRAY_SIZE(octeon_des_pc1), 64); + uint32_t c =3D (permuted >> 28) & 0x0fffffffU; + uint32_t d =3D permuted & 0x0fffffffU; + + for (int i =3D 0; i < 16; i++) { + c =3D octeon_des_rotate28(c, octeon_des_rotations[i]); + d =3D octeon_des_rotate28(d, octeon_des_rotations[i]); + subkeys[i] =3D octeon_des_permute(((uint64_t)c << 28) | d, + octeon_des_pc2, + ARRAY_SIZE(octeon_des_pc2), 56); + } +} + +static uint32_t octeon_des_f(uint32_t r, uint64_t subkey) +{ + uint64_t expanded =3D octeon_des_permute(r, octeon_des_e, + ARRAY_SIZE(octeon_des_e), 32); + uint32_t out =3D 0; + + expanded ^=3D subkey; + for (int i =3D 0; i < 8; i++) { + uint8_t sextet =3D (expanded >> (42 - i * 6)) & 0x3f; + uint8_t row =3D ((sextet & 0x20) >> 4) | (sextet & 0x01); + uint8_t col =3D (sextet >> 1) & 0x0f; + + out =3D (out << 4) | octeon_des_sboxes[i][row * 16 + col]; + } + + return octeon_des_permute(out, octeon_des_p, ARRAY_SIZE(octeon_des_p),= 32); +} + +static uint64_t octeon_des_block_crypt(uint64_t block, uint64_t key, + bool encrypt) +{ + uint64_t subkeys[16]; + uint64_t permuted =3D octeon_des_permute(block, octeon_des_ip, + ARRAY_SIZE(octeon_des_ip), 64); + uint32_t l =3D permuted >> 32; + uint32_t r =3D permuted; + + octeon_des_expand_subkeys(key, subkeys); + + for (int i =3D 0; i < 16; i++) { + uint32_t next =3D l ^ octeon_des_f(r, subkeys[encrypt ? i : 15 - i= ]); + + l =3D r; + r =3D next; + } + + return octeon_des_permute(((uint64_t)r << 32) | l, + octeon_des_fp, ARRAY_SIZE(octeon_des_fp), 64= ); +} + +static uint64_t octeon_3des_block_crypt(uint64_t block, const uint64_t key= s[3], + bool encrypt) +{ + if (encrypt) { + block =3D octeon_des_block_crypt(block, keys[0], true); + block =3D octeon_des_block_crypt(block, keys[1], false); + block =3D octeon_des_block_crypt(block, keys[2], true); + } else { + block =3D octeon_des_block_crypt(block, keys[2], false); + block =3D octeon_des_block_crypt(block, keys[1], true); + block =3D octeon_des_block_crypt(block, keys[0], false); + } + return block; +} + +static void octeon_3des_crypt_common(MIPSOcteonCryptoState *crypto, + uint64_t input_reg, + bool encrypt, bool cbc) +{ + const uint64_t keys[3] =3D { + crypto->des3_key[0], + crypto->des3_key[1], + crypto->des3_key[2], + }; + uint64_t block =3D input_reg; + + if (cbc) { + if (encrypt) { + block ^=3D crypto->des3_iv; + block =3D octeon_3des_block_crypt(block, keys, true); + crypto->des3_iv =3D block; + } else { + block =3D octeon_3des_block_crypt(block, keys, false); + block ^=3D crypto->des3_iv; + crypto->des3_iv =3D input_reg; + } + } else { + block =3D octeon_3des_block_crypt(block, keys, encrypt); + } + + crypto->des3_result =3D block; +} + +static inline uint16_t octeon_rol16(uint16_t value, unsigned int bits) +{ + return (value << bits) | (value >> (16 - bits)); +} + +static void octeon_kasumi_key_schedule(const uint64_t key_regs[2], + OcteonKasumiSubkeys *subkeys) +{ + uint16_t key[8]; + uint16_t key_prime[8]; + + key[0] =3D key_regs[0] >> 48; + key[1] =3D key_regs[0] >> 32; + key[2] =3D key_regs[0] >> 16; + key[3] =3D key_regs[0]; + key[4] =3D key_regs[1] >> 48; + key[5] =3D key_regs[1] >> 32; + key[6] =3D key_regs[1] >> 16; + key[7] =3D key_regs[1]; + + for (int i =3D 0; i < 8; i++) { + key_prime[i] =3D key[i] ^ octeon_kasumi_constants[i]; + } + + for (int i =3D 0; i < 8; i++) { + subkeys->kli1[i] =3D octeon_rol16(key[i], 1); + subkeys->kli2[i] =3D key_prime[(i + 2) & 7]; + subkeys->koi1[i] =3D octeon_rol16(key[(i + 1) & 7], 5); + subkeys->koi2[i] =3D octeon_rol16(key[(i + 5) & 7], 8); + subkeys->koi3[i] =3D octeon_rol16(key[(i + 6) & 7], 13); + subkeys->kii1[i] =3D key_prime[(i + 4) & 7]; + subkeys->kii2[i] =3D key_prime[(i + 3) & 7]; + subkeys->kii3[i] =3D key_prime[(i + 7) & 7]; + } +} + +static uint16_t octeon_kasumi_fi(uint16_t in, uint16_t subkey) +{ + uint16_t nine =3D in >> 7; + uint16_t seven =3D in & 0x7f; + + nine =3D octeon_kasumi_s9[nine] ^ seven; + seven =3D octeon_kasumi_s7[seven] ^ (nine & 0x7f); + seven ^=3D subkey >> 9; + nine ^=3D subkey & 0x1ff; + nine =3D octeon_kasumi_s9[nine] ^ seven; + seven =3D octeon_kasumi_s7[seven] ^ (nine & 0x7f); + return (seven << 9) | nine; +} + +static uint32_t octeon_kasumi_fo(uint32_t in, int index, + const OcteonKasumiSubkeys *subkeys) +{ + uint16_t left =3D in >> 16; + uint16_t right =3D in; + + left ^=3D subkeys->koi1[index]; + left =3D octeon_kasumi_fi(left, subkeys->kii1[index]); + left ^=3D right; + right ^=3D subkeys->koi2[index]; + right =3D octeon_kasumi_fi(right, subkeys->kii2[index]); + right ^=3D left; + left ^=3D subkeys->koi3[index]; + left =3D octeon_kasumi_fi(left, subkeys->kii3[index]); + left ^=3D right; + + return ((uint32_t)right << 16) | left; +} + +static uint32_t octeon_kasumi_fl(uint32_t in, int index, + const OcteonKasumiSubkeys *subkeys) +{ + uint16_t left =3D in >> 16; + uint16_t right =3D in; + uint16_t a =3D left & subkeys->kli1[index]; + uint16_t b; + + right ^=3D octeon_rol16(a, 1); + b =3D right | subkeys->kli2[index]; + left ^=3D octeon_rol16(b, 1); + return ((uint32_t)left << 16) | right; +} + +static uint64_t octeon_kasumi_block_encrypt(uint64_t block, + const uint64_t key_regs[2]) +{ + OcteonKasumiSubkeys subkeys; + uint32_t left =3D block >> 32; + uint32_t right =3D block; + + octeon_kasumi_key_schedule(key_regs, &subkeys); + + for (int i =3D 0; i < 8; ) { + uint32_t temp =3D octeon_kasumi_fl(left, i, &subkeys); + + temp =3D octeon_kasumi_fo(temp, i++, &subkeys); + right ^=3D temp; + temp =3D octeon_kasumi_fo(right, i, &subkeys); + temp =3D octeon_kasumi_fl(temp, i++, &subkeys); + left ^=3D temp; + } + + return ((uint64_t)left << 32) | right; +} + +static void octeon_kasumi_crypt_common(MIPSOcteonCryptoState *crypto, + uint64_t input_reg, bool cbc) +{ + const uint64_t key_regs[2] =3D { + crypto->des3_key[0], + crypto->des3_key[1], + }; + uint64_t block =3D input_reg; + + if (cbc) { + block ^=3D crypto->des3_iv; + } + + block =3D octeon_kasumi_block_encrypt(block, key_regs); + if (cbc) { + crypto->des3_iv =3D block; + } + crypto->des3_result =3D block; +} + +void helper_octeon_cp2_mt_des3_enc_cbc(CPUMIPSState *env, uint64_t value) +{ + octeon_3des_crypt_common(&env->octeon_crypto, value, true, true); +} + +void helper_octeon_cp2_mt_kas_enc_cbc(CPUMIPSState *env, uint64_t value) +{ + octeon_kasumi_crypt_common(&env->octeon_crypto, value, true); +} + +void helper_octeon_cp2_mt_des3_enc(CPUMIPSState *env, uint64_t value) +{ + octeon_3des_crypt_common(&env->octeon_crypto, value, true, false); +} + +void helper_octeon_cp2_mt_kas_enc(CPUMIPSState *env, uint64_t value) +{ + octeon_kasumi_crypt_common(&env->octeon_crypto, value, false); +} + +void helper_octeon_cp2_mt_des3_dec_cbc(CPUMIPSState *env, uint64_t value) +{ + octeon_3des_crypt_common(&env->octeon_crypto, value, false, true); +} + +void helper_octeon_cp2_mt_des3_dec(CPUMIPSState *env, uint64_t value) +{ + octeon_3des_crypt_common(&env->octeon_crypto, value, false, false); +} + void helper_octeon_cp2_mt_snow3g_start(CPUMIPSState *env, uint64_t value) { octeon_snow3g_start(&env->octeon_crypto, value); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427403; cv=none; d=zohomail.com; s=zohoarc; b=fiHgNplpC/DOA6WGY4mWh6ELTvSsDA1I8XP9XAleM7uqNgHkx+lmgnospXdheccUYE6dxMd8ZumAaWvkHINbmSh8yxJ6jMhIXIbf+IAhL7HeBwzwJsSdqzf0cLyTCA2E+8LKpe55QveG8ozJlB4mj/aRBNGcHdk/yvYILtX4Zjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427403; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1/wDEtjpU6/JQCX42z91k/04b23uAyh66zeRkKaauFU=; b=EitMYd0CPn/txhbdbJDVwNULkmy+EwXZmL9qYkhAPBewPACLh69FTMUpWIJFUK0qrz+MjKdZ5lB0k8YoI3r40Fm4jnsWhBOEIsHtBZ9TU/Xc0xaPMizlGbxwYjNV8d1v11HdP1URll6ess53Iz1g4rHR+w9WTPnEUuPPzADtvSc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177942740354894.84561772425172; Thu, 21 May 2026 22:23:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJE-0002bJ-Ri; Fri, 22 May 2026 01:20:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJD-0002Za-DJ for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:31 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJB-00022x-I7 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:31 -0400 Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-4854d5cc708so266423b6e.2 for ; Thu, 21 May 2026 22:20:29 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427228; x=1780032028; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1/wDEtjpU6/JQCX42z91k/04b23uAyh66zeRkKaauFU=; b=Lfj8j9nK8YTPg5dw0vmYfcPLfsuGSjidlNJcGVY1insTd6Dle5dW9z40VzCc+sQOnU 20gYBggzAbH408msbY9VIFdBn0S+lfQmIW3Sm5LK2hSwGfva1ZZv1ZZi70kda+yQ9RfQ g+XBicWgwUTc7Z1cggHA9Dp70U46NTkN4aUfdHn21Pho3/dyK8AweoaGZhQTXtrh6CCZ gJNZU/kgRNoP5Tnk1VYkinf63sZjxLhccRwOR/e3YjWHHPKFUJxaHsDhkpn57TgeZnkZ +hWbOInJRBgraoBlN8NYTUUmHnfekLuvoieNBUCBS5hIHmWACa3Gj4Vp9lbiPGIRNLgF T+nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427228; x=1780032028; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1/wDEtjpU6/JQCX42z91k/04b23uAyh66zeRkKaauFU=; b=SgVXF9tAubEw8Z1rH+xwpPgF3vDJ/QjvHzzhJP9D2CTFUUVVsWVPTZFxbP6d4djldK S2VqZ4aG4uGdRYG2iBy5+rKmZWfYJBF1NoCoRMhBUi7SZAefG7f0X/aecbBCLdEfpOu7 c9VpGgcohYv9xYztMNSlW202pXIRwHOtKUGpW7PtV3saJ/vwseYXy0Gy2VZvKCIJ8nfe rTgXTHyPSA7xCqrwoIG7powkXsSTQlQXfYikyp6W8xweoNRjPrYLRdYT3t4Dd8gCSnR6 QF+SoMnqgH60HLxq9qTLVy7PJnJunzShKnTd0ICBAaj98aMBiRt6UNqoVYOZMp+j+kIH KDmw== X-Gm-Message-State: AOJu0YxNS2DvS7y6FR/ggV7NCiobmIfpPuxQhgukwOu2HGKWhxpJLApq gMcm+PDhT+EkZ5NclX/Lroxk1G7Bvw0VNRnPozjd4ErFvuKfBb8vT6t1 X-Gm-Gg: Acq92OELYeq4y8dpRx1r1xXkbsrj3IJ/nJZZvNuSnN4iMh4ygTj/ICMuwoIfbMPdHNd ewQzfhuCKvy8nc8vJPZ3zobKgVOr1SVX5OVK9Al60spu2FoikRuWAcyCaPOpK0x/f2mzRlbYH0g Y6jLn6m5p5cDcrwk5JQHXx9QrczBvGUzwQyU4R5KrOP+zdIZL6W69Vajqz+V4SksB/bipo+b9wC yHdt5pPIxuiIm27qYhh9oNsZml/vfKl8buoMSg9EHdysKzi6cw34CwOsnY+cRxwXgxFfsNEVGgY Yd/T285gO06fqKRt4X2SiAJSMPe9cEbmXD2tvSi9U5mnjtC8VLhDl2vUlIslXhCnMjQjkAc5egP fgp0FIQbrNkM53UTEpzYlc525lQ/Xrynu3QJ3kpj7EQ4n8d1U3o877CX0F6WJmVuZnXdSv8qFoX UpoWOrTupT/cJ9gfb0B/7rki3kAEE7DRZVaKVL7zATnObZnE48beehC9TMEt2MhaVpTGbGMlEAy mBJeb68u3IE16wAt7QvUpheFXqmScLNd/pkHeFkSNsMM3E0JBTg/S4zTcKpfOpFWXtRHYfiNORT oDpNxNe2A4c/SA== X-Received: by 2002:a05:6808:1b10:b0:482:6b96:5ad0 with SMTP id 5614622812f47-4854a3f730cmr1132095b6e.26.1779427228224; Thu, 21 May 2026 22:20:28 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:54 -0600 Subject: [PATCH v14 12/22] target/mips: add Octeon Camellia COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-12-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427404440158500 Add helper support for the Octeon Camellia ROUND, FL, and FLINV selectors. The engine reuses the AES RESINP bank, and guest-managed key schedules drive the Camellia F-function and FL layers through these COP2 operations. Implement the Camellia F-function and FL layers directly from RFC 3713. Signed-off-by: James Hilliard --- Changes v8 -> v9: - Split Camellia operation selectors into their own COP2 helper patch. - Replace generic selector dispatch with per-operation Camellia helpers. - Add matching helper.h declarations with the helper implementation. Changes v5 -> v6: - Use RESINP wording for the Camellia shared selector aliases. Changes v1 -> v2: - Drop the Octeon prefix from generic Camellia helper routines. (suggested by Philippe Mathieu-Daud=C3=A9) - Add selector dispatch updates in octeon_translate.c after moving COP2 decode out of translate.c. (suggested by Philippe Mathieu-Daud=C3=A9) --- target/mips/helper.h | 3 + target/mips/tcg/octeon_crypto.c | 126 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 129 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 444eeeb3ec..fbf8250932 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -88,6 +88,9 @@ DEF_HELPER_2(octeon_cp2_mt_des3_enc, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_kas_enc, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_des3_dec_cbc, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_des3_dec, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_camellia_fl, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_camellia_flinv, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_camellia_round, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 893f55d1e5..5bb21098fc 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -1614,6 +1614,132 @@ void helper_octeon_cp2_mt_des3_dec(CPUMIPSState *en= v, uint64_t value) octeon_3des_crypt_common(&env->octeon_crypto, value, false, false); } =20 +static const uint8_t camellia_sbox1[256] =3D { + 112, 130, 44, 236, 179, 39, 192, 229, 228, 133, 87, 53, 234, 12, + 174, 65, 35, 239, 107, 147, 69, 25, 165, 33, 237, 14, 79, 78, + 29, 101, 146, 189, 134, 184, 175, 143, 124, 235, 31, 206, 62, 48, + 220, 95, 94, 197, 11, 26, 166, 225, 57, 202, 213, 71, 93, 61, + 217, 1, 90, 214, 81, 86, 108, 77, 139, 13, 154, 102, 251, 204, + 176, 45, 116, 18, 43, 32, 240, 177, 132, 153, 223, 76, 203, 194, + 52, 126, 118, 5, 109, 183, 169, 49, 209, 23, 4, 215, 20, 88, + 58, 97, 222, 27, 17, 28, 50, 15, 156, 22, 83, 24, 242, 34, + 254, 68, 207, 178, 195, 181, 122, 145, 36, 8, 232, 168, 96, 252, + 105, 80, 170, 208, 160, 125, 161, 137, 98, 151, 84, 91, 30, 149, + 224, 255, 100, 210, 16, 196, 0, 72, 163, 247, 117, 219, 138, 3, + 230, 218, 9, 63, 221, 148, 135, 92, 131, 2, 205, 74, 144, 51, + 115, 103, 246, 243, 157, 127, 191, 226, 82, 155, 216, 38, 200, 55, + 198, 59, 129, 150, 111, 75, 19, 190, 99, 46, 233, 121, 167, 140, + 159, 110, 188, 142, 41, 245, 249, 182, 47, 253, 180, 89, 120, 152, + 6, 106, 231, 70, 113, 186, 212, 37, 171, 66, 136, 162, 141, 250, + 114, 7, 185, 85, 248, 238, 172, 10, 54, 73, 42, 104, 60, 56, + 241, 164, 64, 40, 211, 123, 187, 201, 67, 193, 21, 227, 173, 244, + 119, 199, 128, 158, +}; + +static inline uint8_t camellia_rotl8(uint8_t v, unsigned int shift) +{ + return (v << shift) | (v >> (8 - shift)); +} + +static inline uint8_t camellia_sbox2(uint8_t x) +{ + return camellia_rotl8(camellia_sbox1[x], 1); +} + +static inline uint8_t camellia_sbox3(uint8_t x) +{ + return camellia_rotl8(camellia_sbox1[x], 7); +} + +static inline uint8_t camellia_sbox4(uint8_t x) +{ + return camellia_sbox1[camellia_rotl8(x, 1)]; +} + +static uint64_t camellia_f(uint64_t input, uint64_t key) +{ + uint64_t x =3D input ^ key; + uint8_t t1 =3D camellia_sbox1[x >> 56]; + uint8_t t2 =3D camellia_sbox2((x >> 48) & 0xff); + uint8_t t3 =3D camellia_sbox3((x >> 40) & 0xff); + uint8_t t4 =3D camellia_sbox4((x >> 32) & 0xff); + uint8_t t5 =3D camellia_sbox2((x >> 24) & 0xff); + uint8_t t6 =3D camellia_sbox3((x >> 16) & 0xff); + uint8_t t7 =3D camellia_sbox4((x >> 8) & 0xff); + uint8_t t8 =3D camellia_sbox1[x & 0xff]; + uint8_t y1 =3D t1 ^ t3 ^ t4 ^ t6 ^ t7 ^ t8; + uint8_t y2 =3D t1 ^ t2 ^ t4 ^ t5 ^ t7 ^ t8; + uint8_t y3 =3D t1 ^ t2 ^ t3 ^ t5 ^ t6 ^ t8; + uint8_t y4 =3D t2 ^ t3 ^ t4 ^ t5 ^ t6 ^ t7; + uint8_t y5 =3D t1 ^ t2 ^ t6 ^ t7 ^ t8; + uint8_t y6 =3D t2 ^ t3 ^ t5 ^ t7 ^ t8; + uint8_t y7 =3D t3 ^ t4 ^ t5 ^ t6 ^ t8; + uint8_t y8 =3D t1 ^ t4 ^ t5 ^ t6 ^ t7; + + return ((uint64_t)y1 << 56) | ((uint64_t)y2 << 48) | + ((uint64_t)y3 << 40) | ((uint64_t)y4 << 32) | + ((uint64_t)y5 << 24) | ((uint64_t)y6 << 16) | + ((uint64_t)y7 << 8) | y8; +} + +static uint64_t camellia_fl(uint64_t input, uint64_t key) +{ + uint32_t x1 =3D input >> 32; + uint32_t x2 =3D input; + uint32_t k1 =3D key >> 32; + uint32_t k2 =3D key; + + x2 ^=3D rol32(x1 & k1, 1); + x1 ^=3D x2 | k2; + return ((uint64_t)x1 << 32) | x2; +} + +static uint64_t camellia_flinv(uint64_t input, uint64_t key) +{ + uint32_t y1 =3D input >> 32; + uint32_t y2 =3D input; + uint32_t k1 =3D key >> 32; + uint32_t k2 =3D key; + + y1 ^=3D y2 | k2; + y2 ^=3D rol32(y1 & k1, 1); + return ((uint64_t)y1 << 32) | y2; +} + +static void octeon_camellia_round(MIPSOcteonCryptoState *crypto, uint64_t = key) +{ + uint64_t left =3D crypto->aes_resinp[0]; + uint64_t right =3D crypto->aes_resinp[1]; + + crypto->aes_resinp[0] =3D right ^ camellia_f(left, key); + crypto->aes_resinp[1] =3D left; +} + +static void octeon_camellia_fl_layer(MIPSOcteonCryptoState *crypto, + uint64_t key, bool inverse) +{ + uint64_t state =3D crypto->aes_resinp[inverse ? 1 : 0]; + + crypto->aes_resinp[inverse ? 1 : 0] =3D inverse ? + camellia_flinv(state, key) : + camellia_fl(state, key); +} + +void helper_octeon_cp2_mt_camellia_fl(CPUMIPSState *env, uint64_t value) +{ + octeon_camellia_fl_layer(&env->octeon_crypto, value, false); +} + +void helper_octeon_cp2_mt_camellia_flinv(CPUMIPSState *env, uint64_t value) +{ + octeon_camellia_fl_layer(&env->octeon_crypto, value, true); +} + +void helper_octeon_cp2_mt_camellia_round(CPUMIPSState *env, uint64_t value) +{ + octeon_camellia_round(&env->octeon_crypto, value); +} + void helper_octeon_cp2_mt_snow3g_start(CPUMIPSState *env, uint64_t value) { octeon_snow3g_start(&env->octeon_crypto, value); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427422; cv=none; d=zohomail.com; s=zohoarc; b=Y4EhEoYwkp6Jx/0A45CIY7T70N8P/saMgJGyjBQ5aVIxSZOLSTzFKGQq/Z44PQa3O6FfaGohZCGyWFHa0hX5ONglt3VhXx1ey3VPfRK6yVwTOqTwe80fMn2VPUrFdWfMap+9dqwliPGadyWypBCs5LWZTNOITmJwE+kAqJmFjDk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427422; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PZge12psOd2xaJmayrbXAqUYyk1aMCSXLGKP7oqSpY8=; b=g0ScRVAp2RuW9Xyg42mIgM5rxcded8GsFdAzq/5HV1LPISegb+m5CPO4zHpKmunb2yOBWz73tUEh0yrqLqPw5Pw3SI/Rjs4OEWwOeZCu7x6QjSYAT10wrWNPy+lMaWUni5quJcpbYDmqrOOOsb0pIOfRV4IK/CNYk+P0DM566uI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427422136965.1390260846291; Thu, 21 May 2026 22:23:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJI-0002jd-Ab; Fri, 22 May 2026 01:20:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJE-0002bK-UH for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:32 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJC-00024F-Fs for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:32 -0400 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-484cf882ce5so4860935b6e.1 for ; Thu, 21 May 2026 22:20:30 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427229; x=1780032029; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PZge12psOd2xaJmayrbXAqUYyk1aMCSXLGKP7oqSpY8=; b=SFx1T+x5l5hvL2G441hkbxdBMq1CTA7AHxuhPf++kAbfVTautDPCmi4pDGQVRtaHrk plVNssA/nC7fhUhPyQaq9jYeBtIYC8kEKjMmQPhFq5ZPkcLggkJWww93gTjXMk+coa5f SCk2Y0oPjvTHytHwMXt0Ap8R0mONBUkt3G1DMr/UbPXov7bsccMm4hb6pjA/d91lmOyH gCKrdT04gGVRQ/IijCMSj5/Uh+XgeJbDsFDLJAs/48hOThQ2+cHCuUcP+QVFd/Pl5EGB L3mJQ4UpHBM6zlZHJZgqr8aM1TMsRW5hWF/KQg9fJWYlVrhmNZfpT19VU2vz7kTIi78e vCBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427229; x=1780032029; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=PZge12psOd2xaJmayrbXAqUYyk1aMCSXLGKP7oqSpY8=; b=ClxiL5qVPtmFvOb6upWWg10Zk5wuoosDC9N3NzEmgSORquSizN+PDo2AJtEgToKN3o j5AZbxrqYOtkKmapDJfIGnl7MZ5ohAC//rgaTZLsi6wNgyNPuAUuctYr62tTmet3MwQX GNujQE2xEu3fXUat3mlBMahxvLXB54vLSzotSaDPACxGfvNchOuph/vQ/uQewy8oRM7J UT5MBGBQK2kzCMwY6Jj9RMFX0JvoIHwXT0lAIeW/fT+4lDjeS4iFxV41t0eGuKpPWAYu MSCNaPT3sGj99d+MDMgRWp3euIDZCJEwAWDgccOGCY9crtnty3e8SPqUdB0qakdNsD59 xVxA== X-Gm-Message-State: AOJu0YzMAP1yXERQiMSRtR80JeY5vaA4iD6GZQ9mjGWg3D/+0jq4YO9s dK++uRoDzvyuFlDXX5aSvdYXae2WUW/Aq59qPuYe2pphbR47fjL//URH X-Gm-Gg: Acq92OEXr6uG/Ctsal4ihHVgbX7cSECrYNpQ6P9hA7BCL6tktgy5qY7zaUXoFCGcW/r pFnkQbT9PgzgTCoc1zGw95x4mjlXfZVBvV+qknJWlb90P5hLuOzlS3pDlAwQpNUk8rz/aYlhW1v 5pSzp9/cnCQVmBeF3f/GedYY8jDfHBrbPDxDR1EQA3zCK/0ZroXx7X7h4kgip0CXytocYhLL9vm tq8InxXRxVAF92UsYAUgJ7mXitNbPNi/nGrtqvIe7GXMU8r6CfQo0KRxPT2UQ3c0hbJkDbBh8Pf qJTdcqqsgTng3SXF6goCBpmi/Ds1LB0H38Fvdi2TzCMG5TJcRnUBwlb8zq/myuRrGUMI/ihfmvE RAMawwiZHBnhrNPLsTlxhKb7LNTbiOwgMSFQccU1KHkH2Xr+2EpanAs95h3aYS4u1cuPzkuzImp rSjostGpR4WMVNrS12Kxh3Zeul3bfeuqKnvmbYAPNw25MfQRFH1cgmVxdZHhn/kURwuC9HlYwH0 qnlfESou8CRbSxtigznLmAnK7YWZ6j6MR9JwAHAvPrexRyigZERRSrzj9riww6j7Hwa X-Received: by 2002:a05:6808:1997:b0:479:ded7:477 with SMTP id 5614622812f47-4854a24da98mr1340302b6e.40.1779427229331; Thu, 21 May 2026 22:20:29 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:55 -0600 Subject: [PATCH v14 13/22] target/mips: add Octeon HSH COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-13-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427424326154100 Add helper support for the Octeon HSH hash selectors. This includes the base HSH data/IV windows, MD5, SHA1, SHA256, and SHA512 transform paths, and the shared HSH/SHA512 register-window readback and write operations. The SHA512 path shares the wide HSH register bank with SHA3, SNOW3G, and ZUC. Keep the aliased readback and write paths centralized so selector decode can route register accesses through these helpers when side effects are required. Signed-off-by: James Hilliard --- Changes v13 -> v14: - Keep HSH narrow DAT/IV state updates in the low 32-bit halves of the architectural HSH register bank so paired selector transfers preserve the wide shared-window state. Changes v10 -> v13: - Keep the 0x0057 SDK compatibility path as an explicit STARTSHA1 compatibility helper instead of a generic STARTSHA name. Changes v9 -> v10: - Remove references to shared-mode tracking; aliased state is kept in the architectural HSH register banks. Changes v8 -> v9: - Split HSH/SHA helpers into their own COP2 helper patch. - Replace generic selector dispatch with per-operation HSH helpers. - Keep shared-window readback and write helpers grouped with HSH. - Add matching helper.h declarations with the helper implementation. --- target/mips/helper.h | 5 + target/mips/tcg/octeon_crypto.c | 375 ++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 380 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index fbf8250932..d18ade0094 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -91,6 +91,11 @@ DEF_HELPER_2(octeon_cp2_mt_des3_dec, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_camellia_fl, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_camellia_flinv, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_camellia_round, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_hsh_startsha1_compat, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_hsh_startmd5, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_hsh_startsha256, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_hsh_startsha, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_hsh_startsha512, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 5bb21098fc..3db81d608d 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -151,6 +151,348 @@ static void octeon_gfm_mul64_uia2(const uint64_t x[2]= , const uint64_t y[2], out[1] =3D revbit64(res); } =20 +static inline uint32_t octeon_hsh_get32(const uint64_t *regs, + unsigned int index) +{ + return regs[index]; +} + +static inline void octeon_hsh_set32(uint64_t *regs, unsigned int index, + uint32_t value) +{ + regs[index] =3D (regs[index] & ~(uint64_t)UINT32_MAX) | value; +} + +static inline void octeon_hsh_set_pair(uint64_t *regs, unsigned int index, + uint64_t value) +{ + octeon_hsh_set32(regs, index * 2, value >> 32); + octeon_hsh_set32(regs, index * 2 + 1, value); +} + +static void octeon_md5_transform(MIPSOcteonCryptoState *crypto) +{ + static const uint32_t k[64] =3D { + 0xd76aa478U, 0xe8c7b756U, 0x242070dbU, 0xc1bdceeeU, + 0xf57c0fafU, 0x4787c62aU, 0xa8304613U, 0xfd469501U, + 0x698098d8U, 0x8b44f7afU, 0xffff5bb1U, 0x895cd7beU, + 0x6b901122U, 0xfd987193U, 0xa679438eU, 0x49b40821U, + 0xf61e2562U, 0xc040b340U, 0x265e5a51U, 0xe9b6c7aaU, + 0xd62f105dU, 0x02441453U, 0xd8a1e681U, 0xe7d3fbc8U, + 0x21e1cde6U, 0xc33707d6U, 0xf4d50d87U, 0x455a14edU, + 0xa9e3e905U, 0xfcefa3f8U, 0x676f02d9U, 0x8d2a4c8aU, + 0xfffa3942U, 0x8771f681U, 0x6d9d6122U, 0xfde5380cU, + 0xa4beea44U, 0x4bdecfa9U, 0xf6bb4b60U, 0xbebfbc70U, + 0x289b7ec6U, 0xeaa127faU, 0xd4ef3085U, 0x04881d05U, + 0xd9d4d039U, 0xe6db99e5U, 0x1fa27cf8U, 0xc4ac5665U, + 0xf4292244U, 0x432aff97U, 0xab9423a7U, 0xfc93a039U, + 0x655b59c3U, 0x8f0ccc92U, 0xffeff47dU, 0x85845dd1U, + 0x6fa87e4fU, 0xfe2ce6e0U, 0xa3014314U, 0x4e0811a1U, + 0xf7537e82U, 0xbd3af235U, 0x2ad7d2bbU, 0xeb86d391U, + }; + static const uint8_t s[64] =3D { + 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, 7, 12, 17, 22, + 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, 5, 9, 14, 20, + 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, 4, 11, 16, 23, + 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, 6, 10, 15, 21, + }; + uint32_t m[16]; + uint32_t a, b, c, d; + uint32_t aa, bb, cc, dd; + int i; + + for (i =3D 0; i < 16; i++) { + m[i] =3D bswap32(octeon_hsh_get32(crypto->hsh_dat, i)); + } + + a =3D bswap32(octeon_hsh_get32(crypto->hsh_iv, 0)); + b =3D bswap32(octeon_hsh_get32(crypto->hsh_iv, 1)); + c =3D bswap32(octeon_hsh_get32(crypto->hsh_iv, 2)); + d =3D bswap32(octeon_hsh_get32(crypto->hsh_iv, 3)); + aa =3D a; + bb =3D b; + cc =3D c; + dd =3D d; + + for (i =3D 0; i < 64; i++) { + uint32_t f, g, tmp; + + if (i < 16) { + f =3D (b & c) | ((~b) & d); + g =3D i; + } else if (i < 32) { + f =3D (d & b) | ((~d) & c); + g =3D (5 * i + 1) & 0xf; + } else if (i < 48) { + f =3D b ^ c ^ d; + g =3D (3 * i + 5) & 0xf; + } else { + f =3D c ^ (b | (~d)); + g =3D (7 * i) & 0xf; + } + + tmp =3D d; + d =3D c; + c =3D b; + b =3D b + rol32(a + f + k[i] + m[g], s[i]); + a =3D tmp; + } + + a +=3D aa; + b +=3D bb; + c +=3D cc; + d +=3D dd; + octeon_hsh_set32(crypto->hsh_iv, 0, bswap32(a)); + octeon_hsh_set32(crypto->hsh_iv, 1, bswap32(b)); + octeon_hsh_set32(crypto->hsh_iv, 2, bswap32(c)); + octeon_hsh_set32(crypto->hsh_iv, 3, bswap32(d)); +} + +static void octeon_sha1_transform(MIPSOcteonCryptoState *crypto) +{ + uint32_t w[80]; + uint32_t a, b, c, d, e; + uint32_t orig[5]; + int i; + + for (i =3D 0; i < 16; i++) { + w[i] =3D octeon_hsh_get32(crypto->hsh_dat, i); + } + for (i =3D 16; i < 80; i++) { + w[i] =3D rol32(w[i - 3] ^ w[i - 8] ^ w[i - 14] ^ w[i - 16], 1); + } + + for (i =3D 0; i < 5; i++) { + orig[i] =3D octeon_hsh_get32(crypto->hsh_iv, i); + } + a =3D orig[0]; + b =3D orig[1]; + c =3D orig[2]; + d =3D orig[3]; + e =3D orig[4]; + + for (i =3D 0; i < 80; i++) { + uint32_t f, k, temp; + + if (i < 20) { + f =3D (b & c) | ((~b) & d); + k =3D 0x5a827999; + } else if (i < 40) { + f =3D b ^ c ^ d; + k =3D 0x6ed9eba1; + } else if (i < 60) { + f =3D (b & c) | (b & d) | (c & d); + k =3D 0x8f1bbcdc; + } else { + f =3D b ^ c ^ d; + k =3D 0xca62c1d6; + } + + temp =3D rol32(a, 5) + f + e + k + w[i]; + e =3D d; + d =3D c; + c =3D rol32(b, 30); + b =3D a; + a =3D temp; + } + + orig[0] +=3D a; + orig[1] +=3D b; + orig[2] +=3D c; + orig[3] +=3D d; + orig[4] +=3D e; + for (i =3D 0; i < 5; i++) { + octeon_hsh_set32(crypto->hsh_iv, i, orig[i]); + } +} + +static void octeon_sha256_transform(MIPSOcteonCryptoState *crypto) +{ + static const uint32_t k[64] =3D { + 0x428a2f98U, 0x71374491U, 0xb5c0fbcfU, 0xe9b5dba5U, + 0x3956c25bU, 0x59f111f1U, 0x923f82a4U, 0xab1c5ed5U, + 0xd807aa98U, 0x12835b01U, 0x243185beU, 0x550c7dc3U, + 0x72be5d74U, 0x80deb1feU, 0x9bdc06a7U, 0xc19bf174U, + 0xe49b69c1U, 0xefbe4786U, 0x0fc19dc6U, 0x240ca1ccU, + 0x2de92c6fU, 0x4a7484aaU, 0x5cb0a9dcU, 0x76f988daU, + 0x983e5152U, 0xa831c66dU, 0xb00327c8U, 0xbf597fc7U, + 0xc6e00bf3U, 0xd5a79147U, 0x06ca6351U, 0x14292967U, + 0x27b70a85U, 0x2e1b2138U, 0x4d2c6dfcU, 0x53380d13U, + 0x650a7354U, 0x766a0abbU, 0x81c2c92eU, 0x92722c85U, + 0xa2bfe8a1U, 0xa81a664bU, 0xc24b8b70U, 0xc76c51a3U, + 0xd192e819U, 0xd6990624U, 0xf40e3585U, 0x106aa070U, + 0x19a4c116U, 0x1e376c08U, 0x2748774cU, 0x34b0bcb5U, + 0x391c0cb3U, 0x4ed8aa4aU, 0x5b9cca4fU, 0x682e6ff3U, + 0x748f82eeU, 0x78a5636fU, 0x84c87814U, 0x8cc70208U, + 0x90befffaU, 0xa4506cebU, 0xbef9a3f7U, 0xc67178f2U, + }; + uint32_t w[64]; + uint32_t a, b, c, d, e, f, g, h; + uint32_t orig[8]; + int i; + + for (i =3D 0; i < 16; i++) { + w[i] =3D octeon_hsh_get32(crypto->hsh_dat, i); + } + for (i =3D 16; i < 64; i++) { + uint32_t s0 =3D ror32(w[i - 15], 7) ^ + ror32(w[i - 15], 18) ^ + (w[i - 15] >> 3); + uint32_t s1 =3D ror32(w[i - 2], 17) ^ + ror32(w[i - 2], 19) ^ + (w[i - 2] >> 10); + w[i] =3D w[i - 16] + s0 + w[i - 7] + s1; + } + + for (i =3D 0; i < 8; i++) { + orig[i] =3D octeon_hsh_get32(crypto->hsh_iv, i); + } + a =3D orig[0]; + b =3D orig[1]; + c =3D orig[2]; + d =3D orig[3]; + e =3D orig[4]; + f =3D orig[5]; + g =3D orig[6]; + h =3D orig[7]; + + for (i =3D 0; i < 64; i++) { + uint32_t s1 =3D ror32(e, 6) ^ + ror32(e, 11) ^ + ror32(e, 25); + uint32_t ch =3D (e & f) ^ ((~e) & g); + uint32_t temp1 =3D h + s1 + ch + k[i] + w[i]; + uint32_t s0 =3D ror32(a, 2) ^ + ror32(a, 13) ^ + ror32(a, 22); + uint32_t maj =3D (a & b) ^ (a & c) ^ (b & c); + uint32_t temp2 =3D s0 + maj; + + h =3D g; + g =3D f; + f =3D e; + e =3D d + temp1; + d =3D c; + c =3D b; + b =3D a; + a =3D temp1 + temp2; + } + + orig[0] +=3D a; + orig[1] +=3D b; + orig[2] +=3D c; + orig[3] +=3D d; + orig[4] +=3D e; + orig[5] +=3D f; + orig[6] +=3D g; + orig[7] +=3D h; + for (i =3D 0; i < 8; i++) { + octeon_hsh_set32(crypto->hsh_iv, i, orig[i]); + } +} + +static void octeon_sha512_transform(MIPSOcteonCryptoState *crypto) +{ + static const uint64_t k[80] =3D { + 0x428a2f98d728ae22ULL, 0x7137449123ef65cdULL, + 0xb5c0fbcfec4d3b2fULL, 0xe9b5dba58189dbbcULL, + 0x3956c25bf348b538ULL, 0x59f111f1b605d019ULL, + 0x923f82a4af194f9bULL, 0xab1c5ed5da6d8118ULL, + 0xd807aa98a3030242ULL, 0x12835b0145706fbeULL, + 0x243185be4ee4b28cULL, 0x550c7dc3d5ffb4e2ULL, + 0x72be5d74f27b896fULL, 0x80deb1fe3b1696b1ULL, + 0x9bdc06a725c71235ULL, 0xc19bf174cf692694ULL, + 0xe49b69c19ef14ad2ULL, 0xefbe4786384f25e3ULL, + 0x0fc19dc68b8cd5b5ULL, 0x240ca1cc77ac9c65ULL, + 0x2de92c6f592b0275ULL, 0x4a7484aa6ea6e483ULL, + 0x5cb0a9dcbd41fbd4ULL, 0x76f988da831153b5ULL, + 0x983e5152ee66dfabULL, 0xa831c66d2db43210ULL, + 0xb00327c898fb213fULL, 0xbf597fc7beef0ee4ULL, + 0xc6e00bf33da88fc2ULL, 0xd5a79147930aa725ULL, + 0x06ca6351e003826fULL, 0x142929670a0e6e70ULL, + 0x27b70a8546d22ffcULL, 0x2e1b21385c26c926ULL, + 0x4d2c6dfc5ac42aedULL, 0x53380d139d95b3dfULL, + 0x650a73548baf63deULL, 0x766a0abb3c77b2a8ULL, + 0x81c2c92e47edaee6ULL, 0x92722c851482353bULL, + 0xa2bfe8a14cf10364ULL, 0xa81a664bbc423001ULL, + 0xc24b8b70d0f89791ULL, 0xc76c51a30654be30ULL, + 0xd192e819d6ef5218ULL, 0xd69906245565a910ULL, + 0xf40e35855771202aULL, 0x106aa07032bbd1b8ULL, + 0x19a4c116b8d2d0c8ULL, 0x1e376c085141ab53ULL, + 0x2748774cdf8eeb99ULL, 0x34b0bcb5e19b48a8ULL, + 0x391c0cb3c5c95a63ULL, 0x4ed8aa4ae3418acbULL, + 0x5b9cca4f7763e373ULL, 0x682e6ff3d6b2b8a3ULL, + 0x748f82ee5defb2fcULL, 0x78a5636f43172f60ULL, + 0x84c87814a1f0ab72ULL, 0x8cc702081a6439ecULL, + 0x90befffa23631e28ULL, 0xa4506cebde82bde9ULL, + 0xbef9a3f7b2c67915ULL, 0xc67178f2e372532bULL, + 0xca273eceea26619cULL, 0xd186b8c721c0c207ULL, + 0xeada7dd6cde0eb1eULL, 0xf57d4f7fee6ed178ULL, + 0x06f067aa72176fbaULL, 0x0a637dc5a2c898a6ULL, + 0x113f9804bef90daeULL, 0x1b710b35131c471bULL, + 0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, + 0x3c9ebe0a15c9bebcULL, 0x431d67c49c100d4cULL, + 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL, + 0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL, + }; + uint64_t w[80]; + uint64_t a, b, c, d, e, f, g, h; + int i; + + for (i =3D 0; i < 16; i++) { + w[i] =3D crypto->hsh_dat[i]; + } + for (i =3D 16; i < 80; i++) { + uint64_t s0 =3D ror64(w[i - 15], 1) ^ + ror64(w[i - 15], 8) ^ + (w[i - 15] >> 7); + uint64_t s1 =3D ror64(w[i - 2], 19) ^ + ror64(w[i - 2], 61) ^ + (w[i - 2] >> 6); + w[i] =3D w[i - 16] + s0 + w[i - 7] + s1; + } + + a =3D crypto->hsh_iv[0]; + b =3D crypto->hsh_iv[1]; + c =3D crypto->hsh_iv[2]; + d =3D crypto->hsh_iv[3]; + e =3D crypto->hsh_iv[4]; + f =3D crypto->hsh_iv[5]; + g =3D crypto->hsh_iv[6]; + h =3D crypto->hsh_iv[7]; + + for (i =3D 0; i < 80; i++) { + uint64_t s0 =3D ror64(a, 28) ^ + ror64(a, 34) ^ + ror64(a, 39); + uint64_t s1 =3D ror64(e, 14) ^ + ror64(e, 18) ^ + ror64(e, 41); + uint64_t ch =3D (e & f) ^ ((~e) & g); + uint64_t maj =3D (a & b) ^ (a & c) ^ (b & c); + uint64_t temp1 =3D h + s1 + ch + k[i] + w[i]; + uint64_t temp2 =3D s0 + maj; + + h =3D g; + g =3D f; + f =3D e; + e =3D d + temp1; + d =3D c; + c =3D b; + b =3D a; + a =3D temp1 + temp2; + } + + crypto->hsh_iv[0] +=3D a; + crypto->hsh_iv[1] +=3D b; + crypto->hsh_iv[2] +=3D c; + crypto->hsh_iv[3] +=3D d; + crypto->hsh_iv[4] +=3D e; + crypto->hsh_iv[5] +=3D f; + crypto->hsh_iv[6] +=3D g; + crypto->hsh_iv[7] +=3D h; +} + static const uint64_t octeon_sha3_round_constants[24] =3D { 0x0000000000000001ULL, 0x0000000000008082ULL, 0x800000000000808aULL, 0x8000000080008000ULL, @@ -1761,6 +2103,39 @@ void helper_octeon_cp2_mt_zuc_more(CPUMIPSState *env= , uint64_t value) octeon_zuc_more(&env->octeon_crypto, value); } =20 +void helper_octeon_cp2_mt_hsh_startsha1_compat(CPUMIPSState *env, + uint64_t value) +{ + octeon_hsh_set_pair(env->octeon_crypto.hsh_dat, 7, value); + octeon_sha1_transform(&env->octeon_crypto); +} + +void helper_octeon_cp2_mt_hsh_startmd5(CPUMIPSState *env, uint64_t value) +{ + octeon_hsh_set_pair(env->octeon_crypto.hsh_dat, 7, value); + octeon_md5_transform(&env->octeon_crypto); +} + +void helper_octeon_cp2_mt_hsh_startsha256(CPUMIPSState *env, uint64_t valu= e) +{ + octeon_hsh_set_pair(env->octeon_crypto.hsh_dat, 7, value); + octeon_sha256_transform(&env->octeon_crypto); +} + +void helper_octeon_cp2_mt_hsh_startsha(CPUMIPSState *env, uint64_t value) +{ + octeon_hsh_set_pair(env->octeon_crypto.hsh_dat, 7, value); + octeon_sha1_transform(&env->octeon_crypto); +} + +void helper_octeon_cp2_mt_hsh_startsha512(CPUMIPSState *env, uint64_t valu= e) +{ + MIPSOcteonCryptoState *crypto =3D &env->octeon_crypto; + + crypto->hsh_dat[15] =3D value; + octeon_sha512_transform(crypto); +} + uint64_t helper_octeon_cp2_mf_crc_iv_reflect(CPUMIPSState *env) { return octeon_crc_reflect32_by_byte(env->octeon_crypto.crc_iv); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427286; cv=none; d=zohomail.com; s=zohoarc; b=e+6F+UOBrmODR2OQvfzgLRwlUieIyWpJMpjQ5/nZb10J/IzYY4PXifSNJhcioWJsSCn6aS9dh1um0ddFDXe8eCCzUXqH02XU8SqgVkZgVu1s4gV5ijto6BWgniAYeNmaLToGSgnUWUY8xMFVLG1ik7wKyoJvoR9iBOqtbVC/ZgY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427286; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4l2GUnVbAD6E80hsWLa5a+IVZeXD0LsgUMd7LQLMtMM=; b=MPsDPWS43g/3QXa6kKufAxUku+Je7pRGBwjF13wItGkvhh/V/gRmgdoovyDf9UpVn2QtamBctoSN9dmNTfEwEA/oON+vawCWqqtUW7Bfm9egx8xNztRjYc4VAeN59rjNOy5mVeTyOD0plfnUL6ukmld6Sdy3imp7XIFohMSdGCg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427286593423.4632077966987; Thu, 21 May 2026 22:21:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJJ-0002mw-93; Fri, 22 May 2026 01:20:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJG-0002em-9C for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:34 -0400 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJD-00026b-SG for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:33 -0400 Received: by mail-oi1-x235.google.com with SMTP id 5614622812f47-47c35be031dso4821688b6e.3 for ; Thu, 21 May 2026 22:20:31 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427231; x=1780032031; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4l2GUnVbAD6E80hsWLa5a+IVZeXD0LsgUMd7LQLMtMM=; b=bt8FiOMPRNuVL1Zj6but7kQz6i6UcEYCX+NnCWZWb+QcvvlD3WauIDuREAYnA8PTkq ocpY7iNknkeZ5JR5w4Bh6o7dR8dHJM2mX3NDSw0zEyzLb9rCNIV5bUDUz2p+6ICk6meQ 3VLtNoLJ3UDmuSD1MUh5XYTRMRUcBnGG1JxL7wRqWbVBxKb9ddr0KZTZjuA1rJeG2z8h OrjHXOFRtY2fj/LzRyT61fzBsRzRsbX7UOEg/0Xnf1CRG6oF56igxwDdtXrxpXe1/+gW jUhAYssYQ/f1B/Y/u+UAhOM3fyIsEURphv08C3Ewp3iT/wm03mlp7BVlvIbedp7TEtgu gw3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427231; x=1780032031; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4l2GUnVbAD6E80hsWLa5a+IVZeXD0LsgUMd7LQLMtMM=; b=EhRMHOktt6+4N/8kSNVnQALdeyBgiMpzUVcV123T+gzgOyp9pI8MAuIdughqUAS3Rx fAAM2gTU5goroZX3t98B6XG/6ypboW9mxsEz/4qWHujhkfe8XWyh3GSgodIBucgh5Jju BwXi1fTfAutt6oebXBJiSlUHZiHsB7EFlV5Ks0xgT8e4wBkDYMdMEhMnrEdk6XKpCdOM msI/IECssvR1AoJRz2cq0/UTKiJl4wAnIWNMn5UgTO8qN1G1DhGEGp9Z3O4h2upVU3X/ RZXLruOuVxwu3YbQlAzuXbAMDhUe859sf86F2VdpbnBSHB+N8Pd+3bXdM6ZU9PYnQ2fh mLBw== X-Gm-Message-State: AOJu0Yx7aOMqTF1z9zxwbpRfoMehhukTXfHvfHTNXvSQu35+3HH2U5EK +pdDfk9lEXSONPGX95ikuIjeekMSCaBwWT4dJaz5rOFHlM7PuL8igN3q X-Gm-Gg: Acq92OFvqxPeYv8TMyX282nhSwO1lFtaXULpp1fuJhXJMxIEDWPZgjR7d+wybAuYIq1 52DJLA8rY4C/KdWl4u+yoPOT5n6JaDwHD9MbmHJgPBmxn26K0UKVFj3p7jeXimJTk4UqyXfh/9w PW6+4Em8yboh01/8hZfY2nLA2/efJZiPe2DbWg5Ar/ZgSjbPt0j574gr+N8/qg6T972nMWK2Rms oT91oxCJAQ/o9FDMDacgg+NpmyhwtJTzwqrThaRmPgtNl2GJPh9LgXzmFBIQ7c2R0kWBNJu7NJC qvys968I9VlRbjb1QTglIc8X28s2N0EqQZQeU5npgHDLJLLm7O/YCotbVkEVM1+1gNqVrh1uo8t WnSUKKIlCaXinDhh/FuFpZuMmgWnNsrHaq9S+y7iXHRk5uu5XKOWt5zyBRnZ2gzT+KdBvjZCqie LF6w2e6DytXfPsOHWyCOTEEmi3sOLmKS5BMAZgZ/CXU9ZYkLp/6rT5rBuNBvf2zFahUpYTegCy7 qwVlBWsXNV5bmXQ68KKQJdNEifYTYMOOmuBjl/xaZULj2FO2MzD3QN9s8tEwCHhUVHh X-Received: by 2002:a05:6808:1995:b0:47b:d07b:ec9b with SMTP id 5614622812f47-4854a243ffdmr1210633b6e.24.1779427230657; Thu, 21 May 2026 22:20:30 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:56 -0600 Subject: [PATCH v14 14/22] target/mips: add Octeon CHORD and LLM COP2 helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-14-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427288061158501 Add the Octeon CHORD hardware register access path and the LLM 36-bit and 64-bit read and write windows. Model both CHORD access forms, including the RDHWR $30 path and the legacy DMFC2 alias. Implement sparse backing storage for the two LLM sets so user-mode code can save, restore, and probe the architectural state without allocating a full hardware-sized backing array. Signed-off-by: James Hilliard --- Changes v10 -> v13: - Keep this patch limited to CHORD/LLM additions; existing crypto helpers and state fields stay in their original commit order. Changes v8 -> v9: - Split CHORD and LLM helpers into their own COP2 helper patch. - Replace generic selector dispatch with per-operation LLM helpers. - Add matching helper.h declarations with the helper implementation. Changes v5 -> v6: - Rename sparse LLM backing fields from llm_narrow/llm_wide to llm36/llm64 to match the 36-bit and 64-bit selector windows. Changes v1 -> v2: - Use neutral selector-slot wording for the LLM/CHORD alias comment. - Add selector dispatch updates in octeon_translate.c after moving COP2 decode out of translate.c. (suggested by Philippe Mathieu-Daud=C3=A9) --- target/mips/cpu.c | 67 ++++++++++++++++++++++++++++++++++++ target/mips/cpu.h | 5 +++ target/mips/helper.h | 9 +++++ target/mips/internal.h | 3 ++ target/mips/system/machine.c | 67 ++++++++++++++++++++++++++++++++++++ target/mips/tcg/octeon_crypto.c | 75 +++++++++++++++++++++++++++++++++++++= ++++ target/mips/tcg/op_helper.c | 6 ++++ target/mips/tcg/translate.c | 8 +++++ 8 files changed, 240 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index fccc7a711d..b223b767c9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -26,6 +26,7 @@ #include "cpu.h" #include "internal.h" #include "qemu/module.h" +#include "qemu/qtree.h" #include "system/qtest.h" #include "hw/core/qdev-properties.h" #include "hw/core/qdev-clock.h" @@ -181,6 +182,57 @@ static bool mips_cpu_has_work(CPUState *cs) =20 #include "cpu-defs.c.inc" =20 +static gint mips_octeon_u64_tree_compare(gconstpointer a, gconstpointer b, + gpointer user_data) +{ + uint64_t av =3D *(const uint64_t *)a; + uint64_t bv =3D *(const uint64_t *)b; + + return (av > bv) - (av < bv); +} + +QTree *mips_octeon_llm_tree_new(void) +{ + return q_tree_new_full(mips_octeon_u64_tree_compare, + NULL, g_free, g_free); +} + +uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr) +{ + uint64_t key =3D addr; + uint64_t *value =3D tree ? q_tree_lookup(tree, &key) : NULL; + + return value ? *value : 0; +} + +void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value) +{ + uint64_t *key; + uint64_t *stored; + + if (!*treep) { + *treep =3D mips_octeon_llm_tree_new(); + } + + key =3D g_new(uint64_t, 1); + stored =3D g_new(uint64_t, 1); + *key =3D addr; + *stored =3D value; + q_tree_replace(*treep, key, stored); +} + +static void mips_octeon_destroy_llm_state(MIPSOcteonCryptoState *crypto) +{ + if (crypto->llm36) { + q_tree_destroy(crypto->llm36); + crypto->llm36 =3D NULL; + } + if (crypto->llm64) { + q_tree_destroy(crypto->llm64); + crypto->llm64 =3D NULL; + } +} + static void mips_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); @@ -192,6 +244,7 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) mcc->parent_phases.hold(obj, type); } =20 + mips_octeon_destroy_llm_state(&env->octeon_crypto); memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); =20 /* Reset registers to their default values */ @@ -246,6 +299,9 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) env->active_fpu.fcr31 =3D env->cpu_model->CP1_fcr31; env->msair =3D env->cpu_model->MSAIR; env->insn_flags =3D env->cpu_model->insn_flags; + if (env->insn_flags & INSN_OCTEON) { + env->octeon_crypto.chord =3D 1; + } =20 #if defined(CONFIG_USER_ONLY) env->CP0_Status =3D (MIPS_HFLAG_UM << CP0St_KSU); @@ -262,6 +318,9 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) * hardware registers. */ env->CP0_HWREna |=3D 0x0000000F; + if (env->insn_flags & INSN_OCTEON) { + env->CP0_HWREna |=3D 0x40000000u; + } if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->CP0_Status |=3D (1 << CP0St_CU1); } @@ -417,6 +476,13 @@ static void mips_cpu_reset_hold(Object *obj, ResetType= type) #endif } =20 +static void mips_cpu_finalize(Object *obj) +{ + MIPSCPU *cpu =3D MIPS_CPU(obj); + + mips_octeon_destroy_llm_state(&cpu->env.octeon_crypto); +} + static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *= info) { const MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -645,6 +711,7 @@ static const TypeInfo mips_cpu_type_info =3D { .instance_size =3D sizeof(MIPSCPU), .instance_align =3D __alignof(MIPSCPU), .instance_init =3D mips_cpu_initfn, + .instance_finalize =3D mips_cpu_finalize, .abstract =3D true, .class_size =3D sizeof(MIPSCPUClass), .class_init =3D mips_cpu_class_init, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 2dad7f538f..bc427adb97 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -11,6 +11,7 @@ #include "fpu/softfloat-types.h" #include "hw/core/clock.h" #include "mips-defs.h" +#include "qemu/qtree.h" =20 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; =20 @@ -554,6 +555,10 @@ typedef struct MIPSOcteonCryptoState { uint16_t gfm_poly; uint8_t aes_keylen; uint8_t crc_len; + uint64_t chord; + uint64_t llm_data[2]; + QTree *llm36; + QTree *llm64; } MIPSOcteonCryptoState; =20 typedef struct CPUArchState { diff --git a/target/mips/helper.h b/target/mips/helper.h index d18ade0094..c062863582 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -96,6 +96,14 @@ DEF_HELPER_2(octeon_cp2_mt_hsh_startmd5, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_hsh_startsha256, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_hsh_startsha, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_hsh_startsha512, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_read_addr0, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_write_addr0, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_read64_addr0, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_write64_addr0, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_read_addr1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_write_addr1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_read64_addr1, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_llm_write64_addr1, void, env, i64) =20 /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) @@ -267,6 +275,7 @@ DEF_HELPER_1(rdhwr_cc, tl, env) DEF_HELPER_1(rdhwr_ccres, tl, env) DEF_HELPER_1(rdhwr_performance, tl, env) DEF_HELPER_1(rdhwr_xnp, tl, env) +DEF_HELPER_1(rdhwr_chord, tl, env) DEF_HELPER_2(pmon, void, env, int) DEF_HELPER_1(wait, void, env) =20 diff --git a/target/mips/internal.h b/target/mips/internal.h index aab77b1b25..c5c286872e 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -93,6 +93,9 @@ extern const int mips_defs_number; =20 int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +QTree *mips_octeon_llm_tree_new(void); +uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr); +void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value); =20 #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) diff --git a/target/mips/system/machine.c b/target/mips/system/machine.c index 77f576a25b..bd1e4002cf 100644 --- a/target/mips/system/machine.c +++ b/target/mips/system/machine.c @@ -131,6 +131,69 @@ static const VMStateDescription vmstate_octeon_multipl= ier_tc =3D { } }; =20 +typedef struct OcteonLLMTreePutData { + QEMUFile *f; +} OcteonLLMTreePutData; + +static gboolean put_octeon_llm_tree_entry(gpointer key, gpointer value, + gpointer user_data) +{ + OcteonLLMTreePutData *data =3D user_data; + + qemu_put_be64(data->f, *(uint64_t *)key); + qemu_put_be64(data->f, *(uint64_t *)value); + return false; +} + +static int put_octeon_llm_tree(QEMUFile *f, void *pv, size_t size, + const VMStateField *field, JSONWriter *vmde= sc) +{ + QTree *tree =3D *(QTree **)pv; + OcteonLLMTreePutData data =3D { .f =3D f }; + uint32_t nnodes =3D tree ? q_tree_nnodes(tree) : 0; + + qemu_put_be32(f, nnodes); + if (tree) { + q_tree_foreach(tree, put_octeon_llm_tree_entry, &data); + } + + return 0; +} + +static int get_octeon_llm_tree(QEMUFile *f, void *pv, size_t size, + const VMStateField *field) +{ + QTree **treep =3D pv; + uint32_t nnodes =3D qemu_get_be32(f); + + if (*treep) { + q_tree_destroy(*treep); + } + *treep =3D mips_octeon_llm_tree_new(); + + for (uint32_t i =3D 0; i < nnodes; i++) { + uint64_t addr =3D qemu_get_be64(f); + uint64_t value =3D qemu_get_be64(f); + + mips_octeon_llm_store(treep, addr, value); + } + + return 0; +} + +static const VMStateInfo vmstate_info_octeon_llm_tree =3D { + .name =3D "octeon_llm_tree", + .get =3D get_octeon_llm_tree, + .put =3D put_octeon_llm_tree, +}; + +#define VMSTATE_OCTEON_LLM_TREE(_f, _s) { \ + .name =3D stringify(_f), \ + .version_id =3D 1, \ + .info =3D &vmstate_info_octeon_llm_tree, \ + .offset =3D vmstate_offset_pointer(_s, _f, QTree), \ +} + /* MVP state */ =20 static const VMStateDescription vmstate_mvp =3D { @@ -301,6 +364,10 @@ static const VMStateDescription mips_vmstate_octeon_cr= ypto =3D { VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU), VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU), VMSTATE_UINT8(env.octeon_crypto.crc_len, MIPSCPU), + VMSTATE_UINT64(env.octeon_crypto.chord, MIPSCPU), + VMSTATE_UINT64_ARRAY(env.octeon_crypto.llm_data, MIPSCPU, 2), + VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm36, MIPSCPU), + VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm64, MIPSCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 3db81d608d..742c707633 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -17,6 +17,41 @@ #include "qemu/host-utils.h" =20 #define OCTEON_SHA3_DAT15 15 +#define OCTEON_LLM_NARROW_MASK ((1ULL << 36) - 1) + +static uint64_t octeon_llm_pack_narrow(uint64_t value) +{ + value &=3D OCTEON_LLM_NARROW_MASK; + return value | ((uint64_t)(ctpop64(value) & 1) << 36); +} + +static void octeon_llm_read(MIPSOcteonCryptoState *crypto, unsigned int se= t, + uint64_t addr, bool wide) +{ + uint64_t value; + + if (wide) { + value =3D mips_octeon_llm_load(crypto->llm64, addr); + } else { + value =3D octeon_llm_pack_narrow( + mips_octeon_llm_load(crypto->llm36, addr)); + } + + crypto->llm_data[set] =3D value; +} + +static void octeon_llm_write(MIPSOcteonCryptoState *crypto, unsigned int s= et, + uint64_t addr, bool wide) +{ + uint64_t value =3D crypto->llm_data[set]; + + if (wide) { + mips_octeon_llm_store(&crypto->llm64, addr, value); + } else { + mips_octeon_llm_store(&crypto->llm36, addr, + value & OCTEON_LLM_NARROW_MASK); + } +} =20 static inline uint32_t octeon_crc_reflect32_by_byte(uint32_t v) { @@ -2328,3 +2363,43 @@ void helper_octeon_cp2_mt_crc_write_var_reflect(CPUM= IPSState *env, =20 octeon_crc_update_reflect(crypto, value, MIN(8U, crypto->crc_len & 0xf= )); } + +void helper_octeon_cp2_mt_llm_read_addr0(CPUMIPSState *env, uint64_t value) +{ + octeon_llm_read(&env->octeon_crypto, 0, value, false); +} + +void helper_octeon_cp2_mt_llm_write_addr0(CPUMIPSState *env, uint64_t valu= e) +{ + octeon_llm_write(&env->octeon_crypto, 0, value, false); +} + +void helper_octeon_cp2_mt_llm_read64_addr0(CPUMIPSState *env, uint64_t val= ue) +{ + octeon_llm_read(&env->octeon_crypto, 0, value, true); +} + +void helper_octeon_cp2_mt_llm_write64_addr0(CPUMIPSState *env, uint64_t va= lue) +{ + octeon_llm_write(&env->octeon_crypto, 0, value, true); +} + +void helper_octeon_cp2_mt_llm_read_addr1(CPUMIPSState *env, uint64_t value) +{ + octeon_llm_read(&env->octeon_crypto, 1, value, false); +} + +void helper_octeon_cp2_mt_llm_write_addr1(CPUMIPSState *env, uint64_t valu= e) +{ + octeon_llm_write(&env->octeon_crypto, 1, value, false); +} + +void helper_octeon_cp2_mt_llm_read64_addr1(CPUMIPSState *env, uint64_t val= ue) +{ + octeon_llm_read(&env->octeon_crypto, 1, value, true); +} + +void helper_octeon_cp2_mt_llm_write64_addr1(CPUMIPSState *env, uint64_t va= lue) +{ + octeon_llm_write(&env->octeon_crypto, 1, value, true); +} diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 4502ae2b5b..3e586e3049 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -255,6 +255,12 @@ target_ulong helper_rdhwr_xnp(CPUMIPSState *env) return (env->CP0_Config5 >> CP0C5_XNP) & 1; } =20 +target_ulong helper_rdhwr_chord(CPUMIPSState *env) +{ + check_hwrena(env, 30, GETPC()); + return env->octeon_crypto.chord; +} + void helper_pmon(CPUMIPSState *env, int function) { function /=3D 2; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 123d2c89c3..1f44932882 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -10925,6 +10925,14 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, = int sel) } break; #endif + case 30: + if (!(ctx->insn_flags & INSN_OCTEON)) { + gen_reserved_instruction(ctx); + break; + } + gen_helper_rdhwr_chord(t0, tcg_env); + gen_store_gpr(t0, rt); + break; default: /* Invalid */ MIPS_INVAL("rdhwr"); gen_reserved_instruction(ctx); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427329; cv=none; d=zohomail.com; s=zohoarc; b=XYm6jw0GPZiruTTjfFVJ0zyrofuP7KcEkwZuVLM3iOyxovBUlhSSRJ/vLEbwdzofhjMQpY64LybtTDbxNlK+yWiby2/qJCZPw20S7CJR0F7IShrI1yP368bAppXtqnspnsKcRuqxFJG0mLcMUrAxumUwyVmR55X2XQ8cFC5LQPM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427329; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YQl/+OEhwF4NoyNWyxodfcJAzFD2ZvuV+faGp0XUU/Q=; b=blIOx2sEtx4kMdsfo9cDmY4b5R1gcDEiP50YHdMTBqPzF5xAzWaC1+8QgCB4dRNtr4VP0MBsOB5r8IzZFyYrNawar7KqnLFE0eB3OQzn3VA6aIhX2H9kwBbWTu4dkoU41aEx4ncRrCLtSzNsNxhjUHfr3ou77ZNKuWVmNSEJ8WY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427328999470.7193837321919; Thu, 21 May 2026 22:22:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJL-0002xL-4R; Fri, 22 May 2026 01:20:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJH-0002hG-Pn for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:35 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJF-00029n-7G for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:35 -0400 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-48544e7ba58so669189b6e.0 for ; Thu, 21 May 2026 22:20:32 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427232; x=1780032032; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YQl/+OEhwF4NoyNWyxodfcJAzFD2ZvuV+faGp0XUU/Q=; b=QTX24Ot8TFVZnDsayRIhbgPEiNX5uDMiVMOL7jUT5yjqTzpxcuE6YFQloi6oj3Dvw7 rOBzwzZ+pblplX65Lj3XbM3sdZ6WsLWXzcFdtSQz9AFfCe6kjn91uzaV/YJkkC1q4N++ gn30SQnpmZYJeVGxlIsHRD4P5fN3YPSCICIqZV9zfrnFJN2pVkAZkTUmXtUpQ7YRYInS gz01/TfFVZaVaxTFGQfyFJLFsdOOviD+c0979KKG0vgC3i5TM8sMg6WRh35NorImsOrN fIZQ8GOM7lYSfJBhKjYcmXj3SplMUtVE5c8EhareHj93g57w5kRmbLmmi0IyMAWODu+H kkoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427232; x=1780032032; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YQl/+OEhwF4NoyNWyxodfcJAzFD2ZvuV+faGp0XUU/Q=; b=a6wC32lcDVV4eyNzKLVcBModY5v1MMpp46G7u8nGPyF2qE0dCwWTk170J2ym02vOS6 lsFXcIGTy07BldQXgdFRJfh9PLRj/u1Sg07C4krDo+SNgs2nk6laOIOXLZ/Is8v2NkGk 3IY1cmPkTmLrTwXkVXtrl+E9sfDjAyhJEKMh8xlp2Bd3UmE+LoX3UYg5KoyyoQq7U3qw A/3Ip/aMNt11cAhSbMWwLcTJsRTvh1bgNNM2/oom6ZqX1gJHSaGPdYxvbCB1bcccg/OW A2tjjmRhE+isFdYoemo86MMAeq+sY08HD378TvFKij3OIDlPzsAhvJK2avt9NZ2lEuyt nJnQ== X-Gm-Message-State: AOJu0Yw5X39vRd/Bl3YYWLkOCmEbDuYUlK0yttz4x1Ohi4+Ej6CNWAXY gvrnQ0mP8iw8viPSm5KExX6G/a1bbUS9gPs5Tg9c+DvxDdJ0WO4r2mAn X-Gm-Gg: Acq92OEVoGYLyhS06K0FnFCdQyceSKXRQoF7i8lQJQJiCu7E2LjVh+Z3He/U80GBiP1 wABnHeZFiVjZZm393r2pMQXh88hk37Z9T/0y7NxITGU2VEHeSPyvD3W92IeSKP3DkdvPOeJxi/D 5jOY0qaMtOH/Z7WBaowOyPSzQ6RWQ6Nf4RqIRLLcCQHvY4+Ny7AA0puCUodWMsCCLGWoRXMjtrG vZU0pO2fCS+6yLJ6jChsqYPSrQphravdi1hmZ0c5S0sLtvw7thkzIj/mC7lxanK5o7gA5Jmt2YY j40wgjgOl+daoxTeepX7Y/Y/Lo0unk4pqd6eYdu7E/kQ7Y8PLSupLL1GY8s90omAtPKToaElVXi 8RuNQABtcuxvuY2kTEITQr/my7EUg8uvwf268S8iAp7FuIiIhz2/rXGfo3JHpG+Z1oT1NnkVbLk R5rs05BSIbh/HSf/lPy/u/+9CjnSXKCdQgDKHVP0sdlMRSRku2qFHqh48KW5yrThYvffzu0mLYn gfPVHr0F8z/Gfk5T1L7PqQScXnpczmL6lRPczuT9WxjcT6sZMoQLT2lDkpbYgzl93nN6M9qp+Cq peE= X-Received: by 2002:a05:6808:1b2a:b0:479:c81f:8e18 with SMTP id 5614622812f47-48549d6daa6mr1273512b6e.3.1779427231961; Thu, 21 May 2026 22:20:31 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:57 -0600 Subject: [PATCH v14 15/22] target/mips: decode Octeon COP2 register selectors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-15-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427331255154100 Add explicit decodetree entries and translator bindings for Octeon DMFC2/DMTC2 selectors that are simple COP2 register transfers. Emit direct TCG loads and stores for register moves. Use signed 32-bit loads for 32-bit DMFC2 readback and mask narrow writable fields such as AESKEYLEN and CRCLEN on DMTC2. Keep operation selectors with side effects in later functional decode patches. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v13 -> v14: - Add missing HSH DAT readback selectors. - Implement HSH DAT/IV selector transfers as paired low-32 architectural word moves using tcg_gen_concat32_i64(). - Move the CP2_Undef fallback into this selector patch. - Remove the redundant AES RESINP translator path. - Add HSH DAT readback smoke coverage. Changes v10 -> v13: - Keep simple register moves in their own selector patch. - Use final KAS result naming and final CRC register selector names. - Mask AESKEYLEN and CRCLEN direct writes. --- target/mips/tcg/octeon.decode | 80 ++++++++++ target/mips/tcg/octeon_translate.c | 210 ++++++++++++++++++++++= ++++ tests/tcg/mips/user/isa/octeon/octeon-insns.c | 89 +++++++++++ 3 files changed, 379 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 1e44c588dd..09fbc6c1e3 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -97,3 +97,83 @@ LBUX 011111 ..... ..... ..... 00110 001010 @lx LWUX 011111 ..... ..... ..... 10000 001010 @lx LBX 011111 ..... ..... ..... 10110 001010 @lx LDX 011111 ..... ..... ..... 01000 001010 @lx + +# Selector-driven DMFC2/DMTC2 interfaces for Octeon COP2 engines. +&cp2 rt +{ + [ + CVM_MF_HSH_IV0 010010 00001 rt:5 0000 0000 0100 = 1000 &cp2 + CVM_MF_HSH_IV1 010010 00001 rt:5 0000 0000 0100 = 1001 &cp2 + CVM_MF_HSH_IV2 010010 00001 rt:5 0000 0000 0100 = 1010 &cp2 + CVM_MF_HSH_IV3 010010 00001 rt:5 0000 0000 0100 = 1011 &cp2 + CVM_MF_HSH_DAT0 010010 00001 rt:5 0000 0000 0100 = 0000 &cp2 + CVM_MF_HSH_DAT1 010010 00001 rt:5 0000 0000 0100 = 0001 &cp2 + CVM_MF_HSH_DAT2 010010 00001 rt:5 0000 0000 0100 = 0010 &cp2 + CVM_MF_HSH_DAT3 010010 00001 rt:5 0000 0000 0100 = 0011 &cp2 + CVM_MF_HSH_DAT4 010010 00001 rt:5 0000 0000 0100 = 0100 &cp2 + CVM_MF_HSH_DAT5 010010 00001 rt:5 0000 0000 0100 = 0101 &cp2 + CVM_MF_HSH_DAT6 010010 00001 rt:5 0000 0000 0100 = 0110 &cp2 + CVM_MF_3DES_KEY0 010010 00001 rt:5 0000 0000 1000 = 0000 &cp2 + CVM_MF_3DES_KEY1 010010 00001 rt:5 0000 0000 1000 = 0001 &cp2 + CVM_MF_3DES_KEY2 010010 00001 rt:5 0000 0000 1000 = 0010 &cp2 + CVM_MF_3DES_IV 010010 00001 rt:5 0000 0000 1000 = 0100 &cp2 + CVM_MF_3DES_RESULT 010010 00001 rt:5 0000 0000 1000 = 1000 &cp2 + CVM_MF_KAS_RESULT 010010 00001 rt:5 0000 0000 1001 = 1000 &cp2 + CVM_MF_AES_RESINP0 010010 00001 rt:5 0000 0001 0000 = 0000 &cp2 + CVM_MF_AES_RESINP1 010010 00001 rt:5 0000 0001 0000 = 0001 &cp2 + CVM_MF_AES_IV0 010010 00001 rt:5 0000 0001 0000 = 0010 &cp2 + CVM_MF_AES_IV1 010010 00001 rt:5 0000 0001 0000 = 0011 &cp2 + CVM_MF_AES_KEY0 010010 00001 rt:5 0000 0001 0000 = 0100 &cp2 + CVM_MF_AES_KEY1 010010 00001 rt:5 0000 0001 0000 = 0101 &cp2 + CVM_MF_AES_KEY2 010010 00001 rt:5 0000 0001 0000 = 0110 &cp2 + CVM_MF_AES_KEY3 010010 00001 rt:5 0000 0001 0000 = 0111 &cp2 + CVM_MF_AES_KEYLENGTH 010010 00001 rt:5 0000 0001 0001 = 0000 &cp2 + CVM_MF_AES_INP0 010010 00001 rt:5 0000 0001 0001 = 0001 &cp2 + CVM_MF_CRC_POLYNOMIAL 010010 00001 rt:5 0000 0010 0000 = 0000 &cp2 + CVM_MF_CRC_IV 010010 00001 rt:5 0000 0010 0000 = 0001 &cp2 + CVM_MF_CRC_LEN 010010 00001 rt:5 0000 0010 0000 = 0010 &cp2 + CVM_MF_GFM_MUL0 010010 00001 rt:5 0000 0010 0101 = 1000 &cp2 + CVM_MF_GFM_MUL1 010010 00001 rt:5 0000 0010 0101 = 1001 &cp2 + CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 = 1010 &cp2 + CVM_MF_GFM_RESINP1 010010 00001 rt:5 0000 0010 0101 = 1011 &cp2 + CVM_MF_GFM_POLY 010010 00001 rt:5 0000 0010 0101 = 1110 &cp2 + CVM_MT_HSH_DAT0 010010 00101 rt:5 0000 0000 0100 = 0000 &cp2 + CVM_MT_HSH_DAT1 010010 00101 rt:5 0000 0000 0100 = 0001 &cp2 + CVM_MT_HSH_DAT2 010010 00101 rt:5 0000 0000 0100 = 0010 &cp2 + CVM_MT_HSH_DAT3 010010 00101 rt:5 0000 0000 0100 = 0011 &cp2 + CVM_MT_HSH_DAT4 010010 00101 rt:5 0000 0000 0100 = 0100 &cp2 + CVM_MT_HSH_DAT5 010010 00101 rt:5 0000 0000 0100 = 0101 &cp2 + CVM_MT_HSH_DAT6 010010 00101 rt:5 0000 0000 0100 = 0110 &cp2 + CVM_MT_HSH_IV0 010010 00101 rt:5 0000 0000 0100 = 1000 &cp2 + CVM_MT_HSH_IV1 010010 00101 rt:5 0000 0000 0100 = 1001 &cp2 + CVM_MT_HSH_IV2 010010 00101 rt:5 0000 0000 0100 = 1010 &cp2 + CVM_MT_HSH_IV3 010010 00101 rt:5 0000 0000 0100 = 1011 &cp2 + CVM_MT_3DES_KEY0 010010 00101 rt:5 0000 0000 1000 = 0000 &cp2 + CVM_MT_3DES_KEY1 010010 00101 rt:5 0000 0000 1000 = 0001 &cp2 + CVM_MT_3DES_KEY2 010010 00101 rt:5 0000 0000 1000 = 0010 &cp2 + CVM_MT_3DES_IV 010010 00101 rt:5 0000 0000 1000 = 0100 &cp2 + CVM_MT_3DES_RESULT 010010 00101 rt:5 0000 0000 1001 = 1000 &cp2 + CVM_MT_AES_RESINP0 010010 00101 rt:5 0000 0001 0000 = 0000 &cp2 + CVM_MT_AES_RESINP1 010010 00101 rt:5 0000 0001 0000 = 0001 &cp2 + CVM_MT_AES_IV0 010010 00101 rt:5 0000 0001 0000 = 0010 &cp2 + CVM_MT_AES_IV1 010010 00101 rt:5 0000 0001 0000 = 0011 &cp2 + CVM_MT_AES_KEY0 010010 00101 rt:5 0000 0001 0000 = 0100 &cp2 + CVM_MT_AES_KEY1 010010 00101 rt:5 0000 0001 0000 = 0101 &cp2 + CVM_MT_AES_KEY2 010010 00101 rt:5 0000 0001 0000 = 0110 &cp2 + CVM_MT_AES_KEY3 010010 00101 rt:5 0000 0001 0000 = 0111 &cp2 + CVM_MT_AES_ENC_CBC0 010010 00101 rt:5 0000 0001 0000 = 1000 &cp2 + CVM_MT_AES_ENC0 010010 00101 rt:5 0000 0001 0000 = 1010 &cp2 + CVM_MT_AES_DEC_CBC0 010010 00101 rt:5 0000 0001 0000 = 1100 &cp2 + CVM_MT_AES_DEC0 010010 00101 rt:5 0000 0001 0000 = 1110 &cp2 + CVM_MT_AES_KEYLENGTH 010010 00101 rt:5 0000 0001 0001 = 0000 &cp2 + CVM_MT_CRC_IV 010010 00101 rt:5 0000 0010 0000 = 0001 &cp2 + CVM_MT_GFM_MUL0 010010 00101 rt:5 0000 0010 0101 = 1000 &cp2 + CVM_MT_GFM_MUL1 010010 00101 rt:5 0000 0010 0101 = 1001 &cp2 + CVM_MT_GFM_RESINP0 010010 00101 rt:5 0000 0010 0101 = 1010 &cp2 + CVM_MT_GFM_RESINP1 010010 00101 rt:5 0000 0010 0101 = 1011 &cp2 + CVM_MT_GFM_POLY 010010 00101 rt:5 0000 0010 0101 = 1110 &cp2 + CVM_MT_CRC_LEN 010010 00101 rt:5 0001 0010 0000 = 0010 &cp2 + CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 = 0000 &cp2 + ] + CP2_Undef 010010 ----- ----- ---- ---- ----= ---- +} diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index b0af2f4838..b33252dd1f 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -13,6 +13,216 @@ /* Include the auto-generated decoder. */ #include "decode-octeon.c.inc" =20 +#define OCTEON_CRYPTO_OFFSET(FIELD) \ + offsetof(CPUMIPSState, octeon_crypto.FIELD) + +#define CP2_MF_I64(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mf_i64, OCTEON_CRYPTO_OFFSET(FIELD)) +#define CP2_MF_S32(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mf_s32, OCTEON_CRYPTO_OFFSET(FIELD)) +#define CP2_MF_U16(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mf_u16, OCTEON_CRYPTO_OFFSET(FIELD)) +#define CP2_MF_U8(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mf_u8, OCTEON_CRYPTO_OFFSET(FIELD)) +#define CP2_MF_HSH_PAIR(NAME, FIELD, INDEX) \ + TRANS(NAME, trans_octeon_cp2_mf_hsh_pair, \ + OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \ + OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1])) +#define CP2_MT_I64(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mt_i64, OCTEON_CRYPTO_OFFSET(FIELD)) +#define CP2_MT_U32(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mt_u32, OCTEON_CRYPTO_OFFSET(FIELD)) +#define CP2_MT_U16(NAME, FIELD) \ + TRANS(NAME, trans_octeon_cp2_mt_u16, OCTEON_CRYPTO_OFFSET(FIELD)) +#define CP2_MT_U8_MASKED(NAME, FIELD, MASK) \ + TRANS(NAME, trans_octeon_cp2_mt_u8_masked, \ + OCTEON_CRYPTO_OFFSET(FIELD), MASK) +#define CP2_MT_HSH_PAIR(NAME, FIELD, INDEX) \ + TRANS(NAME, trans_octeon_cp2_mt_hsh_pair, \ + OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \ + OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1])) + +#define OCTEON_LO32_OFFSET (HOST_BIG_ENDIAN ? 4 : 0) + +static bool trans_CP2_Undef(DisasContext *ctx, arg_CP2_Undef *a) +{ + generate_exception_err(ctx, EXCP_CpU, 2); + return true; +} + +static bool trans_octeon_cp2_mf_i64(DisasContext *ctx, arg_cp2 *a, int off= set) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + tcg_gen_ld_i64(value, tcg_env, offset); + gen_store_gpr(value, a->rt); + return true; +} + +static bool trans_octeon_cp2_mf_s32(DisasContext *ctx, arg_cp2 *a, int off= set) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + tcg_gen_ld32s_i64(value, tcg_env, offset); + gen_store_gpr(value, a->rt); + return true; +} + +static bool trans_octeon_cp2_mf_u16(DisasContext *ctx, arg_cp2 *a, int off= set) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + tcg_gen_ld16u_i64(value, tcg_env, offset); + gen_store_gpr(value, a->rt); + return true; +} + +static bool trans_octeon_cp2_mf_u8(DisasContext *ctx, arg_cp2 *a, int offs= et) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + tcg_gen_ld8u_i64(value, tcg_env, offset); + gen_store_gpr(value, a->rt); + return true; +} + +static bool trans_octeon_cp2_mf_hsh_pair(DisasContext *ctx, arg_cp2 *a, + int hi_offset, int lo_offset) +{ + TCGv_i64 hi =3D tcg_temp_new_i64(); + TCGv_i64 lo =3D tcg_temp_new_i64(); + + tcg_gen_ld_i64(hi, tcg_env, hi_offset); + tcg_gen_ld_i64(lo, tcg_env, lo_offset); + tcg_gen_concat32_i64(lo, lo, hi); + gen_store_gpr(lo, a->rt); + return true; +} + +static bool trans_octeon_cp2_mt_i64(DisasContext *ctx, arg_cp2 *a, int off= set) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + gen_load_gpr(value, a->rt); + tcg_gen_st_i64(value, tcg_env, offset); + return true; +} + +static bool trans_octeon_cp2_mt_u32(DisasContext *ctx, arg_cp2 *a, int off= set) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + gen_load_gpr(value, a->rt); + tcg_gen_st32_i64(value, tcg_env, offset); + return true; +} + +static bool trans_octeon_cp2_mt_u16(DisasContext *ctx, arg_cp2 *a, int off= set) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + gen_load_gpr(value, a->rt); + tcg_gen_st16_i64(value, tcg_env, offset); + return true; +} + +static bool trans_octeon_cp2_mt_u8_masked(DisasContext *ctx, arg_cp2 *a, + int offset, uint8_t mask) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + gen_load_gpr(value, a->rt); + tcg_gen_andi_i64(value, value, mask); + tcg_gen_st8_i64(value, tcg_env, offset); + return true; +} + +static bool trans_octeon_cp2_mt_hsh_pair(DisasContext *ctx, arg_cp2 *a, + int hi_offset, int lo_offset) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + gen_load_gpr(value, a->rt); + tcg_gen_st32_i64(value, tcg_env, lo_offset + OCTEON_LO32_OFFSET); + tcg_gen_shri_i64(value, value, 32); + tcg_gen_st32_i64(value, tcg_env, hi_offset + OCTEON_LO32_OFFSET); + return true; +} + +CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT0, hsh_dat, 0); +CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT1, hsh_dat, 1); +CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT2, hsh_dat, 2); +CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT3, hsh_dat, 3); +CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT4, hsh_dat, 4); +CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT5, hsh_dat, 5); +CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT6, hsh_dat, 6); +CP2_MF_HSH_PAIR(CVM_MF_HSH_IV0, hsh_iv, 0); +CP2_MF_HSH_PAIR(CVM_MF_HSH_IV1, hsh_iv, 1); +CP2_MF_HSH_PAIR(CVM_MF_HSH_IV2, hsh_iv, 2); +CP2_MF_HSH_PAIR(CVM_MF_HSH_IV3, hsh_iv, 3); +CP2_MF_I64(CVM_MF_3DES_KEY0, des3_key[0]); +CP2_MF_I64(CVM_MF_3DES_KEY1, des3_key[1]); +CP2_MF_I64(CVM_MF_3DES_KEY2, des3_key[2]); +CP2_MF_I64(CVM_MF_3DES_IV, des3_iv); +CP2_MF_I64(CVM_MF_3DES_RESULT, des3_result); +CP2_MF_I64(CVM_MF_KAS_RESULT, des3_result); +CP2_MF_I64(CVM_MF_AES_RESINP0, aes_resinp[0]); +CP2_MF_I64(CVM_MF_AES_RESINP1, aes_resinp[1]); +CP2_MF_I64(CVM_MF_AES_IV0, aes_iv[0]); +CP2_MF_I64(CVM_MF_AES_IV1, aes_iv[1]); +CP2_MF_I64(CVM_MF_AES_KEY0, aes_key[0]); +CP2_MF_I64(CVM_MF_AES_KEY1, aes_key[1]); +CP2_MF_I64(CVM_MF_AES_KEY2, aes_key[2]); +CP2_MF_I64(CVM_MF_AES_KEY3, aes_key[3]); +CP2_MF_U8(CVM_MF_AES_KEYLENGTH, aes_keylen); +CP2_MF_I64(CVM_MF_AES_INP0, aes_resinp[0]); +CP2_MF_S32(CVM_MF_CRC_POLYNOMIAL, crc_poly); +CP2_MF_S32(CVM_MF_CRC_IV, crc_iv); +CP2_MF_U8(CVM_MF_CRC_LEN, crc_len); +CP2_MF_I64(CVM_MF_GFM_MUL0, gfm_mul[0]); +CP2_MF_I64(CVM_MF_GFM_MUL1, gfm_mul[1]); +CP2_MF_I64(CVM_MF_GFM_RESINP0, gfm_resinp[0]); +CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]); +CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly); + +CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT0, hsh_dat, 0); +CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT1, hsh_dat, 1); +CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT2, hsh_dat, 2); +CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT3, hsh_dat, 3); +CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT4, hsh_dat, 4); +CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT5, hsh_dat, 5); +CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT6, hsh_dat, 6); +CP2_MT_HSH_PAIR(CVM_MT_HSH_IV0, hsh_iv, 0); +CP2_MT_HSH_PAIR(CVM_MT_HSH_IV1, hsh_iv, 1); +CP2_MT_HSH_PAIR(CVM_MT_HSH_IV2, hsh_iv, 2); +CP2_MT_HSH_PAIR(CVM_MT_HSH_IV3, hsh_iv, 3); +CP2_MT_I64(CVM_MT_3DES_KEY0, des3_key[0]); +CP2_MT_I64(CVM_MT_3DES_KEY1, des3_key[1]); +CP2_MT_I64(CVM_MT_3DES_KEY2, des3_key[2]); +CP2_MT_I64(CVM_MT_3DES_IV, des3_iv); +CP2_MT_I64(CVM_MT_3DES_RESULT, des3_result); +CP2_MT_I64(CVM_MT_AES_RESINP0, aes_resinp[0]); +CP2_MT_I64(CVM_MT_AES_RESINP1, aes_resinp[1]); +CP2_MT_I64(CVM_MT_AES_IV0, aes_iv[0]); +CP2_MT_I64(CVM_MT_AES_IV1, aes_iv[1]); +CP2_MT_I64(CVM_MT_AES_KEY0, aes_key[0]); +CP2_MT_I64(CVM_MT_AES_KEY1, aes_key[1]); +CP2_MT_I64(CVM_MT_AES_KEY2, aes_key[2]); +CP2_MT_I64(CVM_MT_AES_KEY3, aes_key[3]); +CP2_MT_I64(CVM_MT_AES_ENC_CBC0, aes_resinp[0]); +CP2_MT_I64(CVM_MT_AES_ENC0, aes_resinp[0]); +CP2_MT_I64(CVM_MT_AES_DEC_CBC0, aes_resinp[0]); +CP2_MT_I64(CVM_MT_AES_DEC0, aes_resinp[0]); +CP2_MT_U8_MASKED(CVM_MT_AES_KEYLENGTH, aes_keylen, 3); +CP2_MT_U32(CVM_MT_CRC_IV, crc_iv); +CP2_MT_I64(CVM_MT_GFM_MUL0, gfm_mul[0]); +CP2_MT_I64(CVM_MT_GFM_MUL1, gfm_mul[1]); +CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]); +CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]); +CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly); +CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf); +CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly); + static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) { TCGv_i64 p; diff --git a/tests/tcg/mips/user/isa/octeon/octeon-insns.c b/tests/tcg/mips= /user/isa/octeon/octeon-insns.c index 9153e37e9e..7a7445c40a 100644 --- a/tests/tcg/mips/user/isa/octeon/octeon-insns.c +++ b/tests/tcg/mips/user/isa/octeon/octeon-insns.c @@ -186,6 +186,86 @@ static uint64_t octeon_mtp0_zeroes_p1(void) return rd; } =20 +static uint64_t octeon_cop2_key0_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a80104\n\t" /* dmtc2 $8, AES_KEY0 selector */ + ".word 0x482a0104\n\t" /* dmfc2 $10, AES_KEY0 selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_cop2_key2_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a80106\n\t" /* dmtc2 $8, AES_KEY2 selector */ + ".word 0x482a0106\n\t" /* dmfc2 $10, AES_KEY2 selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_cop2_key3_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a80107\n\t" /* dmtc2 $8, AES_KEY3 selector */ + ".word 0x482a0107\n\t" /* dmfc2 $10, AES_KEY3 selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_cop2_keylength_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a80110\n\t" /* dmtc2 $8, AES_KEYLENGTH selector */ + ".word 0x482a0110\n\t" /* dmfc2 $10, AES_KEYLENGTH selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_cop2_hsh_dat0_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a80040\n\t" /* dmtc2 $8, HSH_DAT0 selector */ + ".word 0x482a0040\n\t" /* dmfc2 $10, HSH_DAT0 selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + int main(void) { assert(octeon_baddu(0x123, 0x0f0) =3D=3D 0x13); @@ -199,6 +279,15 @@ int main(void) assert(octeon_vmm0(5, 13, 7, 11) =3D=3D 59); assert(octeon_vmm0_zeroes_mpl1() =3D=3D 0); assert(octeon_mtp0_zeroes_p1() =3D=3D 0); + assert(octeon_cop2_key0_readback(0x1122334455667788ULL) =3D=3D + 0x1122334455667788ULL); + assert(octeon_cop2_key2_readback(0x8877665544332211ULL) =3D=3D + 0x8877665544332211ULL); + assert(octeon_cop2_key3_readback(0x0102030405060708ULL) =3D=3D + 0x0102030405060708ULL); + assert(octeon_cop2_keylength_readback(0xa5) =3D=3D 1); + assert(octeon_cop2_hsh_dat0_readback(0x0102030405060708ULL) =3D=3D + 0x0102030405060708ULL); =20 return 0; } --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427392; cv=none; d=zohomail.com; s=zohoarc; b=TtJYJ7vm0MvpgWkq70xSVQTyt5Vk7q7BKa4BmpI4eRQMN9F1AMHjj7+S9zY4s8x38EC3Smf6yJk2nNBiTG4HfyrlJ39OuOAXjyQi7CS5A4Z7ze60HKKVa9tmJyitgkqkSi9Jd7puaDJ0AO128n8WZggplcJCG8wryrgn5lkDX4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427392; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/WF+mRTfCc/KOPYVrWPTkEYmSm98aCGr97ayPccbjYA=; b=Jlcx41leMQGx+bA4wWRN3JqXdoCca/93yPCJrxoP5h2Bdefb8baYJ4nCgfz0Vb5Y26PvHsFZEoCERSC0sy3MnBrMDep1WrFZ3QfuwJlpOE4ZxcpxCMyNWvq5lEopl07ZN2p+k1u44yAgLS1exKd8n9MO1pzz1TCTbT4i00gvtVE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427392313241.394282352211; Thu, 21 May 2026 22:23:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJX-0003Il-DN; Fri, 22 May 2026 01:20:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJJ-0002p2-E2 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:37 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJG-0002BF-MK for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:37 -0400 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-479f7e75a6bso2647086b6e.2 for ; Thu, 21 May 2026 22:20:34 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427233; x=1780032033; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/WF+mRTfCc/KOPYVrWPTkEYmSm98aCGr97ayPccbjYA=; b=BMqtNfTnwCAVmmkQ6DoNSHwT6tWLEKjJcgCdZ+yyaQIInxffZv8mGqPvsnQo5zHiMN HSse2P+gPjY661PDP1Le19rPfLExsq9q+Aw3IUO1nSeCu+DoVajUuJn2yMM8CDIQ0+TW 4iDUYcc7+Xd9Y/hDKpRLDtFyta4F+I/PCW3EBUQjQtvo56LYB2WgwE1uhX+bY+ggs1b0 eoW5nNWKpD8pNpzWB4kctKSUeE6z1e96bDlJwpQ/+4rqvZeN/ppKP5XXd+cHDWfAwydD 7scT0bYnr9FSkP55/Io+/1GMeVzCJS9nApGzcZJCgwsUBUZ/n67sGHmnM4BmUD125pC3 nhNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427233; x=1780032033; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=/WF+mRTfCc/KOPYVrWPTkEYmSm98aCGr97ayPccbjYA=; b=W0ZQwM56xlKshIgVGKdJ5VSmbmHiJWKZylyvhWo+FGggGdgth0Vm92ZwXoS9KQa83l AvBUlhYEuZe3sPUZ2ndMus4K+eGVXvh4v1mrDZKID3e7/3W4/GSaljMTHTOWx7k9dE5E 2CszAo8VjQCWrYO9HWoGd0T3bS+8qqynwsc10RhYeOD+IFx9Jk2iOAgBCMU/ipsnTa4i 1d1Fvceag0TkXXP7gj7kifz7EzRDlaJkhxbikDfN1pnE/cRogUjc1nWQLvClcDcScOgf mT9GfjMCFscfSPu6iNIXsC1tLC4XF2/KZj4QerXCNZk/Kgq0bwaP0gSXSqsO1cn16J4T lkHA== X-Gm-Message-State: AOJu0YyhUR5+EHoU43zuLgqCOMxyFBrJLfYmge/x5NAcG/OcS4uhUnj5 tk82JzpjDEtaj1cV/vhsZdrcn9SPosZPHKqptshw+O3374mfnf0BOQ/F X-Gm-Gg: Acq92OGa2sGZmT1NMXHiCLpOEL6beNEfFsI36ymjWpWtQP6OFzY2cZzSma4b95eDxsl QS7rmJI046w0AJJoZboye1aeCYKt7Ij5neHYoiZvJ/wNN8ig/Lm7tExQhEWgmeua7yEVIzv6LWq VMzfdQ7WDndC3JWGhS/cEo3DbOlS+2xFLTdhmGAImJ0TPdY7/diY15FDr8IKlvxXn15yprgGpfm jSO76gGxI/+Ekcnxh3Ev04CbpI76R7mrivP5oDkncTNyVnYPwCS+zDY1eKHoYflyRjl/DKqeokV z2nDg8WdXOwsaoPpZKwAWMFq60ks5p8XjYgn2KLeIoRazEI1bIhQYARKOpUd5QMzw6weZEXPxxN Uez6716GRcEB1wiYOhrNuuuUVEnDt2fhPrtd5kDKVUK7PiD9eUX1b5UuI5EpqbDmgIpJn6u5IRg /nDQ8VXufvBfogCRM00mrhQKHvehDWgVb0rPKwHipxYSgxxkhIWaVKsj2YxeS2DE0q+JMPHJ6Xy uv+PjoNnuOcYHkSX8GLLx1Ib3r/VVwx24NQoTSy8jMSEjwoPOmrAanYXD1vQ+9daVMV4RPCgJN8 LLQ= X-Received: by 2002:a05:6808:5387:b0:485:3dd3:7717 with SMTP id 5614622812f47-4854a181c53mr1234666b6e.24.1779427233242; Thu, 21 May 2026 22:20:33 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:58 -0600 Subject: [PATCH v14 16/22] target/mips: decode Octeon CRC and GFM COP2 selectors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-16-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427394212154100 Add explicit decodetree entries and translator bindings for the Octeon CRC and GFM COP2 operation selectors. Unlike simple register moves, these selectors update CRC or Galois-field state and therefore remain per-operation helper calls. Keep CRC/GFM decode next to the helpers that implement these side effects while avoiding a monolithic selector-dispatch helper. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v10 -> v13: - Split simple register-transfer selectors into a separate COP2 register selector patch. - Use final CRC selector names in this patch instead of renaming them later in the series. - Route reflected GFM selectors through helpers immediately so no non-architectural reflected GFM state is introduced. - Add the reflected CRC polynomial helper with the selector decode that uses it. --- target/mips/helper.h | 1 + target/mips/tcg/octeon.decode | 22 +++++++++ target/mips/tcg/octeon_crypto.c | 7 +++ target/mips/tcg/octeon_translate.c | 50 +++++++++++++++++++ tests/tcg/mips/user/isa/octeon/octeon-insns.c | 70 +++++++++++++++++++++++= ++++ 5 files changed, 150 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index c062863582..2902dde889 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -33,6 +33,7 @@ DEF_HELPER_1(octeon_cp2_mf_gfm_mul_reflect1, i64, env) DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect0, i64, env) DEF_HELPER_1(octeon_cp2_mf_gfm_resinp_reflect1, i64, env) DEF_HELPER_2(octeon_cp2_mt_crc_write_iv_reflect, void, env, i64) +DEF_HELPER_2(octeon_cp2_mt_crc_write_polynomial_reflect, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_byte, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_half, void, env, i64) DEF_HELPER_2(octeon_cp2_mt_crc_write_word, void, env, i64) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 09fbc6c1e3..70e02d0b0e 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -132,6 +132,11 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MF_CRC_POLYNOMIAL 010010 00001 rt:5 0000 0010 0000 = 0000 &cp2 CVM_MF_CRC_IV 010010 00001 rt:5 0000 0010 0000 = 0001 &cp2 CVM_MF_CRC_LEN 010010 00001 rt:5 0000 0010 0000 = 0010 &cp2 + CVM_MF_CRC_IV_REFLECT 010010 00001 rt:5 0000 0010 0000 = 0011 &cp2 + CVM_MF_GFM_MUL_REFLECT0 010010 00001 rt:5 0000 0000 0101 = 1000 &cp2 + CVM_MF_GFM_MUL_REFLECT1 010010 00001 rt:5 0000 0000 0101 = 1001 &cp2 + CVM_MF_GFM_RESINP_REFLECT0 010010 00001 rt:5 0000 0000 0101 = 1010 &cp2 + CVM_MF_GFM_RESINP_REFLECT1 010010 00001 rt:5 0000 0000 0101 = 1011 &cp2 CVM_MF_GFM_MUL0 010010 00001 rt:5 0000 0010 0101 = 1000 &cp2 CVM_MF_GFM_MUL1 010010 00001 rt:5 0000 0010 0101 = 1001 &cp2 CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 = 1010 &cp2 @@ -148,6 +153,9 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_HSH_IV1 010010 00101 rt:5 0000 0000 0100 = 1001 &cp2 CVM_MT_HSH_IV2 010010 00101 rt:5 0000 0000 0100 = 1010 &cp2 CVM_MT_HSH_IV3 010010 00101 rt:5 0000 0000 0100 = 1011 &cp2 + CVM_MT_GFM_MUL_REFLECT0 010010 00101 rt:5 0000 0000 0101 = 1000 &cp2 + CVM_MT_GFM_MUL_REFLECT1 010010 00101 rt:5 0000 0000 0101 = 1001 &cp2 + CVM_MT_GFM_XOR0_REFLECT 010010 00101 rt:5 0000 0000 0101 = 1100 &cp2 CVM_MT_3DES_KEY0 010010 00101 rt:5 0000 0000 1000 = 0000 &cp2 CVM_MT_3DES_KEY1 010010 00101 rt:5 0000 0000 1000 = 0001 &cp2 CVM_MT_3DES_KEY2 010010 00101 rt:5 0000 0000 1000 = 0010 &cp2 @@ -167,13 +175,27 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_AES_DEC0 010010 00101 rt:5 0000 0001 0000 = 1110 &cp2 CVM_MT_AES_KEYLENGTH 010010 00101 rt:5 0000 0001 0001 = 0000 &cp2 CVM_MT_CRC_IV 010010 00101 rt:5 0000 0010 0000 = 0001 &cp2 + CVM_MT_CRC_IV_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0001 &cp2 + CVM_MT_CRC_BYTE 010010 00101 rt:5 0000 0010 0000 = 0100 &cp2 + CVM_MT_CRC_HALF 010010 00101 rt:5 0000 0010 0000 = 0101 &cp2 + CVM_MT_CRC_WORD 010010 00101 rt:5 0000 0010 0000 = 0110 &cp2 + CVM_MT_CRC_BYTE_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0100 &cp2 + CVM_MT_CRC_HALF_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0101 &cp2 + CVM_MT_CRC_WORD_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0110 &cp2 CVM_MT_GFM_MUL0 010010 00101 rt:5 0000 0010 0101 = 1000 &cp2 CVM_MT_GFM_MUL1 010010 00101 rt:5 0000 0010 0101 = 1001 &cp2 CVM_MT_GFM_RESINP0 010010 00101 rt:5 0000 0010 0101 = 1010 &cp2 CVM_MT_GFM_RESINP1 010010 00101 rt:5 0000 0010 0101 = 1011 &cp2 CVM_MT_GFM_POLY 010010 00101 rt:5 0000 0010 0101 = 1110 &cp2 CVM_MT_CRC_LEN 010010 00101 rt:5 0001 0010 0000 = 0010 &cp2 + CVM_MT_CRC_DWORD 010010 00101 rt:5 0001 0010 0000 = 0111 &cp2 + CVM_MT_CRC_VAR 010010 00101 rt:5 0001 0010 0000 = 1000 &cp2 + CVM_MT_CRC_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 = 0111 &cp2 + CVM_MT_CRC_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 = 1000 &cp2 + CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 = 1101 &cp2 CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 = 0000 &cp2 + CVM_MT_CRC_POLYNOMIAL_REFLECT 010010 00101 rt:5 0100 0010 0001 = 0000 &cp2 + CVM_MT_GFM_XORMUL1 010010 00101 rt:5 0100 0010 0101 = 1101 &cp2 ] CP2_Undef 010010 ----- ----- ---- ---- ----= ---- } diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypt= o.c index 742c707633..278780e190 100644 --- a/target/mips/tcg/octeon_crypto.c +++ b/target/mips/tcg/octeon_crypto.c @@ -2305,6 +2305,13 @@ void helper_octeon_cp2_mt_crc_write_iv_reflect(CPUMI= PSState *env, octeon_crc_reflect32_by_byte((uint32_t)value); } =20 +void helper_octeon_cp2_mt_crc_write_polynomial_reflect(CPUMIPSState *env, + uint64_t value) +{ + env->octeon_crypto.crc_poly =3D + octeon_crc_reflect32_by_byte((uint32_t)value); +} + void helper_octeon_cp2_mt_crc_write_byte(CPUMIPSState *env, uint64_t value) { octeon_crc_update_normal(&env->octeon_crypto, value, 1); diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index b33252dd1f..ce4cfcb3f3 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -28,6 +28,9 @@ TRANS(NAME, trans_octeon_cp2_mf_hsh_pair, \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1])) +#define CP2_MF_HELPER(NAME, SUFFIX) \ + TRANS(NAME, trans_octeon_cp2_mf_helper, \ + gen_helper_octeon_cp2_mf_ ## SUFFIX) #define CP2_MT_I64(NAME, FIELD) \ TRANS(NAME, trans_octeon_cp2_mt_i64, OCTEON_CRYPTO_OFFSET(FIELD)) #define CP2_MT_U32(NAME, FIELD) \ @@ -41,6 +44,9 @@ TRANS(NAME, trans_octeon_cp2_mt_hsh_pair, \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX)]), \ OCTEON_CRYPTO_OFFSET(FIELD[2 * (INDEX) + 1])) +#define CP2_MT_HELPER(NAME, SUFFIX) \ + TRANS(NAME, trans_octeon_cp2_mt_helper, \ + gen_helper_octeon_cp2_mt_ ## SUFFIX) =20 #define OCTEON_LO32_OFFSET (HOST_BIG_ENDIAN ? 4 : 0) =20 @@ -99,6 +105,16 @@ static bool trans_octeon_cp2_mf_hsh_pair(DisasContext *= ctx, arg_cp2 *a, return true; } =20 +static bool trans_octeon_cp2_mf_helper(DisasContext *ctx, arg_cp2 *a, + void (*gen_helper)(TCGv_i64, TCGv_e= nv)) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + gen_helper(value, tcg_env); + gen_store_gpr(value, a->rt); + return true; +} + static bool trans_octeon_cp2_mt_i64(DisasContext *ctx, arg_cp2 *a, int off= set) { TCGv_i64 value =3D tcg_temp_new_i64(); @@ -149,6 +165,16 @@ static bool trans_octeon_cp2_mt_hsh_pair(DisasContext = *ctx, arg_cp2 *a, return true; } =20 +static bool trans_octeon_cp2_mt_helper(DisasContext *ctx, arg_cp2 *a, + void (*gen_helper)(TCGv_env, TCGv_i= 64)) +{ + TCGv_i64 value =3D tcg_temp_new_i64(); + + gen_load_gpr(value, a->rt); + gen_helper(tcg_env, value); + return true; +} + CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT0, hsh_dat, 0); CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT1, hsh_dat, 1); CP2_MF_HSH_PAIR(CVM_MF_HSH_DAT2, hsh_dat, 2); @@ -185,6 +211,12 @@ CP2_MF_I64(CVM_MF_GFM_RESINP0, gfm_resinp[0]); CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]); CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly); =20 +CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect); +CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT0, gfm_mul_reflect0); +CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT1, gfm_mul_reflect1); +CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp_reflect0); +CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp_reflect1); + CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT0, hsh_dat, 0); CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT1, hsh_dat, 1); CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT2, hsh_dat, 2); @@ -196,6 +228,9 @@ CP2_MT_HSH_PAIR(CVM_MT_HSH_IV0, hsh_iv, 0); CP2_MT_HSH_PAIR(CVM_MT_HSH_IV1, hsh_iv, 1); CP2_MT_HSH_PAIR(CVM_MT_HSH_IV2, hsh_iv, 2); CP2_MT_HSH_PAIR(CVM_MT_HSH_IV3, hsh_iv, 3); +CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT0, gfm_mul_reflect0); +CP2_MT_HELPER(CVM_MT_GFM_MUL_REFLECT1, gfm_mul_reflect1); +CP2_MT_HELPER(CVM_MT_GFM_XOR0_REFLECT, gfm_xor0_reflect); CP2_MT_I64(CVM_MT_3DES_KEY0, des3_key[0]); CP2_MT_I64(CVM_MT_3DES_KEY1, des3_key[1]); CP2_MT_I64(CVM_MT_3DES_KEY2, des3_key[2]); @@ -223,6 +258,21 @@ CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly); CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf); CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly); =20 +CP2_MT_HELPER(CVM_MT_CRC_POLYNOMIAL_REFLECT, crc_write_polynomial_reflect); +CP2_MT_HELPER(CVM_MT_CRC_IV_REFLECT, crc_write_iv_reflect); +CP2_MT_HELPER(CVM_MT_CRC_BYTE, crc_write_byte); +CP2_MT_HELPER(CVM_MT_CRC_HALF, crc_write_half); +CP2_MT_HELPER(CVM_MT_CRC_WORD, crc_write_word); +CP2_MT_HELPER(CVM_MT_CRC_BYTE_REFLECT, crc_write_byte_reflect); +CP2_MT_HELPER(CVM_MT_CRC_HALF_REFLECT, crc_write_half_reflect); +CP2_MT_HELPER(CVM_MT_CRC_WORD_REFLECT, crc_write_word_reflect); +CP2_MT_HELPER(CVM_MT_CRC_DWORD, crc_write_dword); +CP2_MT_HELPER(CVM_MT_CRC_VAR, crc_write_var); +CP2_MT_HELPER(CVM_MT_CRC_DWORD_REFLECT, crc_write_dword_reflect); +CP2_MT_HELPER(CVM_MT_CRC_VAR_REFLECT, crc_write_var_reflect); +CP2_MT_HELPER(CVM_MT_GFM_XORMUL1_REFLECT, gfm_xormul1_reflect); +CP2_MT_HELPER(CVM_MT_GFM_XORMUL1, gfm_xormul1); + static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) { TCGv_i64 p; diff --git a/tests/tcg/mips/user/isa/octeon/octeon-insns.c b/tests/tcg/mips= /user/isa/octeon/octeon-insns.c index 7a7445c40a..f3c52d7829 100644 --- a/tests/tcg/mips/user/isa/octeon/octeon-insns.c +++ b/tests/tcg/mips/user/isa/octeon/octeon-insns.c @@ -266,6 +266,70 @@ static uint64_t octeon_cop2_hsh_dat0_readback(uint64_t= value) return rd; } =20 +static uint64_t octeon_cop2_crc_len_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a81202\n\t" /* dmtc2 $8, CRC_LEN selector */ + ".word 0x482a0202\n\t" /* dmfc2 $10, CRC_LEN selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_cop2_crc_poly_reflect_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a84210\n\t" /* dmtc2 $8, CRC_POLYNOMIAL_REFLECT selecto= r */ + ".word 0x482a0200\n\t" /* dmfc2 $10, CRC_POLYNOMIAL selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_cop2_gfm_mul_reflect_write_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a80058\n\t" /* dmtc2 $8, GFM_MUL_REFLECT0 selector */ + ".word 0x482a0258\n\t" /* dmfc2 $10, GFM_MUL0 selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_cop2_gfm_mul_reflect_readback(uint64_t value) +{ + uint64_t rd; + + asm volatile( + "move $8, %[value]\n\t" + ".word 0x48a80258\n\t" /* dmtc2 $8, GFM_MUL0 selector */ + ".word 0x482a0058\n\t" /* dmfc2 $10, GFM_MUL_REFLECT0 selector */ + "move %[rd], $10\n\t" + : [rd] "=3Dr" (rd) + : [value] "r" (value) + : "$8", "$10"); + + return rd; +} + int main(void) { assert(octeon_baddu(0x123, 0x0f0) =3D=3D 0x13); @@ -288,6 +352,12 @@ int main(void) assert(octeon_cop2_keylength_readback(0xa5) =3D=3D 1); assert(octeon_cop2_hsh_dat0_readback(0x0102030405060708ULL) =3D=3D 0x0102030405060708ULL); + assert(octeon_cop2_crc_len_readback(0xb5) =3D=3D 5); + assert(octeon_cop2_crc_poly_reflect_readback(0x12345678) =3D=3D 0x482c= 6a1e); + assert(octeon_cop2_gfm_mul_reflect_write_readback( + 0x0123456789abcdefULL) =3D=3D 0xf7b3d591e6a2c480ULL); + assert(octeon_cop2_gfm_mul_reflect_readback( + 0xfedcba9876543210ULL) =3D=3D 0x084c2a6e195d3b7fULL); =20 return 0; } --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427403; cv=none; d=zohomail.com; s=zohoarc; b=HLvsx6gWTsxZBKel86zoxkrUwpCLo/fDaFNyTAbb9tthAgmixcrRtE4Ibq34iHAD+sAEfk2vjoybf/qncT6ew2mie5q2VS5ZYBcYXPtAAGYa+DpZNyLxl7OLfbGim3/hkANgt2/yvBrmXkriFpGZRNvzI+wMdZ7+ncs6fMGZPPY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427403; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dZ4CrzNSbg8N92isrUqhe1gtXsGlHjJdw2HEjLBDLdM=; b=ExXtgYbB4sAoKr7yaZVNWQV5u2KWcDSXcW9rNyk9/kXno9NiLoKBSqJ5QXElG/Le+I7PqQL+MxZvGNE1/cazP8KIlnZmLpwfnJO8Lee3cGt5fUa4J/5Il8PD8kDl4aPpm5zkTgu1abH9LWRfDk3ZASrAmMpFO1mTKxIbvRwYmqA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177942740365722.84680598666273; Thu, 21 May 2026 22:23:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJW-0003De-Pb; Fri, 22 May 2026 01:20:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJK-0002vn-I2 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:38 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJH-0002C9-S8 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:38 -0400 Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-47cba53479aso4800562b6e.0 for ; Thu, 21 May 2026 22:20:35 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427234; x=1780032034; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dZ4CrzNSbg8N92isrUqhe1gtXsGlHjJdw2HEjLBDLdM=; b=HrB48bBLRbXaOrKDptfz/6TAQARCefxZieIuX5ol7tg3ktWv1leAU4Jx5jpt7TFyPy ThnEecTPTRb6wYv/03ZJ1GbeJ6ntCrDpL47i7UCAvtBc0ZCMsbdMMyHHEFhQ+p2vtIFx BF9shNJTOhdd0jOJWlw80Chom1Yke2TU9wZrKZEro1QC8IKI+i9h2O/mtZOQvGKt6DD6 EHRCrcGOBQNvaGaGgPqMZafcLqhniV4LITLKZdGtDJCK6sZMz3Qdlq0HBOdM82beJm+3 IhIuJtsNmwoGD1KHVlzzNoW+vGeWVGVrSQ4n8WdH7B6UAYJTHDWvaXnGq8uSPGw/mGCH dFrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427234; x=1780032034; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dZ4CrzNSbg8N92isrUqhe1gtXsGlHjJdw2HEjLBDLdM=; b=MloXQ+oj+frf11AGbF5lEj7DJyH87VsJKVuxELKp+04b1qizTj6Zia9pDUFJe9WWzE 9XhNEi85GFSrWIq1s/umLz+30XF0Rp6ERwwwhEER8JEqoMw5g8imZCi8MRxGUUWNMlxC oDxVyJ5KQJWlGxlY6dxx29uy2A25MopsjdiLk536VROb5quqJHoyyqLnuDkbneabFJ3i Moq8o1kCsV0y29EPA3LIEsjpySslpatN00MmZym+AJHi0vCTma3WCbUdgB/MqqPm323n JpRHAejB9we5v0XC+5ZxeVfVicAQaiPMqFLV3+Tv3xSKTdU2UBf1UfQG81cJ/V9Urx8D L+bg== X-Gm-Message-State: AOJu0YxNMnZZi/Cl53W+06y4M91FrQfKw3fjpv1RW7qI1mfldmInzRC/ O2GtWlCipJ49nTOl7gqloy4d8nMqRio+6+DblThIm9xY9ODhV2DQIQ1N X-Gm-Gg: Acq92OHzgZy0hSm2AATpdEdm67IQSLWXU8w8aC/TcOSycSJSyHTHWZX5aTaov5SsYEC oGuL+wi/51PorSafXcYbMZbB7MQxn3tDRVmWQ6rJHMWFxbWPCN6aJDi8kop5eagj/ef3okbfVVp jYG+FHiNccf7coaQsfw+dzH+VNqTaWhCU3IHUeIKjYglmnH/xG12H4DjnsU8u2/70uAn4vpqExX 845nThRTKvm2vFh1BMdd4oyOWfpLZC+p9+HNrShJWDm0WwjH9aDDVG1ygVkfTiTvllGhdu0g+U5 gAaTdn2AFrmdXW90EJWOy4xX67TxkNU/XWJGAJ5/QleoBnzhNjk7a/bLQeIzXjtY1KeS0EVzH2Z TgHs2Kgndxc8mBLJyOd+u/ruA9jrmPBVCRbD4Ypi4aNM+rNy2dKN/idd0gBcUFx0LEipTweBdCa Afc90fJUr1YarN1sYMLtt020eX1DFefAd2mgCOYrScqIOBEoBOzMqQoB5C2maCdbk6Ds8+b1RIp XMg6FH9y/vP8kZAzaGjmYWC2TUf0u8XHm8fSlz9ST/qsZU9FaUHtZ1jT1DnMepZ4+RU X-Received: by 2002:a05:6808:17a5:b0:479:f58a:c5d5 with SMTP id 5614622812f47-4854a3d68e1mr1116778b6e.45.1779427234429; Thu, 21 May 2026 22:20:34 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:19:59 -0600 Subject: [PATCH v14 17/22] target/mips: decode Octeon HSH and SHA3 COP2 selectors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-17-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427404457158500 Add explicit decodetree entries and translator bindings for the Octeon HSH shared-window selectors and SHA3 operation selectors. These paths need helper calls because HSH/SHA3 selectors alias the architectural hash register window and operation selectors have visible side effects. Keep HSH/SHA3 decode separate from direct register transfers because the shared hash-window aliases require helper-mediated state updates. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v10 -> v13: - Keep this patch limited to HSH/SHA3 selector additions; CRC/GFM selector finalization stays in the CRC/GFM selector patch. - Name the 0x0057 SDK compatibility selector as STARTSHA1_COMPAT and document why it is kept despite not appearing in the public manuals. Changes v9 -> v10: - Split HSH/SHA3 selector decode out of the monolithic Octeon COP2 selector decode patch. - Reworked the shared HSH/SHA3 register-window transfers around the architectural hash state instead of DATW/IVW shadow state. --- target/mips/tcg/octeon.decode | 77 ++++++++++++++++++++++++++++++++++= ++++ target/mips/tcg/octeon_translate.c | 77 ++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 154 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 70e02d0b0e..b1a63b743f 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -113,6 +113,7 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MF_HSH_DAT4 010010 00001 rt:5 0000 0000 0100 = 0100 &cp2 CVM_MF_HSH_DAT5 010010 00001 rt:5 0000 0000 0100 = 0101 &cp2 CVM_MF_HSH_DAT6 010010 00001 rt:5 0000 0000 0100 = 0110 &cp2 + CVM_MF_SHA3_DAT24 010010 00001 rt:5 0000 0000 0101 = 0000 &cp2 CVM_MF_3DES_KEY0 010010 00001 rt:5 0000 0000 1000 = 0000 &cp2 CVM_MF_3DES_KEY1 010010 00001 rt:5 0000 0000 1000 = 0001 &cp2 CVM_MF_3DES_KEY2 010010 00001 rt:5 0000 0000 1000 = 0010 &cp2 @@ -137,6 +138,30 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MF_GFM_MUL_REFLECT1 010010 00001 rt:5 0000 0000 0101 = 1001 &cp2 CVM_MF_GFM_RESINP_REFLECT0 010010 00001 rt:5 0000 0000 0101 = 1010 &cp2 CVM_MF_GFM_RESINP_REFLECT1 010010 00001 rt:5 0000 0000 0101 = 1011 &cp2 + CVM_MF_HSH_DATW0 010010 00001 rt:5 0000 0010 0100 = 0000 &cp2 + CVM_MF_HSH_DATW1 010010 00001 rt:5 0000 0010 0100 = 0001 &cp2 + CVM_MF_HSH_DATW2 010010 00001 rt:5 0000 0010 0100 = 0010 &cp2 + CVM_MF_HSH_DATW3 010010 00001 rt:5 0000 0010 0100 = 0011 &cp2 + CVM_MF_HSH_DATW4 010010 00001 rt:5 0000 0010 0100 = 0100 &cp2 + CVM_MF_HSH_DATW5 010010 00001 rt:5 0000 0010 0100 = 0101 &cp2 + CVM_MF_HSH_DATW6 010010 00001 rt:5 0000 0010 0100 = 0110 &cp2 + CVM_MF_HSH_DATW7 010010 00001 rt:5 0000 0010 0100 = 0111 &cp2 + CVM_MF_HSH_DATW8 010010 00001 rt:5 0000 0010 0100 = 1000 &cp2 + CVM_MF_HSH_DATW9 010010 00001 rt:5 0000 0010 0100 = 1001 &cp2 + CVM_MF_HSH_DATW10 010010 00001 rt:5 0000 0010 0100 = 1010 &cp2 + CVM_MF_HSH_DATW11 010010 00001 rt:5 0000 0010 0100 = 1011 &cp2 + CVM_MF_HSH_DATW12 010010 00001 rt:5 0000 0010 0100 = 1100 &cp2 + CVM_MF_HSH_DATW13 010010 00001 rt:5 0000 0010 0100 = 1101 &cp2 + CVM_MF_HSH_DATW14 010010 00001 rt:5 0000 0010 0100 = 1110 &cp2 + CVM_MF_HSH_DATW15 010010 00001 rt:5 0000 0010 0100 = 1111 &cp2 + CVM_MF_HSH_IVW0 010010 00001 rt:5 0000 0010 0101 = 0000 &cp2 + CVM_MF_HSH_IVW1 010010 00001 rt:5 0000 0010 0101 = 0001 &cp2 + CVM_MF_HSH_IVW2 010010 00001 rt:5 0000 0010 0101 = 0010 &cp2 + CVM_MF_HSH_IVW3 010010 00001 rt:5 0000 0010 0101 = 0011 &cp2 + CVM_MF_HSH_IVW4 010010 00001 rt:5 0000 0010 0101 = 0100 &cp2 + CVM_MF_HSH_IVW5 010010 00001 rt:5 0000 0010 0101 = 0101 &cp2 + CVM_MF_HSH_IVW6 010010 00001 rt:5 0000 0010 0101 = 0110 &cp2 + CVM_MF_HSH_IVW7 010010 00001 rt:5 0000 0010 0101 = 0111 &cp2 CVM_MF_GFM_MUL0 010010 00001 rt:5 0000 0010 0101 = 1000 &cp2 CVM_MF_GFM_MUL1 010010 00001 rt:5 0000 0010 0101 = 1001 &cp2 CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 = 1010 &cp2 @@ -153,6 +178,10 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_HSH_IV1 010010 00101 rt:5 0000 0000 0100 = 1001 &cp2 CVM_MT_HSH_IV2 010010 00101 rt:5 0000 0000 0100 = 1010 &cp2 CVM_MT_HSH_IV3 010010 00101 rt:5 0000 0000 0100 = 1011 &cp2 + CVM_MT_SHA3_DAT24 010010 00101 rt:5 0000 0000 0101 = 0000 &cp2 + CVM_MT_SHA3_DAT15 010010 00101 rt:5 0000 0000 0101 = 0001 &cp2 + # Cavium SDK code uses 0x0057 as a STARTSHA1 compatibility alias. + CVM_MT_HSH_STARTSHA1_COMPAT 010010 00101 rt:5 0000 0000 0101 = 0111 &cp2 CVM_MT_GFM_MUL_REFLECT0 010010 00101 rt:5 0000 0000 0101 = 1000 &cp2 CVM_MT_GFM_MUL_REFLECT1 010010 00101 rt:5 0000 0000 0101 = 1001 &cp2 CVM_MT_GFM_XOR0_REFLECT 010010 00101 rt:5 0000 0000 0101 = 1100 &cp2 @@ -182,19 +211,67 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_CRC_BYTE_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0100 &cp2 CVM_MT_CRC_HALF_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0101 &cp2 CVM_MT_CRC_WORD_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0110 &cp2 + CVM_MT_HSH_DATW0 010010 00101 rt:5 0000 0010 0100 = 0000 &cp2 + CVM_MT_HSH_DATW1 010010 00101 rt:5 0000 0010 0100 = 0001 &cp2 + CVM_MT_HSH_DATW2 010010 00101 rt:5 0000 0010 0100 = 0010 &cp2 + CVM_MT_HSH_DATW3 010010 00101 rt:5 0000 0010 0100 = 0011 &cp2 + CVM_MT_HSH_DATW4 010010 00101 rt:5 0000 0010 0100 = 0100 &cp2 + CVM_MT_HSH_DATW5 010010 00101 rt:5 0000 0010 0100 = 0101 &cp2 + CVM_MT_HSH_DATW6 010010 00101 rt:5 0000 0010 0100 = 0110 &cp2 + CVM_MT_HSH_DATW7 010010 00101 rt:5 0000 0010 0100 = 0111 &cp2 + CVM_MT_HSH_DATW8 010010 00101 rt:5 0000 0010 0100 = 1000 &cp2 + CVM_MT_HSH_DATW9 010010 00101 rt:5 0000 0010 0100 = 1001 &cp2 + CVM_MT_HSH_DATW10 010010 00101 rt:5 0000 0010 0100 = 1010 &cp2 + CVM_MT_HSH_DATW11 010010 00101 rt:5 0000 0010 0100 = 1011 &cp2 + CVM_MT_HSH_DATW12 010010 00101 rt:5 0000 0010 0100 = 1100 &cp2 + CVM_MT_HSH_DATW13 010010 00101 rt:5 0000 0010 0100 = 1101 &cp2 + CVM_MT_HSH_DATW14 010010 00101 rt:5 0000 0010 0100 = 1110 &cp2 + CVM_MT_HSH_DATW15 010010 00101 rt:5 0000 0010 0100 = 1111 &cp2 + CVM_MT_HSH_IVW0 010010 00101 rt:5 0000 0010 0101 = 0000 &cp2 + CVM_MT_HSH_IVW1 010010 00101 rt:5 0000 0010 0101 = 0001 &cp2 + CVM_MT_HSH_IVW2 010010 00101 rt:5 0000 0010 0101 = 0010 &cp2 + CVM_MT_HSH_IVW3 010010 00101 rt:5 0000 0010 0101 = 0011 &cp2 + CVM_MT_HSH_IVW4 010010 00101 rt:5 0000 0010 0101 = 0100 &cp2 + CVM_MT_HSH_IVW5 010010 00101 rt:5 0000 0010 0101 = 0101 &cp2 + CVM_MT_HSH_IVW6 010010 00101 rt:5 0000 0010 0101 = 0110 &cp2 + CVM_MT_HSH_IVW7 010010 00101 rt:5 0000 0010 0101 = 0111 &cp2 CVM_MT_GFM_MUL0 010010 00101 rt:5 0000 0010 0101 = 1000 &cp2 CVM_MT_GFM_MUL1 010010 00101 rt:5 0000 0010 0101 = 1001 &cp2 CVM_MT_GFM_RESINP0 010010 00101 rt:5 0000 0010 0101 = 1010 &cp2 CVM_MT_GFM_RESINP1 010010 00101 rt:5 0000 0010 0101 = 1011 &cp2 + CVM_MT_GFM_XOR0 010010 00101 rt:5 0000 0010 0101 = 1100 &cp2 CVM_MT_GFM_POLY 010010 00101 rt:5 0000 0010 0101 = 1110 &cp2 + CVM_MT_SHA3_XORDAT0 010010 00101 rt:5 0000 0010 1100 = 0000 &cp2 + CVM_MT_SHA3_XORDAT1 010010 00101 rt:5 0000 0010 1100 = 0001 &cp2 + CVM_MT_SHA3_XORDAT2 010010 00101 rt:5 0000 0010 1100 = 0010 &cp2 + CVM_MT_SHA3_XORDAT3 010010 00101 rt:5 0000 0010 1100 = 0011 &cp2 + CVM_MT_SHA3_XORDAT4 010010 00101 rt:5 0000 0010 1100 = 0100 &cp2 + CVM_MT_SHA3_XORDAT5 010010 00101 rt:5 0000 0010 1100 = 0101 &cp2 + CVM_MT_SHA3_XORDAT6 010010 00101 rt:5 0000 0010 1100 = 0110 &cp2 + CVM_MT_SHA3_XORDAT7 010010 00101 rt:5 0000 0010 1100 = 0111 &cp2 + CVM_MT_SHA3_XORDAT8 010010 00101 rt:5 0000 0010 1100 = 1000 &cp2 + CVM_MT_SHA3_XORDAT9 010010 00101 rt:5 0000 0010 1100 = 1001 &cp2 + CVM_MT_SHA3_XORDAT10 010010 00101 rt:5 0000 0010 1100 = 1010 &cp2 + CVM_MT_SHA3_XORDAT11 010010 00101 rt:5 0000 0010 1100 = 1011 &cp2 + CVM_MT_SHA3_XORDAT12 010010 00101 rt:5 0000 0010 1100 = 1100 &cp2 + CVM_MT_SHA3_XORDAT13 010010 00101 rt:5 0000 0010 1100 = 1101 &cp2 + CVM_MT_SHA3_XORDAT14 010010 00101 rt:5 0000 0010 1100 = 1110 &cp2 + CVM_MT_SHA3_XORDAT15 010010 00101 rt:5 0000 0010 1100 = 1111 &cp2 + CVM_MT_SHA3_XORDAT16 010010 00101 rt:5 0000 0010 1101 = 0000 &cp2 + CVM_MT_SHA3_XORDAT17 010010 00101 rt:5 0000 0010 1101 = 0001 &cp2 CVM_MT_CRC_LEN 010010 00101 rt:5 0001 0010 0000 = 0010 &cp2 CVM_MT_CRC_DWORD 010010 00101 rt:5 0001 0010 0000 = 0111 &cp2 CVM_MT_CRC_VAR 010010 00101 rt:5 0001 0010 0000 = 1000 &cp2 CVM_MT_CRC_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 = 0111 &cp2 CVM_MT_CRC_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 = 1000 &cp2 + CVM_MT_HSH_STARTMD5 010010 00101 rt:5 0100 0000 0100 = 0111 &cp2 + CVM_MT_HSH_STARTSHA256 010010 00101 rt:5 0100 0000 0100 = 1111 &cp2 + CVM_MT_SHA3_STARTOP 010010 00101 rt:5 0100 0000 0101 = 0010 &cp2 + CVM_MT_HSH_STARTSHA 010010 00101 rt:5 0100 0000 0101 = 0111 &cp2 CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 = 1101 &cp2 CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 = 0000 &cp2 CVM_MT_CRC_POLYNOMIAL_REFLECT 010010 00101 rt:5 0100 0010 0001 = 0000 &cp2 + CVM_MT_HSH_STARTSHA512 010010 00101 rt:5 0100 0010 0100 = 1111 &cp2 CVM_MT_GFM_XORMUL1 010010 00101 rt:5 0100 0010 0101 = 1101 &cp2 ] CP2_Undef 010010 ----- ----- ---- ---- ----= ---- diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index ce4cfcb3f3..c8c797e57f 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -212,10 +212,35 @@ CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]); CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly); =20 CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect); +CP2_MF_HELPER(CVM_MF_SHA3_DAT24, sha3_dat24); CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT0, gfm_mul_reflect0); CP2_MF_HELPER(CVM_MF_GFM_MUL_REFLECT1, gfm_mul_reflect1); CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT0, gfm_resinp_reflect0); CP2_MF_HELPER(CVM_MF_GFM_RESINP_REFLECT1, gfm_resinp_reflect1); +CP2_MF_I64(CVM_MF_HSH_DATW0, hsh_dat[0]); +CP2_MF_I64(CVM_MF_HSH_DATW1, hsh_dat[1]); +CP2_MF_I64(CVM_MF_HSH_DATW2, hsh_dat[2]); +CP2_MF_I64(CVM_MF_HSH_DATW3, hsh_dat[3]); +CP2_MF_I64(CVM_MF_HSH_DATW4, hsh_dat[4]); +CP2_MF_I64(CVM_MF_HSH_DATW5, hsh_dat[5]); +CP2_MF_I64(CVM_MF_HSH_DATW6, hsh_dat[6]); +CP2_MF_I64(CVM_MF_HSH_DATW7, hsh_dat[7]); +CP2_MF_I64(CVM_MF_HSH_DATW8, hsh_dat[8]); +CP2_MF_I64(CVM_MF_HSH_DATW9, hsh_dat[9]); +CP2_MF_I64(CVM_MF_HSH_DATW10, hsh_dat[10]); +CP2_MF_I64(CVM_MF_HSH_DATW11, hsh_dat[11]); +CP2_MF_I64(CVM_MF_HSH_DATW12, hsh_dat[12]); +CP2_MF_I64(CVM_MF_HSH_DATW13, hsh_dat[13]); +CP2_MF_I64(CVM_MF_HSH_DATW14, hsh_dat[14]); +CP2_MF_I64(CVM_MF_HSH_DATW15, hsh_dat[15]); +CP2_MF_I64(CVM_MF_HSH_IVW0, hsh_iv[0]); +CP2_MF_I64(CVM_MF_HSH_IVW1, hsh_iv[1]); +CP2_MF_I64(CVM_MF_HSH_IVW2, hsh_iv[2]); +CP2_MF_I64(CVM_MF_HSH_IVW3, hsh_iv[3]); +CP2_MF_I64(CVM_MF_HSH_IVW4, hsh_iv[4]); +CP2_MF_I64(CVM_MF_HSH_IVW5, hsh_iv[5]); +CP2_MF_I64(CVM_MF_HSH_IVW6, hsh_iv[6]); +CP2_MF_I64(CVM_MF_HSH_IVW7, hsh_iv[7]); =20 CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT0, hsh_dat, 0); CP2_MT_HSH_PAIR(CVM_MT_HSH_DAT1, hsh_dat, 1); @@ -254,11 +279,13 @@ CP2_MT_I64(CVM_MT_GFM_MUL0, gfm_mul[0]); CP2_MT_I64(CVM_MT_GFM_MUL1, gfm_mul[1]); CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]); CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]); +CP2_MT_HELPER(CVM_MT_GFM_XOR0, gfm_xor0); CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly); CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf); CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly); =20 CP2_MT_HELPER(CVM_MT_CRC_POLYNOMIAL_REFLECT, crc_write_polynomial_reflect); + CP2_MT_HELPER(CVM_MT_CRC_IV_REFLECT, crc_write_iv_reflect); CP2_MT_HELPER(CVM_MT_CRC_BYTE, crc_write_byte); CP2_MT_HELPER(CVM_MT_CRC_HALF, crc_write_half); @@ -272,6 +299,56 @@ CP2_MT_HELPER(CVM_MT_CRC_DWORD_REFLECT, crc_write_dwor= d_reflect); CP2_MT_HELPER(CVM_MT_CRC_VAR_REFLECT, crc_write_var_reflect); CP2_MT_HELPER(CVM_MT_GFM_XORMUL1_REFLECT, gfm_xormul1_reflect); CP2_MT_HELPER(CVM_MT_GFM_XORMUL1, gfm_xormul1); +CP2_MT_HELPER(CVM_MT_SHA3_DAT24, sha3_dat24); +CP2_MT_HELPER(CVM_MT_SHA3_DAT15, sha3_dat15); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT0, sha3_xordat0); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT1, sha3_xordat1); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT2, sha3_xordat2); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT3, sha3_xordat3); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT4, sha3_xordat4); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT5, sha3_xordat5); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT6, sha3_xordat6); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT7, sha3_xordat7); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT8, sha3_xordat8); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT9, sha3_xordat9); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT10, sha3_xordat10); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT11, sha3_xordat11); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT12, sha3_xordat12); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT13, sha3_xordat13); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT14, sha3_xordat14); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT15, sha3_xordat15); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT16, sha3_xordat16); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT17, sha3_xordat17); +CP2_MT_HELPER(CVM_MT_SHA3_STARTOP, sha3_startop); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA1_COMPAT, hsh_startsha1_compat); +CP2_MT_I64(CVM_MT_HSH_DATW0, hsh_dat[0]); +CP2_MT_I64(CVM_MT_HSH_DATW1, hsh_dat[1]); +CP2_MT_I64(CVM_MT_HSH_DATW2, hsh_dat[2]); +CP2_MT_I64(CVM_MT_HSH_DATW3, hsh_dat[3]); +CP2_MT_I64(CVM_MT_HSH_DATW4, hsh_dat[4]); +CP2_MT_I64(CVM_MT_HSH_DATW5, hsh_dat[5]); +CP2_MT_I64(CVM_MT_HSH_DATW6, hsh_dat[6]); +CP2_MT_I64(CVM_MT_HSH_DATW7, hsh_dat[7]); +CP2_MT_I64(CVM_MT_HSH_DATW8, hsh_dat[8]); +CP2_MT_I64(CVM_MT_HSH_DATW9, hsh_dat[9]); +CP2_MT_I64(CVM_MT_HSH_DATW10, hsh_dat[10]); +CP2_MT_I64(CVM_MT_HSH_DATW11, hsh_dat[11]); +CP2_MT_I64(CVM_MT_HSH_DATW12, hsh_dat[12]); +CP2_MT_I64(CVM_MT_HSH_DATW13, hsh_dat[13]); +CP2_MT_I64(CVM_MT_HSH_DATW14, hsh_dat[14]); +CP2_MT_I64(CVM_MT_HSH_DATW15, hsh_dat[15]); +CP2_MT_I64(CVM_MT_HSH_IVW0, hsh_iv[0]); +CP2_MT_I64(CVM_MT_HSH_IVW1, hsh_iv[1]); +CP2_MT_I64(CVM_MT_HSH_IVW2, hsh_iv[2]); +CP2_MT_I64(CVM_MT_HSH_IVW3, hsh_iv[3]); +CP2_MT_I64(CVM_MT_HSH_IVW4, hsh_iv[4]); +CP2_MT_I64(CVM_MT_HSH_IVW5, hsh_iv[5]); +CP2_MT_I64(CVM_MT_HSH_IVW6, hsh_iv[6]); +CP2_MT_I64(CVM_MT_HSH_IVW7, hsh_iv[7]); +CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512); =20 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) { --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427253; cv=none; d=zohomail.com; s=zohoarc; b=YlSYHMsXgafSgeuGOx94AVYYNPSGH0u89QzGrnMbRH08trV3P1Th0wn/5qKcwwagA2P1Px6ceN4T+kONFpjdBtXOawwtZkigW9zoM/4IfJPBWgJi4grPORclQ3N1hBeO3OLj6eXm/uh7iTrywWP37l3yfXgK7bQjqZ7z+cB7OTg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427253; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IIq/YskjRURxwXRrby+JleJo4nRwydEYBipsWaNUB70=; b=XUAvVb+hfDM6B4v5N/XIg7Ld20dxuQ1r/ex/YO4T6a+jbzXRmgb8D5q2JZ/bX+0/4vP6QJG9Gc+PDq3YGd9QE3e1zIlx/4UwjWQzn2YYQ2D5xdFs6CZ0k2jrFiH1JfUAWwjCLzInahdakoWONFPeBNLbXyMloThyRP3A2eqateE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427253355872.4559773987716; Thu, 21 May 2026 22:20:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJU-000396-OO; Fri, 22 May 2026 01:20:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJK-0002x7-Qa for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:39 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJI-0002CS-RT for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:38 -0400 Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-47c7b282d73so4525598b6e.3 for ; Thu, 21 May 2026 22:20:36 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427236; x=1780032036; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IIq/YskjRURxwXRrby+JleJo4nRwydEYBipsWaNUB70=; b=U+Jy1eMHXZciqrhTCJIMpQOnfXaqnDtuu3ajWoZaFf9G1lvTg+8dOUkFHj1LPbyPSH Bmi58OxCbqVTYeeub9lw79MY9JqnvNYbZH0UcTVNrlG6JdW7r555vSu91RMMDBriYFSr h1j7gc5ySk5reLaxnHxRB95aR8LC19RFqFoQ71HhcUTBmXuBh0l2yRVp5HVu8rc+vp1E S1ipmAqkgKmTqgbjG72V5YilGCCynoyhrqHaoW5PbcO1/lyFSK6+pW/UUfNvGiFsM4ko hm4Hl1zeXrwXq9HFbJtCyAi+9+QBwJoIz5+Hislk/ayhip5cGFImfTwxHcUn/BnmUgx2 zCLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427236; x=1780032036; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=IIq/YskjRURxwXRrby+JleJo4nRwydEYBipsWaNUB70=; b=H08mHUqghfXmRmLIQmGSBp/jcRzXrDPFhr15BGTjsQa8kx5ldDoITjvVOfURIjWNhn vo0SevsJz3AjUv6MLw1oRI3c5gywr7gPi2rg4MTrWQixJaAFjgxgnRZT9PSJxLRdBDOR QrsKYUmK8r7YwL09gfjTp9IutFn2/VCKwZxSqMSy9oQ6Am1As66N6O7W1OKUxrPxgiNP hMq+zEhtp+RjUJ694oXDGUEmGoQ1JD7TgIymjVBAnRW/V7nanq9Ksut2GkhN2rKZ6v/Q e2k/suZvs9XRonCqhMpmdiqe+9S08qsL+FhAYMhzFeN8gPPvDuxnejZmSQkMFim30RPM g22g== X-Gm-Message-State: AOJu0YzH6jAhDLg1R23UOHOyRiehaQi+9MlzYrPfOzF8Vj/5WCVi98aM 8wRM7RndbS1h0RqYQNFMehAzMFnkNZohcIEc3s0zweTzDz+5GiIi/2rR X-Gm-Gg: Acq92OGZ0HP9gelkPALq5F3zJdPGdntLmRTJl3OxzLGbzL+zeSHfZg9dJuRzD1DnuYW M3kXuvTwzIEASSK03aMM1bSzj0RiuRBBQWwh1T0MGvK71Ho04Rd3U9GiaZ0UidRfJ+Z2gtYpgVj Y6kWF9vKavUCjeRL049rDY9p4jX00ETdGmkug3Sr5bXHK8e1el3AE9wcSgOZT+z0MnwVE0SqmZU vKfvjSvJSZFKBLRuBNH98FnyCKumWc7xO6mFb9dpjdWgqjn0z7TueepKo3CVD6fgeG7BqyNJ8cb g1NC9JG9rhD0ZsF0bCpcclmO8DjSdhLcPxy4wcq/qUvalua1WigIEpih3wqqRKzM5ywbT6j16mL OFLhyvV3qG/nrxQp6Vr+WnhJ1E7fONkC1tzZMXfwPLxKgxNUTVUNJRuipT/LPi58jyVQ1U5qs9h rI1Q8bpMC6WJdxnVXS8Rx6ZzaJH6pxsYFFySvOMmzlVPZQGl1mJAMlCjIcRbIgR7t1NMp1WZ7kY pkV/y1wjcNkC5cRCTaByHBlQ5g24bhaJ3rAeBnJA+XYaTljyW+hLBZcrEjLVSpzM3Po X-Received: by 2002:a05:6808:23c9:b0:47c:7c7c:c792 with SMTP id 5614622812f47-48549ecf769mr1444949b6e.7.1779427235763; Thu, 21 May 2026 22:20:35 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:20:00 -0600 Subject: [PATCH v14 18/22] target/mips: decode Octeon ZUC and SNOW3G COP2 selectors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-18-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427254350158500 Add explicit decodetree entries and translator bindings for the Octeon ZUC and SNOW3G COP2 operation selectors. These stream-cipher selectors operate on the shared HSH register window state, so dispatch them through the per-operation helpers added with the corresponding engine support. Keep stream-cipher decode separate because these selectors share the HSH register window with unrelated engines. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v9 -> v10: - Split ZUC/SNOW3G selector decode out of the monolithic Octeon COP2 selector decode patch. - Kept stream-cipher operation selectors helper-backed because they operate on the shared HSH register-window state. --- target/mips/tcg/octeon.decode | 4 ++++ target/mips/tcg/octeon_translate.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index b1a63b743f..2b27fa205f 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -265,8 +265,12 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_CRC_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 = 0111 &cp2 CVM_MT_CRC_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 = 1000 &cp2 CVM_MT_HSH_STARTMD5 010010 00101 rt:5 0100 0000 0100 = 0111 &cp2 + CVM_MT_SNOW3G_START 010010 00101 rt:5 0100 0000 0100 = 1101 &cp2 + CVM_MT_SNOW3G_MORE 010010 00101 rt:5 0100 0000 0100 = 1110 &cp2 CVM_MT_HSH_STARTSHA256 010010 00101 rt:5 0100 0000 0100 = 1111 &cp2 CVM_MT_SHA3_STARTOP 010010 00101 rt:5 0100 0000 0101 = 0010 &cp2 + CVM_MT_ZUC_START 010010 00101 rt:5 0100 0000 0101 = 0101 &cp2 + CVM_MT_ZUC_MORE 010010 00101 rt:5 0100 0000 0101 = 0110 &cp2 CVM_MT_HSH_STARTSHA 010010 00101 rt:5 0100 0000 0101 = 0111 &cp2 CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 = 1101 &cp2 CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 = 0000 &cp2 diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index c8c797e57f..cda9a0e0f5 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -320,6 +320,10 @@ CP2_MT_HELPER(CVM_MT_SHA3_XORDAT15, sha3_xordat15); CP2_MT_HELPER(CVM_MT_SHA3_XORDAT16, sha3_xordat16); CP2_MT_HELPER(CVM_MT_SHA3_XORDAT17, sha3_xordat17); CP2_MT_HELPER(CVM_MT_SHA3_STARTOP, sha3_startop); +CP2_MT_HELPER(CVM_MT_ZUC_START, zuc_start); +CP2_MT_HELPER(CVM_MT_ZUC_MORE, zuc_more); +CP2_MT_HELPER(CVM_MT_SNOW3G_START, snow3g_start); +CP2_MT_HELPER(CVM_MT_SNOW3G_MORE, snow3g_more); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA1_COMPAT, hsh_startsha1_compat); CP2_MT_I64(CVM_MT_HSH_DATW0, hsh_dat[0]); CP2_MT_I64(CVM_MT_HSH_DATW1, hsh_dat[1]); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427369; cv=none; d=zohomail.com; s=zohoarc; b=eBwZYXBtcHm6BfAQgdBHjmbdljeet2668zkOoI9R6vasb3GfQZLCyRSIFt3Ydu9nQdlfRCcs6N9tZ3xhiDvSeU6WPm53SBMB9Rk9srtmDPTIeiJeISr66FFNuJqPa1j1TXygorkHkRSqMQ8A/XH5gkmfgAYH+Jb4TCfgsGQrWas= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427369; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=n1K42f0gAukwwv6uNqW6nLYjU/l4j8XYoW2zZasuf0c=; b=B+0pPEP1ktqumx5s6TCrolvxx4ec2oTd4xkzqNEJJO6nU2GcWsIuh2viAI3Oa2viPxEW6ySbNGTuYBO5HtZIkCANk3rqXXyWLt6U/ahcJsCf1l4jtOMfu9PI2EnlDwCJrroSP5froE7F/1MSsvHj53FonftUYnHNaA7KK52Cu18= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427369146369.967650887025; Thu, 21 May 2026 22:22:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJY-0003Ld-0N; Fri, 22 May 2026 01:20:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJM-0002yx-C1 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:40 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJK-0002Cj-B4 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:39 -0400 Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-484df1dce93so4314243b6e.2 for ; Thu, 21 May 2026 22:20:37 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427237; x=1780032037; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=n1K42f0gAukwwv6uNqW6nLYjU/l4j8XYoW2zZasuf0c=; b=eBovXL7hvd+ACXtSuVe6nvDle4CdfPk6gh+H+bC4/m3Nwg/TBWlCvjWBUQQc3c0s5G FFVAPFWsshqBQBCt0SrQDfXwaOgrEwK6JxFkt9EK+kf4hgKBEZuK99NwPe9Ynju9G+Wt AncXyukAZ5p+nyNhAFEnPpG6Fy8raZM5wJN8owtP4Xj9G2TTfpdaDWueuZCFc6J+yWFE Nu23K+GSP2UpsBGFJQqQpp9A6CnRM4GkpqdmegEolDyLVGEThNFgGgDAvfJGxEI+yzjt PmgkdOlQVv1+LJm5Re2S675L9OaxjWAcKydr32NSMtCZNewP5Bu4zLEVd9KVq6tRmGVv EUIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427237; x=1780032037; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=n1K42f0gAukwwv6uNqW6nLYjU/l4j8XYoW2zZasuf0c=; b=VElQHb88Izwh2sKJZsS2iQ4lx8kJ/RfG+9G/x+w3F/bg4BtjGl7ZarnrDWRF7Fd1ES TDbR6tJxYRvsFpFTZ1wiL+phcRQdBWP6aCirsAObfwahJBc09GV1IU4ukRDnpNEp41bO VB7fnoiByMUAIDfjY4h5VLZLb/nNb/eVeL3nwl4/u2YWyj9am5DqH856bv7LU0m0TZHa lqxfKBimX5C7zhjQikdm1nSQC37MpoWh2m7J8uK9vlxug9Ti49PZbFsNefqKWWmJZXav IMhaE3aXd/TVragVTn95M1iSFWUupy4Y1ZB3ni0pXlEjiLVy5qMxas619YsPMQNSmYee VKuw== X-Gm-Message-State: AOJu0YyRoIfHMCNvL27Dze039t3bGYRt6EHvP4emLEr1hXbNv0hJ9oTv 8tV7FLTJ0TJD6RMqYrpupa4APCkrH9qV//M2Y6CmmkeP3ouVKeRvjmNh X-Gm-Gg: Acq92OEnV3Adepsbp9yBx343xn45AugZ2z6mOVSpGRbW9kDSoP1BZq5iqU3+PT7YQZH u0p6FlIl6JJj32kxDAW3y2dslt6i14Ww8IxK/Yn/bGEGLsWAQOlK5dOX+v0KaBLnbVVfd/QsGR4 0LXK3XemcgXag3WqUSCYKLW8OWqVbf19yWMc8cL4RwMCKMw8Dn9g3NjKEJ6IV3j09RB9p9W+oY8 lbxdX7yOHl2KghHFcwPXwxncZfRpmzea2ptZ7pSYYOAvDKMtlfGcdS/OS/bmGF0f1dMeUNb+ed7 OPvrIBXJCxOK87ERTuAP2mamJdtM09g1w7E4mcK5BGzJFdRrAwkt62m7uwHl6xHjYpV3kjEgV5c +8Yv0CjCRsPWDJSvJ0SBTUfnQP0/aJYnViLc8FqzwcPOV+WgWCGXukHJFMI2VkpWGWaOpi5M3nA toB0T7iAhV4FVBEBE+ud/dLMcfPkJjWizc69N0AldmRMgK+w7sVO3JOfdE/JKiSB2seXnmJf/Gq vyoLOGwuLchXr7Kqp4V2uggq+kVgF4uAZ7dDrUUO8llZ8/5400A0Q2enzhIKUyUZo9cFR1YOZ5n 9ME= X-Received: by 2002:a05:6808:238c:b0:479:2ef3:50a5 with SMTP id 5614622812f47-48549ed043bmr1134851b6e.7.1779427236948; Thu, 21 May 2026 22:20:36 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:20:01 -0600 Subject: [PATCH v14 19/22] target/mips: decode Octeon block-cipher COP2 selectors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-19-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427371712154100 Add explicit decodetree entries and translator bindings for the Octeon AES, SMS4, 3DES, KASUMI, and Camellia COP2 operation selectors. These selectors consume or update engine state, so keep them as per-operation helper calls while the simple block-cipher register moves remain direct TCG loads and stores from the earlier register-selector patch. This completes the block-cipher selector coverage without reintroducing a generic runtime selector dispatch path. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v9 -> v10: - Split AES, SMS4, 3DES, KASUMI, and Camellia selector decode out of the monolithic Octeon COP2 selector decode patch. - Kept block-cipher operation selectors helper-backed while simple register moves remain direct TCG transfers. --- target/mips/tcg/octeon.decode | 17 +++++++++++++++++ target/mips/tcg/octeon_translate.c | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 2b27fa205f..4ac38d264c 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -203,6 +203,8 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_AES_DEC_CBC0 010010 00101 rt:5 0000 0001 0000 = 1100 &cp2 CVM_MT_AES_DEC0 010010 00101 rt:5 0000 0001 0000 = 1110 &cp2 CVM_MT_AES_KEYLENGTH 010010 00101 rt:5 0000 0001 0001 = 0000 &cp2 + CVM_MT_CAMELLIA_FL 010010 00101 rt:5 0000 0001 0001 = 0101 &cp2 + CVM_MT_CAMELLIA_FLINV 010010 00101 rt:5 0000 0001 0001 = 0110 &cp2 CVM_MT_CRC_IV 010010 00101 rt:5 0000 0010 0000 = 0001 &cp2 CVM_MT_CRC_IV_REFLECT 010010 00101 rt:5 0000 0010 0001 = 0001 &cp2 CVM_MT_CRC_BYTE 010010 00101 rt:5 0000 0010 0000 = 0100 &cp2 @@ -264,6 +266,15 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_CRC_VAR 010010 00101 rt:5 0001 0010 0000 = 1000 &cp2 CVM_MT_CRC_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 = 0111 &cp2 CVM_MT_CRC_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 = 1000 &cp2 + CVM_MT_AES_ENC_CBC1 010010 00101 rt:5 0011 0001 0000 = 1001 &cp2 + CVM_MT_AES_ENC1 010010 00101 rt:5 0011 0001 0000 = 1011 &cp2 + CVM_MT_AES_DEC_CBC1 010010 00101 rt:5 0011 0001 0000 = 1101 &cp2 + CVM_MT_AES_DEC1 010010 00101 rt:5 0011 0001 0000 = 1111 &cp2 + CVM_MT_CAMELLIA_ROUND 010010 00101 rt:5 0011 0001 0001 = 0100 &cp2 + CVM_MT_SMS4_ENC_CBC1 010010 00101 rt:5 0011 0001 0001 = 1001 &cp2 + CVM_MT_SMS4_ENC1 010010 00101 rt:5 0011 0001 0001 = 1011 &cp2 + CVM_MT_SMS4_DEC_CBC1 010010 00101 rt:5 0011 0001 0001 = 1101 &cp2 + CVM_MT_SMS4_DEC1 010010 00101 rt:5 0011 0001 0001 = 1111 &cp2 CVM_MT_HSH_STARTMD5 010010 00101 rt:5 0100 0000 0100 = 0111 &cp2 CVM_MT_SNOW3G_START 010010 00101 rt:5 0100 0000 0100 = 1101 &cp2 CVM_MT_SNOW3G_MORE 010010 00101 rt:5 0100 0000 0100 = 1110 &cp2 @@ -273,6 +284,12 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_ZUC_MORE 010010 00101 rt:5 0100 0000 0101 = 0110 &cp2 CVM_MT_HSH_STARTSHA 010010 00101 rt:5 0100 0000 0101 = 0111 &cp2 CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 = 1101 &cp2 + CVM_MT_3DES_ENC_CBC 010010 00101 rt:5 0100 0000 1000 = 1000 &cp2 + CVM_MT_KAS_ENC_CBC 010010 00101 rt:5 0100 0000 1000 = 1001 &cp2 + CVM_MT_3DES_ENC 010010 00101 rt:5 0100 0000 1000 = 1010 &cp2 + CVM_MT_KAS_ENC 010010 00101 rt:5 0100 0000 1000 = 1011 &cp2 + CVM_MT_3DES_DEC_CBC 010010 00101 rt:5 0100 0000 1000 = 1100 &cp2 + CVM_MT_3DES_DEC 010010 00101 rt:5 0100 0000 1000 = 1110 &cp2 CVM_MT_CRC_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 = 0000 &cp2 CVM_MT_CRC_POLYNOMIAL_REFLECT 010010 00101 rt:5 0100 0010 0001 = 0000 &cp2 CVM_MT_HSH_STARTSHA512 010010 00101 rt:5 0100 0010 0100 = 1111 &cp2 diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index cda9a0e0f5..ad71c0a8aa 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -324,6 +324,23 @@ CP2_MT_HELPER(CVM_MT_ZUC_START, zuc_start); CP2_MT_HELPER(CVM_MT_ZUC_MORE, zuc_more); CP2_MT_HELPER(CVM_MT_SNOW3G_START, snow3g_start); CP2_MT_HELPER(CVM_MT_SNOW3G_MORE, snow3g_more); +CP2_MT_HELPER(CVM_MT_AES_ENC_CBC1, aes_enc_cbc1); +CP2_MT_HELPER(CVM_MT_AES_ENC1, aes_enc1); +CP2_MT_HELPER(CVM_MT_AES_DEC_CBC1, aes_dec_cbc1); +CP2_MT_HELPER(CVM_MT_AES_DEC1, aes_dec1); +CP2_MT_HELPER(CVM_MT_SMS4_ENC_CBC1, sms4_enc_cbc1); +CP2_MT_HELPER(CVM_MT_SMS4_ENC1, sms4_enc1); +CP2_MT_HELPER(CVM_MT_SMS4_DEC_CBC1, sms4_dec_cbc1); +CP2_MT_HELPER(CVM_MT_SMS4_DEC1, sms4_dec1); +CP2_MT_HELPER(CVM_MT_3DES_ENC_CBC, des3_enc_cbc); +CP2_MT_HELPER(CVM_MT_KAS_ENC_CBC, kas_enc_cbc); +CP2_MT_HELPER(CVM_MT_3DES_ENC, des3_enc); +CP2_MT_HELPER(CVM_MT_KAS_ENC, kas_enc); +CP2_MT_HELPER(CVM_MT_3DES_DEC_CBC, des3_dec_cbc); +CP2_MT_HELPER(CVM_MT_3DES_DEC, des3_dec); +CP2_MT_HELPER(CVM_MT_CAMELLIA_FL, camellia_fl); +CP2_MT_HELPER(CVM_MT_CAMELLIA_FLINV, camellia_flinv); +CP2_MT_HELPER(CVM_MT_CAMELLIA_ROUND, camellia_round); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA1_COMPAT, hsh_startsha1_compat); CP2_MT_I64(CVM_MT_HSH_DATW0, hsh_dat[0]); CP2_MT_I64(CVM_MT_HSH_DATW1, hsh_dat[1]); --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427325; cv=none; d=zohomail.com; s=zohoarc; b=ZLTWLDPQtHLEtWM2E9VeT6KKErm7Q8LYv4e3hRUf1YlKK4NNhUtuRfmAQXOx6nBM0IACL4QfkYmoWc7FvjFG42o61zEF86HHfSX0Ngo4UiuE35LlUNoFe/IZr/T3tSkHKjR9Sc/vIew7u6cyRMqGsr8wyAJgH9em59D3QMrryX4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427325; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZO1MBdUXHdYjIwpDW060x9EGMTOHxaiqAsOMNIUXc2o=; b=d1TN939ZyNnYpJwuqxVcfSNtHouts1ijmetKakRtJyAH02ad/ZUIxcBodzxm6RD7ApTSJw2nMQJZC+PriNwb42DrysAMkeaiHmQY4qFugP+CyqHcOOIhEGDOSmG9lbVe0zqCx+pOn1C+nXsGvF2yYKOuWmWUNYXWPNL9AGRMS7w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427325687596.2650359694418; Thu, 21 May 2026 22:22:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJY-0003RM-Sc; Fri, 22 May 2026 01:20:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJN-0002zZ-P7 for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:44 -0400 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJL-0002D7-NE for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:41 -0400 Received: by mail-oi1-x232.google.com with SMTP id 5614622812f47-47c6f914617so3331399b6e.1 for ; Thu, 21 May 2026 22:20:39 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427238; x=1780032038; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZO1MBdUXHdYjIwpDW060x9EGMTOHxaiqAsOMNIUXc2o=; b=q2TbU6ZBqEcVfzmigeievwGQaejXFjoCHvGbbuPKS3CMygcMgCS6IiCcPL9woC4+om JNXGFpdzgXLu4/E0/2YQLzrM77fhPgKrWw/q/00b7y597urO5xQC27FK1KcuMHtNddjG 44VC1Or9u/OEMlM8EZm/FJDCykDXy/h0LupVishnPXDMQreRENNlLq36FNrpBVBSKL48 OAeJDwCyGMotMUMbkDgvchxJ3hwPu7QGkOD3DsPRhwG6jGVzLnt1/91u7nCmSNbi0oMQ LB0PgbeRaFsOOHqYy5EGF044CpTLdh2BhLQuQ7fYDLBCxSmds+1A52GXffce/J8jt/JS nKAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427238; x=1780032038; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ZO1MBdUXHdYjIwpDW060x9EGMTOHxaiqAsOMNIUXc2o=; b=JTjyZahE06IxaWEikBn/e6hFkzGAMwiwrLegL2T1uX0D956emDzZgAJR6aE2xSeb/n CLlO1wG+40IiBNsQ+lOLBzbk9qiKMNdW06s1WgEZC50Sjtoq2X4tbfGK1oAAux0VQvsY 1WMzaQb/19gcZMTI3pBBGWDbBlKgVbvGxmsQKcVsJ8Gs1tM8/kQ9IrrcsHlganPqxiZu 7vxDPEX3BEGJU/O55i56uSzuuOYf2K0BX6HZ983EXJEkAtIqFBpbkTL0unQTQ5SmUzgU xdKPOTHuJCpol9CAMqr6TIIzrweud/H0B9qf5sL+ktFdvd9WU1muhpNi5xt9J9FdNWvH NmYQ== X-Gm-Message-State: AOJu0Yw88f95Dneq9tFZzBJ92TA4DtkWr6lcLaZxgZVSOQ2S6UxzSOt9 6dOTzvah0dUJ1hYyYeR3xovBj1bBpmS/ilZL6MyyPo2jXg8zFIPQvluu X-Gm-Gg: Acq92OE3Q1GH1Huw2ssYE654mptYk85vHCUA8TK+xIKwVp/3l2BM4gwiDmWcTFczc/n sl5ee0S+jHieFuczRqaSs9ryJ1P4ckn3qFTh6iJBH3/5OtvUCyDY0UvmiJB2c1qrF8YM3cp7gp3 J9foHDLvOdzXfFYDlYskYS30wJKAH1w6Y8fL7M1stoBeghwpAyf5lfF83rVh71XvjTBX6vkYC2F qMG06BPZOYD7q3+ewvlsJixq1PbvUAKsMLYCIcNEhVl/EPxKWlxD9Mjs+bYvdGS3i22AK7ware3 tGahLm5Gzin7Z/Rv6u2Ly/oWWM8eD528y5/afZ0BiLK9juE+ue10X0H5eG4zsdK2425j1h0WPBs wcIGhbfYeKh1TIXfpgx9A61eFMxKCdRLNoH8pe9uvaIGsU8Cf8pGBjZrC5omLE6ac+6w4xbr0TP aETpNYV3prZ4U/rkltsR8QIpJdd1qOUq+qroTaM7eCGb7bqJdmI2mSlAS1tfJUH+oCCmxLw19ji hhc3D5eKVXs/HnY3IqQIdFjdJ3NuRovx4p07QfhHXqGz0gCy01tP9QSM06et+cRXjIw X-Received: by 2002:a05:6808:191a:b0:485:467f:a321 with SMTP id 5614622812f47-48549d46712mr1142544b6e.12.1779427238334; Thu, 21 May 2026 22:20:38 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:20:02 -0600 Subject: [PATCH v14 20/22] target/mips: decode Octeon CHORD and LLM COP2 selectors MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-20-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427326239158500 Add explicit decodetree entries and translator bindings for the Octeon CHORD and sparse LLM COP2 selectors. CHORD and LLM use their own COP2 selector window rather than the crypto engine windows covered by the preceding decode patches. This completes the explicit COP2 selector coverage by adding the remaining CHORD and LLM register and operation selectors. Signed-off-by: James Hilliard Acked-by: Richard Henderson --- Changes v13 -> v14: - Leave the CP2_Undef fallback in the register-selector patch and keep this patch limited to CHORD/LLM selector additions. Changes v9 -> v10: - Split CHORD/LLM selector decode out of the monolithic Octeon COP2 selector decode patch. - Kept sparse LLM operations helper-backed. --- target/mips/tcg/octeon.decode | 13 +++++++++++++ target/mips/tcg/octeon_translate.c | 13 +++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 4ac38d264c..a8c944e668 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -167,6 +167,9 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 = 1010 &cp2 CVM_MF_GFM_RESINP1 010010 00001 rt:5 0000 0010 0101 = 1011 &cp2 CVM_MF_GFM_POLY 010010 00001 rt:5 0000 0010 0101 = 1110 &cp2 + CVM_MF_CHORD 010010 00001 rt:5 0000 0100 0000 = 0000 &cp2 + CVM_MF_LLM_DATA0 010010 00001 rt:5 0000 0100 0000 = 0010 &cp2 + CVM_MF_LLM_DATA1 010010 00001 rt:5 0000 0100 0000 = 1010 &cp2 CVM_MT_HSH_DAT0 010010 00101 rt:5 0000 0000 0100 = 0000 &cp2 CVM_MT_HSH_DAT1 010010 00101 rt:5 0000 0000 0100 = 0001 &cp2 CVM_MT_HSH_DAT2 010010 00101 rt:5 0000 0000 0100 = 0010 &cp2 @@ -261,6 +264,16 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_SHA3_XORDAT15 010010 00101 rt:5 0000 0010 1100 = 1111 &cp2 CVM_MT_SHA3_XORDAT16 010010 00101 rt:5 0000 0010 1101 = 0000 &cp2 CVM_MT_SHA3_XORDAT17 010010 00101 rt:5 0000 0010 1101 = 0001 &cp2 + CVM_MT_LLM_READ_ADDR0 010010 00101 rt:5 0000 0100 0000 = 0000 &cp2 + CVM_MT_LLM_WRITE_ADDR0 010010 00101 rt:5 0000 0100 0000 = 0001 &cp2 + CVM_MT_LLM_DATA0 010010 00101 rt:5 0000 0100 0000 = 0010 &cp2 + CVM_MT_LLM_READ64_ADDR0 010010 00101 rt:5 0000 0100 0000 = 0100 &cp2 + CVM_MT_LLM_WRITE64_ADDR0 010010 00101 rt:5 0000 0100 0000 = 0101 &cp2 + CVM_MT_LLM_READ_ADDR1 010010 00101 rt:5 0000 0100 0000 = 1000 &cp2 + CVM_MT_LLM_WRITE_ADDR1 010010 00101 rt:5 0000 0100 0000 = 1001 &cp2 + CVM_MT_LLM_DATA1 010010 00101 rt:5 0000 0100 0000 = 1010 &cp2 + CVM_MT_LLM_READ64_ADDR1 010010 00101 rt:5 0000 0100 0000 = 1100 &cp2 + CVM_MT_LLM_WRITE64_ADDR1 010010 00101 rt:5 0000 0100 0000 = 1101 &cp2 CVM_MT_CRC_LEN 010010 00101 rt:5 0001 0010 0000 = 0010 &cp2 CVM_MT_CRC_DWORD 010010 00101 rt:5 0001 0010 0000 = 0111 &cp2 CVM_MT_CRC_VAR 010010 00101 rt:5 0001 0010 0000 = 1000 &cp2 diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index ad71c0a8aa..15a71bc7c3 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -210,6 +210,9 @@ CP2_MF_I64(CVM_MF_GFM_MUL1, gfm_mul[1]); CP2_MF_I64(CVM_MF_GFM_RESINP0, gfm_resinp[0]); CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]); CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly); +CP2_MF_I64(CVM_MF_CHORD, chord); +CP2_MF_I64(CVM_MF_LLM_DATA0, llm_data[0]); +CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]); =20 CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect); CP2_MF_HELPER(CVM_MF_SHA3_DAT24, sha3_dat24); @@ -281,6 +284,8 @@ CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]); CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]); CP2_MT_HELPER(CVM_MT_GFM_XOR0, gfm_xor0); CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly); +CP2_MT_I64(CVM_MT_LLM_DATA0, llm_data[0]); +CP2_MT_I64(CVM_MT_LLM_DATA1, llm_data[1]); CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf); CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly); =20 @@ -370,6 +375,14 @@ CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha); CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512); +CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR0, llm_read_addr0); +CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR0, llm_write_addr0); +CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR0, llm_read64_addr0); +CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR0, llm_write64_addr0); +CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR1, llm_read_addr1); +CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR1, llm_write_addr1); +CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR1, llm_read64_addr1); +CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR1, llm_write64_addr1); =20 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) { --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427354; cv=none; d=zohomail.com; s=zohoarc; b=D78BRcpsdIm/22EjuGRHvhQMZbmvOiI5b50RPDkgeHd2kJg10RU1QdN1NHqiU7z1WdugMNCrmXfEYLs/Mk3vPMRA2qvtg7kQzoPW1CLu18fv2gWQc1NdEqbA40Q5oWvYZlyM5U11H298CiEzF91idx+Jmwm7SadhSvpwdh10NjE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427354; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ligDnecCtveNInNVdf6mxSKRJEEchFOLQXnvzn95ews=; b=O1/0u1PhsGvP7NYoUzmodR90QoMH4BLj8Cyfa+AwSDYZP/xkpqX7zD1pCUXBr2wPeV98ip2A3hlCHv0N6TAExXIqOtkslYPd+XJDxhRly+PtN1eQl2e6jxTPuwjt0wZos9+q0jP2Dex4FlQrOij1DE2M/+RbdsstgMhDlu9gVLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427354613417.1161804079351; Thu, 21 May 2026 22:22:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJX-0003LQ-Un; Fri, 22 May 2026 01:20:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJO-0002za-Ro for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:44 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJM-0002E8-WD for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:42 -0400 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-4855562f32eso5142b6e.2 for ; Thu, 21 May 2026 22:20:40 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427240; x=1780032040; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ligDnecCtveNInNVdf6mxSKRJEEchFOLQXnvzn95ews=; b=GJF0gh+zXKIOMKTY1OmR9H41m9mRZYXe9qLFK4pITsSQXd3boiW4HhSeo5ZJRKVnJk zQPylPp75pFkGL3YXNV++0NKWzI7lnqAw4xqAPCNzJJxwtOBIiSV0QAa68JoNZqSchvt dFKN53nSXrmKAGNOwcdFAKP7RyXZOQGIOUhZ4LzRP65ZonYQBX1mi2FmBOiyxAoIS16g wWi8e/nDkU8R3uNcR+eubHXnqVdeA1R3Bd8uCM7PpnDS7pM1i6td2AtfzSP9I+z3e95Z 9Fha9QG4v17cgBOa4qgXGwBz/Rx3DbQfsM49rpP23GrpRyiJppRJUDbWr5lbcMSJWQuG tA0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427240; x=1780032040; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ligDnecCtveNInNVdf6mxSKRJEEchFOLQXnvzn95ews=; b=iICAmg8CX6MVYcQoHBOR8KajwJDk2C/NDp9Kulb0ccg3ljELdNNz9qy04+8y642Xny FdwF7GdF3ydFBeIu4jingiglbjsnRIESNdZQdPxvWef9zubWeZGyLAVzezQ/ZAnrRcCB 5JpWXwy3encdIetQII6Dg/NInj62p7ujAKtDa50IkFcLZgrHFMrOk2ERLnPeDDiKXEPF oHuJKYP923CFafvJ+AJvddXEraXT6xB2SRVWtzt2jo4BwplLt2aQEiqr85BQL20ldGaP qyITzFvkZnhHWueKpbD3ZxU7CvvUe4k4HsreKS054ueJjXdHJFSwdzDn2vwrXZOhbfRs NbTQ== X-Gm-Message-State: AOJu0YxHRYIIywmgWpRd/jPJq5WN/Lz0KEeYPD1+Llx3WY1MjnNB1dan QsTWndDSWvYg76TzITuOtIEWJVcaOOo+NzN1OJ5RxWxzCaqm2yAIuk67 X-Gm-Gg: Acq92OGizwnsK7U9fbwYMPjD1dVT/U3CD6Z/ZDdveGCbUFScH8XLe/+hFLVKRWF+uOT cALe/piaO8InvSKSzwgdPVgj+MpLx8dRY4cZnf8cNzNjp91SVqs1mpWTcZhr9GWbdw/hNfaoJf5 8MtBEiX8xb9wsvF1W6Aif4d8GobOOFcoKgINzF4y3pdpr/61pnUalbPymOwu56tLQRBo2CCMvqn J9Ln/P813fRZ0BdTyTWLs9daXuzppxYl0PNcZeb7NMFv2vPpz4gC8nemkU7KnK0lRtTFISqHgr1 9pBDhYNRoRtvQrqrY8xSEILHZJLsmBl8p/TDyzRTJxcPSPfruWIOx13rfp3gMv667r5L48UqQPm NvLuQnfBNSTGcTvBdVpZaXouGqOTPFt+UFvb6vcYIRkMZGQhvkXKEZBCYEEBvduE6d7L5A37IlN j+TJmDWSPDY5zkGYmQQxXfnTp76Gv5tWrzktrTDTPPkcvR+xD0h61oYKNkQ543uXiX+l+UN3+cu VOOlSwEa2qcAEhMnJlgRC9zEW92pbo+j0pIhoVLMOugbZNU9nrrCUiACcbTcBDCgLtb9gV///on gJQ= X-Received: by 2002:a05:6808:1804:b0:485:3a2c:e78f with SMTP id 5614622812f47-4854a3fecc3mr1061756b6e.40.1779427239850; Thu, 21 May 2026 22:20:39 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:20:03 -0600 Subject: [PATCH v14 21/22] target/mips: add Octeon CvmCount RDHWR support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-21-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427356258158500 Octeon exposes CvmCount through RDHWR register 31. Add the Octeon-only decode path, enable the corresponding HWREna bit for linux-user, and use an unsigned mask when checking HWREna so bit 31 is handled safely. For user-mode emulation, return host ticks as a monotonic counter source suitable for existing Octeon userspace code. In system mode, fall back to the existing CP0 Count value. Reviewed-by: Richard Henderson Signed-off-by: James Hilliard --- Changes v5 -> v6: - New patch. --- target/mips/cpu.c | 1 + target/mips/helper.h | 1 + target/mips/tcg/op_helper.c | 13 ++++++++++++- target/mips/tcg/translate.c | 11 +++++++++++ tests/tcg/mips/user/isa/octeon/octeon-insns.c | 17 +++++++++++++++++ 5 files changed, 42 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b223b767c9..d72044aef6 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -320,6 +320,7 @@ static void mips_cpu_reset_hold(Object *obj, ResetType = type) env->CP0_HWREna |=3D 0x0000000F; if (env->insn_flags & INSN_OCTEON) { env->CP0_HWREna |=3D 0x40000000u; + env->CP0_HWREna |=3D 0x80000000u; } if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->CP0_Status |=3D (1 << CP0St_CU1); diff --git a/target/mips/helper.h b/target/mips/helper.h index 2902dde889..a755cc5ad5 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -277,6 +277,7 @@ DEF_HELPER_1(rdhwr_ccres, tl, env) DEF_HELPER_1(rdhwr_performance, tl, env) DEF_HELPER_1(rdhwr_xnp, tl, env) DEF_HELPER_1(rdhwr_chord, tl, env) +DEF_HELPER_1(rdhwr_cvmcount, tl, env) DEF_HELPER_2(pmon, void, env, int) DEF_HELPER_1(wait, void, env) =20 diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 3e586e3049..df1b5c3734 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -25,6 +25,7 @@ #include "exec/memop.h" #include "fpu_helper.h" #include "qemu/crc32c.h" +#include "qemu/timer.h" #include =20 static inline target_ulong bitswap(target_ulong v) @@ -209,7 +210,7 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulo= ng arg) =20 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) { - if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { + if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1u << reg)))= { return; } do_raise_exception(env, EXCP_RI, pc); @@ -261,6 +262,16 @@ target_ulong helper_rdhwr_chord(CPUMIPSState *env) return env->octeon_crypto.chord; } =20 +target_ulong helper_rdhwr_cvmcount(CPUMIPSState *env) +{ + check_hwrena(env, 31, GETPC()); +#ifdef CONFIG_USER_ONLY + return cpu_get_host_ticks(); +#else + return (uint32_t)cpu_mips_get_count(env); +#endif +} + void helper_pmon(CPUMIPSState *env, int function) { function /=3D 2; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 1f44932882..e3467d1525 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -10933,6 +10933,17 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, = int sel) gen_helper_rdhwr_chord(t0, tcg_env); gen_store_gpr(t0, rt); break; + case 31: + if (!(ctx->insn_flags & INSN_OCTEON)) { + gen_reserved_instruction(ctx); + break; + } + translator_io_start(&ctx->base); + gen_helper_rdhwr_cvmcount(t0, tcg_env); + gen_store_gpr(t0, rt); + gen_save_pc(ctx->base.pc_next + 4); + ctx->base.is_jmp =3D DISAS_EXIT; + break; default: /* Invalid */ MIPS_INVAL("rdhwr"); gen_reserved_instruction(ctx); diff --git a/tests/tcg/mips/user/isa/octeon/octeon-insns.c b/tests/tcg/mips= /user/isa/octeon/octeon-insns.c index f3c52d7829..6480c8532a 100644 --- a/tests/tcg/mips/user/isa/octeon/octeon-insns.c +++ b/tests/tcg/mips/user/isa/octeon/octeon-insns.c @@ -330,6 +330,22 @@ static uint64_t octeon_cop2_gfm_mul_reflect_readback(u= int64_t value) return rd; } =20 +static uint64_t octeon_rdhwr31_non_decreasing(void) +{ + uint64_t first, second; + + asm volatile( + ".word 0x7c08f83b\n\t" /* rdhwr $8, $31 */ + ".word 0x7c09f83b\n\t" /* rdhwr $9, $31 */ + "move %[first], $8\n\t" + "move %[second], $9\n\t" + : [first] "=3Dr" (first), [second] "=3Dr" (second) + : + : "$8", "$9"); + + return second >=3D first; +} + int main(void) { assert(octeon_baddu(0x123, 0x0f0) =3D=3D 0x13); @@ -358,6 +374,7 @@ int main(void) 0x0123456789abcdefULL) =3D=3D 0xf7b3d591e6a2c480ULL); assert(octeon_cop2_gfm_mul_reflect_readback( 0xfedcba9876543210ULL) =3D=3D 0x084c2a6e195d3b7fULL); + assert(octeon_rdhwr31_non_decreasing()); =20 return 0; } --=20 2.54.0 From nobody Sat May 30 17:44:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779427423; cv=none; d=zohomail.com; s=zohoarc; b=FmL67LErHs4lD+uDpHXVPvDDlK8KM3PI/AM2xCgMXVVz9Y/Pbo36+flmZ0cC3cShe8nhZQOR4A+gkluh+gdZ7VzZhl1Py0ltto059RPNN9eWDVK610AMzH3zD4f1uVqIMPWlOWk559QJMbkyXqFIaVBKzkzDGsbffvcY3XEBFFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779427423; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mu+lYa+gqNWB2nD7pgrIYlNv9/RobAyR2gn9reCR67g=; b=VyyOdSk8xYKo6bJdQFtOjlh/zS9Kq0IgqNmayjzX/HOEjif6lcD0rF1zlDX1dWDiP7Yluha3HAaPnVKpVJVXrJQ8MK8ywFwiK9JgKIdvxZJb5Vb2zj6QWv93IwqKwOJwSHdQsZGm0va7IIEgAh0uS5vodTc11h8LATfzNRjq25M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779427423156486.0440187661435; Thu, 21 May 2026 22:23:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wQIJZ-0003T0-45; Fri, 22 May 2026 01:20:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wQIJQ-0002zk-0T for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:45 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wQIJO-0002Im-0u for qemu-devel@nongnu.org; Fri, 22 May 2026 01:20:43 -0400 Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-4824176bbbeso2391312b6e.0 for ; Thu, 21 May 2026 22:20:41 -0700 (PDT) Received: from mac.localdomain (184-96-131-78.hlrn.qwest.net. [184.96.131.78]) by smtp.gmail.com with ESMTPSA id 5614622812f47-4855476ab77sm59690b6e.17.2026.05.21.22.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 22:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779427241; x=1780032041; darn=nongnu.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mu+lYa+gqNWB2nD7pgrIYlNv9/RobAyR2gn9reCR67g=; b=CwhJKrwmPTytv99bCtTKw4RalpBETRQlyj8z9vzi5LdJoPFL5LmMmT0MosmRKd3tJn YCWNKC0c4bPjJygqykytG0P5y+0/mctJqdlPflB4uO+n8+EWLHtogmPaJvelG9dPjZIA ySgI3hBxmr/tsJQnZWHCplkjybJ2WsZNzHsk+CX2ZlLspUZx9nX9h8ubK14rVQD+R28p KxtRr7Kcj6gfv4KY4r66gM0eaR0VjG249mZUGPZLnk4BnMjrKhxEdsN1qh4RBm7C4Xid znZtG0CBU0raDbOFIkDT53RosPZ7H5u7DAxUJZ0Rp4BRU5/CI3oDG6f47zN1VKXiByJq L+Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779427241; x=1780032041; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mu+lYa+gqNWB2nD7pgrIYlNv9/RobAyR2gn9reCR67g=; b=Sr7uyigIMGJWTOOPXw8C4X8+1hpXCtw3TxAWoIx6cUnpBwW7xFRaeDFhGj2jJweFXC ClXyWnNzRhdsBZeK4n3bXSC4s1ZakTzxYrmvHyG/eCMuM1lB+1iInd0TgJpu8OsJTzn/ f4X6DmOwBjNl1AEWBUvrEMVtorL2PZRF6O3v9M9iRw+PJ/dJbtF9fNB8psMfdlGbOAco cttvMPuS/Q/bLoA7blZVQ48ilGlRuuI+pjPiH2Ls70DGnU0g72xmZh7wcXX8UYEkWnpW OwXjbAhG+c6+5PAFecat80qXn5BFpofberh2vbYT4GKd+/m5ObzqUeflrvUPj4JAKY4h p7lg== X-Gm-Message-State: AOJu0Yw1X7rxDVtIhGxc9F7yBCO6VAuDNyqckwPs9PpDOmI1lCJLL0lI gdHxwooZaP16oCFG08bVVCQ2eLiheuHpwyDTZsePfv/TBnASNQd2E05p X-Gm-Gg: Acq92OGyCUFoNa5GfKnCzYU6b0bxP9tLa2K3g0opGCib5UOv/fu9RSgoKsy5C6kP/EK ZKqvA2eJTl/2UKLnpmign0bPz0Vc7rhspkbLy42gAqSB0FGVgvecRhKT0PUHeXUNl3JCQk9bIEU hT5ya/Zc91U/p/4fyh2DHWOGI7IIcLvtgZ1T2epyMxztYYorIPhf1RDbwvwcjQWRQbazT4MI3It le0Ti28PvE4+Fe1Q9gYNXZ9unDBcalnIXJa2Plv68ibHZYJ0R1jZA4GOs8tntqLOBrslJSZ4BUg OwHdx5qkkjlqmkYHSHY92xmoVUutdwuuq9rEKQlKp8oOE5LKzQ9+AL3OBjQQamG3PMEvtLRHjXC mPL9lhvVUmQcXEeHlg8tbpTG0IxeQNf64290MBTljPekDjJaf14P6aB3jZL1o3sNjqSS20e3G0V /8lA0tfoQ71d5UkDXSsM8NLM0eWOkjXYKWkondOTptTT+WJcdG0YP7jP3gsvjlcaQD4Hf1ZIqK8 E/+TqfGG2BEiq36kQuUvz/0R8BVPX66lmVv3Soe9oAvBiwoIduY8S+x7FoU3M/+vgBCGBOQYdy8 A3o= X-Received: by 2002:a05:6808:c1fb:b0:480:4024:3bb with SMTP id 5614622812f47-4854a29a2cbmr1525309b6e.24.1779427240998; Thu, 21 May 2026 22:20:40 -0700 (PDT) From: James Hilliard Date: Thu, 21 May 2026 23:20:04 -0600 Subject: [PATCH v14 22/22] tests/tcg/mips: cover Octeon QMAC instructions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260521-mips-octeon-missing-insns-v2-v14-22-fbf08e164830@gmail.com> References: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> In-Reply-To: <20260521-mips-octeon-missing-insns-v2-v14-0-fbf08e164830@gmail.com> To: qemu-devel@nongnu.org Cc: Laurent Vivier , Helge Deller , Pierrick Bouvier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , Huacai Chen , Richard Henderson , Paolo Bonzini , James Hilliard X-Mailer: b4 0.15.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=james.hilliard1@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779427424320154100 Add smoke coverage for Octeon QMAC and QMACS fixed-point accumulator instruction paths. The coverage exercises normal accumulation, saturating accumulation, and the sticky saturation flag. Signed-off-by: James Hilliard Reviewed-by: Richard Henderson --- Changes v12 -> v13: - Add QMAC/QMACS smoke coverage. --- tests/tcg/mips/user/isa/octeon/octeon-insns.c | 40 +++++++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/tests/tcg/mips/user/isa/octeon/octeon-insns.c b/tests/tcg/mips= /user/isa/octeon/octeon-insns.c index 6480c8532a..6fffc82010 100644 --- a/tests/tcg/mips/user/isa/octeon/octeon-insns.c +++ b/tests/tcg/mips/user/isa/octeon/octeon-insns.c @@ -129,6 +129,43 @@ static uint64_t octeon_vmm0(uint64_t mpl0, uint64_t p0, return rd; } =20 +static uint64_t octeon_qmac_lo(uint64_t rs, uint64_t rt, uint64_t lo) +{ + uint64_t rd; + + asm volatile( + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + "mtlo %[lo]\n\t" + "mthi $0\n\t" + ".word 0x710904d2\n\t" /* qmac.03 $8, $9 */ + "mflo %[rd]\n\t" + : [rd] "=3Dr" (rd) + : [rs] "r" (rs), [rt] "r" (rt), [lo] "r" (lo) + : "$8", "$9"); + + return rd; +} + +static uint64_t octeon_qmacs_state(uint64_t rs, uint64_t rt, uint64_t lo) +{ + uint64_t hi, rd; + + asm volatile( + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + "mtlo %[lo]\n\t" + "mthi $0\n\t" + ".word 0x71090012\n\t" /* qmacs.00 $8, $9 */ + "mfhi %[hi]\n\t" + "mflo %[rd]\n\t" + : [hi] "=3Dr" (hi), [rd] "=3Dr" (rd) + : [rs] "r" (rs), [rt] "r" (rt), [lo] "r" (lo) + : "$8", "$9"); + + return ((hi & 1) << 32) | (rd & 0xffffffff); +} + static uint64_t octeon_vmm0_zeroes_mpl1(void) { uint64_t rd; @@ -355,6 +392,9 @@ int main(void) assert(octeon_seq(0xabc, 0xdef) =3D=3D 0); assert(octeon_sne(0xabc, 0xabc) =3D=3D 0); assert(octeon_sne(0xabc, 0xdef) =3D=3D 1); + assert(octeon_qmac_lo(0x0003000000000000ULL, 2, 1) =3D=3D 13); + assert(octeon_qmacs_state(1, 1, 0x7ffffffe) =3D=3D 0x17fffffffULL); + assert(octeon_qmacs_state(0x8000, 0x8000, 0) =3D=3D 0x17fffffffULL); assert(octeon_vmulu(5, 7, 11) =3D=3D 46); assert(octeon_vmm0(5, 13, 7, 11) =3D=3D 59); assert(octeon_vmm0_zeroes_mpl1() =3D=3D 0); --=20 2.54.0