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[PATCH v14 20/22] target/mips: decode Octeon CHORD and LLM COP2 selectors

James Hilliard posted 22 patches 2 months, 3 weeks ago
Maintainers: "Philippe Mathieu-Daudé" <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <arikalo@gmail.com>, Richard Henderson <richard.henderson@linaro.org>
There is a newer version of this series
[PATCH v14 20/22] target/mips: decode Octeon CHORD and LLM COP2 selectors
Posted by James Hilliard 2 months, 3 weeks ago 
Add explicit decodetree entries and translator bindings for the Octeon
CHORD and sparse LLM COP2 selectors.  CHORD and LLM use their own COP2
selector window rather than the crypto engine windows covered by the
preceding decode patches.

This completes the explicit COP2 selector coverage by adding the
remaining CHORD and LLM register and operation selectors.

Signed-off-by: James Hilliard <james.hilliard1@gmail.com>

---
Changes v13 -> v14:
  - Leave the CP2_Undef fallback in the register-selector patch and keep
    this patch limited to CHORD/LLM selector additions.

Changes v9 -> v10:
  - Split CHORD/LLM selector decode out of the monolithic Octeon COP2
    selector decode patch.
  - Kept sparse LLM operations helper-backed.
---
 target/mips/tcg/octeon.decode      | 13 +++++++++++++
 target/mips/tcg/octeon_translate.c | 13 +++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 4ac38d264c..a8c944e668 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -167,6 +167,9 @@ LDX          011111 ..... ..... ..... 01000 001010 @lx
     CVM_MF_GFM_RESINP0                   010010 00001 rt:5 0000 0010 0101 1010 &cp2
     CVM_MF_GFM_RESINP1                   010010 00001 rt:5 0000 0010 0101 1011 &cp2
     CVM_MF_GFM_POLY                      010010 00001 rt:5 0000 0010 0101 1110 &cp2
+    CVM_MF_CHORD                         010010 00001 rt:5 0000 0100 0000 0000 &cp2
+    CVM_MF_LLM_DATA0                     010010 00001 rt:5 0000 0100 0000 0010 &cp2
+    CVM_MF_LLM_DATA1                     010010 00001 rt:5 0000 0100 0000 1010 &cp2
     CVM_MT_HSH_DAT0                      010010 00101 rt:5 0000 0000 0100 0000 &cp2
     CVM_MT_HSH_DAT1                      010010 00101 rt:5 0000 0000 0100 0001 &cp2
     CVM_MT_HSH_DAT2                      010010 00101 rt:5 0000 0000 0100 0010 &cp2
@@ -261,6 +264,16 @@ LDX          011111 ..... ..... ..... 01000 001010 @lx
     CVM_MT_SHA3_XORDAT15                 010010 00101 rt:5 0000 0010 1100 1111 &cp2
     CVM_MT_SHA3_XORDAT16                 010010 00101 rt:5 0000 0010 1101 0000 &cp2
     CVM_MT_SHA3_XORDAT17                 010010 00101 rt:5 0000 0010 1101 0001 &cp2
+    CVM_MT_LLM_READ_ADDR0                010010 00101 rt:5 0000 0100 0000 0000 &cp2
+    CVM_MT_LLM_WRITE_ADDR0               010010 00101 rt:5 0000 0100 0000 0001 &cp2
+    CVM_MT_LLM_DATA0                     010010 00101 rt:5 0000 0100 0000 0010 &cp2
+    CVM_MT_LLM_READ64_ADDR0              010010 00101 rt:5 0000 0100 0000 0100 &cp2
+    CVM_MT_LLM_WRITE64_ADDR0             010010 00101 rt:5 0000 0100 0000 0101 &cp2
+    CVM_MT_LLM_READ_ADDR1                010010 00101 rt:5 0000 0100 0000 1000 &cp2
+    CVM_MT_LLM_WRITE_ADDR1               010010 00101 rt:5 0000 0100 0000 1001 &cp2
+    CVM_MT_LLM_DATA1                     010010 00101 rt:5 0000 0100 0000 1010 &cp2
+    CVM_MT_LLM_READ64_ADDR1              010010 00101 rt:5 0000 0100 0000 1100 &cp2
+    CVM_MT_LLM_WRITE64_ADDR1             010010 00101 rt:5 0000 0100 0000 1101 &cp2
     CVM_MT_CRC_LEN                       010010 00101 rt:5 0001 0010 0000 0010 &cp2
     CVM_MT_CRC_DWORD                     010010 00101 rt:5 0001 0010 0000 0111 &cp2
     CVM_MT_CRC_VAR                       010010 00101 rt:5 0001 0010 0000 1000 &cp2
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index ad71c0a8aa..15a71bc7c3 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -210,6 +210,9 @@ CP2_MF_I64(CVM_MF_GFM_MUL1, gfm_mul[1]);
 CP2_MF_I64(CVM_MF_GFM_RESINP0, gfm_resinp[0]);
 CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]);
 CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly);
+CP2_MF_I64(CVM_MF_CHORD, chord);
+CP2_MF_I64(CVM_MF_LLM_DATA0, llm_data[0]);
+CP2_MF_I64(CVM_MF_LLM_DATA1, llm_data[1]);
 
 CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect);
 CP2_MF_HELPER(CVM_MF_SHA3_DAT24, sha3_dat24);
@@ -281,6 +284,8 @@ CP2_MT_I64(CVM_MT_GFM_RESINP0, gfm_resinp[0]);
 CP2_MT_I64(CVM_MT_GFM_RESINP1, gfm_resinp[1]);
 CP2_MT_HELPER(CVM_MT_GFM_XOR0, gfm_xor0);
 CP2_MT_U16(CVM_MT_GFM_POLY, gfm_poly);
+CP2_MT_I64(CVM_MT_LLM_DATA0, llm_data[0]);
+CP2_MT_I64(CVM_MT_LLM_DATA1, llm_data[1]);
 CP2_MT_U8_MASKED(CVM_MT_CRC_LEN, crc_len, 0xf);
 CP2_MT_U32(CVM_MT_CRC_POLYNOMIAL, crc_poly);
 
@@ -370,6 +375,14 @@ CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5);
 CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256);
 CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha);
 CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512);
+CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR0, llm_read_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR0, llm_write_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR0, llm_read64_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR0, llm_write64_addr0);
+CP2_MT_HELPER(CVM_MT_LLM_READ_ADDR1, llm_read_addr1);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE_ADDR1, llm_write_addr1);
+CP2_MT_HELPER(CVM_MT_LLM_READ64_ADDR1, llm_read64_addr1);
+CP2_MT_HELPER(CVM_MT_LLM_WRITE64_ADDR1, llm_write64_addr1);
 
 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
 {

-- 
2.54.0
Re: [PATCH v14 20/22] target/mips: decode Octeon CHORD and LLM COP2 selectors
Posted by Richard Henderson 2 months, 2 weeks ago 
On 5/21/26 22:20, James Hilliard wrote:
> Add explicit decodetree entries and translator bindings for the Octeon
> CHORD and sparse LLM COP2 selectors.  CHORD and LLM use their own COP2
> selector window rather than the crypto engine windows covered by the
> preceding decode patches.
> 
> This completes the explicit COP2 selector coverage by adding the
> remaining CHORD and LLM register and operation selectors.
> 
> Signed-off-by: James Hilliard<james.hilliard1@gmail.com>
> 
> ---
> Changes v13 -> v14:
>    - Leave the CP2_Undef fallback in the register-selector patch and keep
>      this patch limited to CHORD/LLM selector additions.
> 
> Changes v9 -> v10:
>    - Split CHORD/LLM selector decode out of the monolithic Octeon COP2
>      selector decode patch.
>    - Kept sparse LLM operations helper-backed.
> ---
>   target/mips/tcg/octeon.decode      | 13 +++++++++++++
>   target/mips/tcg/octeon_translate.c | 13 +++++++++++++
>   2 files changed, 26 insertions(+)

Not present in the documentation I have, but it looks ok.

Acked-by: Richard Henderson <richard.henderson@linaro.org>

r~
Re: [PATCH v14 20/22] target/mips: decode Octeon CHORD and LLM COP2 selectors
Posted by James Hilliard 2 months, 2 weeks ago 
On Fri, May 22, 2026 at 9:40 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 5/21/26 22:20, James Hilliard wrote:
> > Add explicit decodetree entries and translator bindings for the Octeon
> > CHORD and sparse LLM COP2 selectors.  CHORD and LLM use their own COP2
> > selector window rather than the crypto engine windows covered by the
> > preceding decode patches.
> >
> > This completes the explicit COP2 selector coverage by adding the
> > remaining CHORD and LLM register and operation selectors.
> >
> > Signed-off-by: James Hilliard<james.hilliard1@gmail.com>
> >
> > ---
> > Changes v13 -> v14:
> >    - Leave the CP2_Undef fallback in the register-selector patch and keep
> >      this patch limited to CHORD/LLM selector additions.
> >
> > Changes v9 -> v10:
> >    - Split CHORD/LLM selector decode out of the monolithic Octeon COP2
> >      selector decode patch.
> >    - Kept sparse LLM operations helper-backed.
> > ---
> >   target/mips/tcg/octeon.decode      | 13 +++++++++++++
> >   target/mips/tcg/octeon_translate.c | 13 +++++++++++++
> >   2 files changed, 26 insertions(+)
>
> Not present in the documentation I have, but it looks ok.

I checked this more closely. The CN50XX/CN71XX manuals document RDHWR
$30 as ChOrd. The SDK and this series use the all-caps CHORD spelling
for the same local pending tag-switch bit. I do not find the legacy
DMFC2 0x0400 alias in the manuals.

Mainline Linux uses that same CHORD spelling for the RDHWR path:

https://github.com/torvalds/linux/blob/v7.0/arch/mips/include/asm/octeon/cvmx-pow.h#L1302-L1331

The LLM selector bank also appears to be SDK/kernel ABI rather than
public-manual material. Cavium SDK cvmx-asm.h defines the
0x0400/0x0401/0x0402/0x0404/0x0405 + 8*set LLM selectors, and
cvmx-llm.h uses those selectors for narrow/wide LLM accesses while
documenting the 36-bit data/xxor format. Mainline Linux's Octeon
context switch code also saves/restores LLM state through DMFC2/DMTC2
selectors 0x0402 and 0x040a:

https://github.com/torvalds/linux/blob/v7.0/arch/mips/kernel/octeon_switch.S#L111-L117
https://github.com/torvalds/linux/blob/v7.0/arch/mips/kernel/octeon_switch.S#L276-L280

So RDHWR $30 is the documented ChOrd/CHORD path, while the DMFC2 CHORD
alias and the LLM selector bank are SDK-visible compatibility
interfaces.

>
> Acked-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~

Patchew 2.1-devel-ea86937

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