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([71.212.142.33]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36a3c83f226sm254416a91.0.2026.05.20.10.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 May 2026 10:18:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1779297504; x=1779902304; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x9rWSaQvjbDXBnfVxCErc01A7AXki6hbY0KLzGZpXR4=; b=TKJ47Yk1/Ww8QRVh9DY0+JVI320hVwTYS6XvvfeSA2zjCtAPCTsWbsD4YKTqIZ5Dj2 Bubr9Sa+F/mvz7tlEIuhmK3ryoWzTJ+Qh0Drik8UM1Xnz5Sw8en0vZjFOoojJg9qE7dp jzZhrWG4zdbEu21vtPtmx5OVbtP29s/CV+eo7xYcSaTBsxKW9i76e1RuVZs3U/SK6Tvl YIuRMxS02nTZWMGw8rpnJrKXDNjHKRyqF2IijPoT+PKUTFFtuE8NeAGtXu11PBYTo42F KCBULrxo07ec/XzIkytvx3vhendiOucfJlsTMTxAgkeHXPvG6phrdfXWvkLG5iSuwP8g gK1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779297504; x=1779902304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=x9rWSaQvjbDXBnfVxCErc01A7AXki6hbY0KLzGZpXR4=; b=QSVQchO4Fpm1ax+HR0xwYGQIAyTEAqnrUUc6xZXDKo4Kxo6dxEfx2jYWwWa//iQIMc 85Prc33stAsWU4ClMwgyQ4IYuiKH4kAp2xcLF184ruAPeSdoDreuW+YIN0KXjjhuEpQu VhM8+zXkQ7JBEphvKRfyBm8XBrFBVOC/q5gB9hyHQbMtVwYIV9zY0noKyRwMNfAWXUVO snvKrcE2Z67zWflmzKpc5iMrPuq93ki/ACoR85ko6ElBPIQueHNPUSYZbnAQk7E02Lr6 ZfkJvBnhZuYXqOemLWVWdd0zW9/SUKYppjlgaxcRNPHvAT+phvwGwluWAbcIkBvPmEBN kp5Q== X-Gm-Message-State: AOJu0Yw0OVbUuajTHb43Vj6mGHf53lEYSglgJcESZUqispv4YOEHAI3i dMN8ud0Q1gOiuPtJwOaSBubADEIJ/ugSdNWyPKbwO4kE6nC3fsH7TSdL8t+Nu8JKYsYdja5ZWaK GfpIZb+o= X-Gm-Gg: Acq92OHoSIun2mSMXTbjSSA1/+WYfr0n1soZhXBmxG+N1QjgVA9KfxFjMBIE1leRB5o HPZ87vOgCPCzDbtKryddTLEr5waaB8qpKTsYAqn75qL8P/tVMQe48Aefo6nR/9FHik0+FjW7usJ bpGlcXCUhIRH6zUrHareO+psBv+o7orml1Hct6POfWMc2BHzQuMpi8pD02YWE61Ym/sM/o+ivPI uKR0TWYnIytNN5pIvFm/Tg5xNXgScDmp8Nsz2hPJQZyqjzL/IJSi73j9CZh9G5eJyJmAKOGt0dN XaAu4BKzSsnm2SdnLMpj/zmqmwUGTLlrfMhP+yJzsT6u4jMQBzPrRBETBtJ9HS/J5dkrMGU6jw6 8EkcDulAZ7GQ7GA6cYl2oALOE8aZb9pCCURoqOjZTj6Epj+2xjfHtTkdpnFhAYmEl0GSPExKyVD 1Kc1RZFNvSmDb2lRJv91BlxXg9u7yc X-Received: by 2002:a17:90b:33c4:b0:367:f9f1:af78 with SMTP id 98e67ed59e1d1-369519decbcmr25196137a91.7.1779297503441; Wed, 20 May 2026 10:18:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 02/30] fpu: Reorganize partsN(muladd) Date: Wed, 20 May 2026 10:17:52 -0700 Message-ID: <20260520171820.848839-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260520171820.848839-1-richard.henderson@linaro.org> References: <20260520171820.848839-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1779297646513154100 Content-Type: text/plain; charset="utf-8" Check the likely case of normal product and normal or zero addend first; shift NaN and infinity detection down; end with zero product + addend. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- fpu/softfloat-parts.c.inc | 156 +++++++++++++++++--------------------- 1 file changed, 71 insertions(+), 85 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3a9c2748cd..ca2d7a15c9 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -681,11 +681,47 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, Fl= oatPartsN *b, FloatPartsN *c, int flags, float_status *s) { - int ab_mask, abc_mask; - FloatPartsW p_widen, c_widen; + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + int c_mask =3D float_cmask(c->cls); + int abc_mask =3D ab_mask | c_mask; + bool c_sign =3D c->sign ^ !!(flags & float_muladd_negate_c); + bool p_sign =3D a->sign ^ b->sign ^ !!(flags & float_muladd_negate_pro= duct); =20 - ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); - abc_mask =3D float_cmask(c->cls) | ab_mask; + /* + * The "likely" case is A and B normal, so that the product is normal, + * and C normal or zero so that the result is normal. + */ + int likely_mask =3D ab_mask | (c_mask & ~float_cmask_zero); + if (likely(cmask_is_only_normals(likely_mask))) { + record_denormals_used(abc_mask, s); + + /* Perform the multiplication step. */ + FloatPartsW p_widen =3D { .sign =3D p_sign, .exp =3D a->exp + b->e= xp + 1 }; + fracN(mulw)(&p_widen, a, b); + if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + fracW(add)(&p_widen, &p_widen, &p_widen); + p_widen.exp -=3D 1; + } + + /* Perform the addition step. */ + if (!(c_mask & float_cmask_zero)) { + /* Zero-extend C to less significant bits. */ + FloatPartsW c_widen =3D { .sign =3D c_sign, .exp =3D c->exp }; + fracN(widen)(&c_widen, c); + + if (p_sign =3D=3D c_sign) { + partsW(add_normal)(&p_widen, &c_widen); + } else if (!partsW(sub_normal)(&p_widen, &c_widen)) { + goto return_sub_zero; + } + } + + /* Narrow with sticky bit, for proper rounding later. */ + fracN(truncjam)(a, &p_widen); + a->sign =3D p_widen.sign; + a->exp =3D p_widen.exp; + return a; + } =20 /* * It is implementation-defined whether the cases of (0,inf,qnan) @@ -698,97 +734,47 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, Fl= oatPartsN *b, return a; } =20 - if (flags & float_muladd_negate_c) { - c->sign ^=3D 1; + if (unlikely(ab_mask =3D=3D float_cmask_infzero)) { + /* Inf * Zero =3D=3D NaN */ + float_raise(float_flag_invalid | float_flag_invalid_imz, s); + goto d_nan; } =20 - /* Compute the sign of the product into A. */ - a->sign ^=3D b->sign; - if (flags & float_muladd_negate_product) { - a->sign ^=3D 1; - } - - if (unlikely(!cmask_is_only_normals(ab_mask))) { - if (unlikely(ab_mask =3D=3D float_cmask_infzero)) { - float_raise(float_flag_invalid | float_flag_invalid_imz, s); + if (unlikely(ab_mask & float_cmask_inf)) { + if ((c_mask & float_cmask_inf) && p_sign !=3D c_sign) { + /* Inf - Inf =3D=3D NaN */ + float_raise(float_flag_invalid | float_flag_invalid_isi, s); goto d_nan; } - - if (ab_mask & float_cmask_inf) { - if (c->cls =3D=3D float_class_inf && a->sign !=3D c->sign) { - float_raise(float_flag_invalid | float_flag_invalid_isi, s= ); - goto d_nan; - } - goto return_inf; - } - - g_assert(ab_mask & float_cmask_zero); - if (is_anynorm(c->cls)) { - *a =3D *c; - goto finish_sign; - } - if (c->cls =3D=3D float_class_zero) { - if (flags & float_muladd_suppress_add_product_zero) { - a->sign =3D c->sign; - } else if (a->sign !=3D c->sign) { - goto return_sub_zero; - } - goto return_zero; - } - g_assert(c->cls =3D=3D float_class_inf); + /* Inf + C =3D=3D Inf */ + record_denormals_used(abc_mask, s); + a->sign =3D p_sign; + a->cls =3D float_class_inf; + return a; } - - if (unlikely(c->cls =3D=3D float_class_inf)) { - a->sign =3D c->sign; - goto return_inf; - } - - /* Perform the multiplication step. */ - p_widen.sign =3D a->sign; - p_widen.exp =3D a->exp + b->exp + 1; - fracN(mulw)(&p_widen, a, b); - if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) { - fracW(add)(&p_widen, &p_widen, &p_widen); - p_widen.exp -=3D 1; - } - - /* Perform the addition step. */ - if (c->cls !=3D float_class_zero) { - /* Zero-extend C to less significant bits. */ - fracN(widen)(&c_widen, c); - c_widen.exp =3D c->exp; - - if (a->sign =3D=3D c->sign) { - partsW(add_normal)(&p_widen, &c_widen); - } else if (!partsW(sub_normal)(&p_widen, &c_widen)) { - goto return_sub_zero; - } - } - - /* Narrow with sticky bit, for proper rounding later. */ - fracN(truncjam)(a, &p_widen); - a->sign =3D p_widen.sign; - a->exp =3D p_widen.exp; - - finish_sign: - /* - * All result types except for "return the default NaN - * because this is an Invalid Operation" go through here; - * this matches the set of cases where we consumed a - * denormal input. - */ record_denormals_used(abc_mask, s); - return a; + + /* Only remaining cases are zero product or inf addend. */ + assert((ab_mask & float_cmask_zero) | (c_mask & float_cmask_inf)); + + /* + * P + Inf =3D=3D Inf, or + * 0 + C =3D=3D C, + * except for 0 - 0, which needs special rounding, + * except for when we want to suppress this addition step. + */ + if (!(c_mask & float_cmask_zero) + || p_sign =3D=3D c_sign + || (flags & float_muladd_suppress_add_product_zero)) { + c->sign =3D c_sign; + return c; + } =20 return_sub_zero: + /* 0 - 0 =3D=3D -0 for round_down, +0 otherwise. */ a->sign =3D s->float_rounding_mode =3D=3D float_round_down; - return_zero: a->cls =3D float_class_zero; - goto finish_sign; - - return_inf: - a->cls =3D float_class_inf; - goto finish_sign; + return a; =20 d_nan: *a =3D partsN(default_nan)(s); --=20 2.43.0