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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293321394158500 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Move EXTSWSLI to decodetree using the XS-form layout with a custom %xs_sh field to represent the fractured shift encoding. This replaces legacy GEN_HANDLER-based implementations with a single trans_EXTSWSLI() handler. The implementation intentionally operates directly on the destination GPR to preserve exact TCG output and avoid introducing temporary variables, matching legacy behavior. Testing: - Verified TCG equivalence with legacy implementation. Signed-off-by: Nikhil Kumar Singh Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 8 ++++++++ target/ppc/translate.c | 43 ++++++++++++++-------------------------- 2 files changed, 23 insertions(+), 28 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0e9c68f2fb..342e65dadf 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -117,6 +117,11 @@ &X_sa_rc rs ra rc @X_sa_rc ...... rs:5 ra:5 ..... .......... rc:1 &X_sa_rc =20 +# XS-form with fractured shift amount +%xs_sh 1:1 11:5 +&XS rs ra sh rc +@XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=3D%= xs_sh + %x_frtp 22:4 !function=3Dtimes_2 %x_frap 17:4 !function=3Dtimes_2 %x_frbp 12:4 !function=3Dtimes_2 @@ -1301,6 +1306,9 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 .= .- @XX3_at xa=3D%xx_xa_pair XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=3D%xx_= xa_pair XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=3D%xx_= xa_pair =20 +##Extend Sign Word and Shift Left Immediate XS-form +EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS + ## Vector Division Instructions =20 VDIVSW 000100 ..... ..... ..... 00110001011 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3f6d326cef..e802414fca 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2470,30 +2470,6 @@ static void gen_sradi1(DisasContext *ctx) gen_sradi(ctx, 1); } =20 -/* extswsli & extswsli. */ -static inline void gen_extswsli(DisasContext *ctx, int n) -{ - int sh =3D SH(ctx->opcode) + (n << 5); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - - tcg_gen_ext32s_tl(dst, src); - tcg_gen_shli_tl(dst, dst, sh); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - -static void gen_extswsli0(DisasContext *ctx) -{ - gen_extswsli(ctx, 0); -} - -static void gen_extswsli1(DisasContext *ctx) -{ - gen_extswsli(ctx, 1); -} - /* srd & srd. */ static void gen_srd(DisasContext *ctx) { @@ -5750,6 +5726,21 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *= d, arg_PLS_D *a) return true; } =20 +static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + /* Mimic legacy behavior: operate directly on dst */ + tcg_gen_ext32s_tl(cpu_gpr[a->ra], cpu_gpr[a->rs]); + tcg_gen_shli_tl(cpu_gpr[a->ra], cpu_gpr[a->ra], a->sh); + + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5850,10 +5841,6 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_= 64B), GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), -GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, - PPC_NONE, PPC2_ISA300), -GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, - PPC_NONE, PPC2_ISA300), #endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293372199158500 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Migrate load-and-reserve instructions (lbarx, lharx, lwarx, ldarx, lqarx) to decodetree using the X-form layout. A shared helper (do_load_locked) is introduced for standard-width variants, while LQARX is handled separately due to its 128-bit semantics and register pairing constraints. The implementation preserves legacy behavior, including: - Reservation granularity and overwrite semantics - Alignment requirements - Invalid instruction cases for LQARX Testing: - Verified TCG equivalence with legacy implementation Signed-off-by: Nikhil Kumar Singh Signed-off-by: Chinmay Rath [cr: ppc32 build fix, using @X_rc for decode] --- target/ppc/insn32.decode | 7 ++ target/ppc/translate.c | 142 ++++++++++++++++++++++----------------- 2 files changed, 87 insertions(+), 62 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 342e65dadf..26948e08a7 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1309,6 +1309,13 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010 = ..- @XX3_at xa=3D%xx_xa_pair ##Extend Sign Word and Shift Left Immediate XS-form EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 +## Load and Reserve Instructions +LBARX 011111 ..... ..... ..... 0000110100 . @X_rc +LHARX 011111 ..... ..... ..... 0001110100 . @X_rc +LWARX 011111 ..... ..... ..... 0000010100 . @X_rc +LDARX 011111 ..... ..... ..... 0001010100 . @X_rc +LQARX 011111 ..... ..... ..... 0100010100 . @X_rc + ## Vector Division Instructions =20 VDIVSW 000100 ..... ..... ..... 00110001011 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e802414fca..3f009cd9ca 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2947,30 +2947,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 -static void gen_load_locked(DisasContext *ctx, MemOp memop) -{ - TCGv gpr =3D cpu_gpr[rD(ctx->opcode)]; - TCGv t0 =3D tcg_temp_new(); - - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); - tcg_gen_mov_tl(cpu_reserve, t0); - tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); - tcg_gen_mov_tl(cpu_reserve_val, gpr); -} - -#define LARX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - gen_load_locked(ctx, memop); \ -} - -/* lwarx */ -LARX(lbarx, MO_UB) -LARX(lharx, MO_UW) -LARX(lwarx, MO_UL) - static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv EA, TCGCond cond, int addend) { @@ -3219,42 +3195,9 @@ STCX(sthcx_, MO_UW) STCX(stwcx_, MO_UL) =20 #if defined(TARGET_PPC64) -/* ldarx */ -LARX(ldarx, MO_UQ) /* stdcx. */ STCX(stdcx_, MO_UQ) =20 -/* lqarx */ -static void gen_lqarx(DisasContext *ctx) -{ - int rd =3D rD(ctx->opcode); - TCGv EA, hi, lo; - TCGv_i128 t16; - - if (unlikely((rd & 1) || (rd =3D=3D rA(ctx->opcode)) || - (rd =3D=3D rB(ctx->opcode)))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - gen_set_access_type(ctx, ACCESS_RES); - EA =3D tcg_temp_new(); - gen_addr_reg_index(ctx, EA); - - /* Note that the low part is always in RD+1, even in LE mode. */ - lo =3D cpu_gpr[rd + 1]; - hi =3D cpu_gpr[rd]; - - t16 =3D tcg_temp_new_i128(); - tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIG= N)); - tcg_gen_extr_i128_i64(lo, hi, t16); - - tcg_gen_mov_tl(cpu_reserve, EA); - tcg_gen_movi_tl(cpu_reserve_length, 16); - tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); - tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); -} - /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { @@ -5741,6 +5684,86 @@ static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS= *a) return true; } =20 +/* + * Load-and-reserve core + */ +static bool do_load_locked(DisasContext *ctx, arg_X_rc *a, MemOp memop) +{ + TCGv EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv gpr =3D cpu_gpr[a->rt]; + + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_qemu_ld_tl(gpr, EA, ctx->mem_idx, memop | MO_ALIGN); + + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); + + tcg_gen_mov_tl(cpu_reserve_val, gpr); + + return true; +} + +static bool trans_LBARX(DisasContext *ctx, arg_LBARX *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, ATOMIC_ISA206); + return do_load_locked(ctx, a, DEF_MEMOP(MO_UB)); +} + +static bool trans_LHARX(DisasContext *ctx, arg_LHARX *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, ATOMIC_ISA206); + return do_load_locked(ctx, a, DEF_MEMOP(MO_UW)); +} + +static bool trans_LWARX(DisasContext *ctx, arg_LWARX *a) +{ + return do_load_locked(ctx, a, DEF_MEMOP(MO_UL)); +} + +static bool trans_LDARX(DisasContext *ctx, arg_LDARX *a) +{ + REQUIRE_64BIT(ctx); + return do_load_locked(ctx, a, DEF_MEMOP(MO_UQ)); +} + +static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); +#if defined(TARGET_PPC64) + TCGv EA; + TCGv_i128 t16; + /* Must use even register and avoid overlap */ + if (unlikely((a->rt & 1) || (a->rt =3D=3D a->ra) || (a->rt =3D=3D a->r= b))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + gen_set_access_type(ctx, ACCESS_RES); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + t16 =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + + tcg_gen_extr_i128_i64(cpu_gpr[a->rt + 1], + cpu_gpr[a->rt], + t16); + + tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, 16); + + tcg_gen_st_i64(cpu_gpr[a->rt], + tcg_env, offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_i64(cpu_gpr[a->rt + 1], + tcg_env, offsetof(CPUPPCState, reserve_val2)); +#else + qemu_build_not_reached(); +#endif + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5853,9 +5876,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_S= TRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), -GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), @@ -5864,8 +5884,6 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00= 000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), -GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293410776158500 Content-Type: text/plain; charset="utf-8" From: Nikhil Kumar Singh Convert cache management instructions to decodetree using the X-form layout and dedicated translation functions. Legacy GEN_HANDLER-based implementations are removed. The implementation preserves legacy semantics, including: - MMU-visible accesses for instructions treated as loads (e.g. dcbt, dcbtst, dcbtep, dcbtstep) - Supervisor and BookE-specific constraints - Effective address computation via do_ea_calc() Instructions that were defined as no-ops in the legacy implementation remain no-ops here. Testing: - Verified TCG equivalence for all cache operations Signed-off-by: Nikhil Kumar Singh Signed-off-by: Chinmay Rath [cr: linux user build, flag check, helper function fixes] --- target/ppc/helper.h | 8 +- target/ppc/insn32.decode | 25 ++ target/ppc/mem_helper.c | 8 +- target/ppc/translate.c | 484 +++++++++++++++++++++------------------ 4 files changed, 288 insertions(+), 237 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index e99c8c824b..37803ebb17 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -48,12 +48,12 @@ DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl,= i32) DEF_HELPER_4(lsw, void, env, tl, i32, i32) DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_4(stsw, TCG_CALL_NO_WG, void, env, tl, i32, i32) -DEF_HELPER_FLAGS_3(dcbz, TCG_CALL_NO_WG, void, env, tl, int) +DEF_HELPER_FLAGS_3(DCBZ, TCG_CALL_NO_WG, void, env, tl, int) #ifdef TARGET_PPC64 -DEF_HELPER_FLAGS_2(dcbzl, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(DCBZL, TCG_CALL_NO_WG, void, env, tl) #endif -DEF_HELPER_FLAGS_2(icbi, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(icbiep, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(ICBI, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(ICBIEP, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32) =20 #if defined(TARGET_PPC64) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 26948e08a7..0fbabefba9 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1306,6 +1306,31 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 = ..- @XX3_at xa=3D%xx_xa_pair XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=3D%xx_= xa_pair XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=3D%xx_= xa_pair =20 +## Cache Management Instructions +DCBF 011111 ..... ..... ..... 0001010110 - @X +DCBFEP 011111 ..... ..... ..... 0001111111 - @X +DCBI 011111 ..... ..... ..... 0111010110 - @X +DCBST 011111 ..... ..... ..... 0000110110 - @X +DCBSTEP 011111 ..... ..... ..... 0000111111 - @X +DCBA 011111 ..... ..... ..... 1011110110 - @X + +DCBT 011111 ..... ..... ..... 0100010110 - @X +DCBTEP 011111 ..... ..... ..... 0100111111 - @X +DCBTST 011111 ..... ..... ..... 0011110110 - @X +DCBTSTEP 011111 ..... ..... ..... 0011111111 - @X + +DCBTLS 011111 ..... ..... ..... 0010100110 - @X +DCBLC 011111 ..... ..... ..... 0110000110 - @X + +DCBZ 011111 ..... ..... ..... 1111110110 - @X +DCBZEP 011111 ..... ..... ..... 1111111111 - @X +ICBI 011111 ..... ..... ..... 1111010110 - @X +ICBIEP 011111 ..... ..... ..... 1111011111 - @X + +DST 011111 ..... ..... ..... 0101010110 - @X +DSTST 011111 ..... ..... ..... 0101110110 - @X +DSS 011111 ..... ..... ..... 1100110110 - @X + ##Extend Sign Word and Shift Left Immediate XS-form EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 119dc1df23..5d3d377261 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -319,13 +319,13 @@ static void dcbz_common(CPUPPCState *env, target_ulon= g addr, clear_helper_retaddr(); } =20 -void helper_dcbz(CPUPPCState *env, target_ulong addr, int mmu_idx) +void helper_DCBZ(CPUPPCState *env, target_ulong addr, int mmu_idx) { dcbz_common(env, addr, mmu_idx, env->dcache_line_size, GETPC()); } =20 #ifdef TARGET_PPC64 -void helper_dcbzl(CPUPPCState *env, target_ulong addr) +void helper_DCBZL(CPUPPCState *env, target_ulong addr) { int dcbz_size =3D env->dcache_line_size; =20 @@ -341,7 +341,7 @@ void helper_dcbzl(CPUPPCState *env, target_ulong addr) } #endif =20 -void helper_icbi(CPUPPCState *env, target_ulong addr) +void helper_ICBI(CPUPPCState *env, target_ulong addr) { unsigned mmu_idx =3D cpu_mmu_index(env_cpu(env), false); MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, mmu_idx); @@ -357,7 +357,7 @@ void helper_icbi(CPUPPCState *env, target_ulong addr) cpu_ldl_mmu(env, addr, oi, GETPC()); } =20 -void helper_icbiep(CPUPPCState *env, target_ulong addr) +void helper_ICBIEP(CPUPPCState *env, target_ulong addr) { #if !defined(CONFIG_USER_ONLY) MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, PPC_TLB_EPID_LOAD); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3f009cd9ca..ba1774a539 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4296,216 +4296,6 @@ static void gen_setb(DisasContext *ctx) } #endif =20 -/*** Cache management = ***/ - -/* dcbf */ -static void gen_dcbf(DisasContext *ctx) -{ - /* XXX: specification says this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld8u(ctx, t0, t0); -} - -/* dcbfep (external PID dcbf) */ -static void gen_dcbfep(DisasContext *ctx) -{ - /* XXX: specification says this is treated as a load by the MMU */ - TCGv t0; - CHK_SV(ctx); - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); -} - -/* dcbi (Supervisor only) */ -static void gen_dcbi(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv EA, val; - - CHK_SV(ctx); - EA =3D tcg_temp_new(); - gen_set_access_type(ctx, ACCESS_CACHE); - gen_addr_reg_index(ctx, EA); - val =3D tcg_temp_new(); - /* XXX: specification says this should be treated as a store by the MM= U */ - gen_qemu_ld8u(ctx, val, EA); - gen_qemu_st8(ctx, val, EA); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* dcdst */ -static void gen_dcbst(DisasContext *ctx) -{ - /* XXX: specification say this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_qemu_ld8u(ctx, t0, t0); -} - -/* dcbstep (dcbstep External PID version) */ -static void gen_dcbstep(DisasContext *ctx) -{ - /* XXX: specification say this is treated as a load by the MMU */ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); -} - -/* dcbt */ -static void gen_dcbt(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtep */ -static void gen_dcbtep(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtst */ -static void gen_dcbtst(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtstep */ -static void gen_dcbtstep(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a load by the MMU but - * does not generate any exception - */ -} - -/* dcbtls */ -static void gen_dcbtls(DisasContext *ctx) -{ - /* Always fails locking the cache */ - TCGv t0 =3D tcg_temp_new(); - gen_load_spr(t0, SPR_Exxx_L1CSR0); - tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); - gen_store_spr(SPR_Exxx_L1CSR0, t0); -} - -/* dcblc */ -static void gen_dcblc(DisasContext *ctx) -{ - /* - * interpreted as no-op - */ -} - -/* dcbz */ -static void gen_dcbz(DisasContext *ctx) -{ - TCGv tcgv_addr =3D tcg_temp_new(); - - gen_set_access_type(ctx, ACCESS_CACHE); - gen_addr_reg_index(ctx, tcgv_addr); - -#ifdef TARGET_PPC64 - if (ctx->excp_model =3D=3D POWERPC_EXCP_970 && !(ctx->opcode & 0x00200= 000)) { - gen_helper_dcbzl(tcg_env, tcgv_addr); - return; - } -#endif - - gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(ctx->mem_idx)); -} - -/* dcbzep */ -static void gen_dcbzep(DisasContext *ctx) -{ - TCGv tcgv_addr =3D tcg_temp_new(); - - gen_set_access_type(ctx, ACCESS_CACHE); - gen_addr_reg_index(ctx, tcgv_addr); - gen_helper_dcbz(tcg_env, tcgv_addr, tcg_constant_i32(PPC_TLB_EPID_STOR= E)); -} - -/* dst / dstt */ -static void gen_dst(DisasContext *ctx) -{ - if (rA(ctx->opcode) =3D=3D 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - } else { - /* interpreted as no-op */ - } -} - -/* dstst /dststt */ -static void gen_dstst(DisasContext *ctx) -{ - if (rA(ctx->opcode) =3D=3D 0) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - } else { - /* interpreted as no-op */ - } - -} - -/* dss / dssall */ -static void gen_dss(DisasContext *ctx) -{ - /* interpreted as no-op */ -} - -/* icbi */ -static void gen_icbi(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_helper_icbi(tcg_env, t0); -} - -/* icbiep */ -static void gen_icbiep(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_helper_icbiep(tcg_env, t0); -} - -/* Optional: */ -/* dcba */ -static void gen_dcba(DisasContext *ctx) -{ - /* - * interpreted as no-op - * XXX: specification say this is treated as a store by the MMU - * but does not generate any exception - */ -} - /*** Segment register manipulation = ***/ /* Supervisor only: */ =20 @@ -5764,6 +5554,261 @@ static bool trans_LQARX(DisasContext *ctx, arg_LQAR= X *a) return true; } =20 +/* + * Cache Management Instructions (decodetree) + */ + +static bool trans_DCBA(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE_DCBA); + return true; +} + +static bool trans_DCBT(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + return true; +} + +static bool trans_DCBTEP(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + return true; +} + +static bool trans_DCBTST(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS(ctx, CACHE); + return true; +} + +static bool trans_DCBTSTEP(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + return true; +} + +static bool trans_DCBLC(DisasContext *ctx, arg_X *a) +{ + /* Requires either PPC_BOOKE or PPC2_BOOKE206 */ + if (!(ctx->insns_flags & PPC_BOOKE) && + !(ctx->insns_flags2 & PPC2_BOOKE206)) { + return false; + } + return true; +} + +static bool trans_DSS(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + return true; +} + +static bool trans_DCBTLS(DisasContext *ctx, arg_X *a) +{ + TCGv t0 =3D tcg_temp_new(); + + /* Requires either PPC_BOOKE or PPC2_BOOKE206 */ + if (!(ctx->insns_flags & PPC_BOOKE) && + !(ctx->insns_flags2 & PPC2_BOOKE206)) { + return false; + } + + gen_load_spr(t0, SPR_Exxx_L1CSR0); + tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); + gen_store_spr(SPR_Exxx_L1CSR0, t0); + + return true; +} + +static bool trans_DST(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + + if (a->ra =3D=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + } + + return true; +} + +static bool trans_DSTST(DisasContext *ctx, arg_X *a) +{ + REQUIRE_INSNS_FLAGS(ctx, ALTIVEC); + + if (a->ra =3D=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + } + + return true; +} + +static bool trans_DCBF(DisasContext *ctx, arg_X *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE); + + if (a->rt !=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_qemu_ld8u(ctx, EA, EA); + + return true; +} + +static bool trans_DCBST(DisasContext *ctx, arg_X *a) +{ + + if (a->rt !=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + /* Flags check overlaps with trans_DCBF */ + return trans_DCBF(ctx, a); +} + +static bool trans_DCBFEP(DisasContext *ctx, arg_X *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + + /* Per ISA: RT must be zero for cache management instructions */ + if (a->rt !=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + tcg_gen_qemu_ld_tl(EA, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); + + return true; +} + +static bool trans_DCBSTEP(DisasContext *ctx, arg_X *a) +{ + /* Flags check overlaps with trans_DCBFEP */ + return trans_DCBFEP(ctx, a); +} + +static bool trans_DCBI(DisasContext *ctx, arg_X *a) +{ +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); + return true; +#else + TCGv EA, val; + REQUIRE_INSNS_FLAGS(ctx, CACHE); + + if (a->rt !=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + REQUIRE_SV(ctx); + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + val =3D tcg_temp_new(); + + gen_qemu_ld8u(ctx, val, EA); + gen_qemu_st8(ctx, val, EA); + + return true; +#endif +} + +static bool trans_ICBI(DisasContext *ctx, arg_X *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE_ICBI); + + if (a->rt !=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + + gen_set_access_type(ctx, ACCESS_CACHE); + + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + gen_helper_ICBI(tcg_env, EA); + + return true; +} + +static bool trans_ICBIEP(DisasContext *ctx, arg_X *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + gen_helper_ICBIEP(tcg_env, EA); + return true; +} + +static bool trans_DCBZ(DisasContext *ctx, arg_X *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS(ctx, CACHE_DCBZ); + + if (a->rt !=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + + gen_set_access_type(ctx, ACCESS_CACHE); + + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + +#if defined(TARGET_PPC64) + if (ctx->excp_model =3D=3D POWERPC_EXCP_970 && + !(ctx->opcode & 0x00200000)) { + gen_helper_DCBZL(tcg_env, EA); + return true; + } +#endif + + gen_helper_DCBZ(tcg_env, EA, tcg_constant_i32(ctx->mem_idx)); + return true; +} + +static bool trans_DCBZEP(DisasContext *ctx, arg_X *a) +{ + TCGv EA; + + REQUIRE_INSNS_FLAGS2(ctx, BOOKE206); + + if (a->rt !=3D 0) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + REQUIRE_SV(ctx); + + gen_set_access_type(ctx, ACCESS_CACHE); + EA =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + + gen_helper_DCBZ(tcg_env, EA, tcg_constant_i32(PPC_TLB_EPID_STORE)); + return true; +} + #include "translate/fixedpoint-impl.c.inc" =20 #include "translate/fp-impl.c.inc" @@ -5928,25 +5973,6 @@ GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, = PPC_NONE, PPC2_ISA300), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), -GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), -GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), -GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), -GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE2= 06), -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), -GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), -GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE= 206), -GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE2= 06), -GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), -GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), -GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), -GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE20= 6), -GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293365177154100 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: vmrg{hb, hh, hw, lb, lh, lw} : VX-form The individual gen_vmrg* functions generated by GEN_VXFORM are replaced by a shared do_vmrg() helper dispatching to the existing gen_helper_VMRG* TCG helpers via the TRANS_FLAGS() macro, which also handles the ALTIVEC facility check. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Aboorva Devarajan Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 12 ++++++------ target/ppc/insn32.decode | 9 +++++++++ target/ppc/int_helper.c | 12 ++++++------ target/ppc/translate/vmx-impl.c.inc | 25 +++++++++++++++++++------ target/ppc/translate/vmx-ops.c.inc | 6 ------ 5 files changed, 40 insertions(+), 24 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 37803ebb17..d23260ddd0 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -174,12 +174,12 @@ DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr) DEF_HELPER_4(vcmpbfp_dot, void, env, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglb, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglh, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrglw, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghb, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghh, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_3(vmrghw, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLB, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLH, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGLW, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHB, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHH, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_FLAGS_3(VMRGHW, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESB, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESH, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VMULESW, TCG_CALL_NO_RWG, void, avr, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0fbabefba9..d9cc191de5 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -795,6 +795,15 @@ VNOR 000100 ..... ..... ..... 10100000100 = @VX VXOR 000100 ..... ..... ..... 10011000100 @VX VEQV 000100 ..... ..... ..... 11010000100 @VX =20 +## Vector Merge Instructions + +VMRGHB 000100 ..... ..... ..... 00000001100 @VX +VMRGHH 000100 ..... ..... ..... 00001001100 @VX +VMRGHW 000100 ..... ..... ..... 00010001100 @VX +VMRGLB 000100 ..... ..... ..... 00100001100 @VX +VMRGLH 000100 ..... ..... ..... 00101001100 @VX +VMRGLW 000100 ..... ..... ..... 00110001100 @VX + ## Vector Integer Average Instructions =20 VAVGSB 000100 ..... ..... ..... 10100000010 @VX diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index ef4b2e75d6..a3adf746bd 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -950,7 +950,7 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b, ppc_avr_t *c, } =20 #define VMRG_DO(name, element, access, ofs) = \ - void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) = \ + void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) = \ { = \ ppc_avr_t result; = \ int i, half =3D ARRAY_SIZE(r->element) / 2; = \ @@ -963,11 +963,11 @@ void helper_VMLADDUHM(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, ppc_avr_t *c, } =20 #define VMRG(suffix, element, access) \ - VMRG_DO(mrgl##suffix, element, access, half) \ - VMRG_DO(mrgh##suffix, element, access, 0) -VMRG(b, u8, VsrB) -VMRG(h, u16, VsrH) -VMRG(w, u32, VsrW) + VMRG_DO(MRGL##suffix, element, access, half) \ + VMRG_DO(MRGH##suffix, element, access, 0) +VMRG(B, u8, VsrB) +VMRG(H, u16, VsrH) +VMRG(W, u32, VsrW) #undef VMRG_DO #undef VMRG =20 diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 92d6e8c603..00b359f031 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -350,12 +350,25 @@ GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); -GEN_VXFORM(vmrghb, 6, 0); -GEN_VXFORM(vmrghh, 6, 1); -GEN_VXFORM(vmrghw, 6, 2); -GEN_VXFORM(vmrglb, 6, 4); -GEN_VXFORM(vmrglh, 6, 5); -GEN_VXFORM(vmrglw, 6, 6); + +static bool do_vmrg(DisasContext *ctx, arg_VX *a, + void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + helper(rd, ra, rb); + return true; +} + +TRANS_FLAGS(ALTIVEC, VMRGHB, do_vmrg, gen_helper_VMRGHB); +TRANS_FLAGS(ALTIVEC, VMRGHH, do_vmrg, gen_helper_VMRGHH); +TRANS_FLAGS(ALTIVEC, VMRGHW, do_vmrg, gen_helper_VMRGHW); +TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGLB); +TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH); +TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW); =20 static void trans_vmrgew(DisasContext *ctx) { diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index e28958a126..b8f77d3d2c 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -33,12 +33,6 @@ GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC= _NONE), GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), GEN_VXFORM_300(bcds, 0, 27), -GEN_VXFORM(vmrghb, 6, 0), -GEN_VXFORM(vmrghh, 6, 1), -GEN_VXFORM(vmrghw, 6, 2), -GEN_VXFORM(vmrglb, 6, 4), -GEN_VXFORM(vmrglh, 6, 5), -GEN_VXFORM(vmrglw, 6, 6), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 20 May 2026 16:08:18 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4F3EF20040; Wed, 20 May 2026 16:08:13 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.39.31.153]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 20 May 2026 16:08:13 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=oyA1+XBA1Cgn/zC6X gUm5M3E9TX3Vj3I5TB1Db+sLEw=; b=ShJip1M5AA0G0w/3vTVZqMES2SaarCYlZ NhSAvYLqSH1udCux8e0clj13fldtEIUjrBwnmTdzyZCOoEpcIBHnojzxWwrKhDN7 ohnc1wo4zWUM0wW06SU57rd24zM0sqzxlO8OYsyCTjOMQUkhvDHhzELbzmyKD843 cziKp09RKILWoxXJbAk/9YQcXXbShaAV6+V5JWHspYMWbRHYsLKn/y20C0qTYcfL udcn/8fkfIzAu23KdsSJfw3Liq/Rd2Jjy4Mulk0q8iSkH7orTuEq3TaAi5xj5ghN RgN2efs3V/skgDRHFkSdKbo4AQENKnGhahM8lV9wrhrhUhBSvxwMA== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 05/28] target/ppc: Move vector pack instructions to decodetree Date: Wed, 20 May 2026 21:37:05 +0530 Message-ID: <20260520160728.2283628-6-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX8FQ6ovfYM9or /Vf9gxX/dxOToEZNzd4IUuDjy/urPgmNNe2wIiI7N9kftoXN9G3jHPU9y8nC5A6uHTSdX2Gzx0S Z0AHVxOUOq9+Dmom8nxlp1wJfo9Xi4E5MpOyUzXMobn5FAHvuIrnOnCbdWSYdv0fPuhmdv/wmi0 WvQU/jbJlXP+xb3pnfRiHU/yImBscA54jWA+d+/B3WNszhHeU9T19kCf6xQ8Y0azSZtnD+x5Pvo 3gaLJdOWrw4hF3kh7kp3nTx2zXBCLRsoQCZSL5IeiXRdwXl4+5l+xwAIQ1jqRq+aDyRFlXd7/vV KziuSY31PO2nb33pR69+GmQfgq8JrrfYL2DvrKFzlrd9poT7m/dyqVm600PgoNB6LRNGG/0YkDJ 0Uc+HruAX4dH4trqNp2HreNu4NflzYjHbH4bud/rS9F9Kr00suxn6iH08WiomG74ADCvcd8adr+ szEd2vmBFQf+Fa2mOJA== X-Authority-Analysis: v=2.4 cv=Np/htcdJ c=1 sm=1 tr=0 ts=6a0ddc77 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=opJmo4g-Z6A7KFUJZoIA:9 X-Proofpoint-ORIG-GUID: -wxnOmix3ZjEMQT6CLzavL5gD0b4jmo_ X-Proofpoint-GUID: cLMud6klyqqa62eJEwrGFZRcQvlHFoFJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293367961158500 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: vpkuhum, vpkuwum, vpkuhus, vpkuwus : VX-form (PPC_ALTIVEC) vpkshus, vpkswus, vpkshss, vpkswss : VX-form (PPC_ALTIVEC) vpkpx : VX-form (PPC_ALTIVEC) vpkudum, vpkudus, vpksdus, vpksdss : VX-form (PPC2_ALTIVEC_207) The legacy GEN_VXFORM_ENV/GEN_VXFORM macros that generated gen_vpk*() functions reading register fields from ctx->opcode are replaced by new do_vpk_env()/do_vpk() helpers in vmx-impl.c.inc that use the pre-extracted decodetree argument fields (a->vrt, a->vra, a->vrb) directly. The existing gen_helper_vpk*() implementations in int_helper.c are reused without changes. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' option before and after the patch. Signed-off-by: Aboorva Devarajan Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 26 +++++++-------- target/ppc/insn32.decode | 16 +++++++++ target/ppc/int_helper.c | 28 ++++++++-------- target/ppc/translate/vmx-impl.c.inc | 51 +++++++++++++++++++++-------- target/ppc/translate/vmx-ops.c.inc | 13 -------- 5 files changed, 81 insertions(+), 53 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d23260ddd0..33bb9c9443 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -250,19 +250,19 @@ DEF_HELPER_FLAGS_4(VMSUMUBM, TCG_CALL_NO_RWG, void, a= vr, avr, avr, avr) DEF_HELPER_FLAGS_4(VMSUMMBM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VPERM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VPERMR, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) -DEF_HELPER_4(vpkshss, void, env, avr, avr, avr) -DEF_HELPER_4(vpkshus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkswss, void, env, avr, avr, avr) -DEF_HELPER_4(vpkswus, void, env, avr, avr, avr) -DEF_HELPER_4(vpksdss, void, env, avr, avr, avr) -DEF_HELPER_4(vpksdus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuhus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuwus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkudus, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuhum, void, env, avr, avr, avr) -DEF_HELPER_4(vpkuwum, void, env, avr, avr, avr) -DEF_HELPER_4(vpkudum, void, env, avr, avr, avr) -DEF_HELPER_FLAGS_3(vpkpx, TCG_CALL_NO_RWG, void, avr, avr, avr) +DEF_HELPER_4(VPKSHSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSHUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSWSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSWUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSDSS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKSDUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUHUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUWUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUDUS, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUHUM, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUWUM, void, env, avr, avr, avr) +DEF_HELPER_4(VPKUDUM, void, env, avr, avr, avr) +DEF_HELPER_FLAGS_3(VPKPX, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_5(VMHADDSHS, void, env, avr, avr, avr, avr) DEF_HELPER_5(VMHRADDSHS, void, env, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VMSUMUHM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index d9cc191de5..8c8eca5e46 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1054,6 +1054,22 @@ VSTRIHR 000100 ..... 00011 ..... . 000000110= 1 @VX_tb_rc VCLRLB 000100 ..... ..... ..... 00110001101 @VX VCLRRB 000100 ..... ..... ..... 00111001101 @VX =20 +## Vector Pack Instructions + +VPKUHUM 000100 ..... ..... ..... 0000000111 0 @VX +VPKUWUM 000100 ..... ..... ..... 0000100111 0 @VX +VPKUDUM 000100 ..... ..... ..... 1000100111 0 @VX +VPKUHUS 000100 ..... ..... ..... 0001000111 0 @VX +VPKUWUS 000100 ..... ..... ..... 0001100111 0 @VX +VPKUDUS 000100 ..... ..... ..... 1001100111 0 @VX +VPKSHUS 000100 ..... ..... ..... 0010000111 0 @VX +VPKSWUS 000100 ..... ..... ..... 0010100111 0 @VX +VPKSDUS 000100 ..... ..... ..... 1010100111 0 @VX +VPKSHSS 000100 ..... ..... ..... 0011000111 0 @VX +VPKSWSS 000100 ..... ..... ..... 0011100111 0 @VX +VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX +VPKPX 000100 ..... ..... ..... 0110000111 0 @VX + # VSX Load/Store Instructions =20 LXSD 111001 ..... ..... .............. 10 @DS diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index a3adf746bd..dc55ccadf7 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -1465,7 +1465,7 @@ void helper_VPMSUMD(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b) #else #define PKBIG 0 #endif -void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) +void helper_VPKPX(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) { int i, j; ppc_avr_t result; @@ -1488,7 +1488,7 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_avr= _t *b) } =20 #define VPK(suffix, from, to, cvt, dosat) \ - void helper_vpk##suffix(CPUPPCState *env, ppc_avr_t *r, \ + void helper_VPK##suffix(CPUPPCState *env, ppc_avr_t *r, \ ppc_avr_t *a, ppc_avr_t *b) \ { \ int i; \ @@ -1507,18 +1507,18 @@ void helper_vpkpx(ppc_avr_t *r, ppc_avr_t *a, ppc_a= vr_t *b) } \ } #define I(x, y) (x) -VPK(shss, s16, s8, cvtshsb, 1) -VPK(shus, s16, u8, cvtshub, 1) -VPK(swss, s32, s16, cvtswsh, 1) -VPK(swus, s32, u16, cvtswuh, 1) -VPK(sdss, s64, s32, cvtsdsw, 1) -VPK(sdus, s64, u32, cvtsduw, 1) -VPK(uhus, u16, u8, cvtuhub, 1) -VPK(uwus, u32, u16, cvtuwuh, 1) -VPK(udus, u64, u32, cvtuduw, 1) -VPK(uhum, u16, u8, I, 0) -VPK(uwum, u32, u16, I, 0) -VPK(udum, u64, u32, I, 0) +VPK(SHSS, s16, s8, cvtshsb, 1) +VPK(SHUS, s16, u8, cvtshub, 1) +VPK(SWSS, s32, s16, cvtswsh, 1) +VPK(SWUS, s32, u16, cvtswuh, 1) +VPK(SDSS, s64, s32, cvtsdsw, 1) +VPK(SDUS, s64, u32, cvtsduw, 1) +VPK(UHUS, u16, u8, cvtuhub, 1) +VPK(UWUS, u32, u16, cvtuwuh, 1) +VPK(UDUS, u64, u32, cvtuduw, 1) +VPK(UHUM, u16, u8, I, 0) +VPK(UWUM, u32, u16, I, 0) +VPK(UDUM, u64, u32, I, 0) #undef I #undef VPK #undef PKBIG diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 00b359f031..65230f3461 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1070,19 +1070,44 @@ TRANS(VRLQMI, do_vector_rotl_quad, false, true) =20 GEN_VXFORM_TRANS(vsl, 2, 7); GEN_VXFORM_TRANS(vsr, 2, 11); -GEN_VXFORM_ENV(vpkuhum, 7, 0); -GEN_VXFORM_ENV(vpkuwum, 7, 1); -GEN_VXFORM_ENV(vpkudum, 7, 17); -GEN_VXFORM_ENV(vpkuhus, 7, 2); -GEN_VXFORM_ENV(vpkuwus, 7, 3); -GEN_VXFORM_ENV(vpkudus, 7, 19); -GEN_VXFORM_ENV(vpkshus, 7, 4); -GEN_VXFORM_ENV(vpkswus, 7, 5); -GEN_VXFORM_ENV(vpksdus, 7, 21); -GEN_VXFORM_ENV(vpkshss, 7, 6); -GEN_VXFORM_ENV(vpkswss, 7, 7); -GEN_VXFORM_ENV(vpksdss, 7, 23); -GEN_VXFORM(vpkpx, 7, 12); +static bool do_vpk_env(DisasContext *ctx, arg_VX *a, + void (*gen_helper)(TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + gen_helper(tcg_env, rd, ra, rb); + return true; +} + +static bool do_vpk(DisasContext *ctx, arg_VX *a, + void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr ra, rb, rd; + REQUIRE_VECTOR(ctx); + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + gen_helper(rd, ra, rb); + return true; +} + +TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM) +TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM) +TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM) +TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS) +TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS) +TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS) +TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS) +TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS) +TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS) +TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS) +TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS) +TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS) +TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX) GEN_VXFORM_ENV(vsum4ubs, 4, 24); GEN_VXFORM_ENV(vsum4sbs, 4, 28); GEN_VXFORM_ENV(vsum4shs, 4, 25); diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index b8f77d3d2c..2820976c0f 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -59,19 +59,6 @@ GEN_VXFORM_300(bcdtrunc, 0, 20), GEN_VXFORM_300(bcdutrunc, 0, 21), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), -GEN_VXFORM(vpkuhum, 7, 0), -GEN_VXFORM(vpkuwum, 7, 1), -GEN_VXFORM_207(vpkudum, 7, 17), -GEN_VXFORM(vpkuhus, 7, 2), -GEN_VXFORM(vpkuwus, 7, 3), -GEN_VXFORM_207(vpkudus, 7, 19), -GEN_VXFORM(vpkshus, 7, 4), -GEN_VXFORM(vpkswus, 7, 5), -GEN_VXFORM_207(vpksdus, 7, 21), -GEN_VXFORM(vpkshss, 7, 6), -GEN_VXFORM(vpkswss, 7, 7), -GEN_VXFORM_207(vpksdss, 7, 23), -GEN_VXFORM(vpkpx, 7, 12), GEN_VXFORM(vsum4ubs, 4, 24), GEN_VXFORM(vsum4sbs, 4, 28), GEN_VXFORM(vsum4shs, 4, 25), --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293365338154100 Content-Type: text/plain; charset="utf-8" From: Utkarsh Verma Move the following store conditional instructions to decodetree specification: stbcx. : X-form sthcx. : X-form stwcx. : X-form stdcx. : X-form stqcx. : X-form The changes were verified by checking that the generated TCG ops remain semantically identical to the legacy translation, using logs captured with the -d in_asm,op flag. Signed-off-by: Utkarsh Verma Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 8 ++ target/ppc/translate.c | 103 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 84 +++++++++++++++++ 3 files changed, 92 insertions(+), 103 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 8c8eca5e46..1f363771ed 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -732,6 +732,14 @@ DSCLIQ 111111 ..... ..... ...... 001000010 . = @Z22_tap_sh_rc DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc =20 +### Store Conditional Instructions + +STBCX 011111 ..... ..... ..... 1010110110 1 @X +STHCX 011111 ..... ..... ..... 1011010110 1 @X +STWCX 011111 ..... ..... ..... 0010010110 1 @X +STDCX 011111 ..... ..... ..... 0011010110 1 @X +STQCX 011111 ..... ..... ..... 0010110110 1 @X + ## Vector Exclusive-OR-based Instructions =20 VPMSUMD 000100 ..... ..... ..... 10011001000 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ba1774a539..aeecc06477 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3153,104 +3153,6 @@ static void gen_stdat(DisasContext *ctx) } #endif =20 -static void gen_conditional_store(DisasContext *ctx, MemOp memop) -{ - TCGLabel *lfail; - TCGv EA; - TCGv cr0; - TCGv t0; - int rs =3D rS(ctx->opcode); - - lfail =3D gen_new_label(); - EA =3D tcg_temp_new(); - cr0 =3D tcg_temp_new(); - t0 =3D tcg_temp_new(); - - tcg_gen_mov_tl(cr0, cpu_so); - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, EA); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop),= lfail); - - tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, - cpu_gpr[rs], ctx->mem_idx, - DEF_MEMOP(memop) | MO_ALIGN); - tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); - tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(cr0, cr0, t0); - - gen_set_label(lfail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); - tcg_gen_movi_tl(cpu_reserve, -1); -} - -#define STCX(name, memop) \ -static void gen_##name(DisasContext *ctx) \ -{ \ - gen_conditional_store(ctx, memop); \ -} - -STCX(stbcx_, MO_UB) -STCX(sthcx_, MO_UW) -STCX(stwcx_, MO_UL) - -#if defined(TARGET_PPC64) -/* stdcx. */ -STCX(stdcx_, MO_UQ) - -/* stqcx. */ -static void gen_stqcx_(DisasContext *ctx) -{ - TCGLabel *lfail; - TCGv EA, t0, t1; - TCGv cr0; - TCGv_i128 cmp, val; - int rs =3D rS(ctx->opcode); - - if (unlikely(rs & 1)) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - lfail =3D gen_new_label(); - EA =3D tcg_temp_new(); - cr0 =3D tcg_temp_new(); - - tcg_gen_mov_tl(cr0, cpu_so); - gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, EA); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); - - cmp =3D tcg_temp_new_i128(); - val =3D tcg_temp_new_i128(); - - tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); - - /* Note that the low part is always in RS+1, even in LE mode. */ - tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); - - tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, - DEF_MEMOP(MO_128 | MO_ALIGN)); - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - tcg_gen_extr_i128_i64(t1, t0, val); - - tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); - tcg_gen_xor_tl(t0, t0, cpu_reserve_val); - tcg_gen_or_tl(t0, t0, t1); - - tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); - tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(cr0, cr0, t0); - - gen_set_label(lfail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); - tcg_gen_movi_tl(cpu_reserve, -1); -} -#endif /* defined(TARGET_PPC64) */ - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5923,14 +5825,9 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC= _STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), -GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), -GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), #endif /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index fa0191e866..91f9c6c391 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -204,6 +204,90 @@ TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_UQ) TRANS64(STQ, do_ldst_quad, true, false); TRANS64(PSTQ, do_ldst_quad_PLS_D, true); =20 +/* Store Conditional Instructions */ + +static bool do_store_cond(DisasContext *ctx, arg_X *a, MemOp mop) +{ + TCGLabel *lfail =3D gen_new_label(); + TCGv ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv cr0 =3D tcg_temp_new(); + TCGv t0 =3D tcg_temp_new(); + + tcg_gen_mov_tl(cr0, cpu_so); + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(mop), l= fail); + + tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, + cpu_gpr[a->rt], ctx->mem_idx, + DEF_MEMOP(mop) | MO_ALIGN); + tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(cr0, cr0, t0); + + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); + tcg_gen_movi_tl(cpu_reserve, -1); + return true; +} + +TRANS_FLAGS2(ATOMIC_ISA206, STBCX, do_store_cond, MO_UB); +TRANS_FLAGS2(ATOMIC_ISA206, STHCX, do_store_cond, MO_UW); +TRANS(STWCX, do_store_cond, MO_UL); +TRANS64(STDCX, do_store_cond, MO_UQ); + +static bool trans_STQCX(DisasContext *ctx, arg_STQCX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, LSQ_ISA207); +#if defined(TARGET_PPC64) + TCGLabel *lfail =3D gen_new_label(); + TCGv ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + TCGv cr0 =3D tcg_temp_new(); + TCGv_i128 cmp =3D tcg_temp_new_i128(); + TCGv_i128 val =3D tcg_temp_new_i128(); + + if (unlikely(a->rt & 1)) { + gen_invalid(ctx); + return true; + } + + tcg_gen_mov_tl(cr0, cpu_so); + gen_set_access_type(ctx, ACCESS_RES); + + tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); + + tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); + + /* Note that the low part is always in RS+1, even in LE mode. */ + tcg_gen_concat_i64_i128(val, cpu_gpr[a->rt + 1], cpu_gpr[a->rt]); + + tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + + tcg_gen_extr_i128_i64(t1, t0, val); + + tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); + tcg_gen_xor_tl(t0, t0, cpu_reserve_val); + tcg_gen_or_tl(t0, t0, t1); + + tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(cr0, cr0, t0); + + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); + tcg_gen_movi_tl(cpu_reserve, -1); +#else + qemu_build_not_reached(); +#endif + return true; +} + /* * Fixed-Point Compare Instructions */ --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=reject dis=none) header.from=linux.ibm.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779293379071611.0953376198772; Wed, 20 May 2026 09:09:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPjTo-0000aB-Om; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=f2CUa7Cc0I0t8bRtY 668ZJKc7TdvZm6CM8IWVYziE60=; b=qbZ9qWzevuPGdYiuhM7+uzXyf1k3Pu3Ht FBJntu4611rI8JKC7IRjsVn+zfE5zEOklChpkUJfGjmN2WOeUudS9uQc/QN4lfF5 QE2l8k9BcVotcuk+d/+syLTilk9kh6u/kbbOhpA60Pufg8wk30eGU7Cz0j+BEE6o aAdvDYi8uon//kMws6xmtUBoykzeizUkBfyh85DGwN5Z3t+GzJhf65E3YKTTRc+x +USLv2g3iMkp7yonS0XX1qapX7rMnvOZISPpj7PVta3YtJjGsU0gXJZo/Fo4vW3W nVuY1IYgOP9EOwPWTmQ9TsgOBNnKagOUrQIMI88OHuavyw8Zo57fA== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 07/28] target/ppc: convert slw, srw instruction via decode spec Date: Wed, 20 May 2026 21:37:07 +0530 Message-ID: <20260520160728.2283628-8-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: zVCfeTmvcgqaPQXhbMxwX2qtlPttB5wc X-Authority-Analysis: v=2.4 cv=GYMnWwXL c=1 sm=1 tr=0 ts=6a0ddc82 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=pGLkceISAAAA:8 a=VnNF1IyMAAAA:8 a=Fp1rp7siH0uluUpQqjEA:9 X-Proofpoint-ORIG-GUID: W4XITyrq5__-MQ2AL_5p9mTrqeM6NeaS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX0gqpAfj9Vwuj IOa9+7ZHiislDmwWsaJECMxBsApZ7PN1e/9Eb9e6IRZnkIM93OIqJp+HI3w1ScfBX0fvfyVr32e s2X5OlAAb90Cr449iN67ClwqkgBb6qC3YfjgEGTqKk6rZYeNn5QiMXNltuRHsdGw7YvCzBi3rKn uKrBZQtZQ3APHP9A4VDQ+m6x0LSkcdtUt7V/v59gxspriPZO5n8PPR6S2h34zdqENJYdu1o7rkq 97ZYTXd0hjzgSn9nyb/sX6ARJeLrEuaiKGyju0IEx+/LkiRhi4EHJdfrDGzf+r8sNVy/Q4pFyu+ R27OYZ4kGY8VQhA2fZLl/cLbodwgbsYgEvP+DYynBPu7mP5JXe01W/9Xgbm6NcjPU2qUJi7OSWq WTtYn0Pklh4tbLxnmb5fCQ47AzX1fyyOuktWir0+ZkhLQei797KEIhH8O6VG8S0EJGvdlHLd/9C 7maut4HKOHzxNbZF6Bw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779293381662154100 Content-Type: text/plain; charset="utf-8" From: "Mukesh Kumar Chaurasiya (IBM)" Instructions converted: - slw - srw Signed-off-by: Mukesh Kumar Chaurasiya (IBM) Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 6 +++ target/ppc/translate.c | 49 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 48 +++++++++++++++++++++ 3 files changed, 54 insertions(+), 49 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 1f363771ed..6c3f737657 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -505,6 +505,12 @@ HASHCHK 011111 ..... ..... ..... 1011110010 . = @X_DW HASHSTP 011111 ..... ..... ..... 1010010010 . @X_DW HASHCHKP 011111 ..... ..... ..... 1010110010 . @X_DW =20 +# Fixed-Point Shift Instructions + +SLW 011111 ..... ..... ..... 0000011000 . @X_rc +SRW 011111 ..... ..... ..... 1000011000 . @X_rc + + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index aeecc06477..d4f85b9be5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2315,29 +2315,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); =20 /*** Integer shift = ***/ =20 -/* slw & slw. */ -static void gen_slw(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} =20 /* sraw & sraw. */ static void gen_sraw(DisasContext *ctx) @@ -2379,30 +2356,6 @@ static void gen_srawi(DisasContext *ctx) } } =20 -/* srw & srw. */ -static void gen_srw(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x20 */ -#if defined(TARGET_PPC64) - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); - tcg_gen_sari_tl(t0, t0, 0x3f); -#else - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); - tcg_gen_sari_tl(t0, t0, 0x1f); -#endif - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - tcg_gen_ext32u_tl(t0, t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - #if defined(TARGET_PPC64) /* sld & sld. */ static void gen_sld(DisasContext *ctx) @@ -5801,10 +5754,8 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, P= PC_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), -GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), #if defined(TARGET_PPC64) GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 91f9c6c391..9d04b96316 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1406,3 +1406,51 @@ TRANS(HASHST, do_hash, false, gen_helper_HASHST) TRANS(HASHCHK, do_hash, false, gen_helper_HASHCHK) TRANS(HASHSTP, do_hash, true, gen_helper_HASHSTP) TRANS(HASHCHKP, do_hash, true, gen_helper_HASHCHKP) + +static bool trans_SLW(DisasContext *ctx, arg_SLW *a) +{ + TCGv t0, t1; + + t0 =3D tcg_temp_new(); + /* AND rt with a mask that is 0 when rB >=3D 0x20 */ +#if defined(TARGET_PPC64) + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); + tcg_gen_sari_tl(t0, t0, 0x3f); +#else + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); + tcg_gen_sari_tl(t0, t0, 0x1f); +#endif + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + t1 =3D tcg_temp_new(); + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x1f); + tcg_gen_shl_tl(cpu_gpr[a->ra], t0, t1); + tcg_gen_ext32u_tl(cpu_gpr[a->ra], cpu_gpr[a->ra]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + +static bool trans_SRW(DisasContext *ctx, arg_SRW *a) +{ + TCGv t0, t1; + + t0 =3D tcg_temp_new(); + /* AND rt with a mask that is 0 when rB >=3D 0x20 */ +#if defined(TARGET_PPC64) + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x3a); + tcg_gen_sari_tl(t0, t0, 0x3f); +#else + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x1a); + tcg_gen_sari_tl(t0, t0, 0x1f); +#endif + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + tcg_gen_ext32u_tl(t0, t0); + t1 =3D tcg_temp_new(); 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b=H18EbgmznK2f83vn5IMfdD6pOsi/TA2oU +2HOwu2YA8sA/l2rxEaQ92EG47lxRhBRkEXKoocf0CkSKdIO5GyyhyCQlv28JMRd sWy2pQXP+WW0Unex1mvpX6RyR4/1Ci+6jj6LXNgQPmBXhEYBC9i8HeszqT6a54H6 Adi4s10JRFmtsuEcTf4A0zTSRRN2RYRMyBKbL0CP+H++UtVFra6HopQ8h18gmdLW BelOlm0zcsLo51vzf7gLysNbd5ia0p0FHkzigqjVo7npt1zIJLChhMSZM0J/tWBC 4K7IEifK7UWCxwIQJEXYxE0WxMviYnpGh4HmOBWZMcQ2PeOcLJNSQ== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 08/28] target/ppc: convert sraw[i] instruction via decode spec Date: Wed, 20 May 2026 21:37:08 +0530 Message-ID: <20260520160728.2283628-9-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX1BNRJU2i3Ktc Nx6uJGwVNe2Gw1/Sr8tWxA+WNMkayUO0oEvQ5HRjthEhwhigJz34mtzE7Nb21EiAw2dw2+jAbYW QsSPcA4x/NiN+jlHv3W8rvb7uziT0XB5cCjC4GSQFcwTVymrYk8AVpB6rcdgPmE/e61EJz435Ae YpkRnRMtLZFsyVGN8dAK33cjXhBeEWy65SdvRpD63tCuhiwC73TjDx7i5pmukY4MMCkg/ym7Wnk w6lP+T5C30LHrvIXpg10COP6PJ/tW7NVjczG6Pe0ugerNZij99EwC2FzY9A4gFCk81Vq1zcVPGa eCW2L91jxSq7pcjW2iTikdKBZAYDxopD2qZ9FvIjz/MRtmJiVIxXqYQ1s2tA56VHsgleDRBkx8v soegzwWzbd9tY9ZrmwXmzWzWuUX/G0e64rp+3diUfbG58pFeWdNsBng1QBr2mKpVxrBh+nc0uDZ LUumYMUmz+F3ncFkEmg== X-Proofpoint-GUID: m4EaB5kLJCDzxwYRvYHkV6TVdl39vl33 X-Proofpoint-ORIG-GUID: U8dMITywmj08jl36B6HUBG_WEMNvj5d_ X-Authority-Analysis: v=2.4 cv=aYBRWxot c=1 sm=1 tr=0 ts=6a0ddc89 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=pGLkceISAAAA:8 a=VnNF1IyMAAAA:8 a=8vnlzkHpZUhk_GZ0CsoA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293414143154100 Content-Type: text/plain; charset="utf-8" From: "Mukesh Kumar Chaurasiya (IBM)" Instruction converted: - sraw - srawi Signed-off-by: Mukesh Kumar Chaurasiya (IBM) Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 2 +- target/ppc/insn32.decode | 6 ++-- target/ppc/int_helper.c | 2 +- target/ppc/translate.c | 42 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 41 +++++++++++++++++++++ 5 files changed, 47 insertions(+), 46 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 33bb9c9443..d5283344ba 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -65,7 +65,7 @@ DEF_HELPER_4(DIVWE, tl, env, tl, tl, i32) =20 DEF_HELPER_FLAGS_1(POPCNTB, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(CMPB, TCG_CALL_NO_RWG_SE, tl, tl, tl) -DEF_HELPER_3(sraw, tl, env, tl, tl) +DEF_HELPER_3(SRAW, tl, env, tl, tl) DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 6c3f737657..dd80a25472 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -507,8 +507,10 @@ HASHCHKP 011111 ..... ..... ..... 1010110010 . = @X_DW =20 # Fixed-Point Shift Instructions =20 -SLW 011111 ..... ..... ..... 0000011000 . @X_rc -SRW 011111 ..... ..... ..... 1000011000 . @X_rc +SLW 011111 ..... ..... ..... 0000011000 . @X_rc +SRAW 011111 ..... ..... ..... 1100011000 . @X_rc +SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc +SRW 011111 ..... ..... ..... 1000011000 . @X_rc =20 =20 ## BCD Assist diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index dc55ccadf7..b161f930ec 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -235,7 +235,7 @@ target_ulong helper_CMPB(target_ulong rs, target_ulong = rb) } =20 /* shift right arithmetic helper */ -target_ulong helper_sraw(CPUPPCState *env, target_ulong value, +target_ulong helper_SRAW(CPUPPCState *env, target_ulong value, target_ulong shift) { int32_t ret; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d4f85b9be5..c9d04b4a3c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2316,46 +2316,6 @@ GEN_PPC64_R4(rldimi, 0x1E, 0x06); /*** Integer shift = ***/ =20 =20 -/* sraw & sraw. */ -static void gen_sraw(DisasContext *ctx) -{ - gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - -/* srawi & srawi. */ -static void gen_srawi(DisasContext *ctx) -{ - int sh =3D SH(ctx->opcode); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - if (sh =3D=3D 0) { - tcg_gen_ext32s_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_movi_tl(cpu_ca32, 0); - } - } else { - TCGv t0; - tcg_gen_ext32s_tl(dst, src); - tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_mov_tl(cpu_ca32, cpu_ca); - } - tcg_gen_sari_tl(dst, dst, sh); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - #if defined(TARGET_PPC64) /* sld & sld. */ static void gen_sld(DisasContext *ctx) @@ -5754,8 +5714,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PP= C_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), -GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), #if defined(TARGET_PPC64) GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 9d04b96316..234404e459 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1454,3 +1454,44 @@ static bool trans_SRW(DisasContext *ctx, arg_SRW *a) } return true; } + +/* sraw & sraw. */ +static bool trans_SRAW(DisasContext *ctx, arg_SRAW *a) +{ + gen_helper_SRAW(cpu_gpr[a->ra], tcg_env, + cpu_gpr[a->rt], cpu_gpr[a->rb]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } + return true; +} + +/* srawi & srawi. */ +static bool trans_SRAWI(DisasContext *ctx, arg_SRAWI *a) +{ + TCGv dst =3D cpu_gpr[a->ra]; + TCGv src =3D cpu_gpr[a->rt]; + if (a->rb =3D=3D 0) { + tcg_gen_ext32s_tl(dst, src); + tcg_gen_movi_tl(cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_movi_tl(cpu_ca32, 0); + } + } else { + TCGv t0; + tcg_gen_ext32s_tl(dst, src); + tcg_gen_andi_tl(cpu_ca, dst, (1ULL << a->rb) - 1); + t0 =3D tcg_temp_new(); + tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } + tcg_gen_sari_tl(dst, dst, a->rb); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, dst); + } + return true; +} --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 20 May 2026 16:08:42 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A723020040; Wed, 20 May 2026 16:08:36 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.39.31.153]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 20 May 2026 16:08:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=fQRqzWfQu0MuWyVCj uoQtVymyiJIMZ2VEAgetY75isM=; b=Lh7vsqbWL+LkmuOlWU/iCclRAmsaCGg0F p1q+sqPy1avl8m+h7DkpYH3URUh/TMneJ9ttNM7zw1jVxUBgBevjJcAp/DQJb6nw /4xC44dqOq/lpAE3RrK3n0cdmk0y3LxRRbBuggmweNU4ytGR1QC5xwsi1RwnWSbO TfkR+0+sUfHXp5EPIpraObeGHESDI7YLOqo+5onEsc+Xq3fJwW3uHJix3jw7nut4 itviYyTIvphIpmdM9waudvM9upotfgWcXwDcfAfqv4kJYbokHhJ5Vj9A6R4rH5QR wVRpkuZ3QWSeJ8N+rnFzAs56FVoMox4BC3bxUadHqZKwaGTFOu5kA== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 09/28] target/ppc : Convert mcrf to decode tree Date: Wed, 20 May 2026 21:37:09 +0530 Message-ID: <20260520160728.2283628-10-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=ffCdDUQF c=1 sm=1 tr=0 ts=6a0ddc8f cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=vy6McjWATDkKsZsaVXEA:9 X-Proofpoint-ORIG-GUID: 2NG37qJ6cNz5h5qo6gVz0fvg6VUg-vlN X-Proofpoint-GUID: 0Q92y532vGHmphFFp_v0vWvHPN2nuzXj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX9usWDX2U3t89 VsMaSqFEBxvctDpcZG2WlU0JEcJY5NdOS0AGIU2DNZKFkg5a3Rcopss/EKIpiYKVf2NoynFvDFG 8KNLWJ0l+MD7f/xlKMC2m7AAZtUruK1HbtuwAAXQhJ4aVV0C1yPh7cnIKZjz/g806gInT42Oq92 VV6siuXbDAQIAswEfNDPV8FUG86B6NrEtfknp+Bcobhaz4W9ZgUWKTO38Z6+akgvlFhJkY/678p ggLXvGGYNNagx7+sl7JUCrgxTUJGkddJW/r7lx3yqAuix2roqRw0z/fSIETOGqUqo9OQH/TMFkZ //3xEwHsXpRhxoy8sZVe12zAsa+9kSK7SB/s7seEULMXGRQBUC2jjF/nXVcvI4yqxEE91jucRs3 1Umao3w9IPkuHYSkMnIiVrHPwEjyz8lI8u1uoTkafEfwOfbvlqnP74lDGqQ1fggAA7F6W7ayVkl X5Jmcp2oasFwl63uPRg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293485292154100 Content-Type: text/plain; charset="utf-8" From: Shivani Nittor Convert mcrf to decode tree specification.The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb. Signed-off-by: Shivani Nittor Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 6 ++++++ target/ppc/translate.c | 7 ------- target/ppc/translate/misc-impl.c.inc | 6 ++++++ 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index dd80a25472..db6e9418f3 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1445,6 +1445,12 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - =20 +# Condition Register Field Instruction + +&XL_bfa bf bfa +@XL_bfa ...... bf:3 .. bfa:3 .. ..... ..... ..... . +MCRF 010011 ... -- ... -- ----- 00000 00000 - @XL_bfa + # Branch History Rolling Buffer (BHRB) Instructions =20 &XFX_bhrbe rt bhrbe diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c9d04b4a3c..5be508fcb1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3642,12 +3642,6 @@ GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); /* crxor */ GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); =20 -/* mcrf */ -static void gen_mcrf(DisasContext *ctx) -{ - tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]= ); -} - /*** System linkage = ***/ =20 /* rfi (supervisor only) */ @@ -5746,7 +5740,6 @@ GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLO= W), GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_IS= A207), -GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index cbf82b1ea0..890fbb209e 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -155,3 +155,9 @@ static bool trans_ATTN(DisasContext *ctx, arg_ATTN *a) return false; #endif } + +static bool trans_MCRF(DisasContext *ctx, arg_MCRF *a) +{ + tcg_gen_mov_i32(cpu_crf[a->bf], cpu_crf[a->bfa]); + return true; +} --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293437; cv=none; d=zohomail.com; s=zohoarc; b=jkvJYEySoGGy1/Xkeio4Pnv5uNxMJMEOroRMBiAEujdJbBkcG4m8CBfon3zH1o5vckW5U0RD3MfwtQ2yMVgf8sdRxQvS7nwyO1QwIilzz9zGy3KR8gkB1qEK28PH2OLsIu/p0sc93Oqp1e21LmeTA1uzxLzyOjLFTlf/BdF7r7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779293437; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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b=ew4RK9QOJE9g8bG4l56yp+STcbSzRWdfz wHOYlMskAXKY5aaiaIlt6PYlS7k9CQ4cN90LiL91v7n3doWElBjMvbBEF6iS04A1 PnBZi8g6C0Kw0b3q068Cp3MTudZ2FpH/hDxz0EyVMW8wODX87WwmsHjGibgFgk4I sQhL+gL3lzol2jGXsKxopDgV5797Zubtp45rAVJ180cvXJfsTFLLtCeqIN8H4NSO G0qnibcp59Ca3p3r2pV86Pf+Xwctfxn64QN8m223Z+ieFjkn3MVca6BZEqNsHOKV yNA2rLh1PuYHOzs+BIw54eTIt2TqCzFCoFC8qdCdLEq2JDB8x9W0A== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 10/28] target/ppc: Move fixed-point Shift insns to decodetree Date: Wed, 20 May 2026 21:37:10 +0530 Message-ID: <20260520160728.2283628-11-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: U7Q0cTmPRhTd9-h4L3WsE8Z5l_hgyGaI X-Authority-Analysis: v=2.4 cv=GYMnWwXL c=1 sm=1 tr=0 ts=6a0ddc96 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=70_TU0wQgaf75xgqATAA:9 X-Proofpoint-ORIG-GUID: psDh1EveIHwX6jHfFGW8GFpGBOlbaoJV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX6gFQ/sjZydGl JwKB4POQlv+Ep8csMxLsIOsg8nwMuVcmszunhBWEIXdrUmoI0YkdI3IrnaTKaSjve7Dky6wP//N eZ/bgFd6ABqdVto8+v37riXt7d4ubtnpU2Y+FbmVyTMbPYVnuDENto08llcmQCJTzYv8FdAwOkp QY1kwSPQRk3/oRYVjw6v7yHcJS1FBuGU4pIfZzgYiEVZqXuDhteOD1nEQLWqGoq1j9tZqHXfKPu +yEmrSmBLHCznjsBpqkYUIBBQJ6Zp8xldOd4B3cMOiHz8lVtYvfZHoW4NO/qSB87KtQuKPpA5Xz Nz+criAY6liG2upHKlHsvFZ3/QfLMeTMKLWApB7Lr/3HlOVa98ijHgRB9L6ojy99kcAzl1gbQTK I1Gf4fUucIt5YfDH2gUxa5wlARM8ONB1GQvEjWmf9Mt5NRC7ohS7kf1SHsPaA9aWjga6OskOf4u rQc/eECfSZxL8aByk+g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 clxscore=1011 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293438539154100 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Move the below instructions to decodetree specification: s{r,l}d, and srad[i] : X-form The changes were verified by validating that the TCG ops generated by these instructions remain the same after these changes. The TCG micro-ops were captured with the '-d op,in_asm' QEMU flag. Move all shift insntructions to one place in insn32.decode Signed-off-by: Sathvika Vasireddy Signed-off-by: Amit Machhiwal Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 2 +- target/ppc/insn32.decode | 11 ++- target/ppc/int_helper.c | 2 +- target/ppc/translate.c | 96 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 72 ++++++++++++++++ 5 files changed, 81 insertions(+), 102 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d5283344ba..f267c0d2b8 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -75,7 +75,7 @@ DEF_HELPER_FLAGS_1(CBCDTD, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(CMPEQB, TCG_CALL_NO_RWG_SE, i32, tl, tl) DEF_HELPER_FLAGS_1(POPCNTW, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(BPERMD, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_3(srad, tl, env, tl, tl) +DEF_HELPER_3(SRAD, tl, env, tl, tl) DEF_HELPER_FLAGS_0(DARN32, TCG_CALL_NO_RWG, tl) DEF_HELPER_FLAGS_0(DARN64, TCG_CALL_NO_RWG, tl) #endif diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index db6e9418f3..44ef814fb9 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -119,7 +119,7 @@ =20 # XS-form with fractured shift amount %xs_sh 1:1 11:5 -&XS rs ra sh rc +&XS rs ra sh rc:bool @XS ...... rs:5 ra:5 ..... ......... . rc:1 &XS sh=3D%= xs_sh =20 %x_frtp 22:4 !function=3Dtimes_2 @@ -512,6 +512,12 @@ SRAW 011111 ..... ..... ..... 1100011000 . = @X_rc SRAWI 011111 ..... ..... ..... 1100111000 . @X_rc SRW 011111 ..... ..... ..... 1000011000 . @X_rc =20 +SLD 011111 ..... ..... ..... 0000011011 . @X_rc +SRD 011111 ..... ..... ..... 1000011011 . @X_rc +SRAD 011111 ..... ..... ..... 1100011010 . @X_rc +SRADI 011111 ..... ..... ..... 110011101 . . @XS + +EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 ## BCD Assist =20 @@ -1372,9 +1378,6 @@ DST 011111 ..... ..... ..... 0101010110 -= @X DSTST 011111 ..... ..... ..... 0101110110 - @X DSS 011111 ..... ..... ..... 1100110110 - @X =20 -##Extend Sign Word and Shift Left Immediate XS-form -EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS - ## Load and Reserve Instructions LBARX 011111 ..... ..... ..... 0000110100 . @X_rc LHARX 011111 ..... ..... ..... 0001110100 . @X_rc diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index b161f930ec..8e8076a92c 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -261,7 +261,7 @@ target_ulong helper_SRAW(CPUPPCState *env, target_ulong= value, } =20 #if defined(TARGET_PPC64) -target_ulong helper_srad(CPUPPCState *env, target_ulong value, +target_ulong helper_SRAD(CPUPPCState *env, target_ulong value, target_ulong shift) { int64_t ret; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5be508fcb1..1fc2cd0b14 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2313,95 +2313,6 @@ static void gen_rldimi(DisasContext *ctx, int mbn, i= nt shn) GEN_PPC64_R4(rldimi, 0x1E, 0x06); #endif =20 -/*** Integer shift = ***/ - - -#if defined(TARGET_PPC64) -/* sld & sld. */ -static void gen_sld(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} - -/* srad & srad. */ -static void gen_srad(DisasContext *ctx) -{ - gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, - cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} -/* sradi & sradi. */ -static inline void gen_sradi(DisasContext *ctx, int n) -{ - int sh =3D SH(ctx->opcode) + (n << 5); - TCGv dst =3D cpu_gpr[rA(ctx->opcode)]; - TCGv src =3D cpu_gpr[rS(ctx->opcode)]; - if (sh =3D=3D 0) { - tcg_gen_mov_tl(dst, src); - tcg_gen_movi_tl(cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_movi_tl(cpu_ca32, 0); - } - } else { - TCGv t0; - tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); - t0 =3D tcg_temp_new(); - tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); - tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); - if (is_isa300(ctx)) { - tcg_gen_mov_tl(cpu_ca32, cpu_ca); - } - tcg_gen_sari_tl(dst, src, sh); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, dst); - } -} - -static void gen_sradi0(DisasContext *ctx) -{ - gen_sradi(ctx, 0); -} - -static void gen_sradi1(DisasContext *ctx) -{ - gen_sradi(ctx, 1); -} - -/* srd & srd. */ -static void gen_srd(DisasContext *ctx) -{ - TCGv t0, t1; - - t0 =3D tcg_temp_new(); - /* AND rS with a mask that is 0 when rB >=3D 0x40 */ - tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); - tcg_gen_sari_tl(t0, t0, 0x3f); - tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); - t1 =3D tcg_temp_new(); - tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); - tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); - } -} -#endif - /*** Addressing modes = ***/ /* Register indirect with immediate index : EA =3D (rA|0) + SIMM */ static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, @@ -5708,13 +5619,6 @@ GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, P= PC_NONE, PPC2_ISA300), GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -#if defined(TARGET_PPC64) -GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), -GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), -GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), -GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), -GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), -#endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 234404e459..9f669894a3 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -486,6 +486,76 @@ static bool do_add_const_XO(DisasContext *ctx, arg_XO_= ta *a, TCGv const_val, return true; } =20 +static bool do_shift_X_rc(DisasContext *ctx, arg_X_rc *a, + void(*op)(TCGv, TCGv, TCGv)) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + /* AND rt with a mask that is 0 when rb >=3D 0x40 */ + tcg_gen_shli_tl(t0, cpu_gpr[a->rb], 0x39); + tcg_gen_sari_tl(t0, t0, 0x3f); + tcg_gen_andc_tl(t0, cpu_gpr[a->rt], t0); + tcg_gen_andi_tl(t1, cpu_gpr[a->rb], 0x3f); + op(cpu_gpr[a->ra], t0, t1); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_SRAD(DisasContext *ctx, arg_SRAD *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + gen_helper_SRAD(cpu_gpr[a->ra], tcg_env, cpu_gpr[a->rt], cpu_gpr[a->rb= ]); + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, cpu_gpr[a->ra]); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_SRADI(DisasContext *ctx, arg_SRADI *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + int sh =3D a->sh; + TCGv dst =3D cpu_gpr[a->ra]; + TCGv src =3D cpu_gpr[a->rs]; + if (sh =3D=3D 0) { + tcg_gen_mov_tl(dst, src); + tcg_gen_movi_tl(cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_movi_tl(cpu_ca32, 0); + } + } else { + TCGv t0 =3D tcg_temp_new(); + tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); + tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(cpu_ca, cpu_ca, t0); + tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); + if (is_isa300(ctx)) { + tcg_gen_mov_tl(cpu_ca32, cpu_ca); + } + tcg_gen_sari_tl(dst, src, sh); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, dst); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + TRANS(ADD, do_add_XO, false, false); TRANS(ADDC, do_add_XO, false, true); TRANS(ADDE, do_add_XO, true, true); @@ -493,6 +563,8 @@ TRANS(ADDME, do_add_const_XO, tcg_constant_tl(-1LL), tr= ue, true); TRANS(ADDZE, do_add_const_XO, tcg_constant_tl(0), true, true); TRANS(ADDIC, do_add_D, false, true, false, false); TRANS(ADDIC_, do_add_D, false, true, false, true); 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b=WJr3RW+QwDVKkRAJTb9TAsbyobYYLXQ4N OArSvnDJXv6UPtke5FlHxNn8L8V9YFmYqcbpFZP9x7Cx/WJ9/OuaSwGeNM1T1mNf J4G2J6u/Fn8sxAeF0oaxUA/wSkf4zbx5HZyY5dk+CLYbttjH/Zj6RGcBL4hSDCBt a/VVwtr60gHgSNsva8jRnBS4oSFk2g+4SrZfTX82Gm/ALTa4G4OYk7veqNJqCA4A ZypzGDI/Wd3ZD6drkUrEXB3PV9DXZqHgZ3pZBMsR3IHzUM1desvMVBZtuTOGWqOV Oi6xYWzBOw4GnUAt1st3A9e5wPBQWa9puurtzAv06/GpGluqM2yrw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 11/28] target/ppc: Move fixed-point byte-reversal store insns to decodetree Date: Wed, 20 May 2026 21:37:11 +0530 Message-ID: <20260520160728.2283628-12-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX2QMzSsLzGdCA 1GEOtU7drYJxB6J5vXis3m/u6oYsrr2uiNDXD/X6hZP3sIgpRkDF0lMmtRKY5fhUGmhfNLMEvE8 V76RaNDwI5R3nXS4M8BMPdVlcKFsmrha5vsFLD0SrDRR/mVUic3fYuCGU2+z4lleu8jcBLh2ZHL mre/dcrlrZZGh+QWdsQzPloaBzmUac0D2savOBvIGv8LSk1PsvHDl5zY8ndjFxCmbFCUXjgZJTN noJykBf2IcqrBtJCaNCTHAwp6mv1GUEMzEvrtT2PfuDP168WPvhUnadRSF/YBfQhu5fnGfA5tIt deFzieV5y8WVYLvcUObYHFPiqMk05q/EzEkPjSuuNv8kEYT6HfE/ITfcarj/7flmk2mOt16frXM ZA98+4iWIoojj8lM/d9FkHuPVAgablguj6m3CSEul4PqODpZ5XcV9iha1ktwuX5ee/wPbAUTNdS MAVLO9VtWIvkA8hqd1g== X-Authority-Analysis: v=2.4 cv=BNuDalQG c=1 sm=1 tr=0 ts=6a0ddc9c cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=XjGAUUzDke6TOz208osA:9 X-Proofpoint-ORIG-GUID: Phv08FueONo2eApoaal9e5ryx6DcuJql X-Proofpoint-GUID: ZNW_mcknPYW4u9570PBXVuaClZHaH8aJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293437200158500 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal Move the below PPC instructions to decodetree specification: st{d,h,w}brx, st{d,w,h,b}cix : X-form The changes were verified by validating that the TCG micro-ops generated by those insns remain the same. These TCG micro-ops were captured with the `-d op,in_asm` QEMU flag. Additionally, remove GEN_TX and GEN_STX_E macros as they are no longer used anywhere else. Signed-off-by: Amit Machhiwal Signed-off-by: Chinmay Rath [cr: ppc32 build fix, EA calc fix] --- target/ppc/insn32.decode | 8 +++ target/ppc/translate.c | 52 +++----------- target/ppc/translate/fixedpoint-impl.c.inc | 79 ++++++++++++++++++++++ 3 files changed, 95 insertions(+), 44 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 44ef814fb9..4a28fad64b 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -372,6 +372,14 @@ STVDX 011111 ..... ..... ..... 0010010001 - = @X STSKU 111110 ..... ..... ............. 0 11 @DD STCXU 111110 ..... ..... ............. 1 11 @DD =20 +STDBRX 011111 ..... ..... ..... 1010010100 - @X +STDCIX 011111 ..... ..... ..... 1111110101 - @X +STWCIX 011111 ..... ..... ..... 1110010101 - @X +STHCIX 011111 ..... ..... ..... 1110110101 - @X +STBCIX 011111 ..... ..... ..... 1111010101 - @X +STHBRX 011111 ..... ..... ..... 1110010110 - @X +STWBRX 011111 ..... ..... ..... 1010010110 - @X + ### Fixed-Point Compare Instructions =20 CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1fc2cd0b14..7bfbba85d0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2529,23 +2529,6 @@ GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) #endif =20 -/*** Integer store = ***/ -#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ -static void glue(gen_, name##x)(DisasContext *ctx) = \ -{ = \ - TCGv EA; = \ - chk(ctx); = \ - gen_set_access_type(ctx, ACCESS_INT); = \ - EA =3D tcg_temp_new(); = \ - gen_addr_reg_index(ctx, EA); = \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); = \ -} -#define GEN_STX(name, stop, opc2, opc3, type) = \ - GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) - -#define GEN_STX_HVRM(name, stop, opc2, opc3, type) = \ - GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) - #define GEN_STEPX(name, stop, opc2, opc3) = \ static void glue(gen_, name##epx)(DisasContext *ctx) = \ { = \ @@ -2565,12 +2548,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) #endif =20 -#if defined(TARGET_PPC64) -GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) -GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) -GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) -GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) -#endif /*** Integer load and store with byte reverse = ***/ =20 /* lhbrx */ @@ -2582,15 +2559,8 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); #if defined(TARGET_PPC64) /* ldbrx */ GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); -/* stdbrx */ -GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); #endif /* TARGET_PPC64 */ =20 -/* sthbrx */ -GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); -/* stwbrx */ -GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); - /*** Integer load and store multiple = ***/ =20 /* lmw */ @@ -5117,9 +5087,17 @@ static int64_t dw_compose_ea(DisasContext *ctx, int = x) return true; \ } \ } while (0) +#define REQUIRE_HVRM(CTX) \ + do { \ + if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ + gen_priv_opc(CTX); \ + return true; \ + } \ + } while (0) #else #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) +#define REQUIRE_HVRM(CTX) do { gen_priv_opc(CTX); return true; } while (0) #endif =20 /* @@ -5791,20 +5769,6 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) #endif =20 -#undef GEN_STX_E -#define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) = \ -GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), - -#if defined(TARGET_PPC64) -GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) -GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) -GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) -GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) -GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) -#endif -GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) -GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) - #undef GEN_STEPX #define GEN_STEPX(name, ldop, opc2, opc3) = \ GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, = \ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 9f669894a3..25a60d3d3a 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -566,6 +566,85 @@ TRANS(ADDIC_, do_add_D, false, true, false, true); TRANS(SLD, do_shift_X_rc, tcg_gen_shl_tl); TRANS(SRD, do_shift_X_rc, tcg_gen_shr_tl); =20 +static bool do_stxx(DisasContext *ctx, arg_X *a, + void(*op)(DisasContext *, TCGv, TCGv), bool is_hvrm) +{ + TCGv ea; + + if (is_hvrm) { + REQUIRE_HVRM(ctx); + } + + gen_set_access_type(ctx, ACCESS_INT); + ea =3D do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); + op(ctx, cpu_gpr[a->rt], ea); + + return true; +} + +TRANS(STHBRX, do_stxx, gen_qemu_st16r, 0); +TRANS(STWBRX, do_stxx, gen_qemu_st32r, 0); + +static bool trans_STDBRX(DisasContext *ctx, arg_STDBRX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, DBRX); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st64r_i64, false); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STDCIX(DisasContext *ctx, arg_STDCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st64_i64, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STWCIX(DisasContext *ctx, arg_STWCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st32, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STHCIX(DisasContext *ctx, arg_STHCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st16, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STBCIX(DisasContext *ctx, arg_STBCIX *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS(ctx, CILDST); +#if defined(TARGET_PPC64) + return do_stxx(ctx, a, gen_qemu_st8, true); +#else + qemu_build_not_reached(); +#endif + return true; +} + static bool trans_SUBFIC(DisasContext *ctx, arg_D *a) { gen_op_arith_subf(ctx, cpu_gpr[a->rt], cpu_gpr[a->ra], --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293546788158500 Content-Type: text/plain; charset="utf-8" From: Aboorva Devarajan Move below instructions to decodetree specification: lwat, stwat : X-form (word atomic, ISA 3.0) ldat, stdat : X-form (doubleword atomic, ISA 3.0) The legacy gen_ld_atomic()/gen_st_atomic() functions that read register fields and the function code from ctx->opcode are replaced by new do_ld_atomic()/do_st_atomic() helpers in fixedpoint-impl.c.inc that use the pre-extracted decodetree argument fields (a->rt, a->ra, a->rb) directly. The RB field carries the Function Code (FC) selecting the atomic operation. gen_fetch_inc_conditional() is similarly moved and refactored to accept the destination register number as an explicit parameter instead of extracting it from ctx->opcode. Checked with '-d in_asm,op'. The printed TCG ops may differ from the pre-refactor log because EA now uses do_ea_calc(ctx, ra, 0), which lowers as GPR[ra] + 0 (then narrow in 32-bit mode) instead of mov/ext32u from ra alone. Signed-off-by: Aboorva Devarajan Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 7 + target/ppc/translate.c | 212 -------------------- target/ppc/translate/fixedpoint-impl.c.inc | 215 +++++++++++++++++++++ 3 files changed, 222 insertions(+), 212 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 4a28fad64b..f35f7113a0 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -343,6 +343,13 @@ LSKU 111010 ..... ..... ............. 0 11 = @DD LCXU 111010 ..... ..... ............. 1 11 @DD =20 =20 +### Fixed-Point Atomic Load/Store Instructions + +LWAT 011111 ..... ..... ..... 1001000110 - @X +STWAT 011111 ..... ..... ..... 1011000110 - @X +LDAT 011111 ..... ..... ..... 1001100110 - @X +STDAT 011111 ..... ..... ..... 1011100110 - @X + ### Fixed-Point Store Instructions =20 STB 100110 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7bfbba85d0..2345bf8867 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2741,212 +2741,6 @@ static void gen_isync(DisasContext *ctx) ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } =20 -static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, - TCGv EA, TCGCond cond, int addend) -{ - TCGv t =3D tcg_temp_new(); - TCGv t2 =3D tcg_temp_new(); - TCGv u =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(t2, EA, memop_size(memop)); - tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); - tcg_gen_addi_tl(u, t, addend); - - /* E.g. for fetch and increment bounded... */ - /* mem(EA,s) =3D (t !=3D t2 ? u =3D t + 1 : t) */ - tcg_gen_movcond_tl(cond, u, t, t2, u, t); - tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); - - /* RT =3D (t !=3D t2 ? t : u =3D 1<<(s*8-1)) */ - tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, - tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); -} - -static void gen_ld_atomic(DisasContext *ctx, MemOp memop) -{ - uint32_t gpr_FC =3D FC(ctx->opcode); - TCGv EA =3D tcg_temp_new(); - int rt =3D rD(ctx->opcode); - bool need_serial; - TCGv src, dst; - - gen_addr_register(ctx, EA); - dst =3D cpu_gpr[rt]; - src =3D cpu_gpr[(rt + 1) & 31]; - - need_serial =3D false; - memop |=3D MO_ALIGN; - switch (gpr_FC) { - case 0: /* Fetch and add */ - tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 1: /* Fetch and xor */ - tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 2: /* Fetch and or */ - tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 3: /* Fetch and 'and' */ - tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 4: /* Fetch and max unsigned */ - tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 5: /* Fetch and max signed */ - tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 6: /* Fetch and min unsigned */ - tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 7: /* Fetch and min signed */ - tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); - break; - case 8: /* Swap */ - tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); - break; - - case 16: /* Compare and swap not equal */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); - if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D = 32) { - tcg_gen_mov_tl(t1, src); - } else { - tcg_gen_ext32u_tl(t1, src); - } - tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, - cpu_gpr[(rt + 2) & 31], t0); - tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); - tcg_gen_mov_tl(dst, t0); - } - break; - - case 24: /* Fetch and increment bounded */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); - } - break; - case 25: /* Fetch and increment equal */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); - } - break; - case 28: /* Fetch and decrement bounded */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - need_serial =3D true; - } else { - gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); - } - break; - - default: - /* invoke data storage error handler */ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); - } - - if (need_serial) { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(tcg_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } -} - -static void gen_lwat(DisasContext *ctx) -{ - gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); -} - -#ifdef TARGET_PPC64 -static void gen_ldat(DisasContext *ctx) -{ - gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); -} -#endif - -static void gen_st_atomic(DisasContext *ctx, MemOp memop) -{ - uint32_t gpr_FC =3D FC(ctx->opcode); - TCGv EA =3D tcg_temp_new(); - TCGv src, discard; - - gen_addr_register(ctx, EA); - src =3D cpu_gpr[rD(ctx->opcode)]; - discard =3D tcg_temp_new(); - - memop |=3D MO_ALIGN; - switch (gpr_FC) { - case 0: /* add and Store */ - tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 1: /* xor and Store */ - tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 2: /* Or and Store */ - tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 3: /* 'and' and Store */ - tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); - break; - case 4: /* Store max unsigned */ - tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 5: /* Store max signed */ - tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 6: /* Store min unsigned */ - tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 7: /* Store min signed */ - tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); - break; - case 24: /* Store twin */ - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(tcg_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } else { - TCGv t =3D tcg_temp_new(); - TCGv t2 =3D tcg_temp_new(); - TCGv s =3D tcg_temp_new(); - TCGv s2 =3D tcg_temp_new(); - TCGv ea_plus_s =3D tcg_temp_new(); - - tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); - tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); - tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); - tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); - tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); - tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); - tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); - } - break; - default: - /* invoke data storage error handler */ - gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); - } -} - -static void gen_stwat(DisasContext *ctx) -{ - gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); -} - -#ifdef TARGET_PPC64 -static void gen_stdat(DisasContext *ctx) -{ - gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); -} -#endif - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5608,12 +5402,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_= STRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), -GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), -#if defined(TARGET_PPC64) -GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), -#endif /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 25a60d3d3a..4d35133adc 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1646,3 +1646,218 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAW= I *a) } return true; } + +static void do_fetch_inc_conditional(DisasContext *ctx, MemOp memop, + TCGv EA, int rt, + TCGCond cond, int addend) +{ + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv u =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(t2, EA, memop_size(memop)); + tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); + tcg_gen_addi_tl(u, t, addend); + + /* mem(EA,s) =3D (t cond t2 ? u =3D t + addend : t) */ + tcg_gen_movcond_tl(cond, u, t, t2, u, t); + tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); + + /* RT =3D (t cond t2 ? t : 1<<(s*8-1)) */ + tcg_gen_movcond_tl(cond, cpu_gpr[rt], t, t2, t, + tcg_constant_tl(1 << (memop_size(memop) * 8 - 1))); +} + +/* + * Fixed-Point Atomic Load/Store Instructions + * + * In the X-form encoding the RB field carries the Function Code (FC) + * that selects the atomic operation. EA is computed from RA alone. + */ +static bool do_ld_atomic(DisasContext *ctx, arg_X *a, MemOp memop) +{ + TCGv EA, dst, src; + bool need_serial; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + EA =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(0)); + dst =3D cpu_gpr[a->rt]; + src =3D cpu_gpr[(a->rt + 1) & 31]; + + need_serial =3D false; + memop |=3D MO_ALIGN; + switch (a->rb) { + case 0: /* Fetch and add */ + tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 1: /* Fetch and xor */ + tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Fetch and or */ + tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 3: /* Fetch and 'and' */ + tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Fetch and max unsigned */ + tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 5: /* Fetch and max signed */ + tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 6: /* Fetch and min unsigned */ + tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 7: /* Fetch and min signed */ + tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); + break; + case 8: /* Swap */ + tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); + break; + + case 16: /* Compare and swap not equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); + if ((memop & MO_SIZE) =3D=3D MO_64 || TARGET_LONG_BITS =3D=3D = 32) { + tcg_gen_mov_tl(t1, src); + } else { + tcg_gen_ext32u_tl(t1, src); + } + tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, + cpu_gpr[(a->rt + 2) & 31], t0); + tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); + tcg_gen_mov_tl(dst, t0); + } + break; + + case 24: /* Fetch and increment bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, 1= ); + } + break; + case 25: /* Fetch and increment equal */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_EQ, 1= ); + } + break; + case 28: /* Fetch and decrement bounded */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + need_serial =3D true; + } else { + do_fetch_inc_conditional(ctx, memop, EA, a->rt, TCG_COND_NE, -= 1); + } + break; + + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + return true; + } + + if (need_serial) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(tcg_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } + return true; +} + +static bool do_st_atomic(DisasContext *ctx, arg_X *a, MemOp memop) +{ + TCGv EA, src, discard; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + EA =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(0)); + src =3D cpu_gpr[a->rt]; + discard =3D tcg_temp_new(); + + memop |=3D MO_ALIGN; + switch (a->rb) { + case 0: /* add and Store */ + tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 1: /* xor and Store */ + tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 2: /* Or and Store */ + tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 3: /* 'and' and Store */ + tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); + break; + case 4: /* Store max unsigned */ + tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 5: /* Store max signed */ + tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 6: /* Store min unsigned */ + tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 7: /* Store min signed */ + tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop= ); + break; + case 24: /* Store twin */ + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(tcg_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + } else { + TCGv t =3D tcg_temp_new(); + TCGv t2 =3D tcg_temp_new(); + TCGv s =3D tcg_temp_new(); + TCGv s2 =3D tcg_temp_new(); + TCGv ea_plus_s =3D tcg_temp_new(); + + tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); + tcg_gen_addi_tl(ea_plus_s, EA, memop_size(memop)); + tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); + tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); + tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); + tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); + } + break; + default: + /* invoke data storage error handler */ + gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); + } + return true; +} + +TRANS(LWAT, do_ld_atomic, DEF_MEMOP(MO_UL)) +TRANS(STWAT, do_st_atomic, DEF_MEMOP(MO_UL)) + +static bool trans_LDAT(DisasContext *ctx, arg_LDAT *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + return do_ld_atomic(ctx, a, DEF_MEMOP(MO_UQ)); +#else + qemu_build_not_reached(); +#endif + return true; +} + +static bool trans_STDAT(DisasContext *ctx, arg_STDAT *a) +{ + REQUIRE_64BIT(ctx); +#if defined(TARGET_PPC64) + return do_st_atomic(ctx, a, DEF_MEMOP(MO_UQ)); +#else + qemu_build_not_reached(); +#endif + return true; +} --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293401; cv=none; d=zohomail.com; s=zohoarc; b=J9sYgtVrlikNQVaEHcrVjg1cGpS2MRMkNTsXAC/+2dYRw0d2Qt0gtQZHXnriaLbnQysG0ChwFqPPAEm64O+/2yKmdIPaxKI9Pe7eHFCtA5vnS/+i/OgGX8MH63JbMtQMHQRmtUtLT8qwt+g8ImZ2e7ivWbGE5IUJuIE3ITcaH98= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779293401; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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b=Z5LL9MNRZvY+O14t1HWpKSzNeR8chs9k8 PdjheCKY+u6i2o3pCZ05fxolC6Rb8N+ziCK0uTS2WBSjYmogH+0umunXmR5LoT07 2tL1oUsjkkl75LIL7UvQk8CXmRjtoT/KGz2YUtNAul5h4lD+k5DVI3IsLCockU+W 2KkLufJ6Hgwj5NPVSvDIFVrkRC3P4X2eqxi8KeQFKzIn+YK8u9EYGA2hGpRUR4B7 yJVwPt437LkwF3l7t6L+Qwarpto2d9dt7OfIWIpnyqbhjqGLLfYrBooGj4eWzqUb AAexzsOHenH5/k7+oRQ0GEZLmyzLe3cFhbDtfbptzKUt0OAMsZ1wA== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 13/28] target/ppc: Move isync instruction to decodetree. Date: Wed, 20 May 2026 21:37:13 +0530 Message-ID: <20260520160728.2283628-14-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfXw/otAotkmgyz PuMDu/1FmmyvLbWtX/e+x3fJNmWVIf99mn7aBDQQ69xNXLgCKXuAMPultaY3PI8a3CrdhOlIv2G gdR/ewQ/pUsIJtfsF4RO2M/C56NgAjaP8MBsL6v8LDRZj5jb6jFrolMuZXb5ngQt/wNATCr7Gcl L9gskdSCsN5z6eVRsiVjkFlo4VT4VGy0hI9F4pTK0M5RtrBuyCPbrukll1SLkYrCaVSM4mQT/Wi brYNSO79YuiFFF4Z0iUDZVBUA4rtOf3JmXs/baOoawbdpezsSjQP0yc35qIHT8o79KQy1lopVQo O9eD9dQb2Nl2aKJqR/SQIagwsgUUjaH5psEMrio7JxlJwLcWuMC8goVrmQkQmmMLav0xJPOw5w4 dHaAtyXklMuXLbo3C9Z5FGtxLUDVVIE779MJGJ/mc1lGP/zq82rDCPA9q80SO+JedgUiG1fRah1 A5cj1hC4ViCNJwcz+iw== X-Proofpoint-GUID: evMTthoIr8nyWPS1cDwg0-kj70ynFBE9 X-Proofpoint-ORIG-GUID: fslE-KaODBoeGBsrYdz8r0bgZ0cCkSIr X-Authority-Analysis: v=2.4 cv=aYBRWxot c=1 sm=1 tr=0 ts=6a0ddca7 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=3RUvYVtxcIq7NUn8s_cA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293402454158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Moving the following instructions to decodetree specification : isync The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Ojaswin Mujoo Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 1 + target/ppc/translate.c | 15 --------------- target/ppc/translate/storage-ctrl-impl.c.inc | 17 +++++++++++++++++ 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index f35f7113a0..cbb7a2ed51 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1462,6 +1462,7 @@ MSGSYNC 011111 ----- ----- ----- 1101110110 - @X_sync ...... .. l:3 ... sc:2 ..... .......... . &X_sync SYNC 011111 -- ... --- .. ----- 1001010110 - @X_sync EIEIO 011111 ----- ----- ----- 1101010110 - +ISYNC 010011 ----- ----- ----- 0010010110 - =20 # Condition Register Field Instruction =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 2345bf8867..770f52e7d4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2727,20 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } #endif =20 -/* isync */ -static void gen_isync(DisasContext *ctx) -{ - /* - * We need to check for a pending TLB flush. This can only happen in - * kernel mode however so check MSR_PR - */ - if (!ctx->pr) { - gen_check_tlb_flush(ctx, false); - } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -} - /* wait */ static void gen_wait(DisasContext *ctx) { @@ -5401,7 +5387,6 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_S= TRING), GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), -GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index b8b4454663..943229c438 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -155,6 +155,23 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE= *a) return true; } =20 +static bool trans_ISYNC(DisasContext *ctx, arg_ISYNC *a) +{ + REQUIRE_INSNS_FLAGS(ctx, MEM); + + /* + * We need to check for a pending TLB flush. This can only happen in + * kernel mode however so check MSR_PR + */ + if (!ctx->pr) { + gen_check_tlb_flush(ctx, false); + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; + + return true; +} + static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a) { REQUIRE_64BIT(ctx); --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293401; cv=none; d=zohomail.com; s=zohoarc; b=NrLhvAOYleQ2qsCPEmZp6aRjWjTxOE4FhVcZ2By4+b4hKLHG3LKfZoEWHfEAmgceRiyesiCzYUT7OKeZmhVePCO3G/a0WCIyh6jn2lDeTfPXb7DYuf13HUWhrfSqCv/XDqxprITX8wEsMfpAYU3mjapVBDC9ZWoSnQkZFOBYXKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=yYa81c9xmjpjgkAMs fonQpKG+Ukv+fo340dFx717y5A=; b=LrItLh2/fa6ir76DVc8jZ8bCqfKhsEv3R 6a3AkD8rBIvA4Onp8nXoOuO61T+J8DUmHA+AWQPfGkxV378wNRqboTuHdrSnZ6rH WfWpFl2nwWLXN9PvLLNb+z15/sDZfR0CQVXFmoF8Y2fpbKWvX6MCESpbGiFALB0z aWChYGhgiJzMc67hryj8pND0VlsjAmYG7WQisHpdiCjq145yGGikDoTZdaxztu97 DQfqh1bI1zAGGIFHO2/RCriQKs+ouTFIELIy4SOaWcBtBlk0Zu38zDCvg6is13L/ 1fbXhIpAbpK9Zws/WPHtfq0NJTxROBrs+uSTwGQhQa3S9dI0XVz9A== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 14/28] target/ppc: Convert b{a, l, la} to decode tree Date: Wed, 20 May 2026 21:37:14 +0530 Message-ID: <20260520160728.2283628-15-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: 4ami-BUnNfGJG6YdSQEt_ubzdIUJ0TXf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX1FtffJYpwLFz or7NrkDJD3QBGw5Kfk7raC6KV/tCHsic0ZR7wWKoQmFz1XjaT8yvjsp0abwZraWdZp2M6HoEOvR iuT7G8U6RJuO7ar8BLBYDWnJ8hVqDRSTMiEPk2t6vfUbJdLUYoscutuzpcDkNLSZDFtHpDg1iTr JmaOCRTkFimBX8uu8o5yr7sLe9P+1ALjNLngtPaLmKayPzAlJa061lLMNkLHko3NS/WFXjwp75/ k23CXtgUeFuoEfMO2jDYRrhSHjQki+GI5Q/baBN9epvoymxQKKmqZHbDd77wHvcY2bVe+RYg03E sBE33FCxrSXOqydzNDmMEhPyYEmzX6VkOm8OEpXIcvv2IVVnFlo7duBub0hlmW54u3D3DPKkqoi gZp0qb0yo1c7JTN4AMTYbnZKJfS5KervTda2Rigea11UC+7Kx6g9/pWCv5c/szdNTNma0Vm+YeN 9/kFmubNmfmfCX+mdKg== X-Proofpoint-GUID: aRyxSIGcUuGL9LKRfZrWmGB9tJWpXVmZ X-Authority-Analysis: v=2.4 cv=apyCzyZV c=1 sm=1 tr=0 ts=6a0ddcac cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=8uLd_aw9J8tj_XdJNvAA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293403870154100 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert b, ba, bl and bla to decode tree specification. The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb to confirm LR was correctly populated only when LK is set. Signed-off-by: Ojaswin Mujoo Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 7 +++++++ target/ppc/internal.h | 7 ------- target/ppc/translate.c | 24 ------------------------ target/ppc/translate/branch-impl.c.inc | 24 ++++++++++++++++++++++++ 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index cbb7a2ed51..b98fe01a84 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1478,6 +1478,13 @@ MCRF 010011 ... -- ... -- ----- 00000 000= 00 - @XL_bfa MFBHRBE 011111 ..... ..... ..... 0100101110 - @XFX_bhrbe CLRBHRB 011111 ----- ----- ----- 0110101110 - =20 +# Branch Instructions +%li 2:24 !function=3Dtimes_4 +&I_b li aa:bool lk:bool +@I_b ...... ........................ aa:1 lk:1 &I_b li=3D%li + +B 010010 ........................ . . @I_b + ## Misc POWER instructions =20 ATTN 000000 00000 00000 00000 0100000000 0 diff --git a/target/ppc/internal.h b/target/ppc/internal.h index dda23b6609..fe58cba627 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -198,13 +198,6 @@ EXTRACT_HELPER(L, 16, 2); EXTRACT_HELPER(WC, 21, 2); EXTRACT_HELPER(PL, 16, 2); =20 -/*** Jump target decoding = ***/ -/* Immediate address */ -static inline target_ulong LI(uint32_t opcode) -{ - return (opcode >> 0) & 0x03FFFFFC; -} - static inline uint32_t BD(uint32_t opcode) { return (opcode >> 0) & 0xFFFC; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 770f52e7d4..37a164951f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3089,29 +3089,6 @@ static inline void gen_setlr(DisasContext *ctx, targ= et_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/* b ba bl bla */ -static void gen_b(DisasContext *ctx) -{ - target_ulong li, target; - - /* sign extend LI */ - li =3D LI(ctx->opcode); - li =3D (li ^ 0x02000000) - 0x02000000; - if (likely(AA(ctx->opcode) =3D=3D 0)) { - target =3D ctx->cia + li; - } else { - target =3D li; - } - if (LK(ctx->opcode)) { - gen_setlr(ctx, ctx->base.pc_next); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); - } else { - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); - } - gen_goto_tb(ctx, 0, target); - ctx->base.is_jmp =3D DISAS_NORETURN; -} - #define BCOND_IM 0 #define BCOND_LR 1 #define BCOND_CTR 2 @@ -5390,7 +5367,6 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_= STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index 9ade0c659a..745f71afd1 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -31,3 +31,27 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) return true; } #endif + +static bool trans_B(DisasContext *ctx, arg_I_b *a) +{ + target_ulong target, li; + + /* sign extend LI */ + li =3D (a->li ^ 0x02000000) - 0x02000000; + + if (likely(a->aa =3D=3D 0)) { + target =3D ctx->cia + li; + } else { + target =3D li; + } + if (a->lk) { + gen_setlr(ctx, ctx->base.pc_next); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); + } else { + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); + } + gen_goto_tb(ctx, 0, target); + ctx->base.is_jmp =3D DISAS_NORETURN; + + return true; +} --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293519; cv=none; d=zohomail.com; s=zohoarc; b=PP9EPQY8X5DmKySCk07zqnHABbVV/6CJXAjWsNpt8jWPynad1Ev4W8OQ+gmX6rwhNZ1Dii1WZq7IDwN8N1eMxnVsXwY8T+u0W90tNHakiAf+rlWTSnKAMfoymuqUUt/7NEdB1KKWfdpP2g87yjiKYNGjClS45Td4I26Jfgsn7wM= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=OSMQ2CgdcTdYmFEoq 3HDtzSiv+CQk4h/+JiYs1UqPr4=; b=hUoPNfA5Lp1N2/hg0jxR52+dQa/nK1dsi RtVkRjv4aZhBb9GAeSyn4Rq92BMsSTqT3Sn1YXtZSlmzwv0E7Ki3Hd9Dbc66b0e4 WZBSGKAaSCbnL4itjCpAVoN6jCLiQqkgVuPPpmS/l/E1J5w8TRsNnydNn/9BBKaO 2Iop3zE6zv4dbimaxAjgvN+c7MuYv0bgRkunQOINoXG7ilqv3ex5/C9lZEOW6wSW s8z66g/U2zinokOodQHHypBj2RM2W6g4imM0cvZX7uEclm31uL3ZfFyPUClsD8EV 8b/dvQQc5Zv19uStV9m+Miac9wdnWNSwOMFmLErGsQ59omQUdJI6Q== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 15/28] target/ppc: move various conditional branch insns to decodetree Date: Wed, 20 May 2026 21:37:15 +0530 Message-ID: <20260520160728.2283628-16-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX0CKju6ZqtS4T 2oRpU4Z8ljdl4MsW75LQfyZQsAze6Ud0AHsdU2E0iblNyf89DkBTUiOi/2WNvr9IGNdpP1Z7M1K NmxJfoG9YoYSuDNJwaCtmt1NMuqXp7blZPlveZbE94mc49Fx4tkk2T6LUbno3WZXyzCot3h3tmP zoD4a6bKQ93XrV3u66XLByWXveRqfx1i5xPVUsY3YNMs7wA32PgJkp3ujK2qJE/D8M/c/Ir3RH4 LcqM+FPILhAHWn+OtbEXTjl3y0kdbDp9A3LkU9e7KByaRa1R5GCbxWjOCrjGFCCtVDqpfJBswmg c3HuBXgzxVRPw/bs+YChV4jmPeZmlo4KeNqywYfxBgPUA4FF/BEHh06Dwt6gtf/5cyF4xCmWhhi BE39V1oJ8Jisbz2tWxDlgO476b3256XVCnJbCYtHdhzQyOR7baL6qdLckUaKeVUSvnw+tYJKVWC aVGlo03rgYSS29zDGhQ== X-Proofpoint-GUID: Mg9wdufWrV-NRJx2ztjIpYnBFaCQG3AW X-Proofpoint-ORIG-GUID: r3wclB_-45Xrj8zowKdFSoSyY-tz4phk X-Authority-Analysis: v=2.4 cv=aYBRWxot c=1 sm=1 tr=0 ts=6a0ddcb2 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=CKxRzG1O2kzciCs865QA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293520070154100 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert the following instrunctions to decodetree specification: bc bca bcl bcla bclr bclrl bcctr bcctrl bctar bctarl The branch was tested by comparing the qemu -D log -d op,in_asm output for each instruction and also for the various combinations of branch option (BO) bits for the conditional branch instructions. Additionally, gdb was used to confirm the LR and other register's behavior is consistent to legacy behavior. Further, the changes also pass a boot test into Fedora distro. Signed-off-by: Ojaswin Mujoo Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 13 ++ target/ppc/translate.c | 148 ----------------------- target/ppc/translate/branch-impl.c.inc | 157 +++++++++++++++++++++++++ 3 files changed, 170 insertions(+), 148 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index b98fe01a84..34b36cbef6 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1485,6 +1485,19 @@ CLRBHRB 011111 ----- ----- ----- 0110101110 - =20 B 010010 ........................ . . @I_b =20 +%bd 2:14 !function=3Dtimes_4 +&bcond bo:uint32_t bi bd aa:bool lk:bool +@B_bcond ...... bo:5 bi:5 .............. aa:1 lk:1 &bcond bd=3D%bd + +BC 010000 ..... ..... .............. . . @B_bcond + +&bclr bo bi bh lk:bool +@XL_bclr ...... bo:5 bi:5 --- bh:2 .......... lk:1 &bclr + +BCLR 010011 ..... ..... ---.. 0000010000 . @XL_bclr +BCCTR 010011 ..... ..... ---.. 1000010000 . @XL_bclr +BCTAR 010011 ..... ..... ---.. 1000110000 . @XL_bclr + ## Misc POWER instructions =20 ATTN 000000 00000 00000 00000 0100000000 0 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 37a164951f..22125c30a5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3089,150 +3089,6 @@ static inline void gen_setlr(DisasContext *ctx, tar= get_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -#define BCOND_IM 0 -#define BCOND_LR 1 -#define BCOND_CTR 2 -#define BCOND_TAR 3 - -static void gen_bcond(DisasContext *ctx, int type) -{ - uint32_t bo =3D BO(ctx->opcode); - TCGLabel *l1; - TCGv target; - target_long bhrb_type =3D BHRB_TYPE_OTHER; - - if (type =3D=3D BCOND_LR || type =3D=3D BCOND_CTR || type =3D=3D BCOND= _TAR) { - target =3D tcg_temp_new(); - if (type =3D=3D BCOND_CTR) { - tcg_gen_mov_tl(target, cpu_ctr); - } else if (type =3D=3D BCOND_TAR) { - gen_load_spr(target, SPR_TAR); - } else { - tcg_gen_mov_tl(target, cpu_lr); - } - if (!LK(ctx->opcode)) { - bhrb_type |=3D BHRB_TYPE_INDIRECT; - } - bhrb_type |=3D BHRB_TYPE_XL_FORM; - } else { - target =3D NULL; - } - if (LK(ctx->opcode)) { - gen_setlr(ctx, ctx->base.pc_next); - bhrb_type |=3D BHRB_TYPE_CALL; - } - l1 =3D gen_new_label(); - if ((bo & 0x4) =3D=3D 0) { - /* Decrement and test CTR */ - TCGv temp =3D tcg_temp_new(); - - if (type =3D=3D BCOND_CTR) { - /* - * All ISAs up to v3 describe this form of bcctr as invalid but - * some processors, ie. 64-bit server processors compliant with - * arch 2.x, do implement a "test and decrement" logic instead, - * as described in their respective UMs. This logic involves C= TR - * to act as both the branch target and a counter, which makes - * it basically useless and thus never used in real code. - * - * This form was hence chosen to trigger extra micro-architect= ural - * side-effect on real HW needed for the Spectre v2 workaround. - * It is up to guests that implement such workaround, ie. linu= x, to - * use this form in a way it just triggers the side-effect wit= hout - * doing anything else harmful. - */ - if (unlikely(!is_book3s_arch2x(ctx))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(temp, cpu_ctr); - } else { - tcg_gen_mov_tl(temp, cpu_ctr); - } - if (bo & 0x2) { - tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); - } else { - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); - } - tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); - } else { - tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); - if (NARROW_MODE(ctx)) { - tcg_gen_ext32u_tl(temp, cpu_ctr); - } else { - tcg_gen_mov_tl(temp, cpu_ctr); - } - if (bo & 0x2) { - tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); - } else { - tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); - } - } - bhrb_type |=3D BHRB_TYPE_COND; - } - if ((bo & 0x10) =3D=3D 0) { - /* Test CR */ - uint32_t bi =3D BI(ctx->opcode); - uint32_t mask =3D 0x08 >> (bi & 0x03); - TCGv_i32 temp =3D tcg_temp_new_i32(); - - if (bo & 0x8) { - tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); - tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); - } else { - tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); - tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); - } - bhrb_type |=3D BHRB_TYPE_COND; - } - - gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); - - if (type =3D=3D BCOND_IM) { - target_ulong li =3D (target_long)((int16_t)(BD(ctx->opcode))); - if (likely(AA(ctx->opcode) =3D=3D 0)) { - gen_goto_tb(ctx, 0, ctx->cia + li); - } else { - gen_goto_tb(ctx, 0, li); - } - } else { - if (NARROW_MODE(ctx)) { - tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); - } else { - tcg_gen_andi_tl(cpu_nip, target, ~3); - } - gen_lookup_and_goto_ptr(ctx); - } - if ((bo & 0x14) !=3D 0x14) { - /* fallthrough case */ - gen_set_label(l1); - gen_goto_tb(ctx, 1, ctx->base.pc_next); - } - ctx->base.is_jmp =3D DISAS_NORETURN; -} - -static void gen_bc(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_IM); -} - -static void gen_bcctr(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_CTR); -} - -static void gen_bclr(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_LR); -} - -static void gen_bctar(DisasContext *ctx) -{ - gen_bcond(ctx, BCOND_TAR); -} - /*** Condition register logical = ***/ #define GEN_CRLOGIC(name, tcg_op, opc) = \ static void glue(gen_, name)(DisasContext *ctx) = \ @@ -5367,10 +5223,6 @@ GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC= _STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), -GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), -GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), -GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_IS= A207), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index 745f71afd1..44ed40422e 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -55,3 +55,160 @@ static bool trans_B(DisasContext *ctx, arg_I_b *a) =20 return true; } + +#define BCOND_IM 0 +#define BCOND_LR 1 +#define BCOND_CTR 2 +#define BCOND_TAR 3 + +static bool bcond_helper(DisasContext *ctx, int type, uint32_t bo, int bi, + int bd, int bh, bool aa, bool lk) +{ + TCGLabel *l1; + TCGv target; + target_long bhrb_type =3D BHRB_TYPE_OTHER; + + if (type =3D=3D BCOND_IM && bh !=3D -1) { + /* BCOND_IM should never use bh */ + return false; + } else if (type !=3D BCOND_IM && (bd !=3D -1 || aa !=3D 0)) { + /* Other BCOND types should never use bd or aa */ + return false; + } + + if (type =3D=3D BCOND_LR || type =3D=3D BCOND_CTR || type =3D=3D BCOND= _TAR) { + target =3D tcg_temp_new(); + if (type =3D=3D BCOND_CTR) { + tcg_gen_mov_tl(target, cpu_ctr); + } else if (type =3D=3D BCOND_TAR) { + gen_load_spr(target, SPR_TAR); + } else { + tcg_gen_mov_tl(target, cpu_lr); + } + if (!lk) { + bhrb_type |=3D BHRB_TYPE_INDIRECT; + } + bhrb_type |=3D BHRB_TYPE_XL_FORM; + } else { + target =3D NULL; + } + if (lk) { + gen_setlr(ctx, ctx->base.pc_next); + bhrb_type |=3D BHRB_TYPE_CALL; + } + l1 =3D gen_new_label(); + if ((bo & 0x4) =3D=3D 0) { + /* Decrement and test CTR */ + TCGv temp =3D tcg_temp_new(); + + if (type =3D=3D BCOND_CTR) { + /* + * All ISAs up to v3 describe this form of bcctr as invalid but + * some processors, ie. 64-bit server processors compliant with + * arch 2.x, do implement a "test and decrement" logic instead, + * as described in their respective UMs. This logic involves C= TR + * to act as both the branch target and a counter, which makes + * it basically useless and thus never used in real code. + * + * This form was hence chosen to trigger extra micro-architect= ural + * side-effect on real HW needed for the Spectre v2 workaround. + * It is up to guests that implement such workaround, ie. linu= x, to + * use this form in a way it just triggers the side-effect wit= hout + * doing anything else harmful. + */ + if (unlikely(!is_book3s_arch2x(ctx))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + return true; + } + + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); + } else { + tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(temp, cpu_ctr); + } else { + tcg_gen_mov_tl(temp, cpu_ctr); + } + if (bo & 0x2) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + } + bhrb_type |=3D BHRB_TYPE_COND; + } + if ((bo & 0x10) =3D=3D 0) { + /* Test CR */ + uint32_t mask =3D 0x08 >> (bi & 0x03); + TCGv_i32 temp =3D tcg_temp_new_i32(); + + if (bo & 0x8) { + tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); + tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); + } else { + tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); + tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); + } + bhrb_type |=3D BHRB_TYPE_COND; + } + + gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); + + if (type =3D=3D BCOND_IM) { + target_ulong li =3D (target_long)((int16_t)(bd)); + if (likely(aa =3D=3D 0)) { + gen_goto_tb(ctx, 0, ctx->cia + li); + } else { + gen_goto_tb(ctx, 0, li); + } + } else { + if (NARROW_MODE(ctx)) { + tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); + } else { + tcg_gen_andi_tl(cpu_nip, target, ~3); + } + gen_lookup_and_goto_ptr(ctx); + } + if ((bo & 0x14) !=3D 0x14) { + /* fallthrough case */ + gen_set_label(l1); + gen_goto_tb(ctx, 1, ctx->base.pc_next); + } + ctx->base.is_jmp =3D DISAS_NORETURN; + + return true; +} + +static bool trans_BC(DisasContext *ctx, arg_bcond *a) +{ + /* + * bh is not used for bc variants hence we pass -1 + */ + return bcond_helper(ctx, BCOND_IM, a->bo, a->bi, a->bd, -1, a->aa, a->= lk); +} + +/* + * This helper is shared by bclr, bcctr and bctar. + */ +static bool bclr_helper(DisasContext *ctx, arg_bclr *a, int type) +{ + /* + * bd and aa is not used for bc variants hence we pass -1 and 0 respec= tively + */ + return bcond_helper(ctx, type, a->bo, a->bi, -1, a->bh, 0, a->lk); +} + +TRANS(BCLR, bclr_helper, BCOND_LR) +TRANS(BCCTR, bclr_helper, BCOND_CTR) +TRANS(BCTAR, bclr_helper, BCOND_TAR) + --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293424; cv=none; d=zohomail.com; s=zohoarc; b=XbGzug1o1IH7KQtdcPSx+lMhWYLh0lXH71AvT7VjL48QIC8BGANbps2iTlo6RkMYMBbQ+M96CCzNyLzhvA8yrFKvjRPjQLcx6vrmPQZ6010GsaqgUZq1fx0wdLToU81p0wym5NWmXX6poLWIGlPB7vcZrJCMg1XR11hX0ySlWjM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779293424; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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b=QtmixvkWeaI/P6uYGnJA2A /PKnmUssc53q5B5h3Y5i2p4WUT/q+gHY89tHlT+6PxrDXRMpMeFHfnliOohcbgIg VtzjTmZ/uBF5jeEI9zFEp5iUZO8ukVMoRAVaqZmHfKL5wkb3v2YYTmtHD73J1kGf EyfXf1k67MD+VSfya+5RkGMmreHhbgjxTKSB9jdniCPa8PwgpizwKTVyhvS/xMxo y32seGqldN9TLCUkLYpwSzEY4AkSfaFLffzvFdYni0nN09zQA6NgOL68jP904rXB T9+a3dQVJqE44CXv5JgpmlJGrqip+73fB6/R/MolU9jA64TJarGpF7CzAOlxxrPg == From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 16/28] target/ppc: Fix TRANS* macro variadic arguments handling Date: Wed, 20 May 2026 21:37:16 +0530 Message-ID: <20260520160728.2283628-17-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293425024158500 From: Ojaswin Mujoo Use ##__VA_ARGS__ in TRANS* macros to allow variadic arguments to be optional instead of mandatory. "##" removes the preceding comma when __VA_ARGS__ is empty, enabling macros to work with functions that don't need extra parameters. This avoid compilation errors when using a pattern like below: static bool do_wait(DisasContext *ctx, arg_X_wait *a) {...} TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) Compilation Error: ../target/ppc/translate.c:5526:40: error: expected expression before =E2=80= =98)=E2=80=99 token 5526 | return FUNC(ctx, a, __VA_ARGS__); \ | ^ ../target/ppc/translate/storage-ctrl-impl.c.inc:368:1: note: in expansion o= f macro =E2=80=98TRANS_FLAGS=E2=80=99 368 | TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) Signed-off-by: Ojaswin Mujoo Signed-off-by: Chinmay Rath --- target/ppc/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 22125c30a5..a8ee87ffe2 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4719,29 +4719,29 @@ static int64_t dw_compose_ea(DisasContext *ctx, int= x) */ #define TRANS(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { return FUNC(ctx, a, __VA_ARGS__); } + { return FUNC(ctx, a, ##__VA_ARGS__); } #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } =20 #define TRANS64(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ - { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } + { REQUIRE_64BIT(ctx); return FUNC(ctx, a, ##__VA_ARGS__); } #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ REQUIRE_64BIT(ctx); \ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ - return FUNC(ctx, a, __VA_ARGS__); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ } =20 /* TODO: More TRANS* helpers for extra insn_flags checks. */ --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 20 May 2026 16:09:31 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4F79120040; Wed, 20 May 2026 16:09:24 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.39.31.153]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 20 May 2026 16:09:24 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=zZpwa32X+MU3JKMWE z8QErzGnbzcARALuOXj1hPBfc0=; b=LkYF9iLBSDSa7fDbd/1clxReUWPmP31R1 jyO6GeNODMG/vTP4V9/0Ea8n8FRRpD9yOo+NOq3S0QL7jM7OWtJb8zSOJetzbHGw 1uLtPUcy+hG289hGsBi68ZGeqq9al4GQchgaxQYEELFmm4J/LBiKCXjxKYN3PS3K Ybfr8AaD5hKev/mnGL4NSI1/dNCdpE79SwBqK5pTcfIO7JGL5UG92o67C9HE/0Kq 1UCXtfn2N6tliVCekBaUOeWeh8ztotTJllTwg1EQu7EIbKf39gslU/QVZZFLf74c lwxH6GdzcvnE/N5WI9QLeF/Hg9en+njnkG203Qx1q7b/WPxwzslwQ== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 17/28] target/ppc: Move wait instruction to decodetree Date: Wed, 20 May 2026 21:37:17 +0530 Message-ID: <20260520160728.2283628-18-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfXzPcGSDttK8D1 45RaWO60v4XJtEi9VnUxC1Tz1ETxDDAjRknr/vxMBogs3meZTwxifjc4wQ6I4v2e3ovtyWooQMu gjv3vvDv97/DPwvPwQth5lzcrXrIPH0OI1aaRBkFTbCLosb2nUFCFZpcH8wtypD7VQMldOs2Ww+ XSuUeWgdtIFJ3dJ1pY8X/kqgnTYgvWaahmFf6fitIie0hJOTtr4lk718pf/HtHAkKAHpqb60ZR4 madL9l+ws/BdM/G3O6DAOidjSRgQDIs3ZOcACqdd36JdC97PaAin3SWwGfqmBH644QEf/N+YGSO Crk8wcWXlymOhu9UGLHKSyStV3c+DSRsQcp3zrBtf8CVf/HvaCo9n8yRh1ajLmi1IEovEe5gXJU O+37/vxysau0l7s4yktlIM5dqweE3/87whzCV5XXN2/6CN54475li+A5uipUqgVFIdeSTzSSDpN 4a7/t1DbiULV+fqGUng== X-Authority-Analysis: v=2.4 cv=BNuDalQG c=1 sm=1 tr=0 ts=6a0ddcc1 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=uB9JOsh-sYL72gAx4UQA:9 X-Proofpoint-ORIG-GUID: 0jRnrxw5-fhrU4Z9Jf2U7hPj803JqvYi X-Proofpoint-GUID: MIi6V-MOod6nGP4JfNtG9tsvoUT6NpW4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293469775158500 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Implement wait instruction using decodetree with proper handling of WC and PL fields across different ISA versions. Since the opcode changed between ISA 2.x and 3.x we have defined 2 different decodetree instructions that are handled by the same helper. The changes have been tested by comparing the tcg generated before and after the change for wait instruction. The test was repeated for 2 types of machines: Power10 - which should use the newer wait implementation e500mc - which should use older PPC_WAIT implementation Both generated the same tcg ops with and without the change. Further, with the changes we were able to boot into Fedora distro as well. Signed-off-by: Ojaswin Mujoo Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 15 +++ target/ppc/translate.c | 91 ----------------- target/ppc/translate/storage-ctrl-impl.c.inc | 100 +++++++++++++++++++ 3 files changed, 115 insertions(+), 91 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 34b36cbef6..2c002f8513 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -1470,6 +1470,21 @@ ISYNC 010011 ----- ----- ----- 0010010110 - @XL_bfa ...... bf:3 .. bfa:3 .. ..... ..... ..... . MCRF 010011 ... -- ... -- ----- 00000 00000 - @XL_bfa =20 +# Wait Instructions + +# We can use the same X_wait argument set for both WAIT and older ISA2.x +# compliant WAIT_2_x. Depending on the version, we may or may not use the +# arguments. For more information, check do_wait() helper. + +&X_wait wc pl +@X_wait ...... ..- wc:2 --- pl:2 ----- .......... - &X_wait + +# According to ISA v3.1, bit 6 and 7 are implementation dependent and "unl= ess +# the intention is to use the implementation-dependent field, these bits m= ust be +# coded zero". Hence, we code them to 0. +WAIT 011111 00-.. ---.. ----- 0000011110 - @X_wait +WAIT_ISA_2_X 011111 ---.. ---.. ----- 0000111110 - @X_wait + # Branch History Rolling Buffer (BHRB) Instructions =20 &XFX_bhrbe rt bhrbe diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a8ee87ffe2..4a7fa6a6a9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2727,95 +2727,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } #endif =20 -/* wait */ -static void gen_wait(DisasContext *ctx) -{ - uint32_t wc; - - if (ctx->insns_flags & PPC_WAIT) { - /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ - - if (ctx->insns_flags2 & PPC2_PM_ISA206) { - /* v2.06 introduced the WC field. WC > 0 may be treated as no-= op. */ - wc =3D WC(ctx->opcode); - } else { - wc =3D 0; - } - - } else if (ctx->insns_flags2 & PPC2_ISA300) { - /* v3.0 defines a new 'wait' encoding. */ - wc =3D WC(ctx->opcode); - if (ctx->insns_flags2 & PPC2_ISA310) { - uint32_t pl =3D PL(ctx->opcode); - - /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ - if (wc =3D=3D 3) { - gen_invalid(ctx); - return; - } - - /* PL 1-3 are reserved. If WC=3D2 then the insn is treated as = noop. */ - if (pl > 0 && wc !=3D 2) { - gen_invalid(ctx); - return; - } - - } else { /* ISA300 */ - /* WC 1-3 are reserved */ - if (wc > 0) { - gen_invalid(ctx); - return; - } - } - - } else { - warn_report("wait instruction decoded with wrong ISA flags."); - gen_invalid(ctx); - return; - } - - /* - * wait without WC field or with WC=3D0 waits for an exception / inter= rupt - * to occur. - */ - if (wc =3D=3D 0) { - TCGv_i32 t0 =3D tcg_constant_i32(1); - tcg_gen_st_i32(t0, tcg_env, - -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); - } - - /* - * Other wait types must not just wait until an exception occurs becau= se - * ignoring their other wake-up conditions could cause a hang. - * - * For v2.06 and 2.07, wc=3D1,2,3 are architected but may be implement= ed as - * no-ops. - * - * wc=3D1 and wc=3D3 explicitly allow the instruction to be treated as= a no-op. - * - * wc=3D2 waits for an implementation-specific condition, such could be - * always true, so it can be implemented as a no-op. - * - * For v3.1, wc=3D1,2 are architected but may be implemented as no-ops. - * - * wc=3D1 (waitrsv) waits for an exception or a reservation to be lost. - * Reservation-loss may have implementation-specific conditions, so it - * can be implemented as a no-op. - * - * wc=3D2 waits for an exception or an amount of time to pass. This - * amount is implementation-specific so it can be implemented as a - * no-op. - * - * ISA v3.1 allows for execution to resume "in the rare case of - * an implementation-dependent event", so in any case software must - * not depend on the architected resumption condition to become - * true, so no-op implementations should be architecturally correct - * (if suboptimal). - */ -} - #if defined(TARGET_PPC64) static void gen_doze(DisasContext *ctx) { @@ -5221,8 +5132,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_S= TRING), GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ -GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), -GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index 943229c438..21c7999d5d 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -270,3 +270,103 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *= a, bool local) =20 TRANS_FLAGS(MEM_TLBIE, TLBIE, do_tlbie, false) TRANS_FLAGS(MEM_TLBIE, TLBIEL, do_tlbie, true) + +/* + * Decodetree populates a->wc and a->pl based on ISA v3.1, however they may + * or may not be used based on the ISA: + * For ISA < 2.06 - both wc and pl are ignored + * For ISA =3D=3D 2.06, 2.07, 3.0 - wc is used and pl is ignored + * For ISA 3.1 - both wc and pl are used + */ +static bool do_wait(DisasContext *ctx, arg_X_wait *a) +{ + uint32_t wc; + + if (ctx->insns_flags & PPC_WAIT) { + /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ + + if (ctx->insns_flags2 & PPC2_PM_ISA206) { + /* v2.06 introduced the WC field. WC > 0 may be treated as no-= op. */ + wc =3D a->wc; + } else { + wc =3D 0; + } + + } else if (ctx->insns_flags2 & PPC2_ISA300) { + /* v3.0 defines a new 'wait' encoding. */ + wc =3D a->wc; + if (ctx->insns_flags2 & PPC2_ISA310) { + uint32_t pl =3D a->pl; + + /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ + if (wc =3D=3D 3) { + gen_invalid(ctx); + return true; + } + + /* PL 1-3 are reserved. If WC=3D2 then the insn is treated as = noop. */ + if (pl > 0 && wc !=3D 2) { + gen_invalid(ctx); + return true; + } + + } else { /* ISA300 */ + /* WC 1-3 are reserved */ + if (wc > 0) { + gen_invalid(ctx); + return true; + } + } + + } else { + warn_report("wait instruction decoded with wrong ISA flags."); + gen_invalid(ctx); + return true; + } + + /* + * wait without WC field or with WC=3D0 waits for an exception / inter= rupt + * to occur. + */ + if (wc =3D=3D 0) { + TCGv_i32 t0 =3D tcg_constant_i32(1); + tcg_gen_st_i32(t0, tcg_env, + -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); + } + + /* + * Other wait types must not just wait until an exception occurs becau= se + * ignoring their other wake-up conditions could cause a hang. + * + * For v2.06 and 2.07, wc=3D1,2,3 are architected but may be implement= ed as + * no-ops. + * + * wc=3D1 and wc=3D3 explicitly allow the instruction to be treated as= a no-op. + * + * wc=3D2 waits for an implementation-specific condition, such could be + * always true, so it can be implemented as a no-op. + * + * For v3.1, wc=3D1,2 are architected but may be implemented as no-ops. + * + * wc=3D1 (waitrsv) waits for an exception or a reservation to be lost. + * Reservation-loss may have implementation-specific conditions, so it + * can be implemented as a no-op. + * + * wc=3D2 waits for an exception or an amount of time to pass. This + * amount is implementation-specific so it can be implemented as a + * no-op. + * + * ISA v3.1 allows for execution to resume "in the rare case of + * an implementation-dependent event", so in any case software must + * not depend on the architected resumption condition to become + * true, so no-op implementations should be architecturally correct + * (if suboptimal). + */ + return true; +} + +TRANS_FLAGS(WAIT, WAIT_ISA_2_X, do_wait) +TRANS_FLAGS2(ISA300, WAIT, do_wait) + --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293403; cv=none; d=zohomail.com; s=zohoarc; b=eOZN+p2WqFe4tHTo9qT5NEmEX+U3VP/Ujd6EhV5+N4NcbeTXwOtZZpk+QYjAVMucFznAn2A4RcLFrALv3C6o7QfqUF+3N9ERRmEecNY2NYHZgV+23DAVLI/xEcaPZ8cV33UfIQFnnuEGhnJBMciVKbUiZbhUR0Itgj750eYKG5Y= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293405930154100 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Convert the following instructions to decode tree specification: doze nap sleep rvwinkle stop The functionality was tested by comparing the qemu -D log -d op,in_asm output as well as single stepping gdb to confirm behavior was not changed for ISA3.x (stop) as well as ISA206 (doze, nap, sleep, rvwinkle). Signed-off-by: Ojaswin Mujoo Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 8 ++ target/ppc/translate.c | 85 --------------- .../ppc/translate/processor-ctrl-impl.c.inc | 101 ++++++++++++++++++ 3 files changed, 109 insertions(+), 85 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 2c002f8513..a4454a2292 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -913,6 +913,14 @@ VPERMR 000100 ..... ..... ..... ..... 111011 = @VA =20 VSEL 000100 ..... ..... ..... ..... 101010 @VA =20 +## Power Management Instructions + +DOZE 010011 ----- ----- ----- 0110010010 - +NAP 010011 ----- ----- ----- 0110110010 - +SLEEP 010011 ----- ----- ----- 0111010010 - +RVWINKLE 010011 ----- ----- ----- 0111110010 - +STOP 010011 ----- ----- ----- 0101110010 - + ## Vector Integer Shift Instruction =20 VSLB 000100 ..... ..... ..... 00100000100 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4a7fa6a6a9..d1e9ab61e9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2728,86 +2728,6 @@ static inline void gen_check_tlb_flush(DisasContext = *ctx, bool global) { } #endif =20 #if defined(TARGET_PPC64) -static void gen_doze(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_DOZE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_nap(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_NAP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_stop(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_STOP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_sleep(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_SLEEP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -static void gen_rvwinkle(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - TCGv_i32 t; - - CHK_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_RVWINKLE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ -} - static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, T= CGv value) { TCGv_ptr tmp =3D tcg_temp_new_ptr(); @@ -5141,11 +5061,6 @@ GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC= _NONE, PPC2_ISA300), GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), #endif -GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206= ), -GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), -GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA20= 6), -GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_IS= A206), GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), #endif /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index 8abbb89630..bdbc195294 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -103,3 +103,104 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGS= YNC *a) /* interpreted as no-op */ return true; } + +static bool do_doze(DisasContext *ctx, arg_DOZE *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_DOZE); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + + return true; +} +TRANS_FLAGS2(PM_ISA206, DOZE, do_doze); + +static bool do_nap(DisasContext *ctx, arg_NAP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_NAP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, NAP, do_nap); + +static bool do_sleep(DisasContext *ctx, arg_SLEEP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_SLEEP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep); + +static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_RVWINKLE); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif /* defined(CONFIG_USER_ONLY) */ + return true; +} +TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle); + +static bool do_stop(DisasContext *ctx, arg_STOP *a) +{ + REQUIRE_64BIT(ctx); + +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); +#else + TCGv_i32 t; + + REQUIRE_HV(ctx); + translator_io_start(&ctx->base); + t =3D tcg_constant_i32(PPC_PM_STOP); + gen_helper_pminsn(tcg_env, t); + /* Stop translation, as the CPU is supposed to sleep from now */ + gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); +#endif + return true; +} +TRANS_FLAGS2(ISA300, STOP, do_stop); --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293500; cv=none; d=zohomail.com; s=zohoarc; b=WirHXXh1KlHXeyX6AvU7wl2iUpneo6eYXic4JhQzVcHg5dlqfSWhhDeet2C21His/7ezmEToxoLTbG9jenltpwLjSCN25QH8sgcVYMqQZUjL2seLwtdxXux3+shz9dFaHy+yEr/PEDqvlj1owmajsIJJXDN8LklEwnfial8euhQ= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=uz6MBeiL3q1xToq1f ekr7ZJHRYMI0huEgMQo9+wouDE=; b=lAT3vejFZVumhEB6jxOTPt/XTh5XAVtSZ OHW29mOLAe7TuGEKyPC8VPEIHrc1EhvlZK9zrcXTuejsyNQouORyNskQvkKh7A2g qjzVLAExgBHc3iZkYC4tXhmjVca1d5caxb/ttJ0AACZphfQF0aaiCO2qW2ysAoKM vyodAE4PRLqlBEh0gxanT4X4iENB6/lCppDXKkCozFh8CBczUnJmYAItSEvTZZBU QsTzZSCZ1f6cVcAxBD4Sw/bIVcjDt1Br9lNLpEoejWuhHwH0p5YBmmgbpJ2xJkWQ X9u0gg98dR/qVWEPdJPaPkAu0ppePdxQhsUrb6uhJMLyFPg9IYAkg== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 19/28] target/ppc: Refactor sleep and its variants to use a common helper Date: Wed, 20 May 2026 21:37:19 +0530 Message-ID: <20260520160728.2283628-20-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: KVrCWs8oHtRDTX9kL8RLUV3L3PIGeJ30 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfXzVkhRA9n5tL9 bWT2jWE5T+9cm6wM04mh1VAa8WJoBpDEdlLK6E3sInlFenWD5yevxKjgnOcXiOgpwJhZlrIDiZM 5jCh7NLS3Fio207oD68rn5PwrTkzl4IFRvp3EuoaXEHY+4IjhjQMfaiAuHXlUKjGHIOmYBed1JC fkzmEYFjhwMlnyT5FNHXc8vjYQ5oVBjdy7b+v8TlwTKwAde1nIWVS6YJ4tLS//7sTQxyPe8jh+c m9g/4WwPPx7Z0eFsVCFaEq6Smd55nyGdKy/FQ2liBpd8StrIjwWGv9WoYwG28IsOFIx3uk7hGhm MytcZBzbVYI2EsMdVimR3OTLuIObC5IGgQCdP0DYAe3F1apEoxrbSY5HWLJmxQoNkR4t6kk+71D bt2AKyRnE7T6PYUPp3ddqkbmTtqvB8MfHPeEOVw5tAMqY33ILT+Mqo+xn/vKTdjkZDmKuOi8/JR ZccUnOm/bd0jIWln2Kw== X-Proofpoint-GUID: 3Lpmfzpcc04VE7PYuXTAdNDcDdcLYIO8 X-Authority-Analysis: v=2.4 cv=apyCzyZV c=1 sm=1 tr=0 ts=6a0ddccb cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=AYO248uK6yRxx-YkPnAA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293501658154100 Content-Type: text/plain; charset="utf-8" From: Ojaswin Mujoo Refactor sleep, doze, nap, rvwinkle and stop to use a common helper since they share majority of the code. Also refactor gen_hlper_pminsn() to gen_helper_PMINSN() Signed-off-by: Ojaswin Mujoo Signed-off-by: Chinmay Rath [cr: ppc32 build fix] --- target/ppc/helper.h | 2 +- target/ppc/tcg-excp_helper.c | 2 +- .../ppc/translate/processor-ctrl-impl.c.inc | 99 +++---------------- 3 files changed, 16 insertions(+), 87 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f267c0d2b8..dacc4e223e 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,7 +18,7 @@ DEF_HELPER_1(rfdi, void, env) DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) DEF_HELPER_2(scv, noreturn, env, i32) -DEF_HELPER_2(pminsn, void, env, i32) +DEF_HELPER_2(PMINSN, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 5e6c1e326d..c5ccf7cf92 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -458,7 +458,7 @@ void helper_scv(CPUPPCState *env, uint32_t lev) } } =20 -void helper_pminsn(CPUPPCState *env, uint32_t insn) +void helper_PMINSN(CPUPPCState *env, uint32_t insn) { CPUState *cs =3D env_cpu(env); =20 diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index bdbc195294..3b3ed3019a 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -104,103 +104,32 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSG= SYNC *a) return true; } =20 -static bool do_doze(DisasContext *ctx, arg_DOZE *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_DOZE); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - - return true; -} -TRANS_FLAGS2(PM_ISA206, DOZE, do_doze); - -static bool do_nap(DisasContext *ctx, arg_NAP *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_NAP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, NAP, do_nap); - -static bool do_sleep(DisasContext *ctx, arg_SLEEP *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); -#else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_SLEEP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep); - -static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a) +/* + * Helper to handle DOZE, NAP, SLEEP, RVWINKLE & STOP. Since none of them = use + * any arguments just use a placeholder arg_SLEEP. + */ +static bool do_sleep(DisasContext *ctx, arg_SLEEP *a, powerpc_pm_insn_t ty= pe) { REQUIRE_64BIT(ctx); =20 #if defined(CONFIG_USER_ONLY) gen_priv_opc(ctx); -#else +#elif defined(TARGET_PPC64) TCGv_i32 t; =20 REQUIRE_HV(ctx); translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_RVWINKLE); - gen_helper_pminsn(tcg_env, t); + t =3D tcg_constant_i32(type); + gen_helper_PMINSN(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); -#endif /* defined(CONFIG_USER_ONLY) */ - return true; -} -TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle); - -static bool do_stop(DisasContext *ctx, arg_STOP *a) -{ - REQUIRE_64BIT(ctx); - -#if defined(CONFIG_USER_ONLY) - gen_priv_opc(ctx); #else - TCGv_i32 t; - - REQUIRE_HV(ctx); - translator_io_start(&ctx->base); - t =3D tcg_constant_i32(PPC_PM_STOP); - gen_helper_pminsn(tcg_env, t); - /* Stop translation, as the CPU is supposed to sleep from now */ - gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); + qemu_build_not_reached(); #endif return true; } -TRANS_FLAGS2(ISA300, STOP, do_stop); +TRANS_FLAGS2(PM_ISA206, DOZE, do_sleep, PPC_PM_DOZE); +TRANS_FLAGS2(PM_ISA206, NAP, do_sleep, PPC_PM_NAP); +TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep, PPC_PM_SLEEP); +TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_sleep, PPC_PM_RVWINKLE); +TRANS_FLAGS2(ISA300, STOP, do_sleep, PPC_PM_STOP); --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293512; cv=none; d=zohomail.com; s=zohoarc; b=KzqzCI3EkMFBrR3khQr99FbeaF2sVQGfHyhh7XSNn+EBmBEi/7ySfjLtLrkkDx0gceRj7ol+AFieI7JpqEGY+fe5BJNufaYiisFONnL3wNyOy7YPclYUKcT4sq403UhZc4oRJt2rClKMT7ifoKY4JYljIdpyRwOG53145z7Ug7k= ARC-Message-Signature: i=1; a=rsa-sha256; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=tAKZKfaq7M6LxZInF n5/QUUL9974i65XBXsQ08VqeQo=; b=Oa5ftChvcjIXP4mP9lK8Q5TOKlg3nYRSo gDHjcN2TaZLsc7mmZ8I2lKqQSAMSMcaN+ITiNrXfFZ7nz0vdnkbQVaXMOT2Ne0Mz ALCsa0ySCWKD7QVl5tz5uhQe5lAqIbn99+5iNAtiLleGwpv4vAKZzsOkHCrw97Xe V+aevAVY/uFZGQ73Te1IHvqWDmpNqddGqrKG5EASKKLwWIFZJsWHgHBo/EpQUxTy mHxkiNR3ohEemV9op38le0YhBLDxIhHPK7a98L4SO7kmCI6bdgtHAn5gFf9uFKOa oLT/DRPhBDrPfAdhcVO5H1yxkOvB1YQU2oWX3akJ/Kwi/undANJig== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 20/28] target/ppc: Move Condition Register access instructions to decodetree. Date: Wed, 20 May 2026 21:37:20 +0530 Message-ID: <20260520160728.2283628-21-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfXxzMrm4XFvcrx Adcc0WYuwY55APhAUUGYfWUTTsNFgbQIYWVlPHsxeg8Tq9RgBRQJZRuEdqaEb5rwyfh2S61r4tB gDQb66sSv9WhOElrv1h+azXXB7DJ8nnpuAard4SeCjSOqC8AcOCpJcY023ermJA2XlY57qCPjqv Mxkzdd9b5XvmwwnmH6RRBpoE0IP53M1ao8vgchSKNlcJCo6xyaCXIHd/FWBTeImj7BhzD/+nxRh hIEwjk5WZ/TGYCqKUCbbPWE/gogPP1A5uYjeIUaQO00VQbKeNKOHLjZtAt0ApxPLyssQJzbBxdI tXdGiDUqMY/d1hdPKTW/87B2OcE15FM3iCVxIWwtsUfSj6WK6BzNgK21x/3KDqcfVxtT4TSTWQ7 NqFn4sEvkX7/rZIHUzYy9nxninJvM/oq8G7UIagtjahj221qzz1hD4xWDWpclYS0M7LLE3vGFmX ENniv0THUfuPwP4689A== X-Authority-Analysis: v=2.4 cv=Np/htcdJ c=1 sm=1 tr=0 ts=6a0ddcd1 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=pKujU25TKs9URF08bPwA:9 X-Proofpoint-ORIG-GUID: 2mekRYHVvFN4ssSvc5sqneAR6yqHb9n8 X-Proofpoint-GUID: VAvwka3T78UE0rJac4Nmh-zC4kyAt9Ka X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293513794154100 Content-Type: text/plain; charset="utf-8" From: Shivang Upadhyay Move below instructions to decodetree specification : mfcr, mfocr, mtcrf, mtocrf : XFX-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 8 +++ target/ppc/translate.c | 62 ----------------- target/ppc/translate/fixedpoint-impl.c.inc | 79 ++++++++++++++++++++++ 3 files changed, 87 insertions(+), 62 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index a4454a2292..928ae1f48b 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -70,6 +70,9 @@ %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=3D%d= x_d =20 +&XFX rt fxm +@XFX ...... rt:5 . fxm:8 ...... ..... . &XFX + %md_sh 1:1 11:5 %md_mb 5:1 6:5 &MD rs ra sh mb rc @@ -648,6 +651,11 @@ FSEL 111111 ..... ..... ..... ..... 10111 .= @A =20 ### Move To/From System Register Instructions =20 +MFCR 011111 ..... 0.... ....- 0000010011 - @XFX +MFOCR 011111 ..... 1.... ....- 0000010011 - @XFX +MTCRF 011111 ..... 0.... ....- 0010010000 - @XFX +MTOCRF 011111 ..... 1.... ....- 0010010000 - @XFX + SETBC 011111 ..... ..... ----- 0110000000 - @X_bi SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d1e9ab61e9..d5369549ee 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3131,40 +3131,6 @@ static void gen_mcrxrx(DisasContext *ctx) } #endif =20 -/* mfcr mfocrf */ -static void gen_mfcr(DisasContext *ctx) -{ - uint32_t crm, crn; - - if (likely(ctx->opcode & 0x00100000)) { - crm =3D CRM(ctx->opcode); - if (likely(crm && ((crm & (crm - 1)) =3D=3D 0))) { - crn =3D ctz32(crm); - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]= ); - tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rD(ctx->opcode)], crn * 4); - } - } else { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(t0, cpu_crf[0]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[1]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[2]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[3]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[4]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[5]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[6]); - tcg_gen_shli_i32(t0, t0, 4); - tcg_gen_or_i32(t0, t0, cpu_crf[7]); - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); - } -} - /* mfmsr */ static void gen_mfmsr(DisasContext *ctx) { @@ -3245,32 +3211,6 @@ static void gen_mftb(DisasContext *ctx) gen_op_mfspr(ctx); } =20 -/* mtcrf mtocrf*/ -static void gen_mtcrf(DisasContext *ctx) -{ - uint32_t crm, crn; - - crm =3D CRM(ctx->opcode); - if (likely((ctx->opcode & 0x00100000))) { - if (crm && ((crm & (crm - 1)) =3D=3D 0)) { - TCGv_i32 temp =3D tcg_temp_new_i32(); - crn =3D ctz32(crm); - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_shri_i32(temp, temp, crn * 4); - tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); - } - } else { - TCGv_i32 temp =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); - for (crn =3D 0 ; crn < 8 ; crn++) { - if (crm & (1 << crn)) { - tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); - tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0= xf); - } - } - } -} - /* mtmsr */ #if defined(TARGET_PPC64) static void gen_mtmsrd(DisasContext *ctx) @@ -5067,11 +5007,9 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC= _64H), GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), -GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), -GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), #if defined(TARGET_PPC64) GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 4d35133adc..d768a0454d 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -461,6 +461,85 @@ static bool trans_ADDEX(DisasContext *ctx, arg_X *a) return true; } =20 +static bool trans_MTCRF(DisasContext *ctx, arg_MTCRF *a) +{ + uint32_t crm, crn; + + crm =3D a->fxm; + + TCGv_i32 temp =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]); + + for (crn =3D 0 ; crn < 8 ; crn++) { + if (crm & (1 << crn)) { + tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); + tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); + } + } + + return true; +} + +static bool trans_MTOCRF(DisasContext *ctx, arg_MTOCRF *a) +{ + + uint32_t crm, crn; + + crm =3D a->fxm; + + /* Checking crm > 0 and set_bits(crm) =3D=3D 1 */ + if (crm && ((crm & (crm - 1)) =3D=3D 0)) { + TCGv_i32 temp =3D tcg_temp_new_i32(); + crn =3D ctz32(crm); + tcg_gen_trunc_tl_i32(temp, cpu_gpr[a->rt]); + tcg_gen_shri_i32(temp, temp, crn * 4); + tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); + } + + return true; +} + +static bool trans_MFOCR(DisasContext *ctx, arg_MFOCR *a) +{ + uint32_t crm, crn; + + crm =3D a->fxm; + + /* Checking crm > 0 and set_bits(crm) =3D=3D 1 */ + if (likely(crm && ((crm & (crm - 1)) =3D=3D 0))) { + crn =3D ctz32(crm); + tcg_gen_extu_i32_tl(cpu_gpr[a->rt], cpu_crf[7 - crn]); + tcg_gen_shli_tl(cpu_gpr[a->rt], + cpu_gpr[a->rt], crn * 4); + } + + return true; +} + +static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) +{ + + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_mov_i32(t0, cpu_crf[0]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[1]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[2]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[3]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[4]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[5]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[6]); + tcg_gen_shli_i32(t0, t0, 4); + tcg_gen_or_i32(t0, t0, cpu_crf[7]); + tcg_gen_extu_i32_tl(cpu_gpr[a->rt], t0); + + return true; +} + static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool comput= e_ca, bool compute_ov, bool compute_rc0) { --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 20 May 2026 16:09:54 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2211420040; Wed, 20 May 2026 16:09:49 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.39.31.153]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 20 May 2026 16:09:48 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=NcJx1c2+94suNm1Ft +J4YagjB0scwhW0wz30b9mK9AU=; b=dYkytajqxaiyinfDPyCQ703HdSK8C5V7E M4Ni9iU2KPzfm8eOaRp1E3oAwWzODDkDcGgvhQiX1hgdyvM45Ak3yfEQmwZVLLmq GT4ogNmcWs1WOeeNEBDpqsiIU6Bn8zjVV4ayXLLPmcW4+CGIneoO+yKp8wfQzN/v ZVBWd5Ots9UKyAv/61fyj6HpxRANqzAu1Ucc+fdChGpVS/17N9oYol0+aoKNQFZL aAKJ+YfcBJGPnpcJdUm1ZRhNQtJiMeJU8deJMMoOikj0ss69d8+RAAzWJgw/U67+ Rhp7fie2UygBCGOlSsp0tRzUAyvyd4RKXk23Q2hzgy8cPHGdEl4Dw== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 21/28] target/ppc: Move Condition Register logical instructions to decodetree. Date: Wed, 20 May 2026 21:37:21 +0530 Message-ID: <20260520160728.2283628-22-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX5yrEINEi3fmW 5lC2SP4IU+N6D0i96khrSSEZZKRQXckHDswA9OpJGfjcqVWlpuWLF/XhcRELUHxI+216UdQLZ9S 6+aSk8f7+sCLLAMAqLAy4hG+JbWqz2z1iHddmk2vra0oy3KnyS3PZkFZrHZbZRoYrZ8G8oOAZn5 wLqviuXCe2BiC0QlFhl+vrYbpLKalEq0HqtQkozkjfGHNHVqj0tAgqiN/sGypEwYnUu+uR5Hj3y qxhtQYpcPEEYD6apDsab4rjWjwndoTDRZHge14DH/v+tiH40vwSXmjd42Pl59hmHIGihgNdtqdq WXWz6HOP+PT41JrblB/wNlmylHUvfFdo+PTcnHJX2JYWDp8fXMwd8joBJ+l0rE/q9NkOrIgv5pn rlH5YhafQV6r7GmbpPeFgH5VXD4pYbmYL9KwEFOBOaMG8AA/AuVZL4aY4vKKHd7pP05SZkjVYUQ m19RX3boSsOSeCJgO7w== X-Proofpoint-GUID: kywvsF4mliCWebFig0y41bkUKpuk3bVN X-Proofpoint-ORIG-GUID: clUy0s4ax8X1RzINVJhrqYNeae436Ilb X-Authority-Analysis: v=2.4 cv=aYBRWxot c=1 sm=1 tr=0 ts=6a0ddcd7 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=hG2spAfxjb5FyaO2x7EA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293532451158500 Content-Type: text/plain; charset="utf-8" From: Shivang Upadhyay Move below instructions to decodetree specification : cr{and, or, xor, nand, nor, eqv, andc, orc} : XL-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 11 ++++ target/ppc/translate.c | 59 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 45 +++++++++++++++++ 3 files changed, 56 insertions(+), 59 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 928ae1f48b..f3a1f7970e 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -516,6 +516,17 @@ CFUGED 011111 ..... ..... ..... 0011011100 - = @X PDEPD 011111 ..... ..... ..... 0010011100 - @X PEXTD 011111 ..... ..... ..... 0010111100 - @X =20 +## Condition Register Instructions + +CRAND 010011 ..... ..... ..... 0100000001 - @X +CROR 010011 ..... ..... ..... 0111000001 - @X +CRNAND 010011 ..... ..... ..... 0011100001 - @X +CRXOR 010011 ..... ..... ..... 0011000001 - @X +CRNOR 010011 ..... ..... ..... 0000100001 - @X +CREQV 010011 ..... ..... ..... 0100100001 - @X +CRANDC 010011 ..... ..... ..... 0010000001 - @X +CRORC 010011 ..... ..... ..... 0110100001 - @X + # Fixed-Point Hash Instructions =20 HASHST 011111 ..... ..... ..... 1011010010 . @X_DW diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d5369549ee..85bdb7deab 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2920,53 +2920,6 @@ static inline void gen_setlr(DisasContext *ctx, targ= et_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/*** Condition register logical = ***/ -#define GEN_CRLOGIC(name, tcg_op, opc) = \ -static void glue(gen_, name)(DisasContext *ctx) = \ -{ = \ - uint8_t bitmask; = \ - int sh; = \ - TCGv_i32 t0, t1; = \ - sh =3D (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); = \ - t0 =3D tcg_temp_new_i32(); = \ - if (sh > 0) = \ - tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); = \ - else if (sh < 0) = \ - tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); = \ - else = \ - tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); = \ - t1 =3D tcg_temp_new_i32(); = \ - sh =3D (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); = \ - if (sh > 0) = \ - tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); = \ - else if (sh < 0) = \ - tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); = \ - else = \ - tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); = \ - tcg_op(t0, t0, t1); = \ - bitmask =3D 0x08 >> (crbD(ctx->opcode) & 0x03); = \ - tcg_gen_andi_i32(t0, t0, bitmask); = \ - tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); = \ - tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); = \ -} - -/* crand */ -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); -/* crandc */ -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); -/* creqv */ -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); -/* crnand */ -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); -/* crnor */ -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); -/* cror */ -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); -/* crorc */ -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); -/* crxor */ -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); - /*** System linkage = ***/ =20 /* rfi (supervisor only) */ @@ -5144,18 +5097,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) #endif =20 -#undef GEN_CRLOGIC -#define GEN_CRLOGIC(name, tcg_op, opc) = \ -GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), - #undef GEN_MAC_HANDLER #define GEN_MAC_HANDLER(name, opc2, opc3) = \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index d768a0454d..26b308e435 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -540,6 +540,51 @@ static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) return true; } =20 +static bool cr_logic_common(DisasContext *ctx, arg_X *a, + void (*tcg_op)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + + uint8_t bitmask; + int sh; + TCGv_i32 t0, t1; + sh =3D (a->rt & 0x03) - (a->ra & 0x03); + t0 =3D tcg_temp_new_i32(); + if (sh > 0) { + tcg_gen_shri_i32(t0, cpu_crf[a->ra >> 2], sh); + } else if (sh < 0) { + tcg_gen_shli_i32(t0, cpu_crf[a->ra >> 2], -sh); + } else { + tcg_gen_mov_i32(t0, cpu_crf[a->ra >> 2]); + } + + t1 =3D tcg_temp_new_i32(); + sh =3D (a->rt & 0x03) - (a->rb & 0x03); + if (sh > 0) { + tcg_gen_shri_i32(t1, cpu_crf[a->rb >> 2], sh); + } else if (sh < 0) { + tcg_gen_shli_i32(t1, cpu_crf[a->rb >> 2], -sh); + } else { + tcg_gen_mov_i32(t1, cpu_crf[a->rb >> 2]); + } + tcg_op(t0, t0, t1); + + bitmask =3D 0x08 >> (a->rt & 0x03); + tcg_gen_andi_i32(t0, t0, bitmask); + tcg_gen_andi_i32(t1, cpu_crf[a->rt >> 2], ~bitmask); + tcg_gen_or_i32(cpu_crf[a->rt >> 2], t0, t1); + + return true; +} + +TRANS(CRAND, cr_logic_common, tcg_gen_and_i32); +TRANS(CROR, cr_logic_common, tcg_gen_or_i32); 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=2QJ2P//OGqHj6kLB5 boQpQfdCJ/QYJGflLAeCV9uhQE=; b=MsINr864LJDPIkrNZUFn0XW0y0dq5uBn8 kRYnuHuhAx4lK6deC7S4MT7+KUOfyu0Nn1aH1pOMA9fc/qEBT6/fsekTD9FPmsbQ shWRlzF6a63tIivFm9GBZjY63GZ4Gc2CWXal71NM+KnVlJxLgEV5fN5wwkokxt6V zNt415onkItIdYcFQBw6h9A4I6MrVB+uV9utmfXXcsoci6el5kqelKHM/jsa9FIB 8L3cHKyXafXARv201ptdJHeOHqQYcBdeDbTuea85tRP5j/p9qWtAw4OFE3aGBxmc BPWKD7z0bYMDPslbaM4nw6+ElPH8FxJhwM7vhLsdBHkZj2vQ0ZWuA== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 22/28] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree. Date: Wed, 20 May 2026 21:37:22 +0530 Message-ID: <20260520160728.2283628-23-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX5N9R/MsuoAK3 e5jAGn7uHRat+uEfIhEf5T7Hp9+ZR3suuO4isGB05nTnqMHYeglyD7PZ2zYhoNxfrYLw8TEEEJC 4QSLB3m+uEC3O1WSl2PKUakPyPiqBjyHNbHwipUe2VzOv33SHoqDFPsXUPIm/SgndnpHRSyMShx BM+toSt3Hs3ecVo1PNflUqLv+7JeobsqO6TC2rRx3OqQEt/l9RZ/6ejFACCgQzZ7fR9mB7fiOgs 2sJz5Xtaj5LYU4HjvPbTTUyMb0Es2mB+rECptfRHpIatMpklfl96Lw67rBuhUQ7n65jc9u0p9JN TP0r38j3boguu5mVr3YYIXWkdnBeBzoti3TDlokMy1tboDaAAtUKrhVSWLlnDmlTNZsT4WIrZ1J ei8BJvKR73pIGhmB9OfalOO6Le4b4niIGUfB0dLN/dDgMAiq82jgTVnfMTaTjXlQX7H3Lc9uizb 5s350QQKdOYp/+dfOMg== X-Authority-Analysis: v=2.4 cv=BNuDalQG c=1 sm=1 tr=0 ts=6a0ddcde cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=6C3biiJAFINtBuO-NFUA:9 X-Proofpoint-ORIG-GUID: 08uZo1TnDPZw8s3IE8JHrl7Zp97DfPHO X-Proofpoint-GUID: UaRfm4P-NHuVlHvk3PrPdm0ZdLtMK7im X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293515971154100 Content-Type: text/plain; charset="utf-8" From: Shivang Upadhyay Move below instructions to decodetree specification : lsw{i, x}, stsw{i, x} : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 6 +- target/ppc/insn32.decode | 7 ++ target/ppc/mem_helper.c | 6 +- target/ppc/translate.c | 102 -------------------- target/ppc/translate/fixedpoint-impl.c.inc | 103 +++++++++++++++++++++ 5 files changed, 116 insertions(+), 108 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index dacc4e223e..50493a72a5 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -45,9 +45,9 @@ DEF_HELPER_1(check_tlb_flush_global, void, env) =20 DEF_HELPER_3(lmw, void, env, tl, i32) DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) -DEF_HELPER_4(lsw, void, env, tl, i32, i32) -DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32) -DEF_HELPER_FLAGS_4(stsw, TCG_CALL_NO_WG, void, env, tl, i32, i32) +DEF_HELPER_4(LSW, void, env, tl, i32, i32) +DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) +DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) DEF_HELPER_FLAGS_3(DCBZ, TCG_CALL_NO_WG, void, env, tl, int) #ifdef TARGET_PPC64 DEF_HELPER_FLAGS_2(DCBZL, TCG_CALL_NO_WG, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index f3a1f7970e..0ec9a4d5de 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -527,6 +527,13 @@ CREQV 010011 ..... ..... ..... 0100100001 - = @X CRANDC 010011 ..... ..... ..... 0010000001 - @X CRORC 010011 ..... ..... ..... 0110100001 - @X =20 +# Fixed Point Move Assist Instructions + +LSWI 011111 ..... ..... ..... 1 001010101 - @X +LSWX 011111 ..... ..... ..... 1 000010101 - @X +STSWI 011111 ..... ..... ..... 1 011010101 - @X +STSWX 011111 ..... ..... ..... 1 010010101 - @X + # Fixed-Point Hash Instructions =20 HASHST 011111 ..... ..... ..... 1011010010 . @X_DW diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 5d3d377261..303eec4ee5 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -190,7 +190,7 @@ static void do_lsw(CPUPPCState *env, target_ulong addr,= uint32_t nb, env->gpr[reg] =3D val; } =20 -void helper_lsw(CPUPPCState *env, target_ulong addr, +void helper_LSW(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) { do_lsw(env, addr, nb, reg, GETPC()); @@ -202,7 +202,7 @@ void helper_lsw(CPUPPCState *env, target_ulong addr, * this is valid, but rA won't be loaded. For now, I'll follow the * spec... */ -void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, +void helper_LSWX(CPUPPCState *env, target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb) { if (likely(xer_bc !=3D 0)) { @@ -218,7 +218,7 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, u= int32_t reg, } } =20 -void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, +void helper_STSW(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) { uintptr_t raddr =3D GETPC(); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 85bdb7deab..fc107399db 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2597,104 +2597,6 @@ static void gen_stmw(DisasContext *ctx) gen_helper_stmw(tcg_env, t0, t1); } =20 -/*** Integer load and store strings = ***/ - -/* lswi */ -/* - * PowerPC32 specification says we must generate an exception if rA is - * in the range of registers to be loaded. In an other hand, IBM says - * this is valid, but rA won't be loaded. For now, I'll follow the - * spec... - */ -static void gen_lswi(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - int nb =3D NB(ctx->opcode); - int start =3D rD(ctx->opcode); - int ra =3D rA(ctx->opcode); - int nr; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - if (nb =3D=3D 0) { - nb =3D 32; - } - nr =3D DIV_ROUND_UP(nb, 4); - if (unlikely(lsw_reg_in_range(start, nr, ra))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_register(ctx, t0); - t1 =3D tcg_constant_i32(nb); - t2 =3D tcg_constant_i32(start); - gen_helper_lsw(tcg_env, t0, t1, t2); -} - -/* lswx */ -static void gen_lswx(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2, t3; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - t1 =3D tcg_constant_i32(rD(ctx->opcode)); - t2 =3D tcg_constant_i32(rA(ctx->opcode)); - t3 =3D tcg_constant_i32(rB(ctx->opcode)); - gen_helper_lswx(tcg_env, t0, t1, t2, t3); -} - -/* stswi */ -static void gen_stswi(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - int nb =3D NB(ctx->opcode); - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_register(ctx, t0); - if (nb =3D=3D 0) { - nb =3D 32; - } - t1 =3D tcg_constant_i32(nb); - t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(tcg_env, t0, t1, t2); -} - -/* stswx */ -static void gen_stswx(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1, t2; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - t1 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t1, cpu_xer); - tcg_gen_andi_i32(t1, t1, 0x7F); - t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(tcg_env, t0, t1, t2); -} =20 #if !defined(CONFIG_USER_ONLY) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) @@ -4940,10 +4842,6 @@ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000,= PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), -GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), -GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), -GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 26b308e435..76b1011fad 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -585,6 +585,109 @@ TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32); TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32); TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32); =20 + +/*** Integer load and store strings = ***/ + +/* lswi */ +static bool trans_LSWI(DisasContext *ctx, arg_LSWI *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + int nb =3D a->rb; + int start =3D a->rt; + int ra =3D a->ra; + int nr; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + if (nb =3D=3D 0) { + nb =3D 32; + } + nr =3D DIV_ROUND_UP(nb, 4); + if (unlikely(lsw_reg_in_range(start, nr, ra))) { + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D tcg_temp_new(); + gen_addr_register(ctx, t0); + t1 =3D tcg_constant_i32(nb); + t2 =3D tcg_constant_i32(start); + gen_helper_LSW(tcg_env, t0, t1, t2); + + return true; +} + +/* lswx */ +static bool trans_LSWX(DisasContext *ctx, arg_LSWX *a) +{ + TCGv t0; + TCGv_i32 t1, t2, t3; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D tcg_temp_new(); + gen_addr_reg_index(ctx, t0); + t1 =3D tcg_constant_i32(a->rt); + t2 =3D tcg_constant_i32(a->ra); + t3 =3D tcg_constant_i32(a->rb); + gen_helper_LSWX(tcg_env, t0, t1, t2, t3); + + return true; +} + +/* stswi */ +static bool trans_STSWI(DisasContext *ctx, arg_STSWI *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + int nb =3D a->rb; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D tcg_temp_new(); + gen_addr_register(ctx, t0); + if (nb =3D=3D 0) { + nb =3D 32; + } + t1 =3D tcg_constant_i32(nb); + t2 =3D tcg_constant_i32(a->rt); + gen_helper_STSW(tcg_env, t0, t1, t2); + + return true; +} + +/* stswx */ +static bool trans_STSWX(DisasContext *ctx, arg_STSWX *a) +{ + TCGv t0; + TCGv_i32 t1, t2; + + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + t0 =3D tcg_temp_new(); + gen_addr_reg_index(ctx, t0); + t1 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t1, cpu_xer); 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b=Zpm/sBhHEQ7Ve+ZIxzQN0X7EE5TXgm7bv V0WuHmactViXcxNdOjaHQi0ydf2kEVrq7nofv7z3wJIEOt1xEGzqm0jCDwJlEHuK cV3tBtYCgqBvPMpGt/AGXzVJsL81a/kNkD4bK+oHm/fa1C0YrGwPKpzOGyOoS//2 KOz+zZe5lsMCkx4QexO5znL1miThU3hB8JL3qvCcFJD8WGtqzlKm3VCFb/8AryDN /f+XcQbMFrk3FUETKE85WxdeOli9T9O4J9BEMNJwotx6fYoMbLY/l39qlDyQ6wkL XNz0tji9OxheITdYeoI6gCSquj+u604amTD2xo0EFWFGEVZ2zEsBg== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 23/28] target/ppc: Move VMX integer arithmetic and BCD instructions to decodetree. Date: Wed, 20 May 2026 21:37:23 +0530 Message-ID: <20260520160728.2283628-24-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=ffCdDUQF c=1 sm=1 tr=0 ts=6a0ddce6 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=T2Q9oGb5wVKGsHIgCcQA:9 X-Proofpoint-ORIG-GUID: LtVTxMIdofYCMGsyeU_DT-zjP703R4_s X-Proofpoint-GUID: TWfSRoxiePQHzf1RZpeYxGZVKgWvhaLR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX/3Z4OCpGlSIW 2waEuhSU+AFkUlwQCRBdEUrNtgTU/KlE33KsPNZfc7hNyCDtoMmMnFbPUw+5fvh584JTYrPjkRt rDgs+2NYevlhg0LQn+8jAW9Wv56sXVgVTfrqw9yJ8sFYwClVrxrau4PtQ+eqNpNNCbjJsi2P6JD VWXSwZ9el9TU90i4mKhtuag3xi/Rh2Kyaow6DsYxVe6J9oZeEcl1I8DcXsO7AYQ2pHsfuXyvvWx QYzU/aSQ60pWXGTjkW//Uhwp0t1NA2kAYhyuxI1sOHG+y8mpCPcjT95hgG9BwaZHzHqiXB3vpY8 JSCNiM8b0eB0M0ZnqA0880OaiOagfb5in109cEdmF4I8Lb2tObmK9EJznwBszxh/LZ/HcBVyc2t xh2CUWf0lnGkZP3zZYScxTWBT0aA84B5wKapFxMCePTwV/6MYl62W3qP7I3bIljJfRD0C8ju0zA q1S9/4DrBZnOTgozw5w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293534465158500 Content-Type: text/plain; charset="utf-8" From: Shivang Upadhyay Move below instructions to decodetree specification : vadd{u, s}{b, h, w, d}m[.], vsub{u, s}{b, h, w, d}m[.], vmuluwm[.], vmul10{u, eu, ecu, cu}q[.] : VX-form bcd{add, sub}[.], bcd{s, us}[.], bcdcpsgn[.], bcdct{sq, n}[.], bcdcf{sq, z, n}[.], bcdctz[.], bcdsetsgn[.], bcdsr[.], bcd{u,}trunc[.] : VX-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Shivang Upadhyay Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 30 +-- target/ppc/insn32.decode | 39 ++++ target/ppc/int_helper.c | 32 ++-- target/ppc/translate/vmx-impl.c.inc | 286 +++++++++++++--------------- target/ppc/translate/vmx-ops.c.inc | 22 --- 5 files changed, 200 insertions(+), 209 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 50493a72a5..1db6f81ddc 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -350,21 +350,21 @@ DEF_HELPER_FLAGS_3(vshasigmaw, TCG_CALL_NO_RWG, void,= avr, avr, i32) DEF_HELPER_FLAGS_3(vshasigmad, TCG_CALL_NO_RWG, void, avr, avr, i32) DEF_HELPER_FLAGS_4(vpermxor, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) =20 -DEF_HELPER_FLAGS_4(bcdadd, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdsub, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfz, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctz, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdcfsq, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdctsq, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdcpsgn, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_3(bcdsetsgn, TCG_CALL_NO_RWG, i32, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcds, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdus, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdsr, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdtrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) -DEF_HELPER_FLAGS_4(bcdutrunc, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDADD, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDSUB, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFZ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTZ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCFSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDCTSQ, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDCPSGN, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_3(BCDSETSGN, TCG_CALL_NO_RWG, i32, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDUS, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDSR, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) +DEF_HELPER_FLAGS_4(BCDUTRUNC, TCG_CALL_NO_RWG, i32, avr, avr, avr, i32) =20 DEF_HELPER_4(XSADDDP, void, env, vsr, vsr, vsr) DEF_HELPER_5(xsaddqp, void, env, i32, vsr, vsr, vsr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 0ec9a4d5de..56c9f2568d 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -90,6 +90,9 @@ &VX vrt vra vrb @VX ...... vrt:5 vra:5 vrb:5 .......... . &VX =20 +&VX_ps vrt vra vrb ps +@VX_ps ...... vrt:5 vra:5 vrb:5 . ps:1 ........ . &V= X_ps + &VX_bf bf vra vrb @VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf =20 @@ -108,6 +111,9 @@ &VX_tb vrt vrb @VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb =20 +&VX_tb_ps vrt vrb ps +@VX_tb_ps ...... vrt:5 ..... vrb:5 . ps:1 ......... &VX_t= b_ps + &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X =20 @@ -991,6 +997,10 @@ VADDSBS 000100 ..... ..... ..... 01100000000 = @VX VADDSHS 000100 ..... ..... ..... 01101000000 @VX VADDSWS 000100 ..... ..... ..... 01110000000 @VX =20 +VADDUBM 000100 ..... ..... ..... 00000000000 @VX +VADDUHM 000100 ..... ..... ..... 00001000000 @VX +VADDUWM 000100 ..... ..... ..... 00010000000 @VX +VADDUDM 000100 ..... ..... ..... 00011000000 @VX VADDUBS 000100 ..... ..... ..... 01000000000 @VX VADDUHS 000100 ..... ..... ..... 01001000000 @VX VADDUWS 000100 ..... ..... ..... 01010000000 @VX @@ -1006,6 +1016,10 @@ VSUBSBS 000100 ..... ..... ..... 11100000000= @VX VSUBSHS 000100 ..... ..... ..... 11101000000 @VX VSUBSWS 000100 ..... ..... ..... 11110000000 @VX =20 +VSUBUBM 000100 ..... ..... ..... 10000000000 @VX +VSUBUHM 000100 ..... ..... ..... 10001000000 @VX +VSUBUWM 000100 ..... ..... ..... 10010000000 @VX +VSUBUDM 000100 ..... ..... ..... 10011000000 @VX VSUBUBS 000100 ..... ..... ..... 11000000000 @VX VSUBUHS 000100 ..... ..... ..... 11001000000 @VX VSUBUWS 000100 ..... ..... ..... 11010000000 @VX @@ -1099,6 +1113,13 @@ VMULHSD 000100 ..... ..... ..... 01111001001= @VX VMULHUD 000100 ..... ..... ..... 01011001001 @VX VMULLD 000100 ..... ..... ..... 00111001001 @VX =20 +VMULUWM 000100 ..... ..... ..... 00010001001 @VX + +VMUL10UQ 000100 ..... ..... ..... 01000000001 @VX +VMUL10EUQ 000100 ..... ..... ..... 01001000001 @VX +VMUL10ECUQ 000100 ..... ..... ..... 00001000001 @VX +VMUL10CUQ 000100 ..... ..... ..... 00000000001 @VX + ## Vector Multiply-Sum Instructions =20 VMSUMUBM 000100 ..... ..... ..... ..... 100100 @VA @@ -1141,6 +1162,24 @@ VPKSWSS 000100 ..... ..... ..... 0011100111 = 0 @VX VPKSDSS 000100 ..... ..... ..... 1011100111 0 @VX VPKPX 000100 ..... ..... ..... 0110000111 0 @VX =20 +## Decimal Integer Arithmetic Instructions + +BCDADD 000100 ..... ..... ..... 1.000000001 @VX_ps +BCDSUB 000100 ..... ..... ..... 1.001000001 @VX_ps +BCDUS 000100 ..... ..... ..... 10010000001 @VX +BCDS 000100 ..... ..... ..... 1.011000001 @VX_ps +BCDCTSQ 000100 ..... 00000 ..... 10110000001 @VX_tb +BCDCTN 000100 ..... 00101 ..... 10110000001 @VX_tb +BCDCFSQ 000100 ..... 00010 ..... 1.110000001 @VX_tb_ps +BCDCTZ 000100 ..... 00100 ..... 1.110000001 @VX_tb_ps +BCDCFZ 000100 ..... 00110 ..... 1.110000001 @VX_tb_ps +BCDCFN 000100 ..... 00111 ..... 1.110000001 @VX_tb_ps +BCDSETSGN 000100 ..... 11111 ..... 1.110000001 @VX_tb_ps +BCDCPSGN 000100 ..... ..... ..... 01101000001 @VX +BCDSR 000100 ..... ..... ..... 1.111000001 @VX_ps +BCDTRUNC 000100 ..... ..... ..... 1.100000001 @VX_ps +BCDUTRUNC 000100 ..... ..... ..... 10101000001 @VX + # VSX Load/Store Instructions =20 LXSD 111001 ..... ..... .............. 10 @DS diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 8e8076a92c..86346f5b9a 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -2348,7 +2348,7 @@ static void bcd_sub_mag(ppc_avr_t *t, ppc_avr_t *a, p= pc_avr_t *b, int *invalid, *overflow =3D carry; } =20 -uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) +uint32_t helper_BCDADD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) { =20 int sgna =3D bcd_get_sgn(a); @@ -2395,7 +2395,7 @@ uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, p= pc_avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) +uint32_t helper_BCDSUB(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t= ps) { ppc_avr_t bcopy =3D *b; int sgnb =3D bcd_get_sgn(b); @@ -2406,10 +2406,10 @@ uint32_t helper_bcdsub(ppc_avr_t *r, ppc_avr_t *a,= ppc_avr_t *b, uint32_t ps) } /* else invalid ... defer to bcdadd code for proper handling */ =20 - return helper_bcdadd(r, a, &bcopy, ps); + return helper_BCDADD(r, a, &bcopy, ps); } =20 -uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2445,7 +2445,7 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2479,7 +2479,7 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2523,7 +2523,7 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, ui= nt32_t ps) return cr; } =20 -uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTZ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr =3D 0; @@ -2582,7 +2582,7 @@ static inline int ucmp128(uint64_t alo, uint64_t ahi, (ahi > bhi ? 1 : -1); } =20 -uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCFSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int i; int cr; @@ -2640,7 +2640,7 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, u= int32_t ps) return cr; } =20 -uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDCTSQ(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { uint8_t i; int cr; @@ -2680,7 +2680,7 @@ uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, u= int32_t ps) return cr; } =20 -uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) +uint32_t helper_BCDCPSGN(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) { int i; int invalid =3D 0; @@ -2703,7 +2703,7 @@ uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, = ppc_avr_t *b, uint32_t ps) return bcd_cmp_zero(r); } =20 -uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDSETSGN(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) { int sgnb =3D bcd_get_sgn(b); =20 @@ -2717,7 +2717,7 @@ uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b,= uint32_t ps) return bcd_cmp_zero(r); } =20 -uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) +uint32_t helper_BCDS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) { int cr; int i =3D a->VsrSB(7); @@ -2753,7 +2753,7 @@ uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_= avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) +uint32_t helper_BCDUS(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) { int cr; int i; @@ -2790,7 +2790,7 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) +uint32_t helper_BCDSR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t p= s) { int cr; int unused =3D 0; @@ -2836,7 +2836,7 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc= _avr_t *b, uint32_t ps) return cr; } =20 -uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) +uint32_t helper_BCDTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_= t ps) { uint64_t mask; uint32_t ox_flag =3D 0; @@ -2869,7 +2869,7 @@ uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, = ppc_avr_t *b, uint32_t ps) return bcd_cmp_zero(&ret) | ox_flag; } =20 -uint32_t helper_bcdutrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32= _t ps) +uint32_t helper_BCDUTRUNC(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32= _t ps) { int i; uint64_t mask; diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 65230f3461..78ed7eccf0 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -142,7 +142,8 @@ static void gen_mtvscr(DisasContext *ctx) gen_helper_mtvscr(tcg_env, val); } =20 -static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry) +static bool do_vx_vmul10(DisasContext *ctx, arg_VX *a, + bool add_cin, bool ret_carry) { TCGv_i64 t0; TCGv_i64 t1; @@ -150,10 +151,7 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add_= cin, bool ret_carry) TCGv_i64 avr; TCGv_i64 ten, z; =20 - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } + REQUIRE_VECTOR(ctx); =20 t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); @@ -163,40 +161,33 @@ static void gen_vx_vmul10(DisasContext *ctx, bool add= _cin, bool ret_carry) z =3D tcg_constant_i64(0); =20 if (add_cin) { - get_avr64(avr, rA(ctx->opcode), false); + get_avr64(avr, a->vra, false); tcg_gen_mulu2_i64(t0, t1, avr, ten); - get_avr64(avr, rB(ctx->opcode), false); + get_avr64(avr, a->vrb, false); tcg_gen_andi_i64(t2, avr, 0xF); tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); - set_avr64(rD(ctx->opcode), avr, false); + set_avr64(a->vrt, avr, false); } else { - get_avr64(avr, rA(ctx->opcode), false); + get_avr64(avr, a->vra, false); tcg_gen_mulu2_i64(avr, t2, avr, ten); - set_avr64(rD(ctx->opcode), avr, false); + set_avr64(a->vrt, avr, false); } =20 if (ret_carry) { - get_avr64(avr, rA(ctx->opcode), true); + get_avr64(avr, a->vra, true); tcg_gen_mulu2_i64(t0, t1, avr, ten); tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); - set_avr64(rD(ctx->opcode), avr, false); - set_avr64(rD(ctx->opcode), z, true); + set_avr64(a->vrt, avr, false); + set_avr64(a->vrt, z, true); } else { - get_avr64(avr, rA(ctx->opcode), true); + get_avr64(avr, a->vra, true); tcg_gen_mul_i64(t0, avr, ten); tcg_gen_add_i64(avr, t0, t2); - set_avr64(rD(ctx->opcode), avr, true); + set_avr64(a->vrt, avr, true); } -} - -#define GEN_VX_VMUL10(name, add_cin, ret_carry) \ - static void glue(gen_, name)(DisasContext *ctx) \ - { gen_vx_vmul10(ctx, add_cin, ret_carry); } =20 -GEN_VX_VMUL10(vmul10uq, 0, 0); -GEN_VX_VMUL10(vmul10euq, 1, 0); -GEN_VX_VMUL10(vmul10cuq, 0, 1); -GEN_VX_VMUL10(vmul10ecuq, 1, 1); + return true; +} =20 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ @@ -338,19 +329,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], = rb); \ } =20 -GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); -GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ - vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) -GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1); -GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ - vmul10ecuq, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2); -GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3); -GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); -GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); -GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); -GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); - static bool do_vmrg(DisasContext *ctx, arg_VX *a, void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr)) { @@ -370,6 +348,38 @@ TRANS_FLAGS(ALTIVEC, VMRGLB, do_vmrg, gen_helper_VMRGL= B); TRANS_FLAGS(ALTIVEC, VMRGLH, do_vmrg, gen_helper_VMRGLH); TRANS_FLAGS(ALTIVEC, VMRGLW, do_vmrg, gen_helper_VMRGLW); =20 +static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX *a, MemOp vece, + void (*gen_op)(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t)) +{ + REQUIRE_VECTOR(ctx); + + gen_op(vece, + avr_full_offset(a->vrt), + avr_full_offset(a->vra), + avr_full_offset(a->vrb), + 16, 16); + + return true; +} + +TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add) +TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add) +TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add) +TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add) + +TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub) +TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub) +TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub) +TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub) + +TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul) + +TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true) +TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true) +TRANS_FLAGS2(ISA300, VMUL10UQ, do_vx_vmul10, false, false) +TRANS_FLAGS2(ISA300, VMUL10EUQ, do_vx_vmul10, true, false) + static void trans_vmrgew(DisasContext *ctx) { int VT =3D rD(ctx->opcode); @@ -684,7 +694,6 @@ static void trans_vclzd(DisasContext *ctx) set_avr64(VT, avr, false); } =20 -GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2); GEN_VXFORM(vsrv, 2, 28); GEN_VXFORM(vslv, 2, 29); GEN_VXFORM(vslo, 6, 16); @@ -2523,126 +2532,93 @@ GEN_VXFORM(vpmsumb, 4, 16) GEN_VXFORM(vpmsumh, 4, 17) GEN_VXFORM(vpmsumw, 4, 18) =20 -#define GEN_BCD(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr ra, rb, rd; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - ra =3D gen_avr_ptr(rA(ctx->opcode)); \ - rb =3D gen_avr_ptr(rB(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps =3D tcg_constant_i32((ctx->opcode & 0x200) !=3D 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ -} - -#define GEN_BCD2(op) \ -static void gen_##op(DisasContext *ctx) \ -{ \ - TCGv_ptr rd, rb; \ - TCGv_i32 ps; \ - \ - if (unlikely(!ctx->altivec_enabled)) { \ - gen_exception(ctx, POWERPC_EXCP_VPU); \ - return; \ - } \ - \ - rb =3D gen_avr_ptr(rB(ctx->opcode)); \ - rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - \ - ps =3D tcg_constant_i32((ctx->opcode & 0x200) !=3D 0); \ - \ - gen_helper_##op(cpu_crf[6], rd, rb, ps); \ -} - -GEN_BCD(bcdadd) -GEN_BCD(bcdsub) -GEN_BCD2(bcdcfn) -GEN_BCD2(bcdctn) -GEN_BCD2(bcdcfz) -GEN_BCD2(bcdctz) -GEN_BCD2(bcdcfsq) -GEN_BCD2(bcdctsq) -GEN_BCD2(bcdsetsgn) -GEN_BCD(bcdcpsgn); -GEN_BCD(bcds); -GEN_BCD(bcdus); -GEN_BCD(bcdsr); -GEN_BCD(bcdtrunc); -GEN_BCD(bcdutrunc); - -static void gen_xpnd04_1(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 5: - gen_bcdctn(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } +static bool do_bcd_ps(DisasContext *ctx, arg_VX_ps *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr ra, rb, rd; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + ps =3D tcg_constant_i32(a->ps); + + helper(cpu_crf[6], rd, ra, rb, ps); + return true; } =20 -static void gen_xpnd04_2(DisasContext *ctx) -{ - switch (opc4(ctx->opcode)) { - case 0: - gen_bcdctsq(ctx); - break; - case 2: - gen_bcdcfsq(ctx); - break; - case 4: - gen_bcdctz(ctx); - break; - case 6: - gen_bcdcfz(ctx); - break; - case 7: - gen_bcdcfn(ctx); - break; - case 31: - gen_bcdsetsgn(ctx); - break; - default: - gen_invalid(ctx); - break; - } +static bool do_bcd(DisasContext *ctx, arg_VX *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr ra, rb, rd; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + ra =3D gen_avr_ptr(a->vra); + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + ps =3D tcg_constant_i32(0); + + helper(cpu_crf[6], rd, ra, rb, ps); + return true; +} + +static bool do_bcd_tb(DisasContext *ctx, arg_VX_tb *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr rd, rb; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + + ps =3D tcg_constant_i32(0); + + helper(cpu_crf[6], rd, rb, ps); + + return true; } =20 -GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ - bcdadd, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ - bcdsub, PPC_NONE, PPC2_ALTIVEC_207) -GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ - bcds, PPC_NONE, PPC2_ISA300) -GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \ - bcdus, PPC_NONE, PPC2_ISA300) +static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb_ps *a, + void (*helper)(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32)) +{ + TCGv_ptr rd, rb; + TCGv_i32 ps; + + REQUIRE_VECTOR(ctx); + + rb =3D gen_avr_ptr(a->vrb); + rd =3D gen_avr_ptr(a->vrt); + + ps =3D tcg_constant_i32(a->ps); + + helper(cpu_crf[6], rd, rb, ps); + + return true; +} + +TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD) +TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB) +TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS) +TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS) +TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN) +TRANS_FLAGS2(ISA300, BCDCTN, do_bcd_tb, gen_helper_BCDCTN) +TRANS_FLAGS2(ISA300, BCDCFZ, do_bcd_tb_ps, gen_helper_BCDCFZ) +TRANS_FLAGS2(ISA300, BCDCTZ, do_bcd_tb_ps, gen_helper_BCDCTZ) +TRANS_FLAGS2(ISA300, BCDCFSQ, do_bcd_tb_ps, gen_helper_BCDCFSQ) +TRANS_FLAGS2(ISA300, BCDCTSQ, do_bcd_tb, gen_helper_BCDCTSQ) +TRANS_FLAGS2(ISA300, BCDSETSGN, do_bcd_tb_ps, gen_helper_BCDSETSGN) +TRANS_FLAGS2(ISA300, BCDCPSGN, do_bcd, gen_helper_BCDCPSGN) +TRANS_FLAGS2(ISA300, BCDTRUNC, do_bcd_ps, gen_helper_BCDTRUNC) +TRANS_FLAGS2(ISA300, BCDUTRUNC, do_bcd, gen_helper_BCDUTRUNC) +TRANS_FLAGS2(ISA300, BCDSR, do_bcd_ps, gen_helper_BCDSR) =20 static void gen_vsbox(DisasContext *ctx) { @@ -3502,5 +3478,3 @@ TRANS_FLAGS2(ISA310, VMODUQ, do_vx_helper, gen_helper= _VMODUQ) #undef GEN_VXFORM_NOA #undef GEN_VXFORM_UIMM #undef GEN_VAFORM_PAIRED - -#undef GEN_BCD2 diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-= ops.c.inc index 2820976c0f..c1951c6975 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -24,39 +24,17 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000= 000, type0, type1) GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, = tp1), =20 -GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vadduhm, vmul10ecuq, 0, 1, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM(vadduwm, 0, 2), -GEN_VXFORM_207(vaddudm, 0, 3), -GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), -GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_300(bcds, 0, 27), GEN_VXFORM_300(vextublx, 6, 24), GEN_VXFORM_300(vextuhlx, 6, 25), GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM_300(vextubrx, 6, 28), GEN_VXFORM_300(vextuhrx, 6, 29), GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207), -GEN_VXFORM_207(vmuluwm, 4, 2), GEN_VXFORM_300(vsrv, 2, 28), GEN_VXFORM_300(vslv, 2, 29), GEN_VXFORM(vslo, 6, 16), GEN_VXFORM(vsro, 6, 17), =20 -GEN_VXFORM(xpnd04_1, 0, 22), -GEN_VXFORM_300(bcdsr, 0, 23), -GEN_VXFORM_300(bcdsr, 0, 31), -GEN_VXFORM_300_EXT(vmul10uq, 0, 8, 0x0000F800), -GEN_VXFORM_300(vmul10euq, 0, 9), -GEN_VXFORM_300(bcdcpsgn, 0, 13), -GEN_VXFORM_207(bcdadd, 0, 24), -GEN_VXFORM_207(bcdsub, 0, 25), -GEN_VXFORM_300(bcdtrunc, 0, 28), -GEN_VXFORM_300(xpnd04_2, 0, 30), -GEN_VXFORM_300(bcdtrunc, 0, 20), -GEN_VXFORM_300(bcdutrunc, 0, 21), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vsum4ubs, 4, 24), --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org 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:mime-version:references:subject:to; s=pp1; bh=NxaymOXPa039Hkmom YBKHFY+IMU8wyTJwb6M4tLrYkw=; b=PPFysGOyuL0LU9j73UUBjPIfiodN+h16b zb9LPYnNQksEnT9RIcuWlr9Kc03gHGywq/lNQ6LT8UgfCCmLbFOppdQBK3x8mGS+ tSQ2CrVqhZdsr9VnEk65i7HJsn22GN0Yd2Vksx63cFZAzD2a1iY6uDRObCR+CuY7 LHFy2F+rHSLng9un5UO7JZGxFj5RnzYGIS7VfrVqFMhDBu+U5w6AidKeRdME3Vib mv9glmY8fWhp0knGzfTbLypx36DP8JhoyJ4AOX9A5sETILAHFOcKpyUI+xkWQLrk vcbJsy/1gJeFVxvMOSHnW4stxxSmmA+zNWFqKfTtjt9vyYijFvBwQ== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 24/28] target/ppc: Move rlwimi, rlwinm instructions to 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293524469158500 Content-Type: text/plain; charset="utf-8" From: Tanushree Shah -Moving the following instructions to decodetree specification: rlwimi : M-form rlwimi. : M-form rlwinm : M-form rlwinm. : M-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the destination register is correctly updated based on rotated and masked source values and confirmed that the value was same before and after the change Signed-off-by: Tanushree Shah Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 6 ++ target/ppc/translate.c | 106 --------------------- target/ppc/translate/fixedpoint-impl.c.inc | 98 +++++++++++++++++++ 3 files changed, 104 insertions(+), 106 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 56c9f2568d..bbce48bcbc 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -312,6 +312,9 @@ =20 @Z23_te_tbp ...... ....0 te:5 ....0 rmc:2 ........ rc:1 &Z23_te_tb= frt=3D%z23_frtp frb=3D%z23_frbp =20 +&M ra rs sh mb me rc:bool +@M ...... rs:5 ra:5 sh:5 mb:5 me:5 rc:1 &M + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D @@ -561,6 +564,9 @@ SRADI 011111 ..... ..... ..... 110011101 . . = @XS =20 EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS =20 +RLWIMI 010100 ..... ..... ..... ..... ...... @M +RLWINM 010101 ..... ..... ..... ..... ...... @M + ## BCD Assist =20 ADDG6S 011111 ..... ..... ..... - 001001010 - @X diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fc107399db..89ff4cf190 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2012,110 +2012,6 @@ static void gen_pause(DisasContext *ctx) =20 /*** Integer rotate = ***/ =20 -/* rlwimi & rlwimi. */ -static void gen_rlwimi(DisasContext *ctx) -{ - TCGv t_ra =3D cpu_gpr[rA(ctx->opcode)]; - TCGv t_rs =3D cpu_gpr[rS(ctx->opcode)]; - uint32_t sh =3D SH(ctx->opcode); - uint32_t mb =3D MB(ctx->opcode); - uint32_t me =3D ME(ctx->opcode); - - if (sh =3D=3D (31 - me) && mb <=3D me) { - tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); - } else { - target_ulong mask; - bool mask_in_32b =3D true; - TCGv t1; - -#if defined(TARGET_PPC64) - mb +=3D 32; - me +=3D 32; -#endif - mask =3D MASK(mb, me); - -#if defined(TARGET_PPC64) - if (mask > 0xffffffffu) { - mask_in_32b =3D false; - } -#endif - t1 =3D tcg_temp_new(); - if (mask_in_32b) { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rs); - tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_extu_i32_tl(t1, t0); - } else { -#if defined(TARGET_PPC64) - tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); - tcg_gen_rotli_i64(t1, t1, sh); -#else - g_assert_not_reached(); -#endif - } - - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_andi_tl(t_ra, t_ra, ~mask); - tcg_gen_or_tl(t_ra, t_ra, t1); - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, t_ra); - } -} - -/* rlwinm & rlwinm. */ -static void gen_rlwinm(DisasContext *ctx) -{ - TCGv t_ra =3D cpu_gpr[rA(ctx->opcode)]; - TCGv t_rs =3D cpu_gpr[rS(ctx->opcode)]; - int sh =3D SH(ctx->opcode); - int mb =3D MB(ctx->opcode); - int me =3D ME(ctx->opcode); - int len =3D me - mb + 1; - int rsh =3D (32 - sh) & 31; - - if (sh !=3D 0 && len > 0 && me =3D=3D (31 - sh)) { - tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); - } else if (me =3D=3D 31 && rsh + len <=3D 32) { - tcg_gen_extract_tl(t_ra, t_rs, rsh, len); - } else { - target_ulong mask; - bool mask_in_32b =3D true; -#if defined(TARGET_PPC64) - mb +=3D 32; - me +=3D 32; -#endif - mask =3D MASK(mb, me); -#if defined(TARGET_PPC64) - if (mask > 0xffffffffu) { - mask_in_32b =3D false; - } -#endif - if (mask_in_32b) { - if (sh =3D=3D 0) { - tcg_gen_andi_tl(t_ra, t_rs, mask); - } else { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_trunc_tl_i32(t0, t_rs); - tcg_gen_rotli_i32(t0, t0, sh); - tcg_gen_andi_i32(t0, t0, mask); - tcg_gen_extu_i32_tl(t_ra, t0); - } - } else { -#if defined(TARGET_PPC64) - tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); - tcg_gen_rotli_i64(t_ra, t_ra, sh); - tcg_gen_andi_i64(t_ra, t_ra, mask); -#else - g_assert_not_reached(); -#endif - } - } - if (unlikely(Rc(ctx->opcode) !=3D 0)) { - gen_set_Rc0(ctx, t_ra); - } -} - /* rlwnm & rlwnm. */ static void gen_rlwnm(DisasContext *ctx) { @@ -4833,8 +4729,6 @@ GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PP= C_NONE), GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA30= 0), GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), -GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 76b1011fad..a75ac54191 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -1874,6 +1874,104 @@ static bool trans_SRAWI(DisasContext *ctx, arg_SRAW= I *a) return true; } =20 +static bool trans_RLWIMI(DisasContext *ctx, arg_RLWIMI *a) +{ + TCGv t_ra =3D cpu_gpr[a->ra]; + TCGv t_rs =3D cpu_gpr[a->rs]; + + if (a->sh =3D=3D (31 - a->me) && a->mb <=3D a->me) { + tcg_gen_deposit_tl(t_ra, t_ra, t_rs, a->sh, a->me - a->mb + 1); + } else { + target_ulong mask; + bool mask_in_32b =3D true; + TCGv t1; + +#if defined(TARGET_PPC64) + a->mb +=3D 32; + a->me +=3D 32; +#endif + mask =3D MASK((uint32_t)a->mb, (uint32_t)a->me); + +#if defined(TARGET_PPC64) + if (mask > 0xffffffffu) { + mask_in_32b =3D false; + } +#endif + t1 =3D tcg_temp_new(); + if (mask_in_32b) { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rs); + tcg_gen_rotli_i32(t0, t0, a->sh); + tcg_gen_extu_i32_tl(t1, t0); + } else { +#if defined(TARGET_PPC64) + tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); + tcg_gen_rotli_i64(t1, t1, a->sh); +#else + g_assert_not_reached(); +#endif + } + + tcg_gen_andi_tl(t1, t1, mask); + tcg_gen_andi_tl(t_ra, t_ra, ~mask); + tcg_gen_or_tl(t_ra, t_ra, t1); + } + if (unlikely(a->rc)) { + gen_set_Rc0(ctx, t_ra); + } + return true; +} + +static bool trans_RLWINM(DisasContext *ctx, arg_RLWINM *a) +{ + TCGv t_ra =3D cpu_gpr[a->ra]; + TCGv t_rs =3D cpu_gpr[a->rs]; + int len =3D a->me - a->mb + 1; + int rsh =3D (32 - a->sh) & 31; + + if (a->sh !=3D 0 && len > 0 && a->me =3D=3D (31 - a->sh)) { + tcg_gen_deposit_z_tl(t_ra, t_rs, a->sh, len); + } else if (a->me =3D=3D 31 && rsh + len <=3D 32) { + tcg_gen_extract_tl(t_ra, t_rs, rsh, len); + } else { + target_ulong mask; + bool mask_in_32b =3D true; +#if defined(TARGET_PPC64) + a->mb +=3D 32; + a->me +=3D 32; +#endif + mask =3D MASK(a->mb, a->me); +#if defined(TARGET_PPC64) + if (mask > 0xffffffffu) { + mask_in_32b =3D false; + } +#endif + if (mask_in_32b) { + if (a->sh =3D=3D 0) { + tcg_gen_andi_tl(t_ra, t_rs, mask); + } else { + TCGv_i32 t0 =3D tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t0, t_rs); + tcg_gen_rotli_i32(t0, t0, a->sh); + tcg_gen_andi_i32(t0, t0, mask); + tcg_gen_extu_i32_tl(t_ra, t0); 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=pFb7CB4xJBW4mMK14 SxrpdTZb/pSnb6wD/azC/BSIpA=; b=E0yrSOcacR0HrElO4c9yx5XMvWkyTGWKW SYkIyMgRrHhMyqyOtWt0xTKX83Uz98hIQOiQap78tE6U2TlE6IB3U/9jK/TPwPc3 vapsUkgbcY+cQYkX4NjeG5wHdChjcOdX1n2MYiF43Pwy6mWlaxZCyDa3CWgz1WMz Rezzhbu17N2i8g7+PKhS46Ts4nf8x5QATLBADC1I0/BpNNxqKzPONcV1gexr7ao3 rgZJf6Y6jnC5QsZ4PeXb72N6eMWE55oliZBKCQbgxoIJANcjoWsG1mOI8snII1U6 zkmfwOOwfNADZ7upoHYnWe+5r/S++sGVphsnjuX57Gh1PVt8WhHMg== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 25/28] target/ppc: Move lmw, stmw instructions to decodetree Date: Wed, 20 May 2026 21:37:25 +0530 Message-ID: <20260520160728.2283628-26-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=ffCdDUQF c=1 sm=1 tr=0 ts=6a0ddcf1 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=U7nrCbtTmkRpXpFmAIza:22 a=VnNF1IyMAAAA:8 a=EKBDPzd3v7EvMxvHOJ8A:9 X-Proofpoint-ORIG-GUID: kia0dYMGnMqUT4jDqriFZTgIiFwaJrdU X-Proofpoint-GUID: hs1SUYgbon2CHIUQ52NAqRXtxuzwgKuX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX2PkvcJfBL0CY HM0zrWmixrLV68HBaj4mwz4Z/UEh5GllCGoQpBWtJQbbUzOYteaUzH56YNfyhK+t69q2qxUxFqq 8AymjU5ie55HBxT/E7VPBZ62mFKH+5rBdNrdhibZGpjfHpcA5QvCkpOAJcZI62dIuth9EU2OROB iWC5Ntlz5L7k2mTupsl5a+Nz5tQ99NP13MhhpHXbNXdOEgCUOkiU34Y3hyvOImNI63R/tP4G7JE IX+6tolBGXRJ1wgFZn/yc1VDwDi1Bsh5bUE6yPkIU+fT98lYnWbwpkuXmoegtTT8iX02hqSvT+e c2Du5J7xgDMQ28iuiyhS3QdWjKlU1hwSEGEwECSJHSbfLcsQz+/3AxNTFYoM9jPNAg/tTn5xO8q CEJfm2sIPqQGrrmtMxVuyE2+qpKmrSn58q/i+Rw3bmmlxdhiV4DSlEnsdjgUcnrccsJ85gmkoMX t7SdaYp/IWm9Ipkb13A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293544750158500 Content-Type: text/plain; charset="utf-8" From: Tanushree Shah Moving the following instructions to decodetree specification: lmw : D-form stmw : D-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the "-d in_asm,op" flag. Additionally, validated using small assembly tests confirming the the correct register store/load behavior. Also, confirmed the register values are same before and after the change. Signed-off-by: Tanushree Shah Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 4 +-- target/ppc/insn32.decode | 3 ++ target/ppc/mem_helper.c | 4 +-- target/ppc/translate.c | 39 ---------------------- target/ppc/translate/fixedpoint-impl.c.inc | 32 ++++++++++++++++++ 5 files changed, 39 insertions(+), 43 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 1db6f81ddc..22babb80e9 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -43,8 +43,8 @@ DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) #endif =20 -DEF_HELPER_3(lmw, void, env, tl, i32) -DEF_HELPER_FLAGS_3(stmw, TCG_CALL_NO_WG, void, env, tl, i32) +DEF_HELPER_3(LMW, void, env, tl, i32) +DEF_HELPER_FLAGS_3(STMW, TCG_CALL_NO_WG, void, env, tl, i32) DEF_HELPER_4(LSW, void, env, tl, i32, i32) DEF_HELPER_5(LSWX, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_4(STSW, TCG_CALL_NO_WG, void, env, tl, i32, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index bbce48bcbc..15f4a57fa0 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -354,6 +354,7 @@ LVDX 011111 ..... ..... ..... 0000010001 - = @X LSKU 111010 ..... ..... ............. 0 11 @DD LCXU 111010 ..... ..... ............. 1 11 @DD =20 +LMW 101110 ..... ..... ................ @D =20 ### Fixed-Point Atomic Load/Store Instructions =20 @@ -399,6 +400,8 @@ STBCIX 011111 ..... ..... ..... 1111010101 - @X STHBRX 011111 ..... ..... ..... 1110010110 - @X STWBRX 011111 ..... ..... ..... 1010010110 - @X =20 +STMW 101111 ..... ..... ................ @D + ### Fixed-Point Compare Instructions =20 CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 303eec4ee5..f0c44641ee 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -73,7 +73,7 @@ static void *probe_contiguous(CPUPPCState *env, target_ul= ong addr, uint32_t nb, return NULL; } =20 -void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_LMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); int mmu_idx =3D ppc_env_mmu_index(env, false); @@ -98,7 +98,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint= 32_t reg) } } =20 -void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) +void helper_STMW(CPUPPCState *env, target_ulong addr, uint32_t reg) { uintptr_t raddr =3D GETPC(); int mmu_idx =3D ppc_env_mmu_index(env, false); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 89ff4cf190..bd22b7032d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2457,43 +2457,6 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); #endif /* TARGET_PPC64 */ =20 -/*** Integer load and store multiple = ***/ - -/* lmw */ -static void gen_lmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - t1 =3D tcg_constant_i32(rD(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_lmw(tcg_env, t0, t1); -} - -/* stmw */ -static void gen_stmw(DisasContext *ctx) -{ - TCGv t0; - TCGv_i32 t1; - - if (ctx->le_mode) { - gen_align_no_le(ctx); - return; - } - gen_set_access_type(ctx, ACCESS_INT); - t0 =3D tcg_temp_new(); - t1 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_addr_imm_index(ctx, t0, 0); - gen_helper_stmw(tcg_env, t0, t1); -} - - #if !defined(CONFIG_USER_ONLY) static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { @@ -4734,8 +4697,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_= INTEGER), GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), -GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), /* ISA v3.0 changed the extended opcode from 62 to 30 */ GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), #if defined(TARGET_PPC64) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index a75ac54191..18e4a899f9 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -288,6 +288,38 @@ static bool trans_STQCX(DisasContext *ctx, arg_STQCX *= a) return true; } =20 +/* Load/Store Multiple Word */ +static bool do_ldst_multiple(DisasContext *ctx, arg_D *a, bool store) +{ + TCGv ea; + TCGv_i32 reg; + + REQUIRE_INSNS_FLAGS(ctx, INTEGER); + + /* Little-endian mode is not supported for multiple word operations */ + if (ctx->le_mode) { + gen_align_no_le(ctx); + return true; + } + + gen_set_access_type(ctx, ACCESS_INT); + + reg =3D tcg_constant_i32(a->rt); + ea =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si)); + + /* Call the appropriate helper function */ + if (store) { + gen_helper_STMW(tcg_env, ea, reg); + } else { + gen_helper_LMW(tcg_env, ea, reg); + } + + return true; +} + +TRANS(LMW, do_ldst_multiple, false) +TRANS(STMW, do_ldst_multiple, true) + /* * Fixed-Point Compare Instructions */ --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 20 May 2026 16:10:20 +0000 (GMT) Received: from li-18a0a34c-33fc-11b2-a85c-d9f1631c5692.ibm.com (unknown [9.39.31.153]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 20 May 2026 16:10:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=q4caVHg7aIV4db6NR v60MshPPR0ucxZ1ZzzA1gHlx/c=; b=UvcaaDsomIiH9AcI9gf2t6EA7dUA1OLCs I1BcOCIjrgrkIqj4XhcypwiTCg2IZYC3pViV2rJ2oxSGvNk8o8HW2Kpoz094As21 nIAkDMupewfW0tTgIX0/gYO8p7GQNn6uJbZArEqm0KBK0J1kYBvsDljoqJyJ8zkm +SczRKss64o9ppXhufRKc+9b4iLKgUusHcNGlggBojaB5gP17l93AleH1hyC1mTU nFZI9lbsdCqDZvdAwGtA+yMk6AuAjh4B57CwMP5NEpsenTRp0WDTDb+rXaUGtTQc /S39B3UZRWv5MaaW2p73AhcjiMsiRuFoisYZOJKIsQLNcykDKJcug== From: Chinmay Rath To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, npiggin@gmail.com, harshpb@linux.ibm.com, richard.henderson@linaro.org, peter.maydell@linaro.org, stefanha@redhat.com Cc: milesg@linux.ibm.com, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com, Chinmay Rath Subject: [RFC PATCH 26/28] target/ppc: Move mfmsr, mtmsr[d] instructions to decodetree Date: Wed, 20 May 2026 21:37:26 +0530 Message-ID: <20260520160728.2283628-27-rathc@linux.ibm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260520160728.2283628-1-rathc@linux.ibm.com> References: <20260520160728.2283628-1-rathc@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTIwMDE1NiBTYWx0ZWRfX571ISNfyY/ov tiS6HVuev4QJXQc8ftm/EY1EhsIqlFIUJ4foQ6JwYWSnf+mBoKP/zSzPB28HFtW1HkqOcswUYOc vkxs+WgIuX/HtZuXr2xuwjnrPKV3oa4mkvshRKGadEbm6gt/s4rDaw0ZdsiSnY9x1XcTc3yMNuc ysNq12UdziSCDzXWgma7jcj01UaAkLA2RZ1rYYNU4TXT07MiEjbJcTYQLy/W2/V2OIYH6VXBlk2 OKbIfd7o2Pj+ceGlm7iM8Pu/Tj+LCmZLC7GSLWud1gR7ymvcT3jwR4uo+mAzjdceqXbE46ns9cY pJodyTuLlJjSRNPRh6ZBYbVV9IEF4NpFy4gLMyNPeFQJDx+VWmHa7/vZQgqB2+E9dcVnwXEpoTs 20DY5DFWdT9bkrA/QjQAFjYTG2ENw0iLMjQxo7oQEVLL4/041AKYmdyG2XrMrLVw46YqnwuSM3F l11kqbobj7Rx7lg/ZiA== X-Authority-Analysis: v=2.4 cv=BNuDalQG c=1 sm=1 tr=0 ts=6a0ddcf8 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=fRY7pOLSFYBF0tKEtWUA:9 X-Proofpoint-ORIG-GUID: ZTKjzRRSpZ0HS8tAXKEKHX1E92Pj9v03 X-Proofpoint-GUID: YDmJaJ9wjUpWDTAVm8k0N-D8rAR9Em7t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-20_03,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605200156 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293485951158500 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: mfmsr : X-form mtmsr[d] : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag. This also includes improvements from review feedback: - Gate MFMSR/MTMSR on PPC_MISC via TRANS_FLAGS() - Use UINT32_MAX instead of 0xFFFFFFFF for clarity Signed-off-by: Vishal Chourasia Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 5 ++ target/ppc/translate.c | 97 ---------------------------- target/ppc/translate/misc-impl.c.inc | 64 ++++++++++++++++++ 3 files changed, 69 insertions(+), 97 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 15f4a57fa0..c5e24968e4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -315,6 +315,11 @@ &M ra rs sh mb me rc:bool @M ...... rs:5 ra:5 sh:5 mb:5 me:5 rc:1 &M =20 +### MSR +MFMSR 011111 ..... ----- ----- 0001010011 - @X_t +MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l +MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index bd22b7032d..bb7d704a6b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2845,13 +2845,6 @@ static void gen_mcrxrx(DisasContext *ctx) } #endif =20 -/* mfmsr */ -static void gen_mfmsr(DisasContext *ctx) -{ - CHK_SV(ctx); - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); -} - /* mfspr */ static inline void gen_op_mfspr(DisasContext *ctx) { @@ -2925,93 +2918,6 @@ static void gen_mftb(DisasContext *ctx) gen_op_mfspr(ctx); } =20 -/* mtmsr */ -#if defined(TARGET_PPC64) -static void gen_mtmsrd(DisasContext *ctx) -{ - if (unlikely(!is_book3s_arch2x(ctx))) { - gen_invalid(ctx); - return; - } - - CHK_SV(ctx); - -#if !defined(CONFIG_USER_ONLY) - TCGv t0, t1; - target_ulong mask; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - translator_io_start(&ctx->base); - - if (ctx->opcode & 0x00010000) { - /* L=3D1 form only updates EE and RI */ - mask =3D (1ULL << MSR_RI) | (1ULL << MSR_EE); - } else { - /* mtmsrd does not alter HV, S, ME, or LE */ - mask =3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | - (1ULL << MSR_HV)); - /* - * XXX: we need to update nip before the store if we enter - * power saving mode, we will exit the loop directly from - * ppc_store_msr - */ - gen_update_nip(ctx, ctx->base.pc_next); - } - - tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_andi_tl(t1, cpu_msr, ~mask); - tcg_gen_or_tl(t0, t0, t1); - - gen_helper_store_msr(tcg_env, t0); - - /* Must stop the translation as machine state (may have) changed */ - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -#endif /* !defined(CONFIG_USER_ONLY) */ -} -#endif /* defined(TARGET_PPC64) */ - -static void gen_mtmsr(DisasContext *ctx) -{ - CHK_SV(ctx); - -#if !defined(CONFIG_USER_ONLY) - TCGv t0, t1; - target_ulong mask =3D 0xFFFFFFFF; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - translator_io_start(&ctx->base); - if (ctx->opcode & 0x00010000) { - /* L=3D1 form only updates EE and RI */ - mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); - } else { - if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { - /* mtmsr does not alter S, ME, or LE */ - mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); - } - - /* - * XXX: we need to update nip before the store if we enter - * power saving mode, we will exit the loop directly from - * ppc_store_msr - */ - gen_update_nip(ctx, ctx->base.pc_next); - } - - tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_andi_tl(t1, cpu_msr, ~mask); - tcg_gen_or_tl(t0, t0, t1); - - gen_helper_store_msr(tcg_env, t0); - - /* Must stop the translation as machine state (may have) changed */ - ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; -#endif -} - /* mtspr */ static void gen_mtspr(DisasContext *ctx) { @@ -4713,15 +4619,12 @@ GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PP= C_64H), GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), -GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), #if defined(TARGET_PPC64) -GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), #endif -GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index 890fbb209e..54712f9b73 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -161,3 +161,67 @@ static bool trans_MCRF(DisasContext *ctx, arg_MCRF *a) tcg_gen_mov_i32(cpu_crf[a->bf], cpu_crf[a->bfa]); return true; } + +static bool do_mfmsr(DisasContext *ctx, arg_X_t *a) +{ + REQUIRE_SV(ctx); + tcg_gen_mov_tl(cpu_gpr[a->rt], cpu_msr); + return true; +} +TRANS_FLAGS(MISC, MFMSR, do_mfmsr) + +static bool do_mtmsr(DisasContext *ctx, arg_X_rs_l *a, bool is_mtmsrd) +{ + REQUIRE_SV(ctx); +#if !defined(CONFIG_USER_ONLY) + TCGv t0, t1; + target_ulong mask; + + if (is_mtmsrd) { + if (unlikely(!is_book3s_arch2x(ctx))) { + gen_invalid(ctx); + return true; + } + mask =3D ~(target_ulong)0; + } else { + mask =3D UINT32_MAX; + } + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + translator_io_start(&ctx->base); + + if (a->l) { + /* L=3D1 form only updates EE and RI */ + mask &=3D (1ULL << MSR_RI) | (1ULL << MSR_EE); + } else { + if (is_mtmsrd) { + /* mtmsrd does not alter HV, S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | + (1ULL << MSR_S) | (1ULL << MSR_HV)); + } else if (likely(!(ctx->insns_flags2 & PPC2_PPE42))) { + /* mtmsr does not alter S, ME, or LE */ + mask &=3D ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR= _S)); + } + /* + * XXX: we need to update nip before the store if we enter + * power saving mode, we will exit the loop directly from + * ppc_store_msr + */ + gen_update_nip(ctx, ctx->base.pc_next); + } + + tcg_gen_andi_tl(t0, cpu_gpr[a->rs], mask); + tcg_gen_andi_tl(t1, cpu_msr, ~mask); + tcg_gen_or_tl(t0, t0, t1); + + gen_helper_store_msr(tcg_env, t0); + + /* Must stop the translation as machine state (may have) changed */ + ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; +#endif /* !CONFIG_USER_ONLY */ + return true; +} + +TRANS_FLAGS(MISC, MTMSR, do_mtmsr, false) +TRANS64(MTMSRD, do_mtmsr, true) --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1779293501; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=rathc@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293502048158500 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: brd, brw, brh : X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag. This also includes improvements from review feedback: - Add TARGET_PPC64 guards with qemu_build_not_reached() for 32-bit builds Signed-off-by: Vishal Chourasia Signed-off-by: Chinmay Rath --- target/ppc/insn32.decode | 5 +++ target/ppc/translate.c | 35 ------------------- target/ppc/translate/fixedpoint-impl.c.inc | 40 ++++++++++++++++++++++ 3 files changed, 45 insertions(+), 35 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index c5e24968e4..6e387c4988 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -320,6 +320,11 @@ MFMSR 011111 ..... ----- ----- 0001010011 - = @X_t MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l =20 +### Fixed-Point Byte-Reverse Instructions +BRW 011111 ..... ..... ----- 0010011011 - @X_sa +BRD 011111 ..... ..... ----- 0010111011 - @X_sa +BRH 011111 ..... ..... ----- 0011011011 - @X_sa + ### Fixed-Point Load Instructions =20 LBZ 100010 ..... ..... ................ @D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index bb7d704a6b..cf8fe54bd4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4558,42 +4558,7 @@ static void gen_dform3D(DisasContext *ctx) return gen_invalid(ctx); } =20 -#if defined(TARGET_PPC64) -/* brd */ -static void gen_brd(DisasContext *ctx) -{ - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]= ); -} - -/* brw */ -static void gen_brw(DisasContext *ctx) -{ - tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]= ); - tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], = 32); - -} - -/* brh */ -static void gen_brh(DisasContext *ctx) -{ - TCGv_i64 mask =3D tcg_constant_i64(0x00ff00ff00ff00ffull); - TCGv_i64 t1 =3D tcg_temp_new_i64(); - TCGv_i64 t2 =3D tcg_temp_new_i64(); - - tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); - tcg_gen_and_i64(t2, t1, mask); - tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); - tcg_gen_shli_i64(t1, t1, 8); - tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); -} -#endif - static opcode_t opcodes[] =3D { -#if defined(TARGET_PPC64) -GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), -GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), -GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), -#endif GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA30= 0), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 18e4a899f9..9c7c754db1 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -17,6 +17,46 @@ * License along with this library; if not, see . */ =20 +/* + * Byte-Reverse Instructions + */ +static bool do_byte_reverse_X_sa(DisasContext *ctx, arg_X_sa *a, int kind) +{ +#if defined(TARGET_PPC64) + switch (kind) { + case 0: /* brd */ + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); + break; + case 1: /* brw */ + tcg_gen_bswap64_i64(cpu_gpr[a->ra], cpu_gpr[a->rs]); + tcg_gen_rotli_i64(cpu_gpr[a->ra], cpu_gpr[a->ra], 32); + break; + case 2: /* brh */ + { + TCGv_i64 mask =3D tcg_constant_i64(0x00ff00ff00ff00ffull); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + + tcg_gen_shri_i64(t1, cpu_gpr[a->rs], 8); + tcg_gen_and_i64(t2, t1, mask); + tcg_gen_and_i64(t1, cpu_gpr[a->rs], mask); + tcg_gen_shli_i64(t1, t1, 8); + tcg_gen_or_i64(cpu_gpr[a->ra], t1, t2); + break; + } + default: + g_assert_not_reached(); + } +#else + qemu_build_not_reached(); +#endif + return true; +} + +TRANS64_FLAGS2(ISA310, BRD, do_byte_reverse_X_sa, 0) +TRANS64_FLAGS2(ISA310, BRW, do_byte_reverse_X_sa, 1) +TRANS64_FLAGS2(ISA310, BRH, do_byte_reverse_X_sa, 2) + /* * Fixed-Point Load/Store Instructions */ --=20 2.53.0 From nobody Sat May 30 17:43:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=rathc@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1779293547009154100 Content-Type: text/plain; charset="utf-8" From: Vishal Chourasia Moving the following instructions to decodetree specification: sc, scv : SC-form rfi, rfid, rfscv, hrfid : XL-form This builds upon the previous work that moved mfmsr and mtmsr[d] instructions to decodetree. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the `-d in_asm,op` flag, and also by booting a pseries qemu guest. This also includes improvements from review feedback: - Rename helpers to uppercase (RFI/RFID/RFSCV/HRFID) to match ISA mnemonics - Add TRANS_FLAGS_NOT() and TRANS64_FLAGS() macro variants - Add REQUIRE_INSNS_FLAGS_NOT() check for flag exclusion - Specify lev field as uint8_t in SC instruction format - Remove redundant masking in SCV since lev is already 7-bit - Replace TARGET_PPC64 ifdefs with REQUIRE_64BIT() macro - Gate SC, SCV, RFI, RFID, RFSCV, and HRFID with appropriate flags - Replace runtime is_book3s_arch2x() check in RFI with TRANS_FLAGS_NOT(SEGM= ENT_64B) - Consolidate CONFIG_USER_ONLY guards into single block Signed-off-by: Vishal Chourasia Signed-off-by: Chinmay Rath --- target/ppc/helper.h | 8 +- target/ppc/insn32.decode | 11 +++ target/ppc/tcg-excp_helper.c | 8 +- target/ppc/translate.c | 139 ++++----------------------- target/ppc/translate/misc-impl.c.inc | 105 ++++++++++++++++++++ 5 files changed, 144 insertions(+), 127 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 22babb80e9..02d960ca6b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -11,7 +11,7 @@ DEF_HELPER_4(HASHCHKP, void, env, tl, tl, tl) #if !defined(CONFIG_USER_ONLY) DEF_HELPER_2(store_msr, void, env, tl) DEF_HELPER_1(ppc_maybe_interrupt, void, env) -DEF_HELPER_1(rfi, void, env) +DEF_HELPER_1(RFI, void, env) DEF_HELPER_1(40x_rfci, void, env) DEF_HELPER_1(rfci, void, env) DEF_HELPER_1(rfdi, void, env) @@ -19,9 +19,9 @@ DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(PMINSN, void, env, i32) -DEF_HELPER_1(rfid, void, env) -DEF_HELPER_1(rfscv, void, env) -DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_1(RFID, void, env) +DEF_HELPER_1(RFSCV, void, env) +DEF_HELPER_1(HRFID, void, env) DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 6e387c4988..b42375c364 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -199,6 +199,9 @@ &X_rs_l rs l:bool @X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l =20 +&SC lev:uint8_t +@SC ...... ..... ..... .... lev:7 ... . . &SC + &X_uim5 xt uim:uint8_t @X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt= =3D%x_xt =20 @@ -320,6 +323,14 @@ MFMSR 011111 ..... ----- ----- 0001010011 - = @X_t MTMSR 011111 ..... ---- . ----- 0010010010 - @X_rs_l MTMSRD 011111 ..... ---- . ----- 0010110010 - @X_rs_l =20 +### System Call and Return from Interrupt +SC 010001 ----- ----- ---- ....... --- 1 - @SC +SCV 010001 ----- ----- ---- ....... --- 0 1 @SC +RFI 010011 ----- ----- ----- 0000110010 - +RFID 010011 ----- ----- ----- 0000010010 - +RFSCV 010011 ----- ----- ----- 0001010010 - +HRFID 010011 ----- ----- ----- 0100010010 - + ### Fixed-Point Byte-Reverse Instructions BRW 011111 ..... ..... ----- 0010011011 - @X_sa BRD 011111 ..... ..... ----- 0010111011 - @X_sa diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index c5ccf7cf92..149a2fe745 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -527,13 +527,13 @@ static void do_rfi(CPUPPCState *env, target_ulong nip= , target_ulong msr) check_tlb_flush(env, false); } =20 -void helper_rfi(CPUPPCState *env) +void helper_RFI(CPUPPCState *env) { do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); } =20 #ifdef TARGET_PPC64 -void helper_rfid(CPUPPCState *env) +void helper_RFID(CPUPPCState *env) { /* * The architecture defines a number of rules for which bits can @@ -544,12 +544,12 @@ void helper_rfid(CPUPPCState *env) do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); } =20 -void helper_rfscv(CPUPPCState *env) +void helper_RFSCV(CPUPPCState *env) { do_rfi(env, env->lr, env->ctr); } =20 -void helper_hrfid(CPUPPCState *env) +void helper_HRFID(CPUPPCState *env) { do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index cf8fe54bd4..5dad1d970a 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2681,110 +2681,6 @@ static inline void gen_setlr(DisasContext *ctx, tar= get_ulong nip) tcg_gen_movi_tl(cpu_lr, nip); } =20 -/*** System linkage = ***/ - -/* rfi (supervisor only) */ -static void gen_rfi(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* - * This instruction doesn't exist anymore on 64-bit server - * processors compliant with arch 2.x - */ - if (is_book3s_arch2x(ctx)) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfi(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} - -#if defined(TARGET_PPC64) -static void gen_rfid(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfid(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} - -#if !defined(CONFIG_USER_ONLY) -static void gen_rfscv(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_SV(ctx); - translator_io_start(&ctx->base); - gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); - gen_helper_rfscv(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} -#endif - -static void gen_hrfid(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV(ctx); -#else - /* Restore CPU state */ - CHK_HV(ctx); - translator_io_start(&ctx->base); - gen_helper_hrfid(tcg_env); - ctx->base.is_jmp =3D DISAS_EXIT; -#endif -} -#endif - -/* sc */ -#if defined(CONFIG_USER_ONLY) -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER -#else -#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL -#endif -static void gen_sc(DisasContext *ctx) -{ - uint32_t lev; - - /* - * LEV is a 7-bit field, but the top 6 bits are treated as a reserved - * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is - * for Ultravisor which TCG does not support, so just ignore the top 6. - */ - lev =3D (ctx->opcode >> 5) & 0x1; - gen_exception_err(ctx, POWERPC_SYSCALL, lev); -} - -#if defined(TARGET_PPC64) -#if !defined(CONFIG_USER_ONLY) -static void gen_scv(DisasContext *ctx) -{ - uint32_t lev =3D (ctx->opcode >> 5) & 0x7F; - - /* Set the PC back to the faulting instruction. */ - gen_update_nip(ctx, ctx->cia); - gen_helper_scv(tcg_env, tcg_constant_i32(lev)); - - ctx->base.is_jmp =3D DISAS_NORETURN; -} -#endif -#endif - /*** Trap = ***/ =20 /* Check for unconditional traps (always or never) */ @@ -4044,6 +3940,13 @@ static int64_t dw_compose_ea(DisasContext *ctx, int = x) } \ } while (0) =20 +#define REQUIRE_INSNS_FLAGS_NOT(CTX, NAME) \ + do { \ + if (((CTX)->insns_flags & PPC_##NAME) !=3D 0) { \ + return false; \ + } \ + } while (0) + /* Then special-case the check for 64-bit so that we elide code for ppc32.= */ #if TARGET_LONG_BITS =3D=3D 32 # define REQUIRE_64BIT(CTX) return false @@ -4123,10 +4026,23 @@ static int64_t dw_compose_ea(DisasContext *ctx, int= x) REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ return FUNC(ctx, a, ##__VA_ARGS__); \ } +#define TRANS_FLAGS_NOT(FLAGS, NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { \ + REQUIRE_INSNS_FLAGS_NOT(ctx, FLAGS); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ + } =20 #define TRANS64(NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { REQUIRE_64BIT(ctx); return FUNC(ctx, a, ##__VA_ARGS__); } +#define TRANS64_FLAGS(FLAGS, NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { \ + REQUIRE_64BIT(ctx); \ + REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ + return FUNC(ctx, a, ##__VA_ARGS__); \ + } #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ { \ @@ -4568,21 +4484,6 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC= _INTEGER), GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), /* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205= ), -/* ISA v3.0 changed the extended opcode from 62 to 30 */ -GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), -#if defined(TARGET_PPC64) -GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), -#if !defined(CONFIG_USER_ONLY) -/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ -GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), -GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), -#endif -GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), -#endif -/* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ -GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), -GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), diff --git a/target/ppc/translate/misc-impl.c.inc b/target/ppc/translate/mi= sc-impl.c.inc index 54712f9b73..d41c82a998 100644 --- a/target/ppc/translate/misc-impl.c.inc +++ b/target/ppc/translate/misc-impl.c.inc @@ -225,3 +225,108 @@ static bool do_mtmsr(DisasContext *ctx, arg_X_rs_l *a= , bool is_mtmsrd) =20 TRANS_FLAGS(MISC, MTMSR, do_mtmsr, false) TRANS64(MTMSRD, do_mtmsr, true) + +/* + * System Call and Return from Interrupt Instructions + */ + +static bool do_SC(DisasContext *ctx, arg_SC *a, uint32_t excp) +{ + uint32_t lev; + + /* + * LEV is a 7-bit field, but the top 6 bits are treated as a reserved + * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is + * for Ultravisor which TCG does not support, so just ignore the top 6. + */ + lev =3D a->lev & 0x1; + gen_exception_err(ctx, excp, lev); + return true; +} + +static bool do_SCV(DisasContext *ctx, arg_SC *a) +{ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + /* Set the PC back to the faulting instruction. */ + gen_update_nip(ctx, ctx->cia); + gen_helper_scv(tcg_env, tcg_constant_i32(a->lev)); + + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + gen_invalid(ctx); + return true; +#endif +} + +/* + * Common helper for return-from-interrupt instructions + */ +enum { + RFI =3D 0, + RFID =3D 1, + HRFID =3D 2, + RFSCV =3D 3, +}; + +static bool do_rfi(DisasContext *ctx, arg_RFID *a, int kind) +{ +#if defined(CONFIG_USER_ONLY) + gen_priv_opc(ctx); + return true; +#elif defined(TARGET_PPC64) + /* Privilege check */ + switch (kind) { + case HRFID: + REQUIRE_HV(ctx); + break; + case RFI: + case RFID: + case RFSCV: + REQUIRE_SV(ctx); + break; + default: + g_assert_not_reached(); + } + + translator_io_start(&ctx->base); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); + + switch (kind) { + case RFI: + gen_helper_RFI(tcg_env); + break; + case RFID: + gen_helper_RFID(tcg_env); + break; + case HRFID: + gen_helper_HRFID(tcg_env); + break; + case RFSCV: + gen_helper_RFSCV(tcg_env); + break; + default: + g_assert_not_reached(); + } + + ctx->base.is_jmp =3D DISAS_EXIT; + return true; +#else + gen_invalid(ctx); + return true; +#endif +} + +#if defined(CONFIG_USER_ONLY) +TRANS_FLAGS(FLOW, SC, do_SC, POWERPC_EXCP_SYSCALL_USER) +#else +TRANS_FLAGS(FLOW, SC, do_SC, POWERPC_EXCP_SYSCALL) +#endif + +TRANS64_FLAGS2(ISA300, SCV, do_SCV) + +TRANS_FLAGS_NOT(SEGMENT_64B, RFI, do_rfi, RFI) +TRANS64(RFID, do_rfi, RFID) +TRANS64(HRFID, do_rfi, HRFID) +TRANS64_FLAGS2(ISA300, RFSCV, do_rfi, RFSCV) + --=20 2.53.0