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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197369; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F71HBHl1W+M/uo5lCzlKVd+GPVdXLXIc1bRDPajNYkk=; b=BqpP9Nv3mbQWT1zah90Upo4u+8M7jPzwQ4U6gYEQd8nn8T8H0zNDVbDFgkpNqfiDVObmwX buQ3W9eFGMmguB9Yw73rhKFk3jzc2aER5QFVaEVYAnJ3ZCJ/h08oXgKRR6EVu6fu6EUkvo AZWPj52yt3IfG+JFMuLT2DaUFhUPZBQ= X-MC-Unique: bt1-8tJIPlShTWHHNXs0pQ-1 X-Mimecast-MFC-AGG-ID: bt1-8tJIPlShTWHHNXs0pQ_1779197363 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 01/18] scripts: introduce scripts/update-aarch64-cpu-sysregs-header.py Date: Tue, 19 May 2026 15:27:15 +0200 Message-ID: <20260519132905.145643-2-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1779197409266158502 Content-Type: text/plain; charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc under the form of DEF(, , , , , ). We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] Signed-off-by: Eric Auger [CH: note correct op1 range, don't skip CCSIDR] Signed-off-by: Cornelia Huck Message-ID: <20251208163751.611186-2-eric.auger@redhat.com> --- scripts/update-aarch64-cpu-sysregs-header.py | 134 +++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100755 scripts/update-aarch64-cpu-sysregs-header.py diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-= aarch64-cpu-sysregs-header.py new file mode 100755 index 0000000000..8c337147dd --- /dev/null +++ b/scripts/update-aarch64-cpu-sysregs-header.py @@ -0,0 +1,134 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc +# under the form of DEF(, , , , , ) +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys + +# Some regs have op code values like 000x, 001x. Anyway we don't need +# them. Besides some regs are undesired in the generated file such as +# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we +# are interested in and are tricky to decode as their system accessor +# refer to MPIDR_EL1/MIDR_EL1 respectively + +skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value, 2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers, decode their + opcode and dump the information in target/arm/cpu-sysregs.h.inc + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [r for r in register_data if isinstance(r, dict) and \ + r.get('_type') =3D=3D 'Register'] + + idregs =3D {} + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ + crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): + idregs[reg_name] =3D encoding_str + + return idregs + +if __name__ =3D=3D "__main__": + # Single arg expected: the path to the Registers.json file + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysregs-header.py " + "") + sys.exit(1) + else: + json_file_path =3D sys.argv[1] + + extracted_registers =3D extract_idregs_from_registers_json(json_file_p= ath) + + if extracted_registers: + output_list =3D extracted_registers.items() + + # Sort by register name + sorted_output =3D sorted(output_list, key=3Dlambda item: item[0]) + + # format lines as DEF(, , , , , ) + final_output =3D "" + for reg_name, encoding in sorted_output: + reformatted_encoding =3D encoding.replace(" ", ", ") + final_output +=3D f"DEF({reg_name}, {reformatted_encoding})\n" + + with open("target/arm/cpu-sysregs.h.inc", 'w') as f: + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* This file is autogenerated by ") + f.write("scripts/update-aarch64-cpu-sysregs-header.py */\n") + f.write("/* DEF(, , , , , ) */\= n\n") + f.write(final_output) + print("updated target/arm/cpu-sysregs.h.inc") --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197376; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hf+3kiEe0IH9c2nDgWT2MpE72/lkYGGaXKwgE6gWqfo=; b=I1VuEwGHkEDUCD77V1rEVj5GLkQSFMVtCp4yhdxLEhgOcq6Iq7KlXtWM9M6MDt+15/GEFb Scd6ubnIqLVDmzS9Af3wY8wDTCZOuXb1+phSq7OBSdZbNfEnBg/gdXxCZt0Tvrr7Cqe5Hc OoZCpwCFHqNdsBP+IMmaEVQ7gwkjZeg= X-MC-Unique: Ob3yOT-zPWyVgpwba_tXdA-1 X-Mimecast-MFC-AGG-ID: Ob3yOT-zPWyVgpwba_tXdA_1779197370 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 02/18] target/arm/cpu-sysregs.h.inc: Sort by name alphabetical order Date: Tue, 19 May 2026 15:27:16 +0200 Message-ID: <20260519132905.145643-3-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Sort by register name alphabetical order. This will allow to easily diff with the future content, automatically generated. No functional change intended. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v4 -> v5: - remove spurious CCSIDR definition --- target/arm/cpu-sysregs.h.inc | 42 ++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 3d1ed40f04..a044596135 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,12 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) -DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) -DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) -DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) -DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) -DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(CLIDR_EL1, 3, 1, 0, 0, 1) +DEF(CTR_EL0, 3, 3, 0, 0, 1) +DEF(DCZID_EL0, 3, 3, 0, 0, 7) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) @@ -15,29 +14,30 @@ DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) -DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) -DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) -DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3) -DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) -DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) -DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) -DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0) DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1) DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2) DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3) DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4) DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5) -DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7) +DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) +DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) +DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) +DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7) +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6) +DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) +DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) +DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) -DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) -DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) -DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) -DEF(CLIDR_EL1, 3, 1, 0, 0, 1) -DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) -DEF(CTR_EL0, 3, 3, 0, 0, 1) -DEF(DCZID_EL0, 3, 3, 0, 0, 7) --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197384; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZqvUsFvAPzgPcejYvj5MvHW6fgWe11AjRvksKeD8RSQ=; b=Ob3Sp1d0khb4xVIb2t2FmVHAr1WpYor4F9J/A3qLV4YhKLGnIIHxg7TQSQj73TxZhkPWm6 6B9THRvlM1DfjPDFujx1zCa0wWw9kdL4fdztIgqqnPK4N+F4WrU9IAhm1NEC/yYkzDu0wV J7Tsp7ybw71TLnWoU30jMb9d3pNYSnk= X-MC-Unique: JGdXmrxGN_afjkoIgppp1Q-1 X-Mimecast-MFC-AGG-ID: JGdXmrxGN_afjkoIgppp1Q_1779197377 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 03/18] target/arm/cpu-sysregs.h.inc: Update with automatic generation Date: Tue, 19 May 2026 15:27:17 +0200 Message-ID: <20260519132905.145643-4-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1779197478273158500 Content-Type: text/plain; charset="utf-8" Generated definitions with scripts/update-aarch64-cpu-sysregs-header.py based on "AARCHMRS containing the JSON files for Arm A-profile architecture (2026-03)" Registers.json file. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h.inc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index a044596135..2188cd7be0 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -1,14 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This file is autogenerated by scripts/update-aarch64-cpu-sysregs-header= .py */ +/* DEF(, , , , , ) */ + +DEF(AIDR_EL1, 3, 1, 0, 0, 7) +DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2) +DEF(CCSIDR_EL1, 3, 1, 0, 0, 0) DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(CTR_EL0, 3, 3, 0, 0, 1) DEF(DCZID_EL0, 3, 3, 0, 0, 7) +DEF(GMID_EL1, 3, 1, 0, 0, 4) DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3) DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) @@ -38,6 +49,10 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) +DEF(MIDR_EL1, 3, 0, 0, 0, 0) +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) DEF(MVFR0_EL1, 3, 0, 0, 3, 0) DEF(MVFR1_EL1, 3, 0, 0, 3, 1) DEF(MVFR2_EL1, 3, 0, 0, 3, 2) +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197392; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dwyuT711ANFwkmoW9hE10UVAWRLP0/b2kn74eIoXpnw=; b=CZjDSAZw0gTofs/r3HUIOMhWOt6WN9+ynCKy2kfOaWNudtFX+xJFqnN3ZyHE/iUWnecmqK aWiOZabPy6kxaAe4yKop4r8zylAuEFEbUh39kHKVIb7DwNoOayCQcnRL36iE+IZ5wXqzgL MNj5Xh6RqdaT1El6KQTvT+qsa/900yw= X-MC-Unique: MebOFveqPQa4iCYe-hCsEw-1 X-Mimecast-MFC-AGG-ID: MebOFveqPQa4iCYe-hCsEw_1779197383 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 04/18] arm/cpu: Add infra to handle generated ID register definitions Date: Tue, 19 May 2026 15:27:18 +0200 Message-ID: <20260519132905.145643-5-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The known ID regs are populated in a new initialization function named initialize_cpu_sysreg_properties(). That code will be automatically generated from AARCHMRS Registers.json. For the time being let's just describe a single id reg, CTR_EL0. In this description we only care about non RES/RAZ fields, ie. named fields. The registers are populated in an array indexed by ARMIDRegisterIdx and their fields are added in a sorted list. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- v4 -> v5 - ifdef TARGET_ARM_CPU_IDREGS_H - s/g_list_append/g_list_prepend - void arm64_sysreg_add_field() --- target/arm/cpu-idregs.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 target/arm/cpu-idregs.h diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h new file mode 100644 index 0000000000..664e2d6ddd --- /dev/null +++ b/target/arm/cpu-idregs.h @@ -0,0 +1,33 @@ +/* + * handle ID registers and their fields + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef TARGET_ARM_CPU_IDREGS_H +#define TARGET_ARM_CPU_IDREGS_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + ARMIDRegisterIdx index; /* parent register, e.g. CTR_EL0_IDX */ + int shift; /* lsb of the field in the register */ + int length; /* highest bit number */ +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMIDRegisterIdx index; /* register index, e.g. CTR_EL0_IDX */ + struct ARM64SysRegField *fields; + uint32_t fields_count; +} ARM64SysReg; + +/* + * List of exposed ID regs (automatically populated from AARCHMRS Register= s.json) + */ +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +#endif --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197474; cv=none; d=zohomail.com; s=zohoarc; b=ZHw3qs7rrT7G72mWQa11Em+P6lXjGnLSvem1oHHj6RUsQASstXqwOBmFY8Ovu112UokpR/ts5M+uWQCgsrUNbZ4S2bJEkkyfHdPOaEPYXv0Zwr1BPnd7hp7iJhpylpcaQwnTf01Y+tja8bqhhOCx60ATaEDUr0/b2Ow1V+K2wvs= ARC-Message-Signature: i=1; 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charset="utf-8" We plan to reuse get_opcode() and extract_idregs_from_registers_json() functions in another script. So let's move them into a module No functional change intended. Signed-off-by: Eric Auger --- scripts/aarch64_sysreg_helpers.py | 109 +++++++++++++++++++ scripts/update-aarch64-cpu-sysregs-header.py | 85 +-------------- 2 files changed, 110 insertions(+), 84 deletions(-) create mode 100644 scripts/aarch64_sysreg_helpers.py diff --git a/scripts/aarch64_sysreg_helpers.py b/scripts/aarch64_sysreg_hel= pers.py new file mode 100644 index 0000000000..dd5ec4bafa --- /dev/null +++ b/scripts/aarch64_sysreg_helpers.py @@ -0,0 +1,109 @@ +#!/usr/bin/env python3 + +# Helpers used in aarch64 sysreg definition generation +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os + +# Some regs have op code values like 000x, 001x. Anyway we don't need +# them. Besides some regs are undesired in the generated file such as +# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we +# are interested in and are tricky to decode as their system accessor +# refer to MPIDR_EL1/MIDR_EL1 respectively + +skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value, 2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers, decode their + opcode and dump the information in target/arm/cpu-sysregs.h.inc + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [r for r in register_data if isinstance(r, dict) and \ + r.get('_type') =3D=3D 'Register'] + + idregs =3D {} + + # Some regs have op code values like 000x, 001x. Anyway we don't need + # them. Besides some regs are undesired in the generated file such as + # VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we + # are interested in and are tricky to decode as their system accessor + # refer to MPIDR_EL1/MIDR_EL1 respectively + + skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'VMPIDR_EL2', 'VPIDR_EL2'] + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ + crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): + idregs[reg_name] =3D encoding_str + + return idregs + + + diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-= aarch64-cpu-sysregs-header.py index 8c337147dd..43107264e9 100755 --- a/scripts/update-aarch64-cpu-sysregs-header.py +++ b/scripts/update-aarch64-cpu-sysregs-header.py @@ -17,90 +17,7 @@ import json import os import sys - -# Some regs have op code values like 000x, 001x. Anyway we don't need -# them. Besides some regs are undesired in the generated file such as -# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we -# are interested in and are tricky to decode as their system accessor -# refer to MPIDR_EL1/MIDR_EL1 respectively - -skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ - 'VMPIDR_EL2', 'VPIDR_EL2'] - -# returns the int value of a given @opcode for a reg @encoding -def get_opcode(encoding, opcode): - fvalue =3D encoding.get(opcode) - if fvalue: - value =3D fvalue.get('value') - if isinstance(value, str): - value =3D value.strip("'") - value =3D int(value, 2) - return value - return -1 - -def extract_idregs_from_registers_json(filename): - """ - Load a Registers.json file and extract all ID registers, decode their - opcode and dump the information in target/arm/cpu-sysregs.h.inc - - Args: - filename (str): The path to the Registers.json - returns: - idregs: list of ID regs and their encoding - """ - if not os.path.exists(filename): - print(f"Error: {filename} could not be found!") - return {} - - try: - with open(filename, 'r') as f: - register_data =3D json.load(f) - - except json.JSONDecodeError: - print(f"Could not decode json from '{filename}'!") - return {} - except Exception as e: - print(f"Unexpected error while reading {filename}: {e}") - return {} - - registers =3D [r for r in register_data if isinstance(r, dict) and \ - r.get('_type') =3D=3D 'Register'] - - idregs =3D {} - - for register in registers: - reg_name =3D register.get('name') - - is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) - - if reg_name and not is_skipped: - accessors =3D register.get('accessors', []) - - for accessor in accessors: - type =3D accessor.get('_type') - if type in ['Accessors.SystemAccessor']: - encoding_list =3D accessor.get('encoding') - - if isinstance(encoding_list, list) and encoding_list a= nd \ - isinstance(encoding_list[0], dict): - encoding_wrapper =3D encoding_list[0] - encoding_source =3D encoding_wrapper.get('encoding= s', \ - encoding_wr= apper) - - if isinstance(encoding_source, dict): - op0 =3D get_opcode(encoding_source, 'op0') - op1 =3D get_opcode(encoding_source, 'op1') - op2 =3D get_opcode(encoding_source, 'op2') - crn =3D get_opcode(encoding_source, 'CRn') - crm =3D get_opcode(encoding_source, 'CRm') - encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" - - # ID regs are assumed within this scope - if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ - crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): - idregs[reg_name] =3D encoding_str - - return idregs +from aarch64_sysreg_helpers import extract_idregs_from_registers_json =20 if __name__ =3D=3D "__main__": # Single arg expected: the path to the Registers.json file --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197402; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=G2Xr+fTzJIcnFDLkVVYJvYLH1jE72SWzHC7DC1a1qLo=; b=GUobG6ezIWc/UJyqwPPWyTysVMqCKB8kUab8o87y1HVe/w7ImrP6+ip6XJOjsuHdN1Dckk fC7DDvIKV01zfPB8LYXEBx5vAF0Ern9RlkAt8AygH6V5YCGvDlXDN2gKt68haRSnzhop8W 5+tsMhPYwal6+719kG6OWG1s9gde2zc= X-MC-Unique: bKHvwoyVNR2ZGeg1BBuAZQ-1 X-Mimecast-MFC-AGG-ID: bKHvwoyVNR2ZGeg1BBuAZQ_1779197397 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 06/18] scripts: Introduce scripts/update-aarch64-cpu-sysreg-properties.py Date: Tue, 19 May 2026 15:27:20 +0200 Message-ID: <20260519132905.145643-7-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1779197455144154100 Content-Type: text/plain; charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and automates the generation of system register properties definitions. generates target/arm/cpu-idregs.h.inc containing definitions for feature ID registers. We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 =3D {0,1,3}, crn =3D 0, crm within [0, 7], op2 within [0, 7] Signed-off-by: Eric Auger --- .../update-aarch64-cpu-sysreg-properties.py | 168 ++++++++++++++++++ 1 file changed, 168 insertions(+) create mode 100644 scripts/update-aarch64-cpu-sysreg-properties.py diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/upda= te-aarch64-cpu-sysreg-properties.py new file mode 100644 index 0000000000..3571e228ee --- /dev/null +++ b/scripts/update-aarch64-cpu-sysreg-properties.py @@ -0,0 +1,168 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs target/arm/cpu-sysreg-properties.c content. +# There, initialize_cpu_sysreg_properties() populates arm64_id_regs array +# with the name of each ID register and definition of all its fields +# including their name and min/max bit under the form of the below pattern: +# +# /* CCSIDR2_EL1 */ +# ARM64SysReg *CCSIDR2_EL1 =3D arm64_sysreg_get(CCSIDR2_EL1_IDX); +# CCSIDR2_EL1->name =3D "CCSIDR2_EL1"; +# arm64_sysreg_add_field(CCSIDR2_EL1, "NumSets", 0, 23); +# +# Copyright (C) 2026 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys +from aarch64_sysreg_helpers import extract_idregs_from_registers_json + +def collect_fields(item, bit_offset=3D0): + """ + Recursively finds all field-like objects, handling Fields.Array, + Fields.ArrayField, and ConditionalField structures. + Applies bit_offset from containers to child fields. + """ + fields =3D [] + if not isinstance(item, dict): + return fields + + _type =3D item.get('_type', '') + + # Array types (for example CLIDR_EL1 Ctype, Ttype) + if _type =3D=3D 'Fields.Array': + name_template =3D item.get('name') or item.get('label', '') + index_info =3D item.get('indexes', [{}])[0] + start_idx =3D index_info.get('start', 0) + count =3D index_info.get('width', 0) + + full_range =3D item.get('rangeset', [{}])[0] + bit_start =3D full_range.get('start', 0) + bit_offset + elem_width =3D full_range.get('width', 0) // count if count else 0 + + for i in range(count): + idx =3D start_idx + i + # Correctly handle indexed names like Ctype1, Ctype2 + field_name =3D name_template.replace('', str(idx)) + fields.append({ + 'name': field_name, + 'rangeset': [{ + 'start': bit_start + (i * elem_width), + 'width': elem_width + }], + '_type': 'Fields.Field' + }) + return fields + + # ConditionalFields + elif _type =3D=3D 'Fields.ConditionalField': + inner_offset =3D bit_offset + if item.get('rangeset'): + # Parent container defines the absolute start bit + inner_offset =3D item['rangeset'][0].get('start', bit_offset) + + for entry in item.get('fields', []): + inner =3D entry.get('field') + if inner: + fields.extend(collect_fields(inner, inner_offset)) + return fields + + # Normal Field Types + leaf_types =3D ['Fields.Field', 'Fields.ConstantField', + 'Fields.EnumeratedField', 'Fields.Bitfield'] + if _type in leaf_types: + field_copy =3D item.copy() + if field_copy.get('rangeset'): + new_ranges =3D [] + for r in field_copy['rangeset']: + nr =3D r.copy() + # Apply the cumulative offset to the field's start bit + nr['start'] =3D r.get('start', 0) + bit_offset + new_ranges.append(nr) + field_copy['rangeset'] =3D new_ranges + fields.append(field_copy) + return fields + + # Traverse the hierarchy for other cases + for key in ['fields', 'values', 'fieldsets']: + for nested in item.get(key, []): + fields.extend(collect_fields(nested, bit_offset)) + + return fields + + +def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_= path): + with open(raw_json_path, 'r') as f: + register_data =3D json.load(f) + + regs =3D {r.get('name'): r for r in register_data if r.get('_type') = =3D=3D 'Register'} + + final_output =3D "" + + for reg_name in id_reg_names: + register =3D regs.get(reg_name) + if not register: + continue + + final_output +=3D f" IDREG_START({reg_name})\n" + + unique_fields =3D {} + for fieldset in register.get('fieldsets', []): + candidates =3D collect_fields(fieldset) + for val in candidates: + name =3D (val.get('name') or val.get('label', '')).strip() + if not name or "RESERVED" in name.upper(): + continue + for r in val.get('rangeset', []): + lsb =3D int(r.get('start')) + width =3D r.get('width') + msb =3D lsb + int(width) - 1 + + # Only keep the fields with the highest MSB + # needed fir CCSIDR_EL1 + if name not in unique_fields or msb > unique_fields[na= me]['msb']: + unique_fields[name] =3D {'lsb': lsb, 'msb': msb, '= width': width} + + # Sort decreasing lsbs + sorted_fields =3D sorted(unique_fields.items(), + key=3Dlambda x: x[1]['lsb'], reverse=3DTrue) + + for name, bits in sorted_fields: + line =3D (f" IDREG_FIELD({reg_name}, " + f"{name}, {bits['lsb']}, {bits['width']})\n") + final_output +=3D line + final_output +=3D f" IDREG_END({reg_name})\n" + final_output +=3D "\n" + + os.makedirs("target/arm", exist_ok=3DTrue) + with open("target/arm/cpu-idregs.h.inc", 'w') as f: + f.write("/* AUTOMATICALLY GENERATED, DO NOT MODIFY */\n\n") + f.write("/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n") + f.write("/* IDREG_START(REG) */\n") + f.write("/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */\n") + f.write("/* ... */\n") + f.write("/* IDREG_END(REG) */\n\n") + f.write(final_output) + +if __name__ =3D=3D "__main__": + if len(sys.argv) < 2: + print("Usage: python scripts/update-aarch64-cpu-sysreg-properties.= py " + "") + else: + json_path =3D sys.argv[1] + + id_regs_dict =3D extract_idregs_from_registers_json(json_path) + sorted_names =3D sorted(id_regs_dict.keys()) + + if sorted_names: + generate_sysreg_properties_from_registers_json(sorted_names, j= son_path) + print("Generated target/arm/cpu-idregs.h.inc") --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5IlFfeHJI6VWJEgM1XDgThIEo/nP1HST0muCCuvkW7Y=; b=TgizWBrj36y6r1wi49PPIhEV1aa2Fd7aHu9uEt1hyy9e2Bzi47Xx5/YuNuV+HN2BLZ3t1U 8tQ4xxPR3BggrZU56NOZFF4naO/8AXvTV0PnvINrD1A2eSau+coOzPVv7AVWknGSDwUq2h 3Wnm6xZdQmZIKyGpnx71UEFsGvnasQ8= X-MC-Unique: SjugwpkEOdaoMAeOF790Dw-1 X-Mimecast-MFC-AGG-ID: SjugwpkEOdaoMAeOF790Dw_1779197403 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 07/18] target/arm/cpu-idregs.h.inc: generate with script Date: Tue, 19 May 2026 15:27:21 +0200 Message-ID: <20260519132905.145643-8-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Generate ID reg definitions with the scripts/update-aarch64-cpu-sysreg-prop= erties.py based on AARCHMRS_OPENSOURCE_A_profile_FAT-2026-03 Registers.json Each register and fields are described with this pattern: IDREG_START(REG) IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) ... IDREG_END(REG) Signed-off-by: Eric Auger Suggested-by: Khushit Shah Suggested-by: Shaju Abraham --- target/arm/cpu-idregs.h.inc | 617 ++++++++++++++++++++++++++++++++++++ 1 file changed, 617 insertions(+) create mode 100644 target/arm/cpu-idregs.h.inc diff --git a/target/arm/cpu-idregs.h.inc b/target/arm/cpu-idregs.h.inc new file mode 100644 index 0000000000..7832c52ef7 --- /dev/null +++ b/target/arm/cpu-idregs.h.inc @@ -0,0 +1,617 @@ +/* AUTOMATICALLY GENERATED, DO NOT MODIFY */ + +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* IDREG_START(REG) */ +/* IDREG_FIELD(REG, FIELD, SHIFT, LENGTH) */ +/* ... */ +/* IDREG_END(REG) */ + + IDREG_START(AIDR_EL1) + IDREG_END(AIDR_EL1) + + IDREG_START(CCSIDR2_EL1) + IDREG_FIELD(CCSIDR2_EL1, NumSets, 0, 24) + IDREG_END(CCSIDR2_EL1) + + IDREG_START(CCSIDR_EL1) + IDREG_FIELD(CCSIDR_EL1, NumSets, 32, 24) + IDREG_FIELD(CCSIDR_EL1, Associativity, 3, 21) + IDREG_FIELD(CCSIDR_EL1, LineSize, 0, 3) + IDREG_END(CCSIDR_EL1) + + IDREG_START(CLIDR_EL1) + IDREG_FIELD(CLIDR_EL1, Ttype7, 45, 2) + IDREG_FIELD(CLIDR_EL1, Ttype6, 43, 2) + IDREG_FIELD(CLIDR_EL1, Ttype5, 41, 2) + IDREG_FIELD(CLIDR_EL1, Ttype4, 39, 2) + IDREG_FIELD(CLIDR_EL1, Ttype3, 37, 2) + IDREG_FIELD(CLIDR_EL1, Ttype2, 35, 2) + IDREG_FIELD(CLIDR_EL1, Ttype1, 33, 2) + IDREG_FIELD(CLIDR_EL1, ICB, 30, 3) + IDREG_FIELD(CLIDR_EL1, LoUU, 27, 3) + IDREG_FIELD(CLIDR_EL1, LoC, 24, 3) + IDREG_FIELD(CLIDR_EL1, LoUIS, 21, 3) + IDREG_FIELD(CLIDR_EL1, Ctype7, 18, 3) + IDREG_FIELD(CLIDR_EL1, Ctype6, 15, 3) + IDREG_FIELD(CLIDR_EL1, Ctype5, 12, 3) + IDREG_FIELD(CLIDR_EL1, Ctype4, 9, 3) + IDREG_FIELD(CLIDR_EL1, Ctype3, 6, 3) + IDREG_FIELD(CLIDR_EL1, Ctype2, 3, 3) + IDREG_FIELD(CLIDR_EL1, Ctype1, 0, 3) + IDREG_END(CLIDR_EL1) + + IDREG_START(CTR_EL0) + IDREG_FIELD(CTR_EL0, TminLine, 32, 6) + IDREG_FIELD(CTR_EL0, DIC, 29, 1) + IDREG_FIELD(CTR_EL0, IDC, 28, 1) + IDREG_FIELD(CTR_EL0, CWG, 24, 4) + IDREG_FIELD(CTR_EL0, ERG, 20, 4) + IDREG_FIELD(CTR_EL0, DminLine, 16, 4) + IDREG_FIELD(CTR_EL0, L1Ip, 14, 2) + IDREG_FIELD(CTR_EL0, IminLine, 0, 4) + IDREG_END(CTR_EL0) + + IDREG_START(DCZID_EL0) + IDREG_FIELD(DCZID_EL0, TBS, 5, 4) + IDREG_FIELD(DCZID_EL0, DZP, 4, 1) + IDREG_FIELD(DCZID_EL0, BS, 0, 4) + IDREG_END(DCZID_EL0) + + IDREG_START(GMID_EL1) + IDREG_FIELD(GMID_EL1, BS, 0, 4) + IDREG_END(GMID_EL1) + + IDREG_START(ID_AA64AFR0_EL1) + IDREG_END(ID_AA64AFR0_EL1) + + IDREG_START(ID_AA64AFR1_EL1) + IDREG_END(ID_AA64AFR1_EL1) + + IDREG_START(ID_AA64DFR0_EL1) + IDREG_FIELD(ID_AA64DFR0_EL1, HPMN0, 60, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, ExtTrcBuff, 56, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRBE, 52, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, MTPMU, 48, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceBuffer, 44, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceFilt, 40, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DoubleLock, 36, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSVer, 32, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMSS, 16, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, PMUVer, 8, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, TraceVer, 4, 4) + IDREG_FIELD(ID_AA64DFR0_EL1, DebugVer, 0, 4) + IDREG_END(ID_AA64DFR0_EL1) + + IDREG_START(ID_AA64DFR1_EL1) + IDREG_FIELD(ID_AA64DFR1_EL1, ABL_CMPs, 56, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, DPFZS, 52, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, EBEP, 48, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ITE, 44, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, ABLE, 40, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, PMICNTR, 36, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, SPMU, 32, 4) + IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8) + IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8) + IDREG_END(ID_AA64DFR1_EL1) + + IDREG_START(ID_AA64DFR2_EL1) + IDREG_FIELD(ID_AA64DFR2_EL1, TRBE_EXC, 24, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_nVM, 20, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, SPE_EXC, 16, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, BWE, 4, 4) + IDREG_FIELD(ID_AA64DFR2_EL1, STEP, 0, 4) + IDREG_END(ID_AA64DFR2_EL1) + + IDREG_START(ID_AA64FPFR0_EL1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8CVT, 31, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8FMA, 30, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP4, 29, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8DP2, 28, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM8, 27, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8MM4, 26, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F16MM2, 15, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E4M3, 1, 1) + IDREG_FIELD(ID_AA64FPFR0_EL1, F8E5M2, 0, 1) + IDREG_END(ID_AA64FPFR0_EL1) + + IDREG_START(ID_AA64ISAR0_EL1) + IDREG_FIELD(ID_AA64ISAR0_EL1, RNDR, 60, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TLB, 56, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, TS, 52, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, FHM, 48, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, DP, 44, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SM3, 36, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, RDM, 28, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, Atomic, 20, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_AA64ISAR0_EL1, AES, 4, 4) + IDREG_END(ID_AA64ISAR0_EL1) + + IDREG_START(ID_AA64ISAR1_EL1) + IDREG_FIELD(ID_AA64ISAR1_EL1, LS64, 60, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, XS, 56, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, I8MM, 52, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DGH, 48, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, BF16, 44, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SPECRES, 40, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, SB, 36, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FRINTTS, 32, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPI, 28, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, GPA, 24, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, LRCPC, 20, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, FCMA, 16, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, JSCVT, 12, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, API, 8, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, APA, 4, 4) + IDREG_FIELD(ID_AA64ISAR1_EL1, DPB, 0, 4) + IDREG_END(ID_AA64ISAR1_EL1) + + IDREG_START(ID_AA64ISAR2_EL1) + IDREG_FIELD(ID_AA64ISAR2_EL1, ATS1A, 60, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, LUT, 56, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CSSC, 52, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRFM, 48, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PCDPHINT, 44, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PRFMSLC, 40, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSINSTR_128, 36, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, SYSREG_128, 32, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, PAC_frac, 24, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, BC, 20, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, MOPS, 16, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, APA3, 12, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, GPA3, 8, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, RPRES, 4, 4) + IDREG_FIELD(ID_AA64ISAR2_EL1, WFxT, 0, 4) + IDREG_END(ID_AA64ISAR2_EL1) + + IDREG_START(ID_AA64ISAR3_EL1) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCP, 44, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSCSHINT, 40, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, MTETC, 36, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PAC_frac2, 32, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FPRCVT, 28, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSUI, 24, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, OCCMO, 20, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, LSFE, 16, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, PACM, 12, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, TLBIW, 8, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, FAMINMAX, 4, 4) + IDREG_FIELD(ID_AA64ISAR3_EL1, CPA, 0, 4) + IDREG_END(ID_AA64ISAR3_EL1) + + IDREG_START(ID_AA64MMFR0_EL1) + IDREG_FIELD(ID_AA64MMFR0_EL1, ECV, 60, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, FGT, 56, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ExS, 44, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4_2, 40, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16_2, 32, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran4, 28, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran64, 24, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, TGran16, 20, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEndEL0, 16, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, SNSMem, 12, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, BigEnd, 8, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, ASIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR0_EL1, PARange, 0, 4) + IDREG_END(ID_AA64MMFR0_EL1) + + IDREG_START(ID_AA64MMFR1_EL1) + IDREG_FIELD(ID_AA64MMFR1_EL1, ECBHB, 60, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, CMOW, 56, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TIDCP1, 52, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, nTLBPA, 48, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, AFP, 44, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HCX, 40, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, ETS, 36, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, TWED, 32, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, XNX, 28, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, SpecSEI, 24, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, PAN, 20, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, LO, 16, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HPDS, 12, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VH, 8, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, VMIDBits, 4, 4) + IDREG_FIELD(ID_AA64MMFR1_EL1, HAFDBS, 0, 4) + IDREG_END(ID_AA64MMFR1_EL1) + + IDREG_START(ID_AA64MMFR2_EL1) + IDREG_FIELD(ID_AA64MMFR2_EL1, E0PD, 60, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, EVT, 56, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, BBM, 52, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, TTL, 48, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, FWB, 40, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IDS, 36, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, AT, 32, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, ST, 28, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, NV, 24, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CCIDX, 20, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, VARange, 16, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, IESB, 12, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, LSM, 8, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, UAO, 4, 4) + IDREG_FIELD(ID_AA64MMFR2_EL1, CnP, 0, 4) + IDREG_END(ID_AA64MMFR2_EL1) + + IDREG_START(ID_AA64MMFR3_EL1) + IDREG_FIELD(ID_AA64MMFR3_EL1, Spec_FPACC, 60, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ADERR, 56, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SDERR, 52, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, ANERR, 44, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SNERR, 40, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128_2, 36, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, D128, 32, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, MEC, 28, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, AIE, 24, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2POE, 20, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1POE, 16, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S2PIE, 12, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, S1PIE, 8, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, SCTLRX, 4, 4) + IDREG_FIELD(ID_AA64MMFR3_EL1, TCRX, 0, 4) + IDREG_END(ID_AA64MMFR3_EL1) + + IDREG_START(ID_AA64MMFR4_EL1) + IDREG_FIELD(ID_AA64MMFR4_EL1, MTEFGT, 60, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SCRX, 56, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TEV, 52, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TPS, 48, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, SRMASK, 44, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, TLBID, 40, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E3DSE, 36, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EAESR, 32, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, RMEGDI, 28, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, E2H0, 24, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, NV_frac, 20, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, FGWTE3, 16, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, HACDBS, 12, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, ASID2, 8, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, EIESB, 4, 4) + IDREG_FIELD(ID_AA64MMFR4_EL1, PoPS, 0, 4) + IDREG_END(ID_AA64MMFR4_EL1) + + IDREG_START(ID_AA64PFR0_EL1) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV3, 60, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, CSV2, 56, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RME, 52, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, DIT, 48, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AMU, 44, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, MPAM, 40, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SEL2, 36, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, SVE, 32, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, GIC, 24, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, AdvSIMD, 20, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, FP, 16, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL3, 12, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL2, 8, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL1, 4, 4) + IDREG_FIELD(ID_AA64PFR0_EL1, EL0, 0, 4) + IDREG_END(ID_AA64PFR0_EL1) + + IDREG_START(ID_AA64PFR1_EL1) + IDREG_FIELD(ID_AA64PFR1_EL1, PFAR, 60, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, DF2, 56, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTEX, 52, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, THE, 48, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, GCS, 44, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE_frac, 40, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, NMI, 36, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, CSV2_frac, 32, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RNDR_trap, 28, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SME, 24, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MPAM_frac, 16, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, RAS_frac, 12, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, MTE, 8, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_AA64PFR1_EL1, BT, 0, 4) + IDREG_END(ID_AA64PFR1_EL1) + + IDREG_START(ID_AA64PFR2_EL1) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETCL, 44, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTETC, 40, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, VMTE, 36, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FPMR, 32, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MPAM2, 28, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, FGDT, 24, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEEIRG, 20, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, UINJ, 16, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, GCIE, 12, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEFAR, 8, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTESTOREONLY, 4, 4) + IDREG_FIELD(ID_AA64PFR2_EL1, MTEPERM, 0, 4) + IDREG_END(ID_AA64PFR2_EL1) + + IDREG_START(ID_AA64SMFR0_EL1) + IDREG_FIELD(ID_AA64SMFR0_EL1, FA64, 63, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUT6, 61, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, LUTv2, 60, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMEver, 56, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I64, 52, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F64F64, 48, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I16I32, 44, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16B16, 43, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F16, 42, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F16, 41, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F8F32, 40, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, I8I32, 36, 4) + IDREG_FIELD(ID_AA64SMFR0_EL1, F16F32, 35, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, B16F32, 34, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, BI32I32, 33, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, F32F32, 32, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8FMA, 30, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP4, 29, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SF8DP2, 28, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SBitPerm, 25, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, AES, 24, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SFEXPA, 23, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, STMOP, 16, 1) + IDREG_FIELD(ID_AA64SMFR0_EL1, SMOP4, 0, 1) + IDREG_END(ID_AA64SMFR0_EL1) + + IDREG_START(ID_AA64ZFR0_EL1) + IDREG_FIELD(ID_AA64ZFR0_EL1, F64MM, 56, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F32MM, 52, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, F16MM, 48, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, I8MM, 44, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SM4, 40, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SHA3, 32, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, B16B16, 24, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BF16, 20, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, BitPerm, 16, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, EltPerm, 12, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, AES, 4, 4) + IDREG_FIELD(ID_AA64ZFR0_EL1, SVEver, 0, 4) + IDREG_END(ID_AA64ZFR0_EL1) + + IDREG_START(ID_AFR0_EL1) + IDREG_END(ID_AFR0_EL1) + + IDREG_START(ID_DFR0_EL1) + IDREG_FIELD(ID_DFR0_EL1, TraceFilt, 28, 4) + IDREG_FIELD(ID_DFR0_EL1, PerfMon, 24, 4) + IDREG_FIELD(ID_DFR0_EL1, MProfDbg, 20, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapTrc, 16, 4) + IDREG_FIELD(ID_DFR0_EL1, CopTrc, 12, 4) + IDREG_FIELD(ID_DFR0_EL1, MMapDbg, 8, 4) + IDREG_FIELD(ID_DFR0_EL1, CopSDbg, 4, 4) + IDREG_FIELD(ID_DFR0_EL1, CopDbg, 0, 4) + IDREG_END(ID_DFR0_EL1) + + IDREG_START(ID_DFR1_EL1) + IDREG_FIELD(ID_DFR1_EL1, HPMN0, 4, 4) + IDREG_FIELD(ID_DFR1_EL1, MTPMU, 0, 4) + IDREG_END(ID_DFR1_EL1) + + IDREG_START(ID_ISAR0_EL1) + IDREG_FIELD(ID_ISAR0_EL1, Divide, 24, 4) + IDREG_FIELD(ID_ISAR0_EL1, Debug, 20, 4) + IDREG_FIELD(ID_ISAR0_EL1, Coproc, 16, 4) + IDREG_FIELD(ID_ISAR0_EL1, CmpBranch, 12, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitField, 8, 4) + IDREG_FIELD(ID_ISAR0_EL1, BitCount, 4, 4) + IDREG_FIELD(ID_ISAR0_EL1, Swap, 0, 4) + IDREG_END(ID_ISAR0_EL1) + + IDREG_START(ID_ISAR1_EL1) + IDREG_FIELD(ID_ISAR1_EL1, Jazelle, 28, 4) + IDREG_FIELD(ID_ISAR1_EL1, Interwork, 24, 4) + IDREG_FIELD(ID_ISAR1_EL1, Immediate, 20, 4) + IDREG_FIELD(ID_ISAR1_EL1, IfThen, 16, 4) + IDREG_FIELD(ID_ISAR1_EL1, Extend, 12, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except_AR, 8, 4) + IDREG_FIELD(ID_ISAR1_EL1, Except, 4, 4) + IDREG_FIELD(ID_ISAR1_EL1, Endian, 0, 4) + IDREG_END(ID_ISAR1_EL1) + + IDREG_START(ID_ISAR2_EL1) + IDREG_FIELD(ID_ISAR2_EL1, Reversal, 28, 4) + IDREG_FIELD(ID_ISAR2_EL1, PSR_AR, 24, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultU, 20, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultS, 16, 4) + IDREG_FIELD(ID_ISAR2_EL1, Mult, 12, 4) + IDREG_FIELD(ID_ISAR2_EL1, MultiAccessInt, 8, 4) + IDREG_FIELD(ID_ISAR2_EL1, MemHint, 4, 4) + IDREG_FIELD(ID_ISAR2_EL1, LoadStore, 0, 4) + IDREG_END(ID_ISAR2_EL1) + + IDREG_START(ID_ISAR3_EL1) + IDREG_FIELD(ID_ISAR3_EL1, T32EE, 28, 4) + IDREG_FIELD(ID_ISAR3_EL1, TrueNOP, 24, 4) + IDREG_FIELD(ID_ISAR3_EL1, T32Copy, 20, 4) + IDREG_FIELD(ID_ISAR3_EL1, TabBranch, 16, 4) + IDREG_FIELD(ID_ISAR3_EL1, SynchPrim, 12, 4) + IDREG_FIELD(ID_ISAR3_EL1, SVC, 8, 4) + IDREG_FIELD(ID_ISAR3_EL1, SIMD, 4, 4) + IDREG_FIELD(ID_ISAR3_EL1, Saturate, 0, 4) + IDREG_END(ID_ISAR3_EL1) + + IDREG_START(ID_ISAR4_EL1) + IDREG_FIELD(ID_ISAR4_EL1, SWP_frac, 28, 4) + IDREG_FIELD(ID_ISAR4_EL1, PSR_M, 24, 4) + IDREG_FIELD(ID_ISAR4_EL1, SynchPrim_frac, 20, 4) + IDREG_FIELD(ID_ISAR4_EL1, Barrier, 16, 4) + IDREG_FIELD(ID_ISAR4_EL1, SMC, 12, 4) + IDREG_FIELD(ID_ISAR4_EL1, Writeback, 8, 4) + IDREG_FIELD(ID_ISAR4_EL1, WithShifts, 4, 4) + IDREG_FIELD(ID_ISAR4_EL1, Unpriv, 0, 4) + IDREG_END(ID_ISAR4_EL1) + + IDREG_START(ID_ISAR5_EL1) + IDREG_FIELD(ID_ISAR5_EL1, VCMA, 28, 4) + IDREG_FIELD(ID_ISAR5_EL1, RDM, 24, 4) + IDREG_FIELD(ID_ISAR5_EL1, CRC32, 16, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA2, 12, 4) + IDREG_FIELD(ID_ISAR5_EL1, SHA1, 8, 4) + IDREG_FIELD(ID_ISAR5_EL1, AES, 4, 4) + IDREG_FIELD(ID_ISAR5_EL1, SEVL, 0, 4) + IDREG_END(ID_ISAR5_EL1) + + IDREG_START(ID_ISAR6_EL1) + IDREG_FIELD(ID_ISAR6_EL1, CLRBHB, 28, 4) + IDREG_FIELD(ID_ISAR6_EL1, I8MM, 24, 4) + IDREG_FIELD(ID_ISAR6_EL1, BF16, 20, 4) + IDREG_FIELD(ID_ISAR6_EL1, SPECRES, 16, 4) + IDREG_FIELD(ID_ISAR6_EL1, SB, 12, 4) + IDREG_FIELD(ID_ISAR6_EL1, FHM, 8, 4) + IDREG_FIELD(ID_ISAR6_EL1, DP, 4, 4) + IDREG_FIELD(ID_ISAR6_EL1, JSCVT, 0, 4) + IDREG_END(ID_ISAR6_EL1) + + IDREG_START(ID_MMFR0_EL1) + IDREG_FIELD(ID_MMFR0_EL1, InnerShr, 28, 4) + IDREG_FIELD(ID_MMFR0_EL1, FCSE, 24, 4) + IDREG_FIELD(ID_MMFR0_EL1, AuxReg, 20, 4) + IDREG_FIELD(ID_MMFR0_EL1, TCM, 16, 4) + IDREG_FIELD(ID_MMFR0_EL1, ShareLvl, 12, 4) + IDREG_FIELD(ID_MMFR0_EL1, OuterShr, 8, 4) + IDREG_FIELD(ID_MMFR0_EL1, PMSA, 4, 4) + IDREG_FIELD(ID_MMFR0_EL1, VMSA, 0, 4) + IDREG_END(ID_MMFR0_EL1) + + IDREG_START(ID_MMFR1_EL1) + IDREG_FIELD(ID_MMFR1_EL1, BPred, 28, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1TstCln, 24, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Uni, 20, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1Hvd, 16, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniSW, 12, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdSW, 8, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1UniVA, 4, 4) + IDREG_FIELD(ID_MMFR1_EL1, L1HvdVA, 0, 4) + IDREG_END(ID_MMFR1_EL1) + + IDREG_START(ID_MMFR2_EL1) + IDREG_FIELD(ID_MMFR2_EL1, HWAccFlg, 28, 4) + IDREG_FIELD(ID_MMFR2_EL1, WFIStall, 24, 4) + IDREG_FIELD(ID_MMFR2_EL1, MemBarr, 20, 4) + IDREG_FIELD(ID_MMFR2_EL1, UniTLB, 16, 4) + IDREG_FIELD(ID_MMFR2_EL1, HvdTLB, 12, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdRng, 8, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdBG, 4, 4) + IDREG_FIELD(ID_MMFR2_EL1, L1HvdFG, 0, 4) + IDREG_END(ID_MMFR2_EL1) + + IDREG_START(ID_MMFR3_EL1) + IDREG_FIELD(ID_MMFR3_EL1, Supersec, 28, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMemSz, 24, 4) + IDREG_FIELD(ID_MMFR3_EL1, CohWalk, 20, 4) + IDREG_FIELD(ID_MMFR3_EL1, PAN, 16, 4) + IDREG_FIELD(ID_MMFR3_EL1, MaintBcst, 12, 4) + IDREG_FIELD(ID_MMFR3_EL1, BPMaint, 8, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintSW, 4, 4) + IDREG_FIELD(ID_MMFR3_EL1, CMaintVA, 0, 4) + IDREG_END(ID_MMFR3_EL1) + + IDREG_START(ID_MMFR4_EL1) + IDREG_FIELD(ID_MMFR4_EL1, EVT, 28, 4) + IDREG_FIELD(ID_MMFR4_EL1, CCIDX, 24, 4) + IDREG_FIELD(ID_MMFR4_EL1, LSM, 20, 4) + IDREG_FIELD(ID_MMFR4_EL1, HPDS, 16, 4) + IDREG_FIELD(ID_MMFR4_EL1, CnP, 12, 4) + IDREG_FIELD(ID_MMFR4_EL1, XNX, 8, 4) + IDREG_FIELD(ID_MMFR4_EL1, AC2, 4, 4) + IDREG_FIELD(ID_MMFR4_EL1, SpecSEI, 0, 4) + IDREG_END(ID_MMFR4_EL1) + + IDREG_START(ID_MMFR5_EL1) + IDREG_FIELD(ID_MMFR5_EL1, nTLBPA, 4, 4) + IDREG_FIELD(ID_MMFR5_EL1, ETS, 0, 4) + IDREG_END(ID_MMFR5_EL1) + + IDREG_START(ID_PFR0_EL1) + IDREG_FIELD(ID_PFR0_EL1, RAS, 28, 4) + IDREG_FIELD(ID_PFR0_EL1, DIT, 24, 4) + IDREG_FIELD(ID_PFR0_EL1, AMU, 20, 4) + IDREG_FIELD(ID_PFR0_EL1, CSV2, 16, 4) + IDREG_FIELD(ID_PFR0_EL1, State3, 12, 4) + IDREG_FIELD(ID_PFR0_EL1, State2, 8, 4) + IDREG_FIELD(ID_PFR0_EL1, State1, 4, 4) + IDREG_FIELD(ID_PFR0_EL1, State0, 0, 4) + IDREG_END(ID_PFR0_EL1) + + IDREG_START(ID_PFR1_EL1) + IDREG_FIELD(ID_PFR1_EL1, GIC, 28, 4) + IDREG_FIELD(ID_PFR1_EL1, Virt_frac, 24, 4) + IDREG_FIELD(ID_PFR1_EL1, Sec_frac, 20, 4) + IDREG_FIELD(ID_PFR1_EL1, GenTimer, 16, 4) + IDREG_FIELD(ID_PFR1_EL1, Virtualization, 12, 4) + IDREG_FIELD(ID_PFR1_EL1, MProgMod, 8, 4) + IDREG_FIELD(ID_PFR1_EL1, Security, 4, 4) + IDREG_FIELD(ID_PFR1_EL1, ProgMod, 0, 4) + IDREG_END(ID_PFR1_EL1) + + IDREG_START(ID_PFR2_EL1) + IDREG_FIELD(ID_PFR2_EL1, RAS_frac, 8, 4) + IDREG_FIELD(ID_PFR2_EL1, SSBS, 4, 4) + IDREG_FIELD(ID_PFR2_EL1, CSV3, 0, 4) + IDREG_END(ID_PFR2_EL1) + + IDREG_START(MIDR_EL1) + IDREG_FIELD(MIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(MIDR_EL1, Variant, 20, 4) + IDREG_FIELD(MIDR_EL1, Architecture, 16, 4) + IDREG_FIELD(MIDR_EL1, PartNum, 4, 12) + IDREG_FIELD(MIDR_EL1, Revision, 0, 4) + IDREG_END(MIDR_EL1) + + IDREG_START(MPIDR_EL1) + IDREG_FIELD(MPIDR_EL1, Aff3, 32, 8) + IDREG_FIELD(MPIDR_EL1, U, 30, 1) + IDREG_FIELD(MPIDR_EL1, MT, 24, 1) + IDREG_FIELD(MPIDR_EL1, Aff2, 16, 8) + IDREG_FIELD(MPIDR_EL1, Aff1, 8, 8) + IDREG_FIELD(MPIDR_EL1, Aff0, 0, 8) + IDREG_END(MPIDR_EL1) + + IDREG_START(MVFR0_EL1) + IDREG_FIELD(MVFR0_EL1, FPRound, 28, 4) + IDREG_FIELD(MVFR0_EL1, FPShVec, 24, 4) + IDREG_FIELD(MVFR0_EL1, FPSqrt, 20, 4) + IDREG_FIELD(MVFR0_EL1, FPDivide, 16, 4) + IDREG_FIELD(MVFR0_EL1, FPTrap, 12, 4) + IDREG_FIELD(MVFR0_EL1, FPDP, 8, 4) + IDREG_FIELD(MVFR0_EL1, FPSP, 4, 4) + IDREG_FIELD(MVFR0_EL1, SIMDReg, 0, 4) + IDREG_END(MVFR0_EL1) + + IDREG_START(MVFR1_EL1) + IDREG_FIELD(MVFR1_EL1, SIMDFMAC, 28, 4) + IDREG_FIELD(MVFR1_EL1, FPHP, 24, 4) + IDREG_FIELD(MVFR1_EL1, SIMDHP, 20, 4) + IDREG_FIELD(MVFR1_EL1, SIMDSP, 16, 4) + IDREG_FIELD(MVFR1_EL1, SIMDInt, 12, 4) + IDREG_FIELD(MVFR1_EL1, SIMDLS, 8, 4) + IDREG_FIELD(MVFR1_EL1, FPDNaN, 4, 4) + IDREG_FIELD(MVFR1_EL1, FPFtZ, 0, 4) + IDREG_END(MVFR1_EL1) + + IDREG_START(MVFR2_EL1) + IDREG_FIELD(MVFR2_EL1, FPMisc, 4, 4) + IDREG_FIELD(MVFR2_EL1, SIMDMisc, 0, 4) + IDREG_END(MVFR2_EL1) + + IDREG_START(REVIDR_EL1) + IDREG_END(REVIDR_EL1) + + IDREG_START(SMIDR_EL1) + IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4) + IDREG_FIELD(SMIDR_EL1, HIP, 52, 4) + IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20) + IDREG_FIELD(SMIDR_EL1, Implementer, 24, 8) + IDREG_FIELD(SMIDR_EL1, Revision, 16, 8) + IDREG_FIELD(SMIDR_EL1, SMPS, 15, 1) + IDREG_FIELD(SMIDR_EL1, SH, 13, 2) + IDREG_FIELD(SMIDR_EL1, Affinity, 0, 12) + IDREG_END(SMIDR_EL1) + --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197566; cv=none; d=zohomail.com; s=zohoarc; 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content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=czRYnC1h5hxho7j5XY+hTvhhizrNmuKL0vpohSAAF5c=; b=AqyEWZt+7tLDPToKfZutMxapLtfn+tNI3bFu8g3mLuSLiED1syUzFjrq2SaXd9Zio83xQe +id0BeEko7zrOOMJR5e6Ic1xrIocZekJn4QiYO1RAkUS/WEQ4u/yvUmox1p0za/JbPRQZh 9yLCpoFdEzSHSFb5rCCfCQn8GsY+kHw= X-MC-Unique: FOkC3wPlMLS1hGClBjlfiA-1 X-Mimecast-MFC-AGG-ID: FOkC3wPlMLS1hGClBjlfiA_1779197409 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 08/18] target/arm/cpu_idregs: generate tables for Arm64 ID registers and fields Date: Tue, 19 May 2026 15:27:22 +0200 Message-ID: <20260519132905.145643-9-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1779197567817158500 Content-Type: text/plain; charset="utf-8" From: Shaju Abraham Include cpu-idregs.h.inc multiple times with different definitions for the X-macros. This will generate tables for all Arm64 ID registers and their fields. Additionally, initialize the tables with all architecturally defined values. These tables will be consumed by the property layer in future patches. Co-authored-by: Khushit Shah Signed-off-by: Shaju Abraham Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- target/arm/cpu-idregs.c | 50 +++++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 1 + 2 files changed, 51 insertions(+) create mode 100644 target/arm/cpu-idregs.c diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c new file mode 100644 index 0000000000..f79b22680c --- /dev/null +++ b/target/arm/cpu-idregs.c @@ -0,0 +1,50 @@ +/* + * ARM ID register field table. + * + * Builds the per-id-register field descriptor arrays and the global + * arm_idregs[] table. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "cpu.h" +#include "cpu-idregs.h" + +#define IDREG_START(reg) \ + static ARM64SysRegField reg##_fields[] =3D { + +#define IDREG_END(reg) \ + }; + +#define IDREG_FIELD(reg, field, _shift, _length) \ + { \ + .name =3D #field, \ + .index =3D reg##_IDX, \ + .shift =3D (_shift), \ + .length =3D (_length), \ + }, +#include "cpu-idregs.h.inc" +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD + +/* generate an array of top level ID registers */ +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) + +#define IDREG_START(reg) \ + [reg##_IDX] =3D { \ + .name =3D #reg, \ + .index =3D reg##_IDX, \ + .fields =3D reg##_fields, \ + .fields_count =3D ARRAY_SIZE(reg##_fields), \ + }, + +ARM64SysReg arm64_id_regs[NUM_ID_IDX] =3D { +#include "cpu-idregs.h.inc" +}; +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD diff --git a/target/arm/meson.build b/target/arm/meson.build index 4723f9f170..64d1ec63ab 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -19,6 +19,7 @@ arm_common_ss.add(files( =20 arm_common_system_ss.add(files( 'arm-qmp-cmds.c', + 'cpu-idregs.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm= .c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197590; cv=none; d=zohomail.com; s=zohoarc; b=FEW8RKAeRAX9JtKSFKY43iInXMIwWFLIHw4Qbi2eQ8g3QK0a3+VJDAgXm22KWZv1wpum30QrcpTwObj4F+hsbturTE4kfhx/2qskkq4qh/PkwE1Al03DCLy8WE5TGdkXhRv/I6kqdkoR0z/ZiPQzodIQcwfac/290aAQ8XB1uME= ARC-Message-Signature: i=1; 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charset="utf-8" From: Cornelia Huck Add an helper to retrieve the writable id reg bitmask. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- v4 -> v5: - get rid of IdRegMap datatype - do not store the status of the query in cpu anymore, just return the error in case the retrieval failed - add implementation in kvm-stub.c --- target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 21 +++++++++++++++++++++ target/arm/kvm_arm.h | 2 ++ 3 files changed, 28 insertions(+) diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 88cbe8d85c..cd88eb741a 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -119,3 +119,8 @@ char *kvm_print_register_name(uint64_t regidx) { g_assert_not_reached(); } + +int kvm_arm_get_writable_id_regs(uint64_t *idregmap) +{ + g_assert_not_reached(); +} diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7d194ea112..4adfd20050 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -505,6 +505,27 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features =3D arm_host_cpu_features.features; } =20 +int kvm_arm_get_writable_id_regs(uint64_t *idregmap) +{ + int cap_writable_id_regs; + struct reg_mask_range range =3D { + .range =3D 0, /* up to now only a single range is supported */ + .addr =3D (uint64_t)idregmap, + }; + int ret; + + cap_writable_id_regs =3D + kvm_check_extension(kvm_state, KVM_CAP_ARM_SUPPORTED_REG_MASK_RANG= ES); + + if (!cap_writable_id_regs || + !(cap_writable_id_regs & (1 << KVM_ARM_FEATURE_ID_RANGE))) { + return -ENOSYS; + } + + ret =3D kvm_vm_ioctl(kvm_state, KVM_ARM_GET_REG_WRITABLE_MASKS, &range= ); + return ret; +} + static bool kvm_no_adjvtime_get(Object *obj, Error **errp) { return !ARM_CPU(obj)->kvm_adjvtime; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c40fb003..c1c2e7ec37 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -240,4 +240,6 @@ void arm_gic_cap_kvm_probe(GICCapability *v2, GICCapabi= lity *v3); */ char *kvm_print_register_name(uint64_t regidx); =20 +int kvm_arm_get_writable_id_regs(uint64_t *idregmap); + #endif --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JE0HLZrwJsrBKolW/r84ZwL1/ywjoY3zz9XZRBLF7mk=; b=jQ8vFP4QEm0LLial9bjUyqUWKrpku+3ShRSoCW2e2zP1rLvs7aLiJkXN4DuxTwA9XSi9MZ c7Aonachks64Qzn6iNkct08CqlTBntKo9QubW6cZsp1bvQHJqk4hiBDmRteMUwXvo8VsK2 YGIv1gAtMBCgQFHrD5Wst52fzDaby3U= X-MC-Unique: 1eztZgn9OzObXBXA7DPV-g-1 X-Mimecast-MFC-AGG-ID: 1eztZgn9OzObXBXA7DPV-g_1779197423 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 10/18] target/arm/cpu64: Retrieve writable ID reg map in aarch64_host_initfn() Date: Tue, 19 May 2026 15:27:24 +0200 Message-ID: <20260519132905.145643-11-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Store the writable_map array in the CPU state and populate it in aarch64_host_initfn(). In case the retrieval fails we simply free and null the pointer: this will indicate that the writable_map is not usable in subsequent patches. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- target/arm/cpu.h | 3 +++ target/arm/cpu64.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0a1d7fbe3..3558460333 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1073,6 +1073,9 @@ struct ArchCPU { /* KVM steal time */ OnOffAuto kvm_steal_time; =20 + /* ID reg writable bitmask */ + uint64_t *writable_map; + /* Uniprocessor system with MP extensions */ bool mp_is_up; =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a93ad2da5a..f2edbfc437 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -851,6 +851,7 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cp= u) static void aarch64_host_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + int ret; =20 #if defined(CONFIG_NITRO) if (nitro_enabled()) { @@ -861,6 +862,14 @@ static void aarch64_host_initfn(Object *obj) =20 #if defined(CONFIG_KVM) kvm_arm_set_cpreg_mig_tolerances(cpu); + + cpu->writable_map =3D g_new(uint64_t, KVM_ARM_FEATURE_ID_RANGE_SIZE); + + ret =3D kvm_arm_get_writable_id_regs(cpu->writable_map); + if (ret) { + g_free(cpu->writable_map); + cpu->writable_map =3D NULL; + } kvm_arm_set_cpu_features_from_host(cpu); aarch64_add_sve_properties(obj); #elif defined(CONFIG_HVF) --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197525; cv=none; d=zohomail.com; s=zohoarc; b=h3OTEBgm6323GsWhOppNpVxYZ5Sz4tWXWge/4gcdBsBocgQiY3SCIq6TBJ6P1ovIL/6xJZcF6gLNpBeK9UA0suB0OjpvxNa7Xm57e54V+bCwIV1GCr2S5qxPcEpXTHN82m5wfX7YdjZ9DdR9CYA+p6G+P+n3PRpxKL5rS/IkSsY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779197525; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 19 May 2026 13:30:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=W8DMCPN/WdBIKu5QiyxjCLPAVxgVe9vHmRLSH8oesEs=; b=gAveEPIm1DTkApw4NSXlse8ortpUnMTpu/qKq0TSnx+8311Qcz+0lUd7Grk2fyrEktGzJz fZ/LCtvomrTXpe63GIVl06fj5ActXzQkQ5Oa/+muTyhbc/SBEai5I/ZZVxG6KJwiww6fwM JjaUDCiT6ZaeRkA0hZb91bIM88GNWps= X-MC-Unique: b52CZDXXNAqkb3cCqCQaSA-1 X-Mimecast-MFC-AGG-ID: b52CZDXXNAqkb3cCqCQaSA_1779197429 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 11/18] arm/kvm: Initialize all writable ID registers from host Date: Tue, 19 May 2026 15:27:25 +0200 Message-ID: <20260519132905.145643-12-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We want to allow overwriting writable fields of some ID registers. However currently some of them are never touched, neither read nor w. Examples are CLIDR_EL1, CTR_EL0, REVIDR_EL1, MIDR_EL1. We want to initialize them from the host value, allow overwrite and write back for kvm afterwards. This patch implements the initialization. Introduce a new get_host_cpu_idregs() helper that gets the host values for all writable ID regs and store them in isar.idregs[]. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- --- target/arm/kvm.c | 72 +++++++++++++++++++++++++++++++++++++++-- target/arm/trace-events | 1 + 2 files changed, 71 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 4adfd20050..92219ee62e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -42,6 +42,7 @@ #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" #include "migration/blocker.h" +#include "cpu-idregs.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_INFO(DEVICE_CTRL), @@ -273,7 +274,62 @@ static uint32_t kvm_arm_sve_get_vls(int fd) return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ); } =20 -static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +static int idregs_idx_to_kvm_feature_idx(ARMIDRegisterIdx idx) +{ + ARMSysRegs sysreg =3D id_register_sysreg[idx]; + + return KVM_ARM_FEATURE_ID_RANGE_IDX((sysreg & CP_REG_ARM64_SYSREG_OP0_= MASK) + >> CP_REG_ARM64_SYSREG_OP0_SHI= FT, + (sysreg & CP_REG_ARM64_SYSREG_OP1_= MASK) + >> CP_REG_ARM64_SYSREG_OP1_SHI= FT, + (sysreg & CP_REG_ARM64_SYSREG_CRN_= MASK) + >> CP_REG_ARM64_SYSREG_CRN_SHI= FT, + (sysreg & CP_REG_ARM64_SYSREG_CRM_= MASK) + >> CP_REG_ARM64_SYSREG_CRM_SHI= FT, + (sysreg & CP_REG_ARM64_SYSREG_OP2_= MASK) + >> CP_REG_ARM64_SYSREG_OP2_SHI= FT); +} + +/* + * get_host_cpu_idregs: Read all the writable ID reg host values + * + * Need to be called once the writable mask has been populated + * Note we may want to read all the known id regs but some of them are not + * writable and return an error, hence the choice of reading only those wh= ich + * are writable. Those are also readable! + */ +static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ah= cf) +{ + int err =3D 0; + int i; + + for (i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysRegs sysreg =3D id_register_sysreg[i]; + uint64_t writable_mask =3D + cpu->writable_map[idregs_idx_to_kvm_feature_idx(i)]; + uint64_t *reg; + int ret; + + if (!writable_mask) { + continue; + } + + reg =3D &ahcf->isar.idregs[i]; + ret =3D read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg)); + trace_get_host_cpu_idregs(sysregdesc->name, *reg); + if (ret) { + error_report("%s error reading value of host %s register (%m)", + __func__, sysregdesc->name); + + err =3D ret; + } + } + return err; +} + +static void +kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -359,6 +415,18 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64= only */ err =3D 0; } else { + /* Make sure all writable ID reg values are initialized */ + if (cpu->writable_map) { + err |=3D get_host_cpu_idregs(cpu, fd, ahcf); + } + + /* + * temporarily override the CLIDR_EL1 value since some host values + * trigger "Unified type is not implemented at level n" error in + * fdt_add_cpu_nodes() + */ + SET_IDREG(&ahcf->isar, CLIDR, 0x0); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); @@ -485,7 +553,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; =20 if (!arm_host_cpu_features.dtb_compatible) { - kvm_arm_get_host_cpu_features(&arm_host_cpu_features); + kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features); } =20 cpu->kvm_target =3D arm_host_cpu_features.target; diff --git a/target/arm/trace-events b/target/arm/trace-events index 8502fb3265..8c7faf57c7 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,6 +13,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Sat May 30 18:34:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197549; cv=none; d=zohomail.com; s=zohoarc; b=IrlsbJ9hHKYGFzksnmrylWIVEJkYzxkwr79BMqy6vzYqYu5CS/WVYPxuDXyqultJds1ilH6/MUx+TqbEH0cKFa1OoqYZlMY3dQXhtx+/0ZNJ9yOImsMP7LmnzSgGgwCZg6BCAjaL7icXeOR5S1pt5IAU9i0ggnO/Zi97BGkOwic= ARC-Message-Signature: i=1; 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Tue, 19 May 2026 13:30:35 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.49.207]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8CBC11800352; Tue, 19 May 2026 13:30:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197447; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0JfsTkaVVhnWdu4t9R24wJS1oRYKNcqs6QcOWn6v2Ik=; b=XQ1zW/rAR++OhuEEd8MzFV5hWr2RMl4nzwGX/SAQ3508iwsXAq0TT9aU0EO+X9E/k++yVk D/e/3GezcYjVAepw/fZxKQkUEorhTVKe8BcpMZwifso1l8IUm8NROC1a9Q+WqsxfY30ZS8 o7YJoo0ZSIX1LK0Bua803Wqvfw+rXv0= X-MC-Unique: 9f2ia-YmOj2Kp4fTFrDhgA-1 X-Mimecast-MFC-AGG-ID: 9f2ia-YmOj2Kp4fTFrDhgA_1779197435 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 12/18] arm/kvm: write back modified ID regs to KVM Date: Tue, 19 May 2026 15:27:26 +0200 Message-ID: <20260519132905.145643-13-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" In case some ID reg values were overriden after their initialization in kvm_arm_get_host_cpu_features() we need to copy the new value stored in isar.idregs array back to the cpreg_list and then sync the cpreg_list to KVM. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- v4 -> v5: - only call kvm_arm_writable_idregs_to_cpreg_list and write_list_to_kvmstate if writable_map is allocated - reinitialize the cpreg list after sync (Jinqian) --- target/arm/kvm.c | 69 ++++++++++++++++++++++++++++++++++++++++- target/arm/trace-events | 1 + 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 92219ee62e..30c5175c68 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -274,6 +274,21 @@ static uint32_t kvm_arm_sve_get_vls(int fd) return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ); } =20 +static int kvm_feature_idx_to_idregs_idx(int kidx) +{ + int op1, crm, op2; + ARMSysRegs sysreg; + + op1 =3D kidx / 64; + if (op1 =3D=3D 2) { + op1 =3D 3; + } + crm =3D (kidx % 64) / 8; + op2 =3D kidx % 8; + sysreg =3D ENCODE_ID_REG(3, op1, 0, crm, op2); + return get_sysreg_idx(sysreg); +} + static int idregs_idx_to_kvm_feature_idx(ARMIDRegisterIdx idx) { ARMSysRegs sysreg =3D id_register_sysreg[idx]; @@ -1189,6 +1204,40 @@ bool kvm_arm_cpu_post_load(ARMCPU *cpu) return true; } =20 +/* + * Copy writable ID regs from isar.idregs[] to cpreg_list + * in case their value differs from the original init cpreg value + */ +static void kvm_arm_writable_idregs_to_cpreg_list(ARMCPU *cpu) +{ + for (int i =3D 0; i < KVM_ARM_FEATURE_ID_RANGE_SIZE; i++) { + uint64_t writable_mask =3D cpu->writable_map[i]; + + if (writable_mask) { + int idx =3D kvm_feature_idx_to_idregs_idx(i); + ARM64SysReg *sysregdesc; + uint64_t previous, new; + uint64_t *cpreg; + uint32_t sysreg; + + if (idx =3D=3D -1) { + /* sysreg writable, but we don't know it */ + continue; + } + sysregdesc =3D &arm64_id_regs[idx]; + sysreg =3D id_register_sysreg[idx]; + cpreg =3D kvm_arm_get_cpreg_ptr(cpu, idregs_sysreg_to_kvm_reg(= sysreg)); + previous =3D *cpreg; + new =3D cpu->isar.idregs[idx]; + if (previous !=3D new) { + *cpreg =3D new; + trace_kvm_arm_writable_idregs_to_cpreg_list(sysregdesc->na= me, + previous, new); + } + } + } +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -2140,7 +2189,25 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - return kvm_arm_init_cpreg_list(cpu); + ret =3D kvm_arm_init_cpreg_list(cpu); + if (ret) { + return ret; + } + /* overwrite writable ID regs with their updated property values */ + if (cpu->writable_map) { + kvm_arm_writable_idregs_to_cpreg_list(cpu); + ret =3D write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE); + if (!ret) { + return -1; + } + /* + * modified values may have changed the visibility of some regs, + * reinitialize the cpreg_list accordingly + */ + ret =3D kvm_arm_init_cpreg_list(cpu); + } + + return ret; } =20 int kvm_arch_destroy_vcpu(CPUState *cs) diff --git a/target/arm/trace-events b/target/arm/trace-events index 8c7faf57c7..c25d2a1191 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -14,6 +14,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 +kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Sat May 30 18:34:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197450; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SY/z/63+m4hMzLeyKBNakc3vBE3ErHiwR/jYVe53dHc=; b=HQgx0sUdF///zJpWoEigmrGqchj0tUNHkGtjR1Xqy3HRDkJw6oZGM0eTRczJCEIeAVSRJ8 dQi+eVBeltKvAofGuUrVkO2fIBoq6G0/Y3qEBFDLZ4OJMe+XqHjxSH4vyRPD+EwCWb1QTq fSlc0dCCzLc0SmQLY/+qDTPaYX4hgLs= X-MC-Unique: nFl3KB4TP8CzSOd9g2v6ww-1 X-Mimecast-MFC-AGG-ID: nFl3KB4TP8CzSOd9g2v6ww_1779197441 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 13/18] target/arm/kvm: Introduce kvm_arm_expose_idreg_properties Date: Tue, 19 May 2026 15:27:27 +0200 Message-ID: <20260519132905.145643-14-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1779197626740158500 Content-Type: text/plain; charset="utf-8" This helper decode the ID reg writable mask, matches it against ID reg fields defined in target/arm/cpu-idregs.h.inc and for each writable named field, generates a uint64 property. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- v4 -> v5: - free prop_name - check cpu->writable_map as a preamble in kvm_arm_expose_idreg_properties --- target/arm/kvm.c | 135 ++++++++++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 10 +++ target/arm/trace-events | 4 ++ 3 files changed, 149 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 30c5175c68..960052e67e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -343,6 +343,141 @@ static int get_host_cpu_idregs(ARMCPU *cpu, int fd, A= RMHostCPUFeatures *ahcf) return err; } =20 +static ARM64SysRegField *get_field(int i, ARM64SysReg *reg) +{ + for (int f =3D 0; f < reg->fields_count; f++) { + struct ARM64SysRegField *field =3D ®->fields[f]; + int upper =3D field->shift + field->length - 1; + + if (i >=3D field->shift && i <=3D upper) { + return field; + } + } + return NULL; +} + +static void set_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t old, value, mask; + int lower =3D field->shift; + int length =3D field->length; + int index =3D field->index; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (length < 64 && value > ((1 << length) - 1)) { + error_setg(errp, + "idreg %s set value (0x%lx) exceeds length of field (%d= )!", + name, value, length); + return; + } + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D value << lower; + old =3D idregs[index]; + idregs[index] =3D old & ~mask; + idregs[index] |=3D value; + trace_set_sysreg_prop(name, old, mask, value, idregs[index]); +} + +static void get_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t value, mask; + int lower =3D field->shift; + int length =3D field->length; + int index =3D field->index; + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D (idregs[index] & mask) >> lower; + visit_type_uint64(v, name, &value, errp); + trace_get_sysreg_prop(name, value); +} + +/* + * decode_idreg_writemap: Generate props for writable fields + * + * @obj: CPU object + * @index: index of the sysreg + * @map: writable map for the sysreg + * @reg: description of the sysreg + */ +static int +decode_idreg_writemap(Object *obj, int index, uint64_t map, ARM64SysReg *r= eg) +{ + int i =3D ctz64(map); + int nb_sysreg_props =3D 0; + + while (map) { + ARM64SysRegField *field =3D get_field(i, reg); + int lower, upper; + char *prop_name; + uint64_t mask; + + if (!field) { + warn_report("%s bit %d of %s is writable but no named field " + "in target/arm/cpu-idregs.h.inc", + __func__, i, reg->name); + warn_report("%s is target/arm/cpu-idregs.h.inc?", __func__); + map =3D map & ~BIT_ULL(i); + i =3D ctz64(map); + continue; + } + lower =3D field->shift; + upper =3D field->shift + field->length - 1; + prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); + trace_decode_idreg_writemap(field->name, lower, upper, prop_name); + object_property_add(obj, prop_name, "uint64", + get_sysreg_prop, set_sysreg_prop, NULL, field); + g_free(prop_name); + nb_sysreg_props++; + + mask =3D MAKE_64BIT_MASK(lower, field->length); + map =3D map & ~mask; + i =3D ctz64(map); + } + trace_nb_sysreg_props(reg->name, nb_sysreg_props); + return 0; +} + +/* analyze the writable mask and generate properties for writable fields */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs) +{ + int i, idx; + Object *obj =3D OBJECT(cpu); + + if (!cpu->writable_map) { + return; + } + + for (i =3D 0; i < KVM_ARM_FEATURE_ID_RANGE_SIZE; i++) { + uint64_t mask =3D cpu->writable_map[i]; + + if (mask) { + /* reg @i has some writable fields, decode them */ + idx =3D kvm_feature_idx_to_idregs_idx(i); + if (idx < 0) { + /* no matching reg? */ + warn_report("%s: reg %d writable, but not in list of idreg= s?", + __func__, i); + } else { + decode_idreg_writemap(obj, i, mask, ®s[idx]); + } + } + } +} + static void kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf) { diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index c1c2e7ec37..8446a9cbf0 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -142,6 +142,16 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); */ void kvm_arm_add_vcpu_properties(ARMCPU *cpu); =20 +typedef struct ARM64SysReg ARM64SysReg; +/** + * kvm_arm_expose_idreg_properties: + * @cpu: The CPU object to generate the properties for + * @reg: registers from the host + * + * analyze the writable mask and generate properties for writable fields + */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs); + /** * kvm_arm_steal_time_finalize: * @cpu: ARMCPU for which to finalize kvm-steal-time diff --git a/target/arm/trace-events b/target/arm/trace-events index c25d2a1191..d72ad6b671 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,6 +15,10 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_ir= q: timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 +decode_idreg_writemap(const char* name, int lower, int upper, char *prop_n= ame) "%s [%d:%d] is writable (prop %s)" +get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 +set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 +nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.53.0 From nobody Sat May 30 18:34:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197457; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nYpIswBUbvAWx5c0QdJS1zE0eazgwAPhomjHPpZ7pys=; b=S3t7cJpNIgcVeP2tmYZeZjmf9BGKkYd27ir9jWAd90UfHlJFGuhmEoGzgVYTzIlByGgh2l SXe3EbUAa6jaYU9KzbdmXpunfZNp97SD3NwxBYigoJtEp8Lk79ZdoC2l7dMHo1TTNGQZbF LH89uZb2OsG0h70jvzI4Ujsoh40OezE= X-MC-Unique: O16OgMxxObS4d8EfO-avrw-1 X-Mimecast-MFC-AGG-ID: O16OgMxxObS4d8EfO-avrw_1779197448 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 14/18] target/arm/kvm: Special case REVIDR_EL1 and AIDR_EL1 Date: Tue, 19 May 2026 15:27:28 +0200 Message-ID: <20260519132905.145643-15-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Special case REVIDR_EL1 and AIDR_EL1 which are writable but does not expose named fields. They will need to be handled separately Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- target/arm/kvm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 960052e67e..6373a66bbd 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -472,7 +472,15 @@ void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM6= 4SysReg *regs) warn_report("%s: reg %d writable, but not in list of idreg= s?", __func__, i); } else { - decode_idreg_writemap(obj, i, mask, ®s[idx]); + /* + * special case REVIDR_EL1 and AIDR_EL1 which are writable= but + * does not expose named fields. They will need to be hand= led + * separately + */ + if (strcmp(regs[idx].name, "REVIDR_EL1") && + strcmp(regs[idx].name, "AIDR_EL1")) { + decode_idreg_writemap(obj, i, mask, ®s[idx]); + } } } } --=20 2.53.0 From nobody Sat May 30 18:34:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197620; cv=none; d=zohomail.com; s=zohoarc; b=VHoD7Uj8IxHb++iJlwtAtc1jSTCfa/NPolcxgitJ0TVNeRwWJCM4VzJeze8j3BiaJnJ0cZ9xQpeLuF82DMPrmPO4/x16VeIXKT1aPaGWKazqlX1fWwQPqWwe5N8ef41C7DWdgsOPDs/QGwKrF2NiO1mIdHQCKr+IEhB0V6e4GXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779197620; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 19 May 2026 13:30:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197464; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=16khiiboxEtagPZ7yiPX8BOR+daPNKuEG2RYsB0whyg=; b=WFwH0FiH7mwrsZ+kQUJWwDa94ffmbImX8enRuKEXiESHWZAIEMYYoxBFyt/Ppo2YzzrVAh ysO3wUfMwHPK6lAzMetTaR6MLmfnR15I5tq3Zg7ND7s8qVWur08n4BY1Axi02x03L+vvM+ 9p0xCeH0Go2uDUqV2KXlw0T898DGMow= X-MC-Unique: pV_ITPC0P8CtW3NVtGMRNA-1 X-Mimecast-MFC-AGG-ID: pV_ITPC0P8CtW3NVtGMRNA_1779197454 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 15/18] target/arm/kvm: Ignore some writable bits that shouldn't be Date: Tue, 19 May 2026 15:27:29 +0200 Message-ID: <20260519132905.145643-16-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" KVM currently reports some bits as writable whereas they are RES0 or RAZ. This is detected because the code attempts to match those bits against a named field and this later does not exist in target/arm/cpu-idregs.h.inc. Let's silence warnings until those bits get fixed in the kernel. This was observed with v7.1-rc4 kernel. Signed-off-by: Eric Auger --- target/arm/kvm.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6373a66bbd..1688cc2106 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -405,6 +405,19 @@ static void get_sysreg_prop(Object *obj, Visitor *v, trace_get_sysreg_prop(name, value); } =20 +static bool ignore_unnamed_writable_field(ARM64SysReg *reg, int i) +{ + if ((!strcmp(reg->name, "ID_ISAR0_EL1") && i >=3D 28 && i <=3D 31) || = /* RES0 */ + (!strcmp(reg->name, "ID_ISAR5_EL1") && i >=3D 20 && i <=3D 23) || = /* RES0 */ + (!strcmp(reg->name, "MVFR2_EL1") && i >=3D 8 && i <=3D 31) || /* R= ES0 */ + (!strcmp(reg->name, "ID_PFR2_EL1") && i >=3D 12 && i <=3D 31) || /= * RES0 */ + (!strcmp(reg->name, "ID_MMFR5_EL1") && i >=3D 8 && i <=3D 31) || /= * RES0 */ + (!strcmp(reg->name, "ID_AA64FPFR0_EL1") && i >=3D 2 && i <=3D 7)) = { /* RAZ */ + return true; + } + return false; +} + /* * decode_idreg_writemap: Generate props for writable fields * @@ -426,10 +439,12 @@ decode_idreg_writemap(Object *obj, int index, uint64_= t map, ARM64SysReg *reg) uint64_t mask; =20 if (!field) { - warn_report("%s bit %d of %s is writable but no named field " - "in target/arm/cpu-idregs.h.inc", - __func__, i, reg->name); - warn_report("%s is target/arm/cpu-idregs.h.inc?", __func__); + if (!ignore_unnamed_writable_field(reg, i)) { + warn_report("%s bit %d of %s is writable but no named fiel= d " + "in target/arm/cpu-idregs.h.inc", + __func__, i, reg->name); + warn_report("%s is target/arm/cpu-idregs.h.inc?", __func__= ); + } map =3D map & ~BIT_ULL(i); i =3D ctz64(map); continue; --=20 2.53.0 From nobody Sat May 30 18:34:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197525; cv=none; d=zohomail.com; s=zohoarc; b=WK5dsfxKx3MSiophQ8+l93oaHzcSbmy2iSGAS5QG4onuMYluUPMuU1r0kT5PTe0RFt0EQZP5QpbxPd5KQVxULEzp2hH/pqeM+LYo6XSWZl/VHV43ldTXLqwEunqb1SVPWifgJJk6Gm3SkkRpY6fqVTAA6jeTtKxGAYncrWrW2oQ= ARC-Message-Signature: i=1; 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Tue, 19 May 2026 13:31:00 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.49.207]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 12A02180034E; Tue, 19 May 2026 13:30:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197467; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AqN7LyQkpVzsmK2HDdemrDuDRczsABmmtqsqw6bIJnM=; b=gQ88RU8ZtOQKR+Ifj5Xtcqq6DC+CJCpsVmJjW8EnXRJK5Y6CWO9vTAa3JMTFRMDmVWkAPh 9lPTBJVDZOSfybYUCgZdf2T+T3wyirBXGjgRpaVzPmISj2VNnciOeTWona/zn1lW75R6RW pTvBct27V/XCxddqkZGgJQBxToT412o= X-MC-Unique: 1otgUIMGMAW_t3_jJjq3pQ-1 X-Mimecast-MFC-AGG-ID: 1otgUIMGMAW_t3_jJjq3pQ_1779197460 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 16/18] target/arm/cpu: Expose writable ID reg field properties on the kvm host vcpu model Date: Tue, 19 May 2026 15:27:30 +0200 Message-ID: <20260519132905.145643-17-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" If the host supports KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES and KVM_ARM_GET_REG_WRITABLE_MASKS ioctl successfully retrieved the mask of writable fields for all ID regs, expose uint64 SYSREG properties for all the writable ID reg fields exposed by the host kernel which can be matched in target/arm/cpu-idregs.h.inc. Properties are named SYSREG__ with REG and FIELD being those used ARCHMRS Registers.json. When such properties are set, they override the default field value retrieved from the host and reinjected into KVM. Then the actual value being applied at KVM depends on the register, ie. it can be sanitized. In case the field value is rejected by KVM, the vpcu init fails. Anyway there is a first attempt to write back this value into KVM. Then legacy CPU options (virtualization, secure, ...) can still override the previous value. So low level IDREG field properties apply before the legacy ones. An example of invocation is: -cpu host,SYSREG_ID_AA64MMFR0_EL1_ECV=3D0x0 which sets ECV field of ID_AA64MMFR0_EL1 to 0 (enhanced counter virtualization). Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- v4 -> v5: - get rid of ret local variable, dynamically allocate and free writable_map here --- target/arm/cpu64.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f2edbfc437..e0e1ff6cfb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -37,6 +37,7 @@ #include "hw/core/qdev-properties.h" #include "internals.h" #include "cpu-features.h" +#include "cpu-idregs.h" =20 /* convert between _IDX and SYS_ */ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ @@ -851,7 +852,6 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cp= u) static void aarch64_host_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - int ret; =20 #if defined(CONFIG_NITRO) if (nitro_enabled()) { @@ -865,13 +865,18 @@ static void aarch64_host_initfn(Object *obj) =20 cpu->writable_map =3D g_new(uint64_t, KVM_ARM_FEATURE_ID_RANGE_SIZE); =20 - ret =3D kvm_arm_get_writable_id_regs(cpu->writable_map); - if (ret) { + if (kvm_arm_get_writable_id_regs(cpu->writable_map)) { g_free(cpu->writable_map); cpu->writable_map =3D NULL; } kvm_arm_set_cpu_features_from_host(cpu); aarch64_add_sve_properties(obj); + + if (cpu->writable_map) { + /* generate SYSREG properties according to writable masks */ + kvm_arm_expose_idreg_properties(cpu, arm64_id_regs); + } + #elif defined(CONFIG_HVF) hvf_arm_set_cpu_features_from_host(cpu); #elif defined(CONFIG_WHPX) --=20 2.53.0 From nobody Sat May 30 18:34:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197629; cv=none; d=zohomail.com; s=zohoarc; b=Q8cY3UpQOPlaHVuvf0wMkJAz4la38dA/cckAiQbXpDWoE4dvKGb3AH2k5R9Rd8zqAFIUZUrR8Z2Fa7MwtQtpybgQbF46Ct55RVX3ylsjgT8bympVnRvg/g2KOIHPQ1NCYyvckvT7ZI46zpIY+33uoJJvDSZa1k9p0YasNseAmCc= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1779197630779158500 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Implement the capability to query available ID register values by adding SYSREG_* options and values to the cpu model expansion for the host model, if available. Excerpt: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} {"return": {"model": {"name": "host", "props": {"SYSREG_ID_AA64PFR0_EL1_EL3": 1224979098931106066, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, ../.. So this allows the upper stack to detect available writable ID regs and the "host passthrough model" values. [CH: moved SYSREG_* values to host model] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- TODO: Add the moment there is no way to test changing a given ID reg field value. ie: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host", "prop"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x13}} --- target/arm/arm-qmp-cmds.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 83ec95c290..e6c717a872 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/target-info.h" #include "hw/core/boards.h" #include "kvm_arm.h" @@ -190,6 +191,24 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } } =20 + /* If writable ID regs are supported, add them as well */ + if (ARM_CPU(obj)->writable_map) { + ObjectProperty *prop; + ObjectPropertyIterator iter; + + object_property_iter_init(&iter, obj); + + while ((prop =3D object_property_iter_next(&iter))) { + QObject *value; + + if (!g_str_has_prefix(prop->name, "SYSREG_")) { + continue; + } + value =3D object_property_get_qobject(obj, prop->name, &error_= abort); + qdict_put_obj(qdict_out, prop->name, value); + } + } + if (!qdict_size(qdict_out)) { qobject_unref(qdict_out); } else { --=20 2.53.0 From nobody Sat May 30 18:34:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1779197572; cv=none; d=zohomail.com; s=zohoarc; b=V298fwlovaI8WFBgqILqTUbnmpSPH9LDXyez9jTdxP19F5yZUxiExBKp3AZ0pG33JEAKZPQFFFyNToO/oq5L6wBIfl16DfCqI7CvDpA5XjnjROR4G1CtBE7mIoi8eRgGPX4ZJ8WVEBPNQo1aK9Hr4+3/otd3Rk0XumIZfAiDkp8= ARC-Message-Signature: i=1; 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Tue, 19 May 2026 13:31:13 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.49.207]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 6EC851800576; Tue, 19 May 2026 13:31:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1779197486; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gnuxKRpheDBPZeR/bIhsWSKjaJS14cMQQIOMtiNgg0U=; b=jWQB8DEhhR1DhuCSSvjVVdTnPRMPlkDRxtk3IbZnlldiMpVj0EVTbEEqAiQhf46R5NksGn b9H6kiTgzxcC/xjNJbOk7p5YrnB99KOQjMBIAYwAQA+h56IJIsHaWTrPTRU+2ZbNN7i1Y+ GvCRe3byNnVeiNRQnq6eZR+6bTjgFx0= X-MC-Unique: QYibuWQ-PHiMpTWUY2Fa5A-1 X-Mimecast-MFC-AGG-ID: QYibuWQ-PHiMpTWUY2Fa5A_1779197473 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, shaju.abraham@nutanix.com, khushit.shah@nutanix.com, yangjinqian1@huawei.com, cohuck@redhat.com, richard.henderson@linaro.org, sebott@redhat.com, skolothumtho@nvidia.com, philmd@linaro.org Cc: maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Subject: [PATCH v5 18/18] arm/cpu-features: document ID reg properties Date: Tue, 19 May 2026 15:27:32 +0200 Message-ID: <20260519132905.145643-19-eric.auger@redhat.com> In-Reply-To: <20260519132905.145643-1-eric.auger@redhat.com> References: <20260519132905.145643-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1779197574705154100 Content-Type: text/plain; charset="utf-8" From: Cornelia Huck Add some documentation for how individual ID registers can be configured with the host cpu model. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck Reviewed-by: Sebastian Ott --- docs/system/arm/cpu-features.rst | 106 ++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 10b0eff27e..6203757781 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -2,7 +2,10 @@ Arm CPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 CPU features are optional features that a CPU of supporting type may -choose to implement or not. In QEMU, optional CPU features have +choose to implement or not. QEMU provides two different mechanisms +to configure those features: + +1. For most CPU models, optional CPU features may have corresponding boolean CPU proprieties that, when enabled, indicate that the feature is implemented, and, conversely, when disabled, indicate that it is not implemented. An example of an Arm CPU feature @@ -31,6 +34,18 @@ running guests in AArch32. CPU features that are inherently specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 +2. Additionally, the ``host`` CPU model on KVM allows to configure optional +CPU features via the corresponding ID registers. The host kernel allows +to write a subset of ID register fields. The host model exposes +properties for each writable ID register field. Those options are named +SYSREG__. IDREG and FIELD names are those used in the +ARM ARM Reference Manual. Their availability depend on the host capability +to let the userspace write those fields. Values set with those properties +override the initial values retrieved from the host. They are written back +to KVM and the eventual value applied by KVM depends on whether the value +is sanitized or not by the host kernel. Then those field values are likely +to be overriden again by legacy CPU options which apply at the end. + CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -126,13 +141,20 @@ A note about CPU models and KVM =20 Named CPU models generally do not work with KVM. There are a few cases that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a -seattle host, but mostly if KVM is enabled the ``host`` CPU type must be -used. This means the guest is provided all the same CPU features as the -host CPU type has. And, for this reason, the ``host`` CPU type should -enable all CPU features that the host has by default. Indeed it's even -a bit strange to allow disabling CPU features that the host has when using -the ``host`` CPU type, but in the absence of CPU models it's the best we c= an -do if we want to launch guests without all the host's CPU features enabled. +seattle host, but mostly if KVM is enabled, the ``host`` CPU model must be +used. + +Using the ``host`` type means the guest is provided all the same CPU +features as the host CPU type has. And, for this reason, the ``host`` +CPU type should enable all CPU features that the host has by default. + +In case some features need to be hidden from the guest, and the host kernel +supports it, the ``host`` model can be instructed to disable individual +ID register values. This is especially useful for migration purposes. +However, this interface will not allow configuring an arbitrary set of +features; the ID registers must describe a subset of the host's features, +and all differences to the host's configuration must actually be supported +by the kernel to be deconfigured. =20 Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. = The affect is not only limited to specific features, as pointed out in example @@ -169,6 +191,13 @@ disabling many SVE vector lengths would be quite verbo= se, the ``sve`` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 +Additionally, if supported by KVM on the host kernel, the ``host`` CPU mod= el +may be configured via individual ID register field properties, for example= :: + + $ qemu-system-aarch64 -M virt -cpu host,SYSREG_ID_AA64ISAR0_EL1_DP=3D0x0 + +This forces ID_AA64ISAR0_EL1 DP field to 0. + KVM VCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -495,3 +524,64 @@ Legal values for ``S`` are 30, 34, 36, and 39; the def= ault is 30. =20 As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or removed in some future QEMU release. + +Configuring CPU features via ID register fields +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Note that this is currently only supported under KVM, and with the +``host`` CPU model. + +Querying available ID register fields +------------------------------------- + +QEMU will create properties for all ID register fields that are +reported as being writable by the kernel, and that are known to the +QEMU instance. Therefore, the same QEMU binary may expose different +properties when run under a different kernel. + +To find out all available writable ID register fields, use the +``query-cpu-model-expansion`` QMP command:: + + (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} + {"return": { + "model": {"name": "host", "props": { + "SYSREG_ID_AA64PFR0_EL1_EL3": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, + "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_CTR_EL0_DminLine": 4, + "SYSREG_ID_AA64MMFR0_EL1_BIGEND": 1, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0, + "SYSREG_ID_AA64MMFR2_EL1_CnP": 1, "SYSREG_ID_DFR0_EL1_PerfMon": 4, + "SYSREG_ID_AA64PFR0_EL1_DIT": 0, "SYSREG_ID_AA64MMFR1_EL1_HAFDBS": 2, + "SYSREG_ID_AA64ISAR0_EL1_FHM": 0, "SYSREG_ID_AA64ISAR2_EL1_CSSC": 0, + "SYSREG_ID_AA64ISAR0_EL1_DP": 1, (...) + }}}} + +If a certain field in an ID register does not show up in this list, it +is not writable with the specific host kernel. + +A note on compatibility +----------------------- + +A common use case for providing a defined set of ID register values is +to be able to present a fixed set of features to a guest, often referred +to as "stable guest ABI". This may take the form of ironing out differences +between two similar CPUs with the intention of being able to migrate +between machines with those CPUs, or providing the same CPU across Linux +kernel updates on the host. + +Over the course of time, the Linux kernel is changing the set of ID regist= er +fields that are writable by userspace. Newly introduced writable ID +registers should be initialized to 0 to ensure compatibility. However, ID +registers that have already been introduced that undergo a change as to +which fields are writable may introduce incompatibilities that need to be +addressed on a case-by-case basis for the systems that you wish to migrate +inbetween. + +A note on Arm CPU features (FEAT_xxx) +------------------------------------- + +Configuring CPUs is done on a feature level on other architectures, and th= is +would imply configuring FEAT_xxx values on Arm. However, differences betwe= en +CPUs may not map to FEAT_xxx, but to differences in other registers in the +ID register range; for example, differences in the cache architecture expo= sed +via ``CTR_EL0``. We therefore cannot rely on configuration via FEAT_xxx. A +feature-based interface more similar to other architectures may be impleme= nted +on top of the ID register interface in the future. --=20 2.53.0