From nobody Sat May 30 18:34:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187150413662.0393046712998; Tue, 19 May 2026 03:39:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHqq-0007nG-2l; Tue, 19 May 2026 06:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqo-0007ik-Cm; Tue, 19 May 2026 06:39:02 -0400 Received: from mail-westcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c112::7] helo=CY3PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqm-0006QA-Jm; Tue, 19 May 2026 06:39:02 -0400 Received: from DS7PR05CA0080.namprd05.prod.outlook.com (2603:10b6:8:57::18) by SJ2PR12MB8035.namprd12.prod.outlook.com (2603:10b6:a03:4d3::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.24; Tue, 19 May 2026 10:38:39 +0000 Received: from CY4PEPF0000EE33.namprd05.prod.outlook.com (2603:10b6:8:57:cafe::25) by DS7PR05CA0080.outlook.office365.com (2603:10b6:8:57::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.15 via Frontend Transport; Tue, 19 May 2026 10:38:39 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE33.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:38:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:18 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:15 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=aVLJKGVn23ImcksluxsvLrTpHlZSnk3Bwq4CkmpEiXxTH9RAPv594i5q9qQvaDbWhLvXRfjJ1wyvoWPmrqD0lIl/MycySG6dsaHNqeGj/OTRcVUvbIvYYX/GCoJsMG/tGVZUDjEd8Wh3WAKBAPmDMBQvR75vLwQyUhsmDe0r3ECDLicwmWMXQ+/13TYjqIj1MLHWsISiNZSxVJ+8IzPdVWzrSlXhTC2aRdc/dsh7pD1aZCnAo+g2qF7M53JAzRZV36pwFUOKt0WZLF58BbL5XOKTXbkCH911/8SpLSv5Msi9h11V8rwER+GrvJk4dq0iBj/NFIhXm1KzG+7eTp+knQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JgTNy3hszip6UP8F32rndIUFqSreKJiMal1aSrvLFBQ=; b=a9Z9+GSMdYss9dBhtxbZVo4zu7/boR++WDkZmW51r1n+2HXwF2zkmMMxhfAiiCy/j6JhxhMrkbnS9uUPfB26s8yNsFw+wxe94KsZXVW0FWLqbe/oW1zR9+Rx4hyQyalfSd5DXD64oNFQxGC7C6M2E9tJg2SMP/bjCHKkal8evx8UVThLFyAz/DaOBfc8XgTwA2axD53efkjwy4D8Dm2bPgOcGdcdKMqEzmzJO1rOUn5IUCX/dqH7YWwcAZld9g5mFjXke/Upc9Pd8wbt3CKV04KhYKH2oMNGELtukpPGGWoO64uwIX75Fp9H/TZ62h85u5Z1+Yt/54LB9F11hpR9bA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JgTNy3hszip6UP8F32rndIUFqSreKJiMal1aSrvLFBQ=; b=P+CYus4lwoMpLO5kko0nzNl10B7vyEqyg8F4GgGEU73GmyL75DNVsmCXcCtL/52SBH6oKBi0Svw3zTN+755VIQuKjHJhIPCc5sf0QS4zoOEWVxtQ/Ay2LKNW4S5dRFowJ0jM5qqYr1PnmtbT7Y4sN9y5Z9BNkdrUsS+upgwDYS7kfCyKPUtqaMXf4ymum+IkwF8g0TPPaplLNaMGtf0OnDFlP+MmGW/ec4MNfN2XbSAYuhjRVeQCLnAcVlfHz0at0V67Imo7tnSqJQyC1tgBkS65hZd0pBOzOCTNzGl7o0GaNdPSpWkGsk6Qf+gHEf5mH0hMThklHRNtGqTgUTu0/Q== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 01/32] backends/iommufd: Update iommufd_backend_get_device_info Date: Tue, 19 May 2026 11:36:39 +0100 Message-ID: <20260519103727.899332-2-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|SJ2PR12MB8035:EE_ X-MS-Office365-Filtering-Correlation-Id: f4911ff0-c761-4987-e0ba-08deb592c9d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700016|11063799006|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: YYraPJt4lv8CynqWHv9ANqj4bMpzYsAkJpsPHI2Ixtx2IMD3BIu3YrwGj2udvX/r5/awgZfOqdZCI5Gb96gbEp7ouf3Dcnch9DazTWYZljjKMulF9WZHWKHtGwf69O6vWwhieVi4Akb+VxzcsuTIX4+50CAoyH/OIkHvfUkkPoiqMi+7r/gmOWhHa7UPLX/icx7E4JbffWr0gbsjz8+uAEEZKyAoTCTfxNuc1hG2IiwhHGQF+kO1BOhemdoZ4w3t1WgtUGbnswR1X6ZeboFHPMA+qEJIyAS0mCA0KASDLOd7dT/jPm/aD8yMRdyU0NEk7Rj38x36c9M9DKgQQd4rttBH/kN4vrCldAaqvQPF8wKRDdjWsQYCFExpiJdbnewqR5RNhCyQHQLee/lhV2C4NS8kIX8qcs0CwlL68N8WkVA7wcCHVingYP2gQis2askQMMLvf9UXLFbucjgccabeLz0ic7dveVXVgAxa/QJb1FD1eEybPkPBubJNAKvTbJBUW/FPqpFxkhJ2UX/VHMHvY1ORuD9OIUzALoNzzZVyH1TTSj67pw2Iy9YRHB7Qv9HAwh9L9H7pameY1ACeCpasoykhGOO9MyQrSd8q1VZDVta/rR880OgNE6RbTXJjwiwh1B53ylXKIH/L65gR+a7agAJHgb5jRDP2XoY+u/9cu4J5sDRxzdW1CXMqr1Ep5PN8j5ZWoM2EuYA6x4zLcfhQvQUMDRRKUaGPn0mCsBLZchA= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(11063799006)(56012099003)(22082099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DBiwEJRffNEd52eSE4wTZ3Wk56rBJDUASfu27I94k/Qv9K0Cl47Mza6JTlMPQsv3zfewq+UESM4Xzb9C7q+WNm8epUTeRC8SKvJGdA6+A8qK722wl9wIbHfm+BTDDol26er1z3oCNH+AotFgx9mJNYWBEgLKn2k+ZS7C+zvGaXznx04UvswhTULy6D7vVYG2+R22wytnvnbMOylk4VzrTU7rTjp32Tdv9tn+hqLzhw0wsXdz+syUelDuG3H4H7tQiY+RDeC8Az2Zwf/jycGZiysaHOSs5pXsPRs5kL01oHo1NrIop7qfQLsrfCDKSjHrj26cqEewqfPIT9JWLFQZTOW66/LIU0Y+P864aNSYyXwwOdOQgRHMpCzFd1FABMD71LWJec6vyGu2E0BqYqbB5ZnLj12XLJERJ5OMJYJe4DHxVOLsETE8ovlkbakIIKwY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:38:38.7863 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4911ff0-c761-4987-e0ba-08deb592c9d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8035 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=skolothumtho@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187153614154100 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The updated IOMMUFD uAPI introduces the ability for userspace to request a specific hardware info data type via IOMMU_GET_HW_INFO. Update iommufd_backend_get_device_info() to set IOMMU_HW_INFO_FLAG_INPUT_TYPE when a non-zero type is supplied, and adjust all callers to pass a type value explicitly initialised to zero (IOMMU_HW_INFO_TYPE_DEFAULT) when no specific type is requested. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 7 +++++++ hw/arm/smmuv3-accel.c | 2 +- hw/vfio/iommufd.c | 4 ++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index 410b044370..8c3a981392 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -390,16 +390,23 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend = *be, return true; } =20 +/* + * @type can carry a desired HW info type defined in the uapi headers. If = caller + * doesn't have one, indicating it wants the default type, then @type shou= ld be + * zeroed (i.e. IOMMU_HW_INFO_TYPE_DEFAULT). + */ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, uint64_t *caps, uint8_t *max_pasid_lo= g2, Error **errp) { struct iommu_hw_info info =3D { + .flags =3D (*type) ? IOMMU_HW_INFO_FLAG_INPUT_TYPE : 0, .size =3D sizeof(info), .dev_id =3D devid, .data_len =3D len, .data_uptr =3D (uintptr_t)data, + .in_data_type =3D *type, }; =20 if (ioctl(be->fd, IOMMU_GET_HW_INFO, &info)) { diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 05257f74ed..eb13c0b91c 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -176,7 +176,7 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *hiodi, Error **errp) { struct iommu_hw_info_arm_smmuv3 info; - uint32_t data_type; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint64_t caps; =20 if (!iommufd_backend_get_device_info(hiodi->iommufd, hiodi->devid, diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index df148a49a7..495a59cc2e 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -353,7 +353,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, IOMMUFDBackend *iommufd =3D vbasedev->iommufd; VFIOContainer *bcontainer =3D VFIO_IOMMU(container); bool viommu_nesting, viommu_nesting_dirty; - uint32_t type, flags =3D 0; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT, flags =3D 0; uint64_t hw_caps; VendorCaps caps; VFIOIOASHwpt *hwpt; @@ -948,7 +948,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *= hiod, void *opaque, HostIOMMUDeviceIOMMUFD *hiodi; HostIOMMUDeviceCaps *caps =3D &hiod->caps; VendorCaps *vendor_caps =3D &caps->vendor_caps; - enum iommu_hw_info_type type; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint8_t max_pasid_log2; uint64_t hw_caps; =20 --=20 2.43.0 From nobody Sat May 30 18:34:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1779187159; cv=pass; d=zohomail.com; s=zohoarc; b=VhM2ZbqkVISnOCdezdtJ7oJo0964OhMKkIa/DEXiK8Qqmnp4i6v8QcRhD3jggYjyhUb+FOLmZ2UUl0dWUUIJgMKAx062CzWhPT/5jfPvNVOkWj03ifdq1O6LbW+CzwOT3gA7ia+3xznoHv+ObOpiwAHWvcKGoh7Ek2IjXBlzx4w= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779187159; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0DHalkl6U1SnjL4NrFI5rvhEuwvggRbVJd5vIrE2NmI=; b=g+W01oQ3mtVHG4w1U/mvvBxPTAJSJRh1+YAfVz1EpfDeG8LKUSPdvgzdEBEMFAcBRmIqWWXiisXIXQDqSYOeDtrYdmUA3HIOhCTERMv8p2EiZn1hVWG6UCA1qc+CwXqGZa0m9r3fHdF63YVv1OYygo1/7UHaSP2eLbqIzDVdL7g= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187159609650.7952066353881; Tue, 19 May 2026 03:39:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHqd-0007T1-8l; Tue, 19 May 2026 06:38:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqc-0007Sm-20; Tue, 19 May 2026 06:38:50 -0400 Received: from mail-westus3azlp170120001.outbound.protection.outlook.com ([2a01:111:f403:c107::1] helo=PH8PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqa-0006Ov-Co; Tue, 19 May 2026 06:38:49 -0400 Received: from IA4P220CA0002.NAMP220.PROD.OUTLOOK.COM (2603:10b6:208:558::13) by BN7PPFED9549B84.namprd12.prod.outlook.com (2603:10b6:40f:fc02::6e7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.20; Tue, 19 May 2026 10:38:39 +0000 Received: from BL02EPF0001A106.namprd05.prod.outlook.com (2603:10b6:208:558:cafe::e9) by IA4P220CA0002.outlook.office365.com (2603:10b6:208:558::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:38:38 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A106.mail.protection.outlook.com (10.167.241.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:38:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:22 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:19 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=L00ECBITNvO+YdBx2KS+ZM8pEZh30ZU6wAG+L6yW5Lp5FrwrNlK9zDAnbQnCFUkXHNjkzTcxR4AIFb5BnuYMGHp/5kmPjO9bA5p+p7vUedK5BQ9y/qsoXPd7q58La9DZDx542wZPg/Yr5dnscfJ8/O3mIPkknnZlvFSLR21JpoXUuy0E7cXdNQp7ymVwMwKCTB8tlw81dRUUZcNWm3QZ1QeY0/dfsdKSh/jN2W6f+9JKmu658cjfvCgIaGH1PzRDmCR36F+vzICQQgDnjabs/TUngObjR8ZSmdqTL8Qz9/9brg2XbdsaqAO8BusulcndPWckGTQIG3H1FnAxzyANTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0DHalkl6U1SnjL4NrFI5rvhEuwvggRbVJd5vIrE2NmI=; b=f1++4DhMtBhjqAwBokdtshXh29DIab9XBe6r1qvH8kuwasYQsalIY0/Xv/6vkEaeWjQ87wLxwyWyPohWwE+HCK0gdNAHs1dhfdiFnzIR8MqlJ2frRsdVsfwNXzW5g9wDA7BbXZoAvmR5/EgQC6vdfpulaD7nfDvgBorzUVk4JcSQbgF7npprfDJOMAinqMlrrd2HfXXEF7DS1YCveDg2+E7MJ1rJAjUYLEl3p4Y8oBHj1+Wx2003YmBOzutKezLmIGUwYD7gsJOYWXSQDPDIXr+bXirw34pGhe0ExKHMFVvKU1jXX+Ug/lH2QkUX7wF+5cFI7OsU6DO/79/2yhgcBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0DHalkl6U1SnjL4NrFI5rvhEuwvggRbVJd5vIrE2NmI=; b=hLjvq4d4kU5BYrRnO09pDt3gK+0Km+tvmTMXE4svvgmcdPe6qjmx1x43YRkvOH6Szmr1E/QGaRfVuMUX9J5aRK606f90H/nANbTJPwJlNLjPm7GY9sjdPTksvonOgmbE9mFh2zz4pKxEgRQCKwQYLpWz5IgdbHzjCrK4WR11+mNZIPbQDAc9LsMSOOBRK7CUp2dZARrygTygLRZRCbbgaw/Ko/LMLEZq3rPqdWA6EZwrh/EFfdApcvxUrNwNGEubo5f04Zl2esx2biNZx27wD+fcUe9hvgzMfD7gp9zSen2d7yg/ccJNKNCi1bj6l52kxbclKhvzZplcd0n8vxUJmg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 02/32] backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr Date: Tue, 19 May 2026 11:36:40 +0100 Message-ID: <20260519103727.899332-3-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A106:EE_|BN7PPFED9549B84:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d911c3d-7780-420c-be6f-08deb592c9bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|18002099003|56012099003|11063799006; X-Microsoft-Antispam-Message-Info: aMqitr3QZW7ffagpbLJ+Bzn2mYX/9fo9SKcjC8ZjP1mC/r6BN7/juwhv4nA3Ql/GAJBd1zGfbE/Y37sSalLgGH741b97ZmucSiOK+U0GRfoSgQsY/ZkRUwnBFW8J5gPHA3bx953FPR5oVmRnSOJv2XY9W9vbkHiEsn0pKIFO1FRnebL5fqLUqOYVul2sJCF1JLaBIzoNCEzMujF2Zxm3E1QHG90Jx4sb3cSBboQgY9pWF1PipmXK1UqI1S7Vu9fJe392E8oXWvZCf5DvVLGDta9LY+DY7BPnpIfqZB5LLoQQQPF/eVi/4kZCK1SGFKN5cbx6S1lUPtPMFdxd4EfMeLLMzrQk2+fq4s7iaDtc9aRRIm0HRSSBqnoc+HByX7/nNt0MhJ+HrrL/RSrWSC0Vv3Uu6HYIU44Sr/7RPPvjhYFI8wkTu640yl7P0VbKtBjY5ZhCFiXaw0xql6rAiAgxYUFnnnZeLS3rkGzg/AQVz9W++KBeqXReFZhf+g1R2KVz1s4V6i+InbloywwXKFeOzLvs08lUBtK/I8E0ggeevM9mq/IL0DDqSc8q51/CUTW/KLZvqiyRVw+KyDWeHATgQfgCMIZRU1D7TTDpgPci0/q1AQklkaV5FXn1ZhPpVvq8QvQhVRRDj7JBAIrdkQVYC5SDTn+XcDwxBZAGgUvKXZmhw7h1GGT2Jn1Bx3eTVeAlHEICztVMNhnsg3ZYpdaHaQnSKTFexd3AuKcMx5tv5MI= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(18002099003)(56012099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VlDqapv0cC00CzeCXV3hg94CGTLHkki72cl7cilB4moRPdkdWXKnhvlwdJx+tkmH1KMhVIZzcGU+mfmK/vCNEYAgrLRvWelO4y3KdRBeDEOD9AWfn496iDWI7Fmu4O+8yH+DRSkm8Q45ciDAUh6ZCdo/IpiQP3QEZIqUN9gx/ai5F9DfZzOLY+jmaKhYX86E8Xs2+ZWAnjNxyr7+9SnWuJl1HF44PTEko/oYUhW5twQgf3bHhD13IbnbIzwm5X+1HWnVWN13m8fFqin6vU4Y8r8KgFBp4H3C2TcUrlwPuZ8YfAl3rWsywwLRJi7g8ZQa6YvB881jhywn9Om3Tq3SEd0tw2AuOavvvWaouYZpw7bLmogC74RmxfO/F6y8w+uxhgw/OhaUhz7k/KwpIqxvwlqVJiqgMfAtxb6qoct83HdPDDAxWV+ooVoJxC9jgjgT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:38:38.6091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d911c3d-7780-420c-be6f-08deb592c9bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A106.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPFED9549B84 Received-SPF: permerror client-ip=2a01:111:f403:c107::1; envelope-from=skolothumtho@nvidia.com; helo=PH8PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187161487158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data buffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend iommufd_backend_alloc_viommu() to pass a user pointer and size to the kernel. Update the caller accordingly. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 1 + backends/iommufd.c | 4 ++++ hw/arm/smmuv3-accel.c | 4 ++-- backends/trace-events | 2 +- 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 2925d116ac..1b0266f660 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -89,6 +89,7 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint3= 2_t dev_id, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_hwpt, Error **errp); =20 bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 8c3a981392..c745dbd2b1 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -463,6 +463,7 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *b= e, uint32_t id, =20 bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_viommu_id, Error **errp) { int ret; @@ -471,11 +472,14 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be,= uint32_t dev_id, .type =3D viommu_type, .dev_id =3D dev_id, .hwpt_id =3D hwpt_id, + .data_len =3D data_len, + .data_uptr =3D (uintptr_t)data_ptr, }; =20 ret =3D ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); =20 trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_i= d, + (uintptr_t)data_ptr, data_len, alloc_viommu.out_viommu_id, ret); if (ret) { error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index eb13c0b91c..bfa6a03f9e 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -582,8 +582,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *hiodi, IOMMUFDViommu *viommu; =20 if (!iommufd_backend_alloc_viommu(hiodi->iommufd, hiodi->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, - s2_hwpt_id, &viommu_id, errp)) { + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, + NULL, 0, &viommu_id, errp)) { return false; } =20 diff --git a/backends/trace-events b/backends/trace-events index b9365113e7..3ba0c3503c 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,7 +21,7 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" -iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" =20 --=20 2.43.0 From nobody Sat May 30 18:34:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187184355940.0481857005035; Tue, 19 May 2026 03:39:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHqh-0007Tr-0s; Tue, 19 May 2026 06:38:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqf-0007Te-0k; Tue, 19 May 2026 06:38:53 -0400 Received: from mail-centralusazlp170110009.outbound.protection.outlook.com ([2a01:111:f403:c111::9] helo=DM5PR21CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqd-0006PM-9F; Tue, 19 May 2026 06:38:52 -0400 Received: from BL1PR13CA0226.namprd13.prod.outlook.com (2603:10b6:208:2bf::21) by CYYPR12MB8964.namprd12.prod.outlook.com (2603:10b6:930:bc::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.21; Tue, 19 May 2026 10:38:44 +0000 Received: from BL02EPF0001A107.namprd05.prod.outlook.com (2603:10b6:208:2bf:cafe::6c) by BL1PR13CA0226.outlook.office365.com (2603:10b6:208:2bf::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:38:43 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A107.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:38:43 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:26 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:23 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VFc3ZCUBmf5mUNUyPuyNxXrye+evBqv53UPphHmBYmwttalmnsIY6Sgc+j3zxutPRledpE326YKhShOnIvF4tybcgHnf8KGBTb07sTMya0AWIIdmFv0rTjAr6UWjBTZLqd+rI+4tAazCjYWZ657WbdPfOKgLRFQI/J2pkARj0Ovi6JaJ4Re4KJ0+n1ETLCa+cQYDXyjtVybv4yKW/PEt41+DIoAiXIf5FCY+snOgp0dgENWc5kxwNms0yGaM87NLX8FwkY5CWxmg0aFZmiyqbBNGqbDydvBZXzA1pUY4lBvttELZbrANWVyQv4Mu3NsHsRyQGEq7CCHW8Cta67vNhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Uayp8/2xIDziKqIY63vmrqb1h45tpB77/C7GEy1wyoM=; b=Ugn0mNW5KQJBzodf+155nlAgKcP0DeXm3CIJi90vROdtV/TVRL/bVI1kuIhYO5LVuHGJSarf3BS8hwIJefxdUxo+vBwt6f/uWImWNDlCs8VGtTzsNswsPNYztep7sKA3qvALyji6pdZRKEysi/YlFuc8A3fPXrtucW/GOSjeiUtSbw1kFpTSST9U857MxAmt2hrI/SfAKPLSw2DxM4w73CPaMqPlE4TR0ww56eSIw79lDJvjKb+xBjqxIcdiLM6oJppHOxj0XC7h2UDSm8cqCtRNf61G6tpBNOIr+NRXBCAosoLpshlLbTMkRNZ6jNLterhmqJWWetZs3jqCNakExw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Uayp8/2xIDziKqIY63vmrqb1h45tpB77/C7GEy1wyoM=; b=OtZjpe+6mivdPrwXEgeeJbPrVRlw/fvH/+bJfOjMh0aAHRbwHVTQqcR3pwTLbtwIbOc/WwUWltypqG8pJXY3bO8NAvL62vqu2X+mbYG8G34gJ0ZZVy2/6a7rK6eG8HxO4wE6zkX0tDK8r6elYVjUazNLRtugiaxogXqcmUwqUnKH8IF+VADasu0hckptsf5i2LaHlhCxT2e8Ccn9cXt8ZWEJCwBH3u03wPJH9l9Y+jnUwMoNyCxeSghRD0wfMeo0F02RnbsQ2kJLDDvX9YLOdXU9G3csDQzxqwtfGeM/JV2vIDMYFa/8vXB8KmFh3mNCqF+RVJgo2fClpV16IFH83A== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 03/32] backends/iommufd: Introduce iommufd_backend_alloc_hw_queue Date: Tue, 19 May 2026 11:36:41 +0100 Message-ID: <20260519103727.899332-4-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|CYYPR12MB8964:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e8153e7-ed52-46dd-76af-08deb592cc7f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|82310400026|1800799024|11063799006|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: Dy8XXmNYcNuLISZ0I6cKBBa6cYw9Ps60PJAdv0tjTLNyyvzUI0NU/RqeNXOieqJK0dmlMtHihdzZiDHMT5JzFWDI0UCJ+reefrzv9qRW0KJLmkZsAkwM139wkXlfJs6IGXl1e0p4yilJ1Up9r0PwIHgEChITrJXMvSLOCC2FKZC6GMX43VIzcu1F1dSX7nFJHu8RVkV417Em73Ncpnop2Ia9988v5Dd97ynYojx5Km5GXCSg1XmUqUt3a/7lLURqsXKKePxBs62EWLFYs4TH1edhjLDw6MHQgv8HN7d5G8sitiAXoYb5nA0JCUu3ZJ3zqGqCIEub+PPObYJceXmThA0fhY4Aa6fvLtUXIgOEfsnnZly0AUH3LsG0UXGqVI99cpOZJSJwqtf/ogllendSrWt0IuXyK/rse5csF2lSgMzcSwrNHu2dUj2gM7pIax36Z0+arHzjSO6zNjywbZvvzq6kuKUVoWk8ItJMP62GDmLQvMUqFS938Cdvn2jfmgkNN1HUQS6EnAU36dWQIrDe+FbY4hN3DD1knSpStzal2I6HuJnu9qbg2zuAcwDzInbBdRIwWH2uni2jP5DhxSw9LSvQYQrhpP1UDpFHD4I68WgR5K+FrdcJfmNyAP2HBQBr9G9qlvHxSdSTkRxE84PbCh9H5SoBlyROp8fiGduNfFf5YPsI7mpfP1DvbHBe5IPeOnIXHHMYTzQYIrTkLKsX2xObqaRUYmSvk499jZ7CEmw= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(11063799006)(18002099003)(22082099003)(56012099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: d8NHsJg6mxoW34lgCE0EjJ7oAKzdk6nt2Rj7CPVY1BZhri7T4Ybhzan+Ip+lnu2LEyhl/fdKJ9uuMrWJRPHLQkAVYmUp7cSkRwMZ8fB7rmkOAYi27xtr01768hKaDCNbM2768onXUmtNL2nyGdVT/fHaqOTPD4Y5z0IhWGWz/9ZrGCcBRXK5hEeH/3YP7jG7vEk6aNQMQCs871SNLi+y1W9EfnOil312yXKFwRIZh3vmYuH6dqBbT6CJsQaOwLow8D08X3wpAx6+IiIO1diz93+QAIzql+6zuPshdGbfYsHU3IxepnoGN/u+4M/jqsFmcwxQMsP1IQvxsUjWd1CnF5VtX7JfSgwLmA4VnEhDEGQVzccOePfJVCcfkrGPSBiUHsz+S6HgeK+4VY1r56509lChvvd4VX6b/ceL716RasaKTzKu6XpEhX3fc+cPCE9M X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:38:43.2062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e8153e7-ed52-46dd-76af-08deb592cc7f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8964 Received-SPF: permerror client-ip=2a01:111:f403:c111::9; envelope-from=skolothumtho@nvidia.com; helo=DM5PR21CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187185477158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd backed HW queue for a vIOMMU. While at it, define a struct IOMMUFDHWqueue for use by vendor implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 11 +++++++++++ backends/iommufd.c | 31 +++++++++++++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 43 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 1b0266f660..c6f2e87a7e 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -65,6 +65,12 @@ typedef struct IOMMUFDVeventq { bool event_start; /* True after first valid event; cleared on overflow= */ } IOMMUFDVeventq; =20 +/* HW queue object for a vIOMMU-specific HW-accelerated queue */ +typedef struct IOMMUFDHWqueue { + IOMMUFDViommu *viommu; + uint32_t hw_queue_id; +} IOMMUFDHWqueue; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -101,6 +107,11 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index c745dbd2b1..8eaaf456e8 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -549,6 +549,37 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, return true; } =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p) +{ + int ret; + struct iommu_hw_queue_alloc alloc_hw_queue =3D { + .size =3D sizeof(alloc_hw_queue), + .flags =3D 0, + .viommu_id =3D viommu_id, + .type =3D queue_type, + .index =3D index, + .nesting_parent_iova =3D addr, + .length =3D length, + }; + + ret =3D ioctl(be->fd, IOMMU_HW_QUEUE_ALLOC, &alloc_hw_queue); + + trace_iommufd_backend_alloc_hw_queue(be->fd, viommu_id, queue_type, + index, addr, length, + alloc_hw_queue.out_hw_queue_id, r= et); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_HW_QUEUE_ALLOC failed"); + return false; + } + + g_assert(out_hw_queue_id); + *out_hw_queue_id =3D alloc_hw_queue.out_hw_queue_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 3ba0c3503c..c5c1d95aad 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -24,6 +24,7 @@ iommufd_backend_invalidate_cache(int iommufd, uint32_t id= , uint32_t data_type, u iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" +iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" --=20 2.43.0 From nobody Sat May 30 18:34:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187191028432.12661011235025; Tue, 19 May 2026 03:39:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHqm-0007ad-Kf; Tue, 19 May 2026 06:39:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHql-0007Xi-7K; Tue, 19 May 2026 06:38:59 -0400 Received: from mail-westus3azlp170110003.outbound.protection.outlook.com ([2a01:111:f403:c107::3] helo=PH0PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqj-0006Q1-K2; Tue, 19 May 2026 06:38:58 -0400 Received: from BL1PR13CA0166.namprd13.prod.outlook.com (2603:10b6:208:2bd::21) by DM6PR12MB4434.namprd12.prod.outlook.com (2603:10b6:5:2ad::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.25; Tue, 19 May 2026 10:38:49 +0000 Received: from BL02EPF0001A103.namprd05.prod.outlook.com (2603:10b6:208:2bd:cafe::1d) by BL1PR13CA0166.outlook.office365.com (2603:10b6:208:2bd::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:38:49 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A103.mail.protection.outlook.com (10.167.241.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:38:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:30 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:27 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dXYiUNksPPK9B9ncnVH96jZHZgF79enpUI2xCuMIuVyGrWxqGsax9IPmJXWmdMYS/kaIc9bhDY30u2KSoj6yaEGxdSdzc2EdlthjhYjJaxGavk13piibE8OSsu9Iokn8PYlXVB5lR1eJ8kN1wPd9j7gSBFnU9m9V62BuIiZO9SgFx3wzh8YrP7k2vg3LtufpaIdTKGMJLaoLe2YSHccKJyN0Rxqqh+GZt2veXccQ3EPYleQI0SZjrrgifzwngohsLHPrXLfXoSJ3JHrqycHIojRIW0HOAyAo9sT2UZQFOi2mW2SQVpzGD3NqyCoJyUGCTmXNmSjDEbSdX6vUHI6sEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AlD6pyhUH8jjkVrSnNE4WiCKsyHJm9VqTGxARHi+44g=; b=FxxfZfBn9nVDp1KI4C6eS472RTAvIAnwlPthIHfOzQMpwC71S73FIAb0xKeCbHz84IQ5hJEkImFiN6FhW8jF/U2M1id79SYL/K5gtk8MYdiTYf3HnotaaImeV2dBhIGt5i/Uot1qmaS34+50KnTAeFqV/SnVw6ZAjVUPFCQP/ei5wSnfIBMdFVB0Ie4IWjbn7I+6HsLwpF3g5LiWksWId33SL6eJoP56ui6Yt5Mqs7vAwCXlU2TUKUjTyajBwIoOGNh6Rg066te8ZK842LgEo5ogMtor1Js2i75KQKgQ69JE3p++c3ylri0nuTJZvJn9NFrAZoVTAQCMb+yqYjjQ9A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AlD6pyhUH8jjkVrSnNE4WiCKsyHJm9VqTGxARHi+44g=; b=qATrYslZP71X1dVMnvKz61x5xQT8Ae7TWFkySWOvMzuPKQp9JgleBYCQtm+fsI6AYW9SsWzUI89+OAYG4q7qCe9ReoFb/pOpDVt/FesySk0guWDhQt6nuC2noj3MwsKslcy+W8/Rfzyc9DJbYETw4aMc8XwlDb4vqjRkzp8nxzuWptrBmGveXIip8Mrm5sCF+TJi8q3ZNTrz9Y14UvZ8e4x7htNLCqhmwk/NGOvyXYcRmGRBDlQikEGgO5Id0402lAisbM3eltGjdbb2qze+pJgxt82kz+AAZGfJJ5XFEO2zkmiRiPxss6yD6wLV1j7ABLA/QzAa9tN8uajcH4fNWA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 04/32] backends/iommufd: Introduce iommufd_backend_viommu_mmap Date: Tue, 19 May 2026 11:36:42 +0100 Message-ID: <20260519103727.899332-5-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|DM6PR12MB4434:EE_ X-MS-Office365-Filtering-Correlation-Id: b2990cca-5259-4cba-fccf-08deb592d034 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|376014|1800799024|11063799006|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: 4dG6jvaF+5UAF7TK271hEeHhz/Q60Bha8s4dQMR1Hrzb/RsBOLtoHMpoOGDOzKIFnNy/hUfHyzly1NopYniQdmZBoT3F32XO8kVTogbO9mPhnJcZn7hLuPtAyxGlXxlyb+5wB6qivO+bMjs24enSIHcAEM9VO3UhyrU9xac51Ke7O+nocn08l7evPtS4W3aqKYTYPhQw8HvzkB1sAK0kMkljJBzGwA8YUcwVWQnt4nwyj14DpuT0r2es6ftxagWddwoSBfyd6RoxfF5KcmX9lAeTMHbyLcYiXQCPUE7ANB3wca+23GcT0c09Ljfacfz4+qo+KcJpcg4FlwujSG2w8V+YUZivpdbiwAmNpxmJ4RX0uOLsVFgsgfz7qbi2r7d8xqZHkKtqVwi8kisQ3bmVs6J4Tp0xvUp4mUxpDiKJBzvILiHGvi6heFD7AIa+icZhIiDntzZVWDP18FQWPEDBkLrhJmabgqzaD91STT0ZK9MJydJQWOmvAjrFVTQfsMoJEFRn1tVRy8TmvlrXlA7YwNxunrGUCwTkD4eje3QbaJmJWVfZnJi2ECRypo7Wuu3q0nGrw3byPiib9Ut5oT3U/WOIee93ZTxuz/EpJvx1nweeb0mgEiK+U3pdEwsq9F1itx/RGKCsketcUtZYSf7bzAXpD/mcg9AJI6RD0xqICcduWn3dPs1721u832oGV9Wg3IsFQY4nEQbudx4JZKnjm6wQQjayedKd0QoLPInXjuo= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(11063799006)(18002099003)(56012099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OVzxC8gF2dLKytCvrgsfB/sUMdOqzdDAWp3eg97ZUNh99RbnTVJjDBNIRBqzH2ZpXaQL1vid9p6jsJmL3qltAhLQR7a7FmvZZ29ewbhpcW1ugF7pM3Ngl1vufxctFzBj1DCnl/VsFfu14U3XVIKrOui1KnraZ++hto5CuPcB0nWB5BmCKzphtPhGSeosLmIJEVTZwX9bwMaj512dQgFUKgKH2fxP0215gv3OInFoToKWfn5U0JlQN5bBvQfWUotZISVTMzxNL+3jzhF0VhMlT1aB6KTMj5oT2gYuphV5iR0PrU1ynS1Arzmci8LUx4Cu+QnEd1u4bgIQfHCQzs3tVk6fiGMx8DkgLLMzNaXBo44M5YnKsih6YyX5NBTOZixJYZeLddoiLHXqLp7c9Ecae0Hoa+jhOR6s81jr20Uwm7oftBiIWxznO3Z5R0kMHshZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:38:49.4303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2990cca-5259-4cba-fccf-08deb592d034 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4434 Received-SPF: permerror client-ip=2a01:111:f403:c107::3; envelope-from=skolothumtho@nvidia.com; helo=PH0PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187192093154100 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a backend helper to mmap hardware MMIO regions exposed via iommufd for a vIOMMU instance. This allows user space to access HW-accelerated MMIO pages provided by the vIOMMU. The caller is responsible for unmapping the returned region. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 4 ++++ backends/iommufd.c | 22 ++++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 27 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index c6f2e87a7e..bb8d5081d7 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -112,6 +112,10 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, uint64_t addr, uint64_t length, uint32_t *out_hw_queue_id, Error **err= p); =20 +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 8eaaf456e8..440c1b82bc 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -580,6 +580,28 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, return true; } =20 +/* + * Helper to mmap HW MMIO regions exposed via iommufd for a vIOMMU instanc= e. + * The caller is responsible for unmapping the mapped region. + */ +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp) +{ + g_assert(viommu_id); + g_assert(out_ptr); + + *out_ptr =3D mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, be->= fd, + offset); + trace_iommufd_backend_viommu_mmap(be->fd, viommu_id, size, offset); + if (*out_ptr =3D=3D MAP_FAILED) { + error_setg_errno(errp, errno, "IOMMUFD vIOMMU mmap failed"); + return false; + } + + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *hiodi, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index c5c1d95aad..b63420b73e 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -25,6 +25,7 @@ iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id= , uint32_t type, uint32 iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" +iommufd_backend_viommu_mmap(int iommufd, uint32_t viommu_id, uint64_t size= , uint64_t offset) " iommufd=3D%d viommu_id=3D%u size=3D0x%"PRIx64" offset= =3D0x%"PRIx64 =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" --=20 2.43.0 From nobody Sat May 30 18:34:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177918727786673.8423034581208; Tue, 19 May 2026 03:41:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHqu-0007pb-09; Tue, 19 May 2026 06:39:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqs-0007oH-3m; Tue, 19 May 2026 06:39:06 -0400 Received: from mail-westcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c112::7] helo=CY3PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqq-0006Qe-Ip; Tue, 19 May 2026 06:39:05 -0400 Received: from BL1PR13CA0239.namprd13.prod.outlook.com (2603:10b6:208:2bf::34) by DS0PR12MB7874.namprd12.prod.outlook.com (2603:10b6:8:141::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.21; Tue, 19 May 2026 10:38:53 +0000 Received: from BL02EPF0001A107.namprd05.prod.outlook.com (2603:10b6:208:2bf:cafe::c) by BL1PR13CA0239.outlook.office365.com (2603:10b6:208:2bf::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:38:52 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A107.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:38:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:35 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:31 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=V9MULfVM/fdiQgTMbyIOUXUcVzH1ZqLh9RgQ5FBGTTkN4o9luvCXR1eE9ZPhtinSbz8HxvciyKHayLpys/6Prd0H5RtFjft1S6hlug6rqbT9ARaCf2gyCUJTq4v/CjVChYAq4PggFakPi24MyMQ69SF2stkeZ5Tc+owrKIKsGlA10NICmC4r/BF/ndS1fHRH+yV+EX+V9GUiBgCoG5QJghgQN+Qgh9vT0JNpfAMZAfyfGOUL3C21F5Kg6caWNaGm6kiVuQSif5mVgpXQl7hl7DQRmaq9TlvSfRKQzue1WmRKZ/Re9LTshibIYnKMa8FitWO+9L9LuVbsDd9b8W49jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QzN3gQSCr3I3Ifm8NwiaRMXUJ5s5wawTFcIcy3w7rpc=; b=JeFgsF3HqMNfZVpN+p6vMH9m88c2/0jCJ8lFvhCuO3bXTpM9ZeHx22ca2E2jnE2MMEmYVnA8gshpg2aHkBO0mQ5Uo6nMTNBJP494mooIce+lntl0z4gWqmjOrn16GYW3wr+GR3vp+J2Ekfo4pnbURA0tJIjC1PDFlMoykjJnA9LlNmsCYAYmRdXHWf7F6MTqv8cXlfg6BgQzHtVaQjkrccD0HqSaikaqRrz7h/EvEa4gGJF3EYuXTrB9jSi8ZbksnI9hYo0AW85U6xlaNZT6Vv+8gYW3gthBK0blEcv2FA5aQaCsVEFeP/vWT5xJWi1tBK8HEntzpi5f4u21k+zzCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QzN3gQSCr3I3Ifm8NwiaRMXUJ5s5wawTFcIcy3w7rpc=; b=Z6sQ6GR0UbK5xJyGodfGihEfLzqSRXZEW3+hGVrcKDpO0vcTcKZzcRLmHEjrDD9Z/GkP3HYHcZMXEJljyNQOngKCjez9HZqrvkN721TZlGujRm1A7q0WhHe+b5hsrAcVXE857tmtKdLjDPWfUkJyAaRRlNPkAu5L2J7tPetVcuYEF2TKMRk1wfTnJS80UVPueHZl+sX47k3+c8o1u5xqRoxiG3uH2SuKOzKDwDioYL7YSUDqZ5Y5usLx/jOnqObjpFCUpi4BFuq93ZTgwu+yb4CtnEggLUP4cMqJHiOZH5dM+N1e4iWS3ty/SjhTAQeVCCEyqIjw5Qyu5WkkbT4qmQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 05/32] system/iommufd: Remove unused viommu pointer from IOMMUFDVeventq Date: Tue, 19 May 2026 11:36:43 +0100 Message-ID: <20260519103727.899332-6-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|DS0PR12MB7874:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ab83e40-9490-4de1-694f-08deb592d243 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|1800799024|82310400026|22082099003|56012099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: 3+AhyveI+1J3mPRgxxskPJXXa6ALEIg7iSDcFpnUZY1cfjUs2YtLeDbsh+xB44OJyoWed/vk4uMqLjgt/SYVWPYZE91D4dCAtV8YGlBosSM9hyCTOlFAM22CW4/USESFCwNBqtUQifI/h6atm828Jcj0eNqZ6VcixIP+mszWyUEdE7y21woMk7PxORAAo1utm2uCrDLcP6VeebJYUYr5RzNUfbPDCbdV1erCj/OL6gE2slY1z+DrVlI/vffSOHcj0rSP/Xoj7hZ7Gp203P4g6YI5FISBv4GVFEYYeBufnaM0R9lcH2anBy2VI6SvE85V8uE1fHIVFyahPziQDi0pi/c6p2gm9MiZOnq1B+dsRWGWzaKsAXJ8wfImep3AS3sxZcNH2jf04oPNU4trUnA50o20ti0HIZCvjEd1C/pfwr1bwQakDdn4y509xd8umEJiWuqVvOVP98j7jlffAP5ooVTh2e7bsMWJulkmNTZx86HdojMt9i9u6i0Cmgb4RvFD1O1sX2YoF8DMYZjjzGX+5cLoSJnTuO5aCA5SD+n0SN2XsJbp7DyCpw7lxEICRfJlB9mUd7bjqZbCL1t5Cezl/8JLFvMO5cT2QPy3R5iu7Wmt9wq5eX9XYo7QU30bbMgAvElL0L6T8EvAqXFk/X9pXm/6lhTiCnBRH55//RI/tJ3QLAQ9AgV3WBJhpGzbE1qW5++A+PY7wypxwIlqYFkBds5yf+VmV7yoBmnk99Gr4Sg= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(22082099003)(56012099003)(18002099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DnAPVijAhvb/PVyGWkKf+cS0Xpw9gDPYo9Qdcmry84+5aIAW2eUIbSm8b5yuteY3RfPC+O4Y8V6t2Z8LWjnnwALDvPQO34sH4QoTdsesuqAXGFI75J0hTKlinee31A3WyetDh2dHlgvR2Hcc2HbwnWu6zB82yeCmfelEpSUVCgobASF4Ch7mmUWvZTBmgaNkJ7i8oQ9DHLckxeP6WkDvM2/0Mixdyz9afsAkxybto4nByjpoO6b8wHm1DvhbZoRS6mlXXY7jKuu3FLD0HvjYxjKN1QuNk6jfwquZDbogAwLUZPYN347YxH3EAaLa1GkadGRJztv6GFph6TFrFNe6zhKKCp7ExA8l4Xtk/hA69zy823f6PkASnIpRwLBDJkJ3aa/e4ygmIzjp/gz0gcWR4F8U4nrLvgTS7klLN+Bp/aEokSy7R2kHxJ5k2GICB+i1 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:38:52.8693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ab83e40-9490-4de1-694f-08deb592d243 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7874 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=skolothumtho@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187278138158500 Content-Type: text/plain; charset="utf-8" The viommu field is assigned but never used. Callers freeing the veventq already have access to the IOMMUFDViommu object through other references, so this field is redundant. Removing it also simplifies upcoming changes where veventq is allocated based on the viommu id before the IOMMUFDViommu object is created (e.g. vendor CMDQV-based veventq allocation). No functional change. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 1 - hw/arm/smmuv3-accel.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index bb8d5081d7..da68ba0037 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -58,7 +58,6 @@ typedef struct IOMMUFDVdev { =20 /* Virtual event queue interface for a vIOMMU */ typedef struct IOMMUFDVeventq { - IOMMUFDViommu *viommu; uint32_t veventq_id; uint32_t veventq_fd; uint32_t last_event_seq; /* Sequence number of last processed event */ diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index bfa6a03f9e..30c498ffcf 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -553,7 +553,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error *= *errp) veventq =3D g_new0(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; - veventq->viommu =3D accel->viommu; accel->veventq =3D veventq; =20 /* Set up event handler for veventq fd */ --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187175025396.75827179003943; Tue, 19 May 2026 03:39:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHqt-0007pN-FR; Tue, 19 May 2026 06:39:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqs-0007oG-3c; Tue, 19 May 2026 06:39:06 -0400 Received: from mail-centralusazlp170110009.outbound.protection.outlook.com ([2a01:111:f403:c111::9] helo=DM5PR21CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqq-0006Qg-Iz; Tue, 19 May 2026 06:39:05 -0400 Received: from BL1PR13CA0219.namprd13.prod.outlook.com (2603:10b6:208:2bf::14) by SJ0PR12MB5664.namprd12.prod.outlook.com (2603:10b6:a03:42b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.24; Tue, 19 May 2026 10:38:57 +0000 Received: from BL02EPF0001A107.namprd05.prod.outlook.com (2603:10b6:208:2bf:cafe::a0) by BL1PR13CA0219.outlook.office365.com (2603:10b6:208:2bf::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:38:57 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A107.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:38:57 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:38 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:35 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YipEh0AavSJTlqtsmuCHABQRGc4kRBNYIAVEqAlfHMMXA3bwjVZjJBfg+KjFWIkgiB/UDvg0+bxQ6ef1OH9QNNFZFtfWfUhHg2veYphe6zwozSzNonvh6SJ51ys/vuEi50FaJSNFzaTE4m+UY2rUzerjhxx8KdkGcsj9VoiriuFUtYblZRUbexTBnb8XNQymmHPx3U3ZMNyMkZsrrPseun/YKFq2/18qkG2TsveUPu3904RWKtN20ipXQLuxWfVcvsmCOeTKWD49k1m4+mk912kW1MUeZq9wM8NZeJEFKfxZCggfym7ET2y6DL/QT8UYBx4c0pTNEDxbZxD8JuQC7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VXwoDOs5zkQzXbcqUq9sdFg0aBSrecsoVza9NedzfL4=; b=bPKOCQ55H5Nn/Zrmq+lMg6PG9PQ66cPYyMo2z0CdjhSnzEJr8lXShy9tWMx0vDB64XScz51wAr11jKwYYEOOeNkPwnOZkF9zfqVsITlsdfCe+HgrCwFM0jtRmX1zbvi8TXQjMy42/r3VC0ulSMaorcGsqry39Or4CPwdu6MNsOqN0PHx7stNaAbkHWix4ZrjNXuSiDpciFN1AXeOw8icWGIFGfgbUJ9F5aGCw52FTqTNi2YbBka5DA2Z+v60th80Dj/awfe7tKjp17WCJHT1XVqAtM+0Ms9qdG+BSx63voBTbjwfPthLJhyzeoAPF0Ge+8sWQNz8sRzbLDYkZp0iBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VXwoDOs5zkQzXbcqUq9sdFg0aBSrecsoVza9NedzfL4=; b=Ygv7+Ci3d2UAufNlvJUDFCmKxpbY2EL1+9deFDm9vhwBookz5Hr40Ggnisso1JGRxKUpqoDYhdJXO7XyAc3R0V8OPgwGpbKw+7Eqo4U3bKrtDJPpBhYpX9nBGJ6dIArQqP0rpF7DrS40PhfmoMZJR+NQW7NyAIDHJllGmPflZqUdWODav6YMcF+tautv6pgVdQUovCMGJ61f5m4b9+9+uxErmtHKHMuTXfVOMr6IBVEDfYdg+XFvfTGTu2CbbwUanp/hzOB1+HLTC03sGNkC2hedxEMWixCDul3F1RaMl+LNzYrgPqBenRX7/TkSKvGjDx8rxxPoKy4bUsTiU+2TOw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 06/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface Date: Tue, 19 May 2026 11:36:44 +0100 Message-ID: <20260519103727.899332-7-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|SJ0PR12MB5664:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c0dd2c9-f309-4826-f973-08deb592d4e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700016|376014|11063799006|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: 0hr4LiLV1Bo9vehINSWPUY/xhXasIgBXpTLe4ySVp7na2aqQ5oEHA8k+JmvG4Fo3lRHF8x6It67drmk9xz/62VWDq7AJ/9mH5JmUwnfYEWea8V0sABfPV3cs4Niv8niJHyJXOtqgkn/0s3EFkgVrf6ZtUxCbp7Rc6M8zDmtfnVjbLHh4AZKmfAmeEzSmJ5KOLQiT1MMmOUOkmOMoUKMBaziWUoZofJZS9TWPY6QYwmY1RADYKIzuoZhQFWmEuDRg8+fnB+H6k9aaxwiwmsXMZ3ev3nitTdA78alptwjnvkFkeBXFJmaoNY34R+YlOuAUp2lJ6KElW4wP+VzH6P/rILQCC8ZyiKceReFrXLNVf9HEJYBAmLTUC+2r/xZDaN5H8WnV37X5l8TeYBkssmKKkhNQrRNDPvR5vsLvgw0vlAl5qh+LUbnsXHOpEbIr8wOumLkYTVyHi6wsCQU+k9WnfKeJ9F/mgMlA5khxntMk+TWSnYXpjPW72TRoOpRlYwSpA3vtuXXq2yqO+a1p1m4lll/G4IIz3/p9gpV6hP/NvYxwKuNtOzCYINKi4QULws/3j3HtN+Kfsvs3mJBzWAzGy+oMj88a3GFpoEB2R50W2zLomrJb5vamqgFCYhIvMA8MsI5W0uxv/4CwMaBAePli2u1jOv33LcdcdsOSEbzB7Eaq0QLCcxyDjCZcZ4l79GYYFXPjqCmLGZIvjNzuVIbFwtL99Ra0YHv+lZWFdmlUDdw= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(11063799006)(22082099003)(18002099003)(56012099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: W1dHcnxvJC5Q0oTpYISVmMNFTS7GtDi4r+9/JteRbcVMwt9vHqHChr0sR356STnhIf1l42SaRtLnS7hVlcE11/KAMexpluV5D5//MnmhAeiEHTOBA66uLWoGoumfhiIBJHJjNLmwGBHS93lUOl8sVszEMv29qov/8B7CDg1Tx8Py80/VQBrH/JlQyZ8LYtjGacK97/blgjDv6lyW94iDKIpv1EXwftGvptQsrI7aETSxv+SOKYQOIlUItIrI+esOEoU8Hv1aXJNtJsK8620sxKiPgNdc87zsTDvdNCfJRRqGzF0vfPvP0PpBt/NDkEstIHF+0O3bCXOfxPa/+rkCPRS/Vw3sajsocR2Hu3wPvYqOHR25REk4JcECnnf4cYzYAyTLFsQPOa7PuGBdcZVmHkupVeD//oaRttZIhOvijyJWdHsZDLT1fPIY38/FIgB2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:38:57.3108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c0dd2c9-f309-4826-f973-08deb592d4e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5664 Received-SPF: permerror client-ip=2a01:111:f403:c111::9; envelope-from=skolothumtho@nvidia.com; helo=DM5PR21CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187175948154100 Content-Type: text/plain; charset="utf-8" Command Queue Virtualization (CMDQV) is a hardware extension available on certain platforms that allows the SMMUv3 command queue to be virtualized and passed through to a VM, improving performance. For example, NVIDIA Tegra241 implements CMDQV to support virtualization of multiple command queues (VCMDQs). The term CMDQV is used here generically to refer to any platform that provides hardware support to virtualize the SMMUv3 command queue. CMDQV support is a specialization of the IOMMUFD-backed accelerated SMMUv3 path. Introduce an ops interface to factor out CMDQV-specific probe, initialization, and vIOMMU allocation logic from the base implementation. The ops pointer and associated state are stored in the accelerated SMMUv3 state. This provides an extensible design to support future vendor-specific CMDQV implementations. No functional change. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 87fecb5c68..f82a7112d8 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -10,11 +10,45 @@ #define HW_ARM_SMMUV3_ACCEL_H =20 #include "hw/arm/smmu-common.h" +#include "hw/arm/smmuv3.h" #include "system/iommufd.h" #ifdef CONFIG_LINUX #include #endif =20 +/* + * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to + * support multiple VCMDQs with virtualization capabilities. + * CMDQV specific behavior is factored behind this ops interface. + */ +typedef struct SMMUv3AccelCmdqvOps { + /** + * @probe: Optional callback. Vendor-specific device probing. + */ + bool (*probe)(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **er= rp); + /** + * @init: Optional callback. Initialize CMDQV hardware. + */ + bool (*init)(SMMUv3State *s, Error **errp); + /** + * @alloc_viommu: Mandatory when probe is implemented. + * Allocate CMDQV viommu resources. + */ + bool (*alloc_viommu)(SMMUv3State *s, + HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, + Error **errp); + /** + * @free_viommu: Optional callback. Free CMDQV viommu resources. + * If NULL, the viommu_id is freed directly via iommufd_backend_free_i= d(). + */ + void (*free_viommu)(SMMUv3State *s); + /** + * @reset: Optional callback. Reset CMDQV state. + */ + void (*reset)(SMMUv3State *s); +} SMMUv3AccelCmdqvOps; + /* * Represents an accelerated SMMU instance backed by an iommufd vIOMMU obj= ect. * Holds bypass and abort proxy HWPT IDs used for device attachment. @@ -27,6 +61,7 @@ typedef struct SMMUv3AccelState { QLIST_HEAD(, SMMUv3AccelDevice) device_list; bool auto_mode; bool auto_finalised; + const SMMUv3AccelCmdqvOps *cmdqv_ops; } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187179656156.02649919445741; Tue, 19 May 2026 03:39:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHr0-0007xN-I1; Tue, 19 May 2026 06:39:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqy-0007wF-SY; Tue, 19 May 2026 06:39:12 -0400 Received: from mail-southcentralusazlp170130001.outbound.protection.outlook.com ([2a01:111:f403:c10c::1] helo=SA9PR02CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqx-0006RK-2C; Tue, 19 May 2026 06:39:12 -0400 Received: from PH8PR07CA0042.namprd07.prod.outlook.com (2603:10b6:510:2cf::8) by MW4PR12MB6803.namprd12.prod.outlook.com (2603:10b6:303:20e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Tue, 19 May 2026 10:39:01 +0000 Received: from CY4PEPF0000EE36.namprd05.prod.outlook.com (2603:10b6:510:2cf:cafe::ec) by PH8PR07CA0042.outlook.office365.com (2603:10b6:510:2cf::8) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:01 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:00 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:42 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:39 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=U70e9wYFI7iwmOuPlkPdoHkUoKRQCvrfXmWJhVOMiWB1IY6T0N6RrIUwaKpXBZ5B24LeJ71GW0/zOSpgtt3ytr50LjqXYPJndOzel+DumRgqOAT/mVEwKB9ZgJsveiyvpavAFOVU9mJVHjn1Ffatvbm/LwzIYLmVMLSYxeD+DA5fhjP2SczBD6sl71bUqQdVT1fD4SOqib1R+sx+9WQBXldfs/KWl2bJBDjGJozOJuWn6qRzpOauWszcEco/L/mGpwdFoiI0NQGG+etho1Rrh389CDhEUwB1pk0nOiLa176bboEQmAMCjqqFF/SCMOiCZjhtq3iBiPESZWvhn97fLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3ds2Y+CR8XiYsWCWdLOZnt5ZQSYGCDFvc+NhmyzE1oI=; b=hqAi3oKvAYbzbrhzW4Xn5siNgqYXVTXj7EE6citIIWJhQClonvrI6h+otVVm3jbHzWCYsrqamckHy7hqywZ1C2k1SpPtyw/cFnCv+3jzsadn3Jax+jeLqWIyHyIafeDADV01bsWUcXzVMTMbe3ruepvW5wy2iu/LO3axG9fMGzs7camiMr5OvcJtPWCkHclyiY2eEKBpCC1GfL8F9Td8JdGvxvfal/pjESbrz83MEF0Z+WcBvud8C8I/smkMCSkchXkL6ycj/U2ZzjVNLFzlvdYSVlFiOwy2NYyF7m10KxH819hyRXi9yhpBcFK2tFQCLHigiQbJXo9msBsP6/O64A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3ds2Y+CR8XiYsWCWdLOZnt5ZQSYGCDFvc+NhmyzE1oI=; b=Sxt4ZZjAnfC2P92MgD/hsexJCwM/mQ+cQILrb0G6TXgD7u/OxwfFT+/UBypjMilx3RjK3oTRANd+LVo9e1AoKhj8PiHoCcjD/TgT+L3le3Rre/5My1knJSURrJC8y5PP4EHU6KsXm7uJ9EFTKCHgxmPqE0nGIcNx/x44gws46l9xKAGK19RWdvt782o1Osu6VIeNkTL55IOfet4S0cjGvTXoKShbhq9ehckQdACLP7uPcw/6PkeuPHGV9+2Wi8x9gFLxhjK0BM89rXBIWk7KEnPrpoduxJT+Oq7wH75Rb2TAtYikPprSi5dhOqS/vEV/ziyVOiEvSusK3K2TS/zMGg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 07/32] hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub Date: Tue, 19 May 2026 11:36:45 +0100 Message-ID: <20260519103727.899332-8-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|MW4PR12MB6803:EE_ X-MS-Office365-Filtering-Correlation-Id: b078d099-f8ef-4afd-45a8-08deb592d705 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|82310400026|376014|11063799006|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: jcbhExdD4ZH16zZfsleuKPBKewjg7Lf2sS9Njzy6o6gZygYKsMreBB30HGwP1PpJRZsRbYVzGy4e0Z7WlXxRKhRpugaec6j3RW+66FbdEdisToBYTkjstB7cBBpmNh8oVlJfTaJhI7lKbvz8nA4KJuVjXBah+mG8MSP46WzHJL9DgUxYoO7uswmQqia6GCRbsznbnCvrgy2TAjsDJ6qrfCsw2k5i0xz7df1fZximiauCXAlnRXBQynoP4/vZxrRaCMY+PRaIHUxQOoKpbKpLc78lDZUdMj33AF81uUz6DQLQ9fB/FLtfxqbYZAioFAbtcR+nD70o3WUQ/rwA3slj9HwT1y0kdiTGihcN7Ig1T9mZwwS8ke0obi5WfhcAvIcgHef5c43pCO7b5LTiUQNcFsUP34lQICIYadoX9UKCs64Z8HJ7QxBqVDPAtyZVZdU5tP5ippzNmy2TKSWMUILZVtgzZhMCxGG4FUevAxdURstlh+9vQyzOjgyJmFiZOhg76gzAMXnjzSH0vGdH2WsbWBMdKaiaqOwpzpF1JrO+r+F96q+yEBXP7wMyKZvK8RNvdgmWFf7VajweeNGSapaPlIGC39OC5oNAPb2AkLRw2pb4JsdZXqA5Smo9hA5rKTb0ucgbFSVsIO3pe/XsQZ6CWlNr6Zm4aAIu4pguuTa4tUezUtair6NMHU5y/aVA9rhG5qzrzn7Te8gzT8hR2TsaiPhBNzrTUG8cOktkmPyqoRQ= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(11063799006)(22082099003)(56012099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FlbPUw/fBx/lSDLPqlr+M99kjTor+hYb3f63ClC7DoFSHfGEOAhoCtmVIbkcDq5g/zKkNF4MljQRSXkkmzQlFJk+cKQgO6INNwxpdhXIX5P6+9+AoUI2C+q41cHrmR5g2nenyNXpg2OJvYOnrJx8GDamFy5+9NLhXAfsaFHBgWX5o2nXweuc8MT7/POHtLqBl4Wz9gWm13Pxll4QtvxTaxJ8lEFHKewYpdVuWfjbCEWbXoLgPXuWqQv2oR2yH+CfpL40tHdDE0bjScpvtKJQoMyO70yw+hipE6NywPkObZJRYi7jsVsMtA+j+0x2z+Flb55qEP7ftiR2P8yA9YPfwB4g7u+p0wCWb/1TTI5JF6xyVC81A7hqxg8j1Nr3V8a69rw5VksPYzCT96QlnuDVMCV1tYgONgbZtsPtYC/S81XZA+whHzC9eFjKU2MJW/Fg X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:00.9088 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b078d099-f8ef-4afd-45a8-08deb592d705 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6803 Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=skolothumtho@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187181547158500 Content-Type: text/plain; charset="utf-8" Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated CMDQV ops interface. This patch wires up the Tegra241 CMDQV backend and provides a stub implementation for CMDQV probe, initialization, vIOMMU allocation and reset handling. Functional CMDQV support is added in follow-up patches. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 15 ++++++++++ hw/arm/tegra241-cmdqv-stubs.c | 16 ++++++++++ hw/arm/tegra241-cmdqv.c | 56 +++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 2 ++ 5 files changed, 94 insertions(+) create mode 100644 hw/arm/tegra241-cmdqv.h create mode 100644 hw/arm/tegra241-cmdqv-stubs.c create mode 100644 hw/arm/tegra241-cmdqv.c diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h new file mode 100644 index 0000000000..74a6954017 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_TEGRA241_CMDQV_H +#define HW_ARM_TEGRA241_CMDQV_H + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); + +#endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv-stubs.c b/hw/arm/tegra241-cmdqv-stubs.c new file mode 100644 index 0000000000..4669f5c5f5 --- /dev/null +++ b/hw/arm/tegra241-cmdqv-stubs.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * + * Stubs for Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "smmuv3-accel.h" +#include "hw/arm/tegra241-cmdqv.h" + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return NULL; +} diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c new file mode 100644 index 0000000000..ad5a0d4611 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + +static void tegra241_cmdqv_free_viommu(SMMUv3State *s) +{ +} + +static bool +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_reset(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, + Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { + .probe =3D tegra241_cmdqv_probe, + .init =3D tegra241_cmdqv_init, + .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, + .free_viommu =3D tegra241_cmdqv_free_viommu, + .reset =3D tegra241_cmdqv_reset, +}; + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return &tegra241_cmdqv_ops; +} diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 5b198402d5..f73ad9727a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -642,6 +642,10 @@ config FSL_IMX8MM_EVK depends on TCG select FSL_IMX8MM =20 +config TEGRA241_CMDQV + bool + depends on ARM_SMMUV3_ACCEL + config ARM_SMMUV3_ACCEL bool depends on ARM_SMMUV3 @@ -649,6 +653,7 @@ config ARM_SMMUV3_ACCEL config ARM_SMMUV3 bool select ARM_SMMUV3_ACCEL if IOMMUFD + imply TEGRA241_CMDQV =20 config FSL_IMX6UL bool diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 80068f70bb..eb16ffcc34 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -84,6 +84,8 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MM_EVK', if_true:= files('imx8mm-evk.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-= accel.c')) stub_ss.add(files('smmuv3-accel-stubs.c')) +arm_common_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-= cmdqv.c')) +stub_ss.add(files('tegra241-cmdqv-stubs.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1779187285; cv=pass; d=zohomail.com; s=zohoarc; b=CS+hjPjsyjic6vjAReYb5ljSF01vwhvR73BFnMFcOYmdzApd3S0CjmUlkEv9cGX46wTU6sOfccFGfTraXEBBwH4lYJRtuAPOCbj0pn1tgMtaNdkvI9OAVtntZOSqsLBu9Gxb7+iexSbNpdM0sKuGqAhBMvHIq4zFzHh+k5XkliE= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779187285; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rU8LZ9SZsyYKNXO7x8R25TWPj49t75jyOAFAIAd+FrQ=; b=Te+qxxkbaqdN36xAc2NVteY01nT3JokeWmwpsZuuv/Yy69l+c3UyS4hVfStzpzR/oa+Av9bh8j6V5I1HDNbezds/CoD/VN1MELje3P9UMvghsiNbMkyav5UMv9hYk7r7RivCZLSpkA+4I/HMTylGMgzBSOYsauzYjPzC4d16DVI= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177918728507556.02487607413923; Tue, 19 May 2026 03:41:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHr3-00080n-6m; Tue, 19 May 2026 06:39:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHr1-0007xi-5X; Tue, 19 May 2026 06:39:15 -0400 Received: from mail-centralusazlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c111::5] helo=DM1PR04CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHqz-0006RX-At; Tue, 19 May 2026 06:39:14 -0400 Received: from PH8P221CA0059.NAMP221.PROD.OUTLOOK.COM (2603:10b6:510:349::10) by EAYPR12MB999179.namprd12.prod.outlook.com (2603:10b6:303:2bf::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9913.11; Tue, 19 May 2026 10:39:05 +0000 Received: from CY4PEPF0000EE34.namprd05.prod.outlook.com (2603:10b6:510:349:cafe::c) by PH8P221CA0059.outlook.office365.com (2603:10b6:510:349::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:05 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE34.mail.protection.outlook.com (10.167.242.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:46 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:43 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nKnEfBPXPVN6z3e+on0NUyP3r6fM6mIpyfAqsQ2+Hel+Pw+jEAByhV47GEr3X8KKLemhxdxb25kpnvKxpqkHu5gTkUwDNZKo4EuMCcKCquJU5hh8dJO9hzlQKD8OH4pxYowck1YOZ3v+M0ZTJCjNjNR8vkCi4h7GiB0c1G4MKuPiBzwz1q7bM2PleNJTmEjAbhR0/tCP10zgDCMevdtrf5OKLEzvlcjjhfdzuTBAbpqGwfAW5h/j7CTzMDEMbNJVmTFmL9vQQ4+4z7BePju/57bIvdhqKwJDoAK7vCQ+nbLY0WmnJwyqEQilaGAKUFdsN3P9AjmFa+OQqVTa5xoGsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rU8LZ9SZsyYKNXO7x8R25TWPj49t75jyOAFAIAd+FrQ=; b=TXxm6M/aia5VgsTnCVAtHqbSXkLY9aU5x8NG8cs9y74K/JWLjOuGCGZEiPB2AcOIAyiYKG5Mb7IaYtb8gxFcaQYsQ12l9NRlNejqAcNAHM+7SRUob4S6vZbAUwk1MO+t09yYqhueiNHmKETa9sCPfFgOQeaeYjsTwolJ9rMY9SF3FUzxnsfoR/n8e9/J3YEmpt4Mor+5qjw2k8woteRM36ACX0xsoQ+p0i9k9uU+xwe2apfQSSGMc6xtYtn4lMKsao9VeF7JKdoTs2/BQm5QCPIrsVLZNq6PqhCy8YB413bdBizn9pMpEd3MEm8lcZMFucPcw9WM+gCgzqISD+8CVw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rU8LZ9SZsyYKNXO7x8R25TWPj49t75jyOAFAIAd+FrQ=; b=L4Ay6jkddxjwv05SXMchktXjz7WTPHjHlEZ7/hd1KXgfPdqKf3wakQLHpZnV4PhOcivwA9OaqQ8A11v2ZBRqqfLunVpzIh6Q5SRuIyUw/2Z6cSpJfoO1HYfkikctpaivZNcSeq1oknQSUg6fxaxBHMZja69n58LFXIyAv7l+Os4OCs0csmt9Kpa821OefPMphFWWF7/FywO4rH7kOvjrHonT5Q61zMbVEy4roM4cow/KbHPeu6/kxTLAiw0Q9lsOo5o40ghrwTvD4gBPm1he9uW5N4FIlsA7PtReCs+9h4WYUKyJihksoaLZATqUwWxU9XBOKlObFJ515E/wL7HXug== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 08/32] hw/arm/smmuv3-accel: Wire CMDQV ops into accel lifecycle Date: Tue, 19 May 2026 11:36:46 +0100 Message-ID: <20260519103727.899332-9-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE34:EE_|EAYPR12MB999179:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e802deb-4ca2-40cf-bee1-08deb592d96a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|1800799024|82310400026|22082099003|56012099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: Q3mGneSpjGU0B4hHMY+9PVkPa6j5fkMzSUw2e9LPu3HR8TsKFKuDbq83tmb5LTZw1pL7L4rJdNKL8lW+jNP2jebFdPHTD8re7XgjJt9RGquRAxHwkULGzyo2SmZ+/W8S80ch6hMGdZua45dWg1R3d5uSI8zxQUe/ZpGg40Er7chb/ZiRUlAnAmKxvBnqqksaxEFuvE/MYOzIqs0vGoyVqY5x+O+95vNvzfEB4vFKVm9Ey+w7LJ1mFyDBp7+shDFkMsd9njudUsQj+qDMQi9E005yr8DB9gwflv977g5pv7HpcwQ8CG5YrAx/o4Qg7XqCAPjKzjodYcGbCYb1b0PPuqrmePGJNU6DyeJOTM86OexuulDn1obToU2EdRXDSHw45Dhd3jo6sOZTmsVw4ifj7KNtFk/5qSf9V75wsQ4lcBsN+M7UyPUP2G0HJraaReqo+bomskc3FtdYNQKwORLlOySqLPQy/V7ITb2stE11uobTjRfTj307/7wLfe0/r5GitxbWubCcWNW/5fEfzb1wTfL5znqgESW1zqDCHTgInTjvp05y8oDwqujKjH/r3Y2qO28YbiQWvlyLfpKp5Tr1f793rcWqfZdlu0TfsmkuP1OHpEdVN1AovsEMfJ7QnjYvJE8d/OM3HLwf1w6WzgmzDQky6wfenNQbE0bfqry2H8pGDXHWhroVFjJZPDjcdGojjM+BF+jMtZ34LVr5t874hZEpGKNNmLPHasLSPWQIcjw= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(22082099003)(56012099003)(18002099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Gn4h9PnHi2AIxMot756TK+FOHwYJInjJOJAOLmdud/KM8bfcgvvAm5d7xtm/6YqLOOndoabTLclK/bKCH6xTnaR4GS3iV+Idjo1JAzXY5aIPxp8StyPRalJfTxjg7h6ftoCuGDoygBu3LbiRTIII+xgbS0Uxhh+IQDxQU2NmxAW3YYAkrDIpeMInBHHNSpegoXsBDPTB2z53PGxfwnM9NRC3S3xP0lKlRL5Lt9Nbd+0AvfHsXto4ZMuhYxTMXE7jdTXJsncB8mmh7KWW6E/6ok0raRCCtdBEecE/kgdZ7BHsmx5vzlSfHNlmhXURyuLZISm2RwjZifFMJazf839g//IjLquNmQMccR2ARz/oUSPCPJ30t71FIB/RSUPOxODA9gZfXE+FFLIFBH4UAxx1Ku36n4V0zqvvyu3bCh4aq6+1CvbBtU+sWTYwDeTGv8r4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:04.9379 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e802deb-4ca2-40cf-bee1-08deb592d96a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE34.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: EAYPR12MB999179 Received-SPF: permerror client-ip=2a01:111:f403:c111::5; envelope-from=skolothumtho@nvidia.com; helo=DM1PR04CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187285836154100 Content-Type: text/plain; charset="utf-8" Add support for selecting and initializing a CMDQV backend based on the cmdqv OnOffAuto property. If set to OFF, CMDQV is not used and the default IOMMUFD-backed allocation path is taken. If set to AUTO, QEMU attempts to probe a CMDQV backend during device setup. If probing succeeds, the selected ops are stored in the accelerated SMMUv3 state and used. If probing fails, QEMU silently falls back to the default path. If set to ON, QEMU requires CMDQV support. Probing is performed during setup and failure results in an error. When a CMDQV backend is active, its callbacks are used for vIOMMU allocation, free, and reset handling. Otherwise, the base implementation is used. The current implementation wires up the Tegra241 CMDQV backend through the generic ops interface. Functional CMDQV behaviour is added in subsequent patches. No functional change. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- include/hw/arm/smmuv3.h | 2 + hw/arm/smmuv3-accel.c | 96 ++++++++++++++++++++++++++++++++++++++--- 2 files changed, 91 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index fe0493c1aa..aa6a79237a 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -74,6 +74,8 @@ struct SMMUv3State { OnOffAuto ats; OasMode oas; SsidSizeMode ssidsize; + /* SMMU CMDQV extension */ + OnOffAuto cmdqv; =20 Notifier machine_done; }; diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 30c498ffcf..202b1aedd9 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -19,6 +19,7 @@ #include "smmuv3-internal.h" #include "smmuv3-accel.h" #include "system/system.h" +#include "tegra241-cmdqv.h" =20 /* * The root region aliases the global system memory, and shared_as_sysmem @@ -570,6 +571,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *hiodi, Error **errp) { SMMUv3AccelState *accel =3D s->s_accel; + const SMMUv3AccelCmdqvOps *cmdqv_ops =3D accel->cmdqv_ops; struct iommu_hwpt_arm_smmuv3 bypass_data =3D { .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, }; @@ -580,10 +582,17 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *hiodi, uint32_t viommu_id, hwpt_id; IOMMUFDViommu *viommu; =20 - if (!iommufd_backend_alloc_viommu(hiodi->iommufd, hiodi->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, - NULL, 0, &viommu_id, errp)) { - return false; + if (cmdqv_ops) { + if (!cmdqv_ops->alloc_viommu(s, hiodi, &viommu_id, errp)) { + return false; + } + } else { + if (!iommufd_backend_alloc_viommu(hiodi->iommufd, hiodi->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, NULL, 0, &viommu_id, + errp)) { + return false; + } } =20 viommu =3D g_new0(IOMMUFDViommu, 1); @@ -629,12 +638,72 @@ free_bypass_hwpt: free_abort_hwpt: iommufd_backend_free_id(hiodi->iommufd, accel->abort_hwpt_id); free_viommu: - iommufd_backend_free_id(hiodi->iommufd, viommu->viommu_id); + if (cmdqv_ops && cmdqv_ops->free_viommu) { + cmdqv_ops->free_viommu(s); + } else { + iommufd_backend_free_id(hiodi->iommufd, viommu->viommu_id); + } g_free(viommu); accel->viommu =3D NULL; return false; } =20 +static const SMMUv3AccelCmdqvOps * +smmuv3_accel_probe_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D tegra241_cmdqv_get_ops(); + + if (!ops || !ops->probe) { + error_setg(errp, "No CMDQV ops found"); + return NULL; + } + + if (!ops->probe(s, idev, errp)) { + return NULL; + } + return ops; +} + +static bool +smmuv3_accel_select_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D NULL; + + if (s->s_accel->cmdqv_ops) { + return true; + } + + switch (s->cmdqv) { + case ON_OFF_AUTO_OFF: + s->s_accel->cmdqv_ops =3D NULL; + return true; + case ON_OFF_AUTO_AUTO: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, NULL); + break; + case ON_OFF_AUTO_ON: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, errp); + if (!ops) { + error_append_hint(errp, "CMDQV requested but not supported"); + return false; + } + break; + default: + g_assert_not_reached(); + } + + if (ops) { + g_assert(ops->alloc_viommu); + } + + if (ops && ops->init && !ops->init(s, errp)) { + return false; + } + s->s_accel->cmdqv_ops =3D ops; + return true; +} + static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, HostIOMMUDevice *hiod, Error **e= rrp) { @@ -669,6 +738,10 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, goto done; } =20 + if (!smmuv3_accel_select_cmdqv(s, hiodi, errp)) { + return false; + } + if (!smmuv3_accel_alloc_viommu(s, hiodi, errp)) { error_append_hint(errp, "Unable to alloc vIOMMU: hiodi devid 0x%x:= ", hiodi->devid); @@ -946,8 +1019,17 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Er= ror **errp) =20 void smmuv3_accel_reset(SMMUv3State *s) { - /* Attach a HWPT based on GBPA reset value */ - smmuv3_accel_attach_gbpa_hwpt(s, NULL); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel) { + return; + } + /* Attach a HWPT based on GBPA reset value */ + smmuv3_accel_attach_gbpa_hwpt(s, NULL); + + if (accel->cmdqv_ops && accel->cmdqv_ops->reset) { + accel->cmdqv_ops->reset(s); + } } =20 static void smmuv3_accel_as_init(SMMUv3State *s) --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1779187297; cv=pass; d=zohomail.com; s=zohoarc; b=UXuKJFVR+RwdGJN1SZt21WudBwzEK0Tw/41ccRKJcSYKCOFoIAD2/eqFC1uGVm3PSs7z2HhhvC/89L7z+3HPpPxRZfYykpQwFzNpIjOM4fVvZPE67iKodZnVB+M1GiCVvNfGF2DNTb1pMpq2gwfH4ywG7/9XPdGXE6tNtVYx+24= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779187297; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IH4u9PW9lnocK+hhANt40X30OtDZmInB9Pr5onX109A=; b=ThMZXN1LU2W+0AvvuX0TmLGRJNzTE9JbaCE4A3r/9ijt+UmMs3dQ3/HIrzRzLqiqzORJYJZBtPNJ3QYMC/oUPjUErajvZxDhloPr/NhflyLj3L2XRYl1K/9zhEOI66PIWONeTD0LF910q+p3EDwKhg1KbcLBmAhSAMXq5P6om8A= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187297333375.977548139898; Tue, 19 May 2026 03:41:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrD-0008GB-Oo; Tue, 19 May 2026 06:39:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHr5-0008As-M9; Tue, 19 May 2026 06:39:19 -0400 Received: from mail-eastusazlp170120007.outbound.protection.outlook.com ([2a01:111:f403:c101::7] helo=BL0PR03CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHr3-0006Ry-LK; Tue, 19 May 2026 06:39:19 -0400 Received: from PH8PR07CA0048.namprd07.prod.outlook.com (2603:10b6:510:2cf::19) by SA5PPFB9BA66B77.namprd12.prod.outlook.com (2603:10b6:80f:fc04::8df) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.26; Tue, 19 May 2026 10:39:09 +0000 Received: from CY4PEPF0000EE36.namprd05.prod.outlook.com (2603:10b6:510:2cf:cafe::77) by PH8PR07CA0048.outlook.office365.com (2603:10b6:510:2cf::19) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:09 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:09 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:50 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:47 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gz+ooDksxBdaUms/i9fQdIMA8fwMJBz6LmjAyH98ykdYdc+kd/x79M8b3/tkPQVR/2kt3mPQpFj3VKk/XSWckrtT76mcZyJ0pAAywg6UGvr7Gpf9e0yAFIb2EB8cQ/shd2jjTW0mF0SaAlRApLbxSgaVE8ELMaAOnlPAefuErjx8NAMDv3ALswS/A8P3Ly+1xMKYDksHCuKMnv/AQYt62zQva33HdCEOGrjIKy9mYcED6PAzBUhfATIhkvFhYQHah6h+VH+09SQPigajr5oOwU6azW/+GhDY8HMQIfVsnPhuvbQMxOb/mhMusd/Ct4r69TvHfKoz7it1d0Mzm6vFIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IH4u9PW9lnocK+hhANt40X30OtDZmInB9Pr5onX109A=; b=thCixS7PyDhRrTcxUIwAjxjkohhm3wZ18k6N+i60q2gV5Ab+IqyAgcd2ZaQE1Nl6fLUbnvHVQUj6vq+zvjYyPliDvEfnlMCbp874pNz+cNQ5QPG8fWZu+HEeQ/TIwg7SRwTueoLa6p8iVvJExJ59AzsGW4BIZ+pTqMNFUkG46mry0C5Pte5Uw9hfzKenk4cytFIS0Cn1lb6e1Th7h4Wm1zVENeoIm8UFXqs17LosAe7fMN98kiJwT6SLghpGEAV7qwxRV50grIVwbVsd8WiCWihC4sIa9oy3RBX1Z2Cp5VqQZZmeHj1V94Irr9x9ZXT+Rb/k1/YzF7TuvYvlSOL3gw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IH4u9PW9lnocK+hhANt40X30OtDZmInB9Pr5onX109A=; b=ceUW5+zjGmNAF+51g8k0Jcpd7IwrEL8rrP7xvU5fuLhfBiJNV3df/2EYmWTkT2TMA86iZUGSzW6hK/SrlWrG7ZDDnIxfnzHPuRI7/YvJR5CUe9bcruAv/fongMZz2mTS8zzCuReO3j4mnRkSf5pJ2zb7IeB/AIhGN0Pd3InVkZJu0bGbTJEtZss5MZqyyuNZu/xVSt1qkCV0ILuINx3hB0eQuttIJGn8oTHjBDunENiHOcUT3hIZkhdavk/iQxjcTW9rHBjjDPGzjN8kCVU4HswVzaCydoJGItqLi555dTR6zrKy9nP4G8Ws0dwlRIP2+omYxPg4DmCB3fmJi3RJQA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 09/32] hw/arm/virt: Use stored SMMUv3 device list for IORT build Date: Tue, 19 May 2026 11:36:47 +0100 Message-ID: <20260519103727.899332-10-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|SA5PPFB9BA66B77:EE_ X-MS-Office365-Filtering-Correlation-Id: 613ee3b5-5a64-437c-cee9-08deb592dbdd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|376014|1800799024|11063799006|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: uyUJgsmoq8V8JINr8yAX02kEF7ICTXWBHYI2Q8BRz7vcbvcpfsCs0asI8U/zW+sr6slwoIHTYP+WkrN/OT9bcmcDntdjPBUlyPIo5i8ALM+ZJFCU0EefBQnWetIYAiSxNJ61/yE7qwECIS9W4mC7APHqGITksk6L9v8EG1COV4NnaoROWA7C1t7x7KCZUzqfmGOpu26QMHa9nKEUn2JhWqlSL8Pk8zvBC1Y5zQk8YHHHqeXqLij4dNVg2wV2MspE/vW+BuKoT7yKLBWsbY7cXUKW2yU8QdyqJP3h8FXO0/qkYq9fQkTIfnkq9U3Vmc7PL/MpQgoxiYnjDY3VXTbJklWo7Mt82NLdssxR2QP8rNr/lk2ye4t6EHpukWz/8YF2WC9w0qtDSMLbQnrBjlvCMISQHnhJx3g4v5b6/j4xBUSqBskH/anQZaE9gj43LSOS7SfYEEoNNcdQfiTbmd/EqK9UYf4EjmzW5s9DXK1wjmwykTIVFw26PkGFrpDZGn8vFz3pkotGYWvQjnaGwJc9YFtJWq0rULIB+sTmGysh15Cm7/CD+XYJ5uxGbfWQnxo4H6XmX0bEJIIiYAihZN73p6sFjwTVA1KuPdAxVGv+YDnxJAbIKfC1IS+rdlKiOcmYZLGe/WZivdYzB7ZbaS/UUk9GtXen4Im4JkJu/TbC3p/xbBM5LJh17AGya/Oc29qkX5RuZRYIA+NoG+wyfNbPNODemm+JmRWgaQJvdRa3h3A= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(11063799006)(56012099003)(18002099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jsw9KPpaFMT7iDRxJ/c6kQbCiR3RH81CunxdtUOUQB7mNAmy+k06dfg4rlVaNrpNoG6QNbRms11KIE05OXNS7j2nkIOmA9d2QOoKb/jZFvbtnmRk5nPqwBHPoiI/DuM60D2U9lCdkm06GqRbr6pTAZdFACk2yqi82VExgMBFlxpJcJzNx8exO8RtnqxGr26UP5WUvgAKbQ1Mz8AuuOVZ2NKR6hEHd65uB3W/t+cEfamnY+Ncx6vjRzNAwsDkGrE8HP5gnz7uGFqmKFelpVVAb5LkBnbkTqgl1ytLcncHNgf2mO75xOoFRlDeSUbDiib/xLLhz0Wtt0bBpkEbaJABYmAYVaB2rPaREs5yUZNWiGe82p5T8GkNS9WPKFJS8rvT6Zti9s/9egCRh8M1b8yI51B0uqW2dJWCvsQSvi/Suz00OjtMEETMhi4FYgbidVEy X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:09.0110 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 613ee3b5-5a64-437c-cee9-08deb592dbdd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFB9BA66B77 Received-SPF: permerror client-ip=2a01:111:f403:c101::7; envelope-from=skolothumtho@nvidia.com; helo=BL0PR03CU003.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187298285158500 Content-Type: text/plain; charset="utf-8" Introduce a GPtrArray in VirtMachineState to track all SMMUv3 devices created on the virt machine, and use it when building the IORT table instead of relying on object_child_foreach_recursive() walks of the object tree. This avoids recursive object traversal and provides a foundation for subsequent patches that need direct access to SMMUv3 instances for CMDQV-related handling. No functional change. No bios-tables qtest failures observed. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- include/hw/arm/virt.h | 1 + hw/arm/virt-acpi-build.c | 70 ++++++++++++++++++---------------------- hw/arm/virt.c | 3 ++ 3 files changed, 35 insertions(+), 39 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 3ba33b4bd2..171d44c644 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -207,6 +207,7 @@ struct VirtMachineState { MemoryRegion *sysmem; MemoryRegion *secure_sysmem; bool pci_preserve_config; + GPtrArray *smmuv3_devices; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3f285ff6c7..b00f3477ca 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -392,49 +392,41 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, = gconstpointer b) return map_a->input_base - map_b->input_base; } =20 -static int iort_smmuv3_devices(Object *obj, void *opaque) -{ - VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); - AcpiIortSMMUv3Dev sdev =3D {0}; - GArray *sdev_blob =3D opaque; - AcpiIortIdMapping idmap; - PlatformBusDevice *pbus; - int min_bus, max_bus; - SysBusDevice *sbdev; - PCIBus *bus; - - if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { - return 0; - } - - bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); - sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); - pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - sbdev =3D SYS_BUS_DEVICE(obj); - sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); - sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; - sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); - sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; - sdev.irq +=3D ARM_SPI_BASE; - - pci_bus_range(bus, &min_bus, &max_bus); - sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); - idmap.input_base =3D min_bus << 8, - idmap.id_count =3D (max_bus - min_bus + 1) << 8, - g_array_append_val(sdev.rc_smmu_idmaps, idmap); - g_array_append_val(sdev_blob, sdev); - return 0; -} - /* * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and * return the total number of idmaps. */ -static int populate_smmuv3_dev(GArray *sdev_blob) +static int populate_smmuv3_dev(VirtMachineState *vms, GArray *sdev_blob) { - object_child_foreach_recursive(object_get_root(), - iort_smmuv3_devices, sdev_blob); + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + AcpiIortSMMUv3Dev sdev =3D {0}; + AcpiIortIdMapping idmap; + PlatformBusDevice *pbus; + int min_bus, max_bus; + SysBusDevice *sbdev; + PCIBus *bus; + + bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", + &error_abort)); + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); + sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + sdev.irq +=3D ARM_SPI_BASE; + + pci_bus_range(bus, &min_bus, &max_bus); + sdev.rc_smmu_idmaps =3D g_array_new(false, true, + sizeof(AcpiIortIdMapping)); + idmap.input_base =3D min_bus << 8; + idmap.id_count =3D (max_bus - min_bus + 1) << 8; + g_array_append_val(sdev.rc_smmu_idmaps, idmap); + g_array_append_val(sdev_blob, sdev); + } /* Sort the smmuv3 devices(if any) by smmu idmap input_base */ g_array_sort(sdev_blob, smmuv3_dev_idmap_compare); /* @@ -568,7 +560,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) if (vms->legacy_smmuv3_present) { rc_smmu_idmaps_len =3D populate_smmuv3_legacy_dev(smmuv3_devs); } else { - rc_smmu_idmaps_len =3D populate_smmuv3_dev(smmuv3_devs); + rc_smmu_idmaps_len =3D populate_smmuv3_dev(vms, smmuv3_devs); } =20 num_smmus =3D smmuv3_devs->len; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b090233893..ac0606fe87 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3865,6 +3865,7 @@ static void virt_machine_device_plug_cb(HotplugHandle= r *hotplug_dev, } =20 create_smmuv3_dev_dtb(vms, dev, bus, errp); + g_ptr_array_add(vms->smmuv3_devices, dev); } } =20 @@ -4319,6 +4320,8 @@ static void virt_instance_init(Object *obj) vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); cxl_machine_init(obj, &vms->cxl_devices_state); + + vms->smmuv3_devices =3D g_ptr_array_new_with_free_func(NULL); } =20 static void virt_instance_finalize(Object *obj) --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187254656455.91945176002184; Tue, 19 May 2026 03:40:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrG-0008LP-Fu; Tue, 19 May 2026 06:39:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHr8-0008Bs-UU; Tue, 19 May 2026 06:39:24 -0400 Received: from mail-westcentralusazlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c112::5] helo=CY7PR03CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHr7-0006SO-89; Tue, 19 May 2026 06:39:22 -0400 Received: from PH8PR07CA0031.namprd07.prod.outlook.com (2603:10b6:510:2cf::11) by DM4PR12MB5844.namprd12.prod.outlook.com (2603:10b6:8:67::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Tue, 19 May 2026 10:39:14 +0000 Received: from CY4PEPF0000EE36.namprd05.prod.outlook.com (2603:10b6:510:2cf:cafe::9d) by PH8PR07CA0031.outlook.office365.com (2603:10b6:510:2cf::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:14 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:14 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:55 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:51 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=j3OThLZwAbW7PNFSxOtpdwCivtdet3QyhPWEF//9+zwV8Ghy/RqnlB9nFa4xvJSuIIGjDqGDIV9uxmWmIq9gKO3Gz5nbTUlnNalG4L0Cn8S0NhKepYoj8cXhzSAYGOIWbq/9JdwDBLw0HTtnlSyGHzfIpYNAfqnV+dtsCekqncw1rrFB030DBhWy5kXvJbE7YVeASKp0AbB5A0sAlELFkPPvK6/atNLFnEkpOoW9ihf8A/djOIJ0PrNSEVlShlyvaq3n0PPQsiVQietGKvEolbLLKtK4Lhmj36CsUvvf5n3aHjWHEJAgnE8cJoG3VwPNZAF4XlfgIRqA+MbHqqcxXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=o80xHJPipyEQz163kC0jClUds8kjHNw4Ko2fDKo4Xqw=; b=XOgNeyUTqH2oOYzlFQGePva3aDh1AiVx87FV0267wBwXYo9Nv5vSHtxQWgvyV8A1DdklD+ZCc0L7CuEysagFY9LFdMQoW+eSfta3GAWND6dD9L4Sa+lmrqdX6R32aHIrM/dZAwA8MnVMkX5wxENAsqHDNKYD7vTUHL8B44cyb8MiVUT070z+1QDoLJMUhDtSM3e2WLHWz7Xb041FJtH2T7m989gfQ1ImBlWRMHmBD/pxhr7eadoZMu/RQW2CvVfXIHTNy6buVXui2Qzx0GKsotqu7W8LqlCjNtiS12FDKIvJHZAWW4GZtQFM+zcVosmxSAe9ekwXevuvE3+vSrNsKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o80xHJPipyEQz163kC0jClUds8kjHNw4Ko2fDKo4Xqw=; b=Zsd7dHMDNIIbIWvjQjH5ptSnifvvcv4oUKeFh7u9FBJ3NNAoL78hEryBH+zhjbhF/wat8qK3BXkx52ZUub0BIGmcOJsLONYBndPlxxd/+CtDTV6oLR/K0IJZepZLCPKKRbL6b5o5Rjr0PfUjOvJsb/h+PqsmUKSztd0uC5sCGcKVwy3WSIs6FSvBsTF6O8wO9qENGnY5fdGaRGqPdZXF0NX15UjKLoo/D3nJ6th+njCGCdeSSeicjSpnTT2hub+W6smqsrVZ/d6BFV2c4hI0ug5fmkLnMHeJjIoEIR4zHm5xKv4sFiJDV0YoZXBnTm08w2nm9Uy6cmxyDGHzzdFgdQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 10/32] hw/arm/tegra241-cmdqv: Probe host Tegra241 CMDQV support Date: Tue, 19 May 2026 11:36:48 +0100 Message-ID: <20260519103727.899332-11-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|DM4PR12MB5844:EE_ X-MS-Office365-Filtering-Correlation-Id: 85f9bb93-231d-45ce-c734-08deb592df0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700016|376014|11063799006|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: 2QYkOUFXTtPkkHeQXTbIZpXSp7yrNu+ln+B3GxYvPw0URZLUfXQDLHIf40YLyJRSpxFhQDoo9sxjFstbDrbN7TRDNJJaFIVdxde/qFpp1pwGab8ba2pkhWAMMrwIUkZumLGeoD6oXICgcxfwrbkyeQVsY64ujVPvdQCKROtrq2eimOB+Gy4e7q+JjE7kvET6o9i6rM8+5jPS43500H0Xi5kXEJNCZygjStpe+7XLz6Wgu2+0WDLCQD1D5IU7slqZxClKd5N3mdNcseIGxtck8rZ7Ja9LgdnAubs0owCC3zIU7k9+2vAYT+N9MsQu1eAMAcAZpQBWMcn62mS5ISxkLb8JRQxxd4L5MBOVEu2K4dcLskWEOkVOJWnouEMFvCBWpdCRpgHJ3fbaUijgJhvOKKX2gc5XuATjvO1iKawTHihbIhdloourig2rtnJ0Ps0WO6odHbDiU+sD7U8r2O8dHVF/SdGLw4vM1l81uhKRR5h7M0dMNN+308rS7VMXiLA4DYmtcwZuFHMzYok8tWIoSHCpqm11a5GQYCKuXlRaQ8RRdjomBzgN1cZpWS4je5Cj2EqirKEvGuTdLoxcg+yL12RQWq2Yn6SU7HN5bDTVnwug0eDuhP1CPFYDNQPJBm1LHUksjRBBLl8wm+s3NAJCGmF2LG9/KnKt6Ym9xS/CJucXdiodYDv2vUaeq9fO0wCZ4NE9Uc0w9hLJTW53PH7PqJ9HEe68L4Hy1WsYt6vo95A= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(11063799006)(22082099003)(56012099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nwYoaOkKfiRAcegVH0DP7PBsM2rkJ/40fZ8wj4s8eODltx//dCqKkAtt5GkZqRu18nrj2VxJrW2QIS0922ZFw6Np3EN+L3Px3kGriHDM5EijyJWOC+Tzr6fek4qCCkXvFqRHjU4tf4yJasvrAU/8ebklSdTRurcyZ4iV9y20+bqn0V/wKcu9VUGC6Ee3/eepG2zFK7nnxPcRB+5GeJG1OAESxmbBtWeMt4dGAugZI2qdssAjq6oPOm8xziHr5h8bqD+J7r6t/49vSJpXK8CvPx5hNFs044sH7c9F+0Loatwcl/EFZijx+B9bTtsXMx3foUk0YQGtBokGXayajZ2mJ6BlDT4uEWwsGC32dWhYzwzjs5ITridqD+Ta3v9pjnHIL3Xwpck2mECA/c3meXEcEKbId1Te4bLCt3GxNIvjgwkmF8FEcZkc6OXPcPVRvqZD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:14.3864 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85f9bb93-231d-45ce-c734-08deb592df0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5844 Received-SPF: permerror client-ip=2a01:111:f403:c112::5; envelope-from=skolothumtho@nvidia.com; helo=CY7PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187257206154100 Content-Type: text/plain; charset="utf-8" Use IOMMU_GET_HW_INFO to query host support for Tegra241 CMDQV. Validate the returned data type, version, and minimum number of vCMDQs and SIDs per Tegra241 CMDQ Virtual Interface(VI). Fail the probe if the host does not meet these requirements. The QEMU model supports one Virtual Interface(VI) per VM with 2 vCMDQs and 16 SIDs per VI, so the probe ensures the host implementation is compatible with these limits. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 4 ++++ hw/arm/tegra241-cmdqv.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 74a6954017..38c8b27b4d 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,6 +10,10 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#define CMDQV_VER 1 +#define CMDQV_NUM_CMDQ_LOG2 1 +#define CMDQV_NUM_SID_PER_VI_LOG2 4 + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ad5a0d4611..3a19a1af56 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -38,8 +38,36 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error **= errp) static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV; + struct iommu_hw_info_tegra241_cmdqv cmdqv_info; + uint64_t caps; + + if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, + &cmdqv_info, sizeof(cmdqv_info), = &caps, + NULL, errp)) { + return false; + } + if (data_type !=3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) { + error_setg(errp, "Host CMDQV: unexpected data type %u (expected %u= )", + data_type, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV); + return false; + } + if (cmdqv_info.version !=3D CMDQV_VER) { + error_setg(errp, "Host CMDQV: unsupported version %u (expected %u)= ", + cmdqv_info.version, CMDQV_VER); + return false; + } + if (cmdqv_info.log2vcmdqs < CMDQV_NUM_CMDQ_LOG2) { + error_setg(errp, "Host CMDQV: insufficient vCMDQs log2=3D%u (need = >=3D %u)", + cmdqv_info.log2vcmdqs, CMDQV_NUM_CMDQ_LOG2); + return false; + } + if (cmdqv_info.log2vsids < CMDQV_NUM_SID_PER_VI_LOG2) { + error_setg(errp, "Host CMDQV: insufficient SIDs log2=3D%u (need >= =3D %u)", + cmdqv_info.log2vsids, CMDQV_NUM_SID_PER_VI_LOG2); + return false; + } + return true; } =20 static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187335222435.314761199215; Tue, 19 May 2026 03:42:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrI-0008SW-Oz; Tue, 19 May 2026 06:39:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrE-0008IH-HE; Tue, 19 May 2026 06:39:28 -0400 Received: from mail-southcentralusazlp170110003.outbound.protection.outlook.com ([2a01:111:f403:c10d::3] helo=SN4PR0501CU005.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrC-0006T2-RI; Tue, 19 May 2026 06:39:28 -0400 Received: from PH8P221CA0055.NAMP221.PROD.OUTLOOK.COM (2603:10b6:510:349::8) by DS0PR12MB8813.namprd12.prod.outlook.com (2603:10b6:8:14e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Tue, 19 May 2026 10:39:18 +0000 Received: from CY4PEPF0000EE31.namprd05.prod.outlook.com (2603:10b6:510:349:cafe::c6) by PH8P221CA0055.outlook.office365.com (2603:10b6:510:349::8) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:17 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE31.mail.protection.outlook.com (10.167.242.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:17 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:58 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:55 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=J4TN0VI8H9nRWIwJ9vmTbr8P6vSZ2MW8rdQxV+25LJ5RjSW/wMG3Gs8FdUpxe43Ln3vQm7MG1fQ+uUanO3TtziAk+ArOrB8kErJtxBczRVF3Pbww8esDp52bdrxss7LkdfT8WdCtAioDQmWyQbR80A2C2I4q/0Mg+CCorpanEie1C/kc9odh/odMbaME/SeRHNxTU6yOZAPC4rhkweyevLZD4fBJCEQJp1a7Pez1MgwMya2QFRyNI3nnH3mf/Ibb5F10BQvfN94mmtWFmmy9NcF82njN7kDQjoDIT+P2jiUqt+oZc5t7/KgOyjGp5g7fqgWlDFYq1ib0tz1Y4k8Z2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zbERKWR323EwSXNMs/LzmHmvRZGslLcH5WfYwbtkN50=; b=ocU1/G7ii/NPx0jB2sAuX1QFTdn4RHZ77AOG1o/rLkzQA1MmP73o3NV3LrXHOYqdKNuPEL+gQk3ZHKFDkOEZ1MxK3uYI9FqBqsCqwr/95LMEqerjc93sLHZXA14E7zLFaFmwF4oFM59g+xmBUJdLVVs/N9nFloVXho8Yz9ywx+XbR3bgf2VRwF1mvL17bTzIHjU8kpU/pvknxwIVfKcQI/+wth2hbiQEzWq/92ZkbVI83nS5RgvxEibq8Gn7CK1YiGkG8FYqd+pHG/QSLHVspWg3IDSKsVP2iV1M00nmy4dyB0HsaVPAvoHlwM+X4hdqbiOWPkeZbn4J+DbT0Jfxfw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zbERKWR323EwSXNMs/LzmHmvRZGslLcH5WfYwbtkN50=; b=QZ9mC40w16v2Ch6mLJQfMmj7QqmbpIzI2bp7p4rjUYOIscsny5nw5+FEwGlbYZYDL59FVuzPNobTFo4f5woN2qzr1cj6wJ9w8K9Y5tHcnXjUXW3WZ45JIkAmxcFwsZODPbREfrEQ+9UX0orAQGxSUiuARyIIXyjOHcxyinHKuIu9MrWgS5RTqkkS2PkoTJnYZMLt/A+zD/qkGSkvV6Ri5XDHK0A3OMLxSkYWXMmoAAL2Mg0LxYHir3GsN0uFwb+go1G07/4WYx6czD3uHiuGgDAzkZcWQYAztOqup1YhGnn0yXFeow5Oh+IdcsvpXAwKJRPQELQZWiqQn50g65LLOA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 11/32] hw/arm/tegra241-cmdqv: Implement CMDQV init Date: Tue, 19 May 2026 11:36:49 +0100 Message-ID: <20260519103727.899332-12-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE31:EE_|DS0PR12MB8813:EE_ X-MS-Office365-Filtering-Correlation-Id: 05d36f67-2bfe-4685-6e35-08deb592e0ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700016|376014|11063799006|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: AmAkBgkigcEtLNTWn+2C9YEGdBwJpzbgtyZNrUjuyXr2K7vZlR0zN6itqt0X/0jZPSdAn3CNSiVzJxn0ai8SHghjlVv2gBmZDo7OrJBXUre0/UAPuVGynnWGdVAjQX7lt01llr/5x70uag7m7SjyBN95NbPzQUqYnGV7RNYQQ6ZJeuVINmEeIkSSMqyVnfDuO6bLXR7Q1dcz+4aLwc60yTfxB6f1zWzx2bVzfgM0RXzkj2PFpmmJZotCNEW89BkiuUDKfy62ulJVH+pAVIR7xjWjKi8unsByd4rdBqcblapaV2J3i5iTBWMRgaC1aE1eeA24C+zB4SnRnDhQzKKthrOCfTNq9uREz8GLkmFPbYwWogYadSQpZwqNUN5EOip0/e1CZKiFbQRr0D/VwbuWGE1kHiFsDdSnfDCxNjQA8X0gSRZAx5tgxpq6eVbQuAMyT2uSs4Gu9KsSqXKiWyHVPu71envCy1BEMkkdV2JeXz0yOPcLukuSRIM7A2DIg3dQuYPoN5ktWfZyqYigHS0EuTAHmO94DoKJSgUi1y1H+qOm80kyy3/RUPia8OinBVvN8Voy4oGa+SFy0nhuvWv6/X0Mct8CPtpjIL1m5qwQlao/3DZwrgeacH9m0kaPFVsHAtpBBQRc12ZnDl1Nl42r/oS4+AGwqwJ1n92hR8x4iEKneOtJ8NhY8xt32k9jKYfleLnH6NUTskkTZ5FXEiVZNwBSBnBFe3L1zHrmEbUcy8k= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(11063799006)(22082099003)(18002099003)(56012099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RUuFCDBgk3saib6wgn8n64bcKYdJhY6E2wcqZ43dLqKbD6RVnzxIQOhR+c1Wgkhy69Ho553Ag8LRvdNmNTnr4f8RVKCJPF1rMyBVQmbkmnIflzkyL7fdEb4HEQRXXAh3Loo2gA4zkpkgF4AI2iOI+oUKOmzsqojeeB7Z16R0XjAhPhzfvZBeK9pMw8aqH44qmBRQrmq0nioXP1LLP4XyvhAVI+GsbIhoKXtW+vU3hqhwaI0D8knayGwSEEPDK5IswRDhgH4EZ8s0ONtJ8zi5zZsYF9RpkqcWPFs6uwYjY11sNa7NpV+EUuki09+9IoTyAcAFjmz5ACRIulKznvnZKZmKiDn2m2UJ5QtMCMil3gNq4FcTSxY46P14IaYP35mB4ARAsDt9iSrYXMyGHP807NKMV48MKTOzxg2+QfjrfDIqstu6tEAOTCnlfdkkxrTw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:17.3126 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05d36f67-2bfe-4685-6e35-08deb592e0ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8813 Received-SPF: permerror client-ip=2a01:111:f403:c10d::3; envelope-from=skolothumtho@nvidia.com; helo=SN4PR0501CU005.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187336741154101 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV extends SMMUv3 with support for virtual command queues (VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split into 64KB pages: 0x00000 (CMDQ-V Config page) 0x10000 (CMDQ-V CMDQ Page0) 0x20000 (CMDQ-V CMDQ Page1) 0x30000 (Virtual Interface Page0) 0x40000 (Virtual Interface Page1) This patch wires up the Tegra241 CMDQV init callback and allocates vendor-specific CMDQV state. The state pointer is stored in SMMUv3AccelState for use by subsequent CMDQV operations. The CMDQV MMIO region and a dedicated IRQ line are registered with the SMMUv3 device. The MMIO read/write handlers are currently stubs and will be implemented in later patches. The CMDQV interrupt is edge-triggered and indicates VCMDQ or VINTF error conditions. This patch only registers the IRQ line. Interrupt generation and propagation to the guest will be added in a subsequent patch. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 1 + hw/arm/tegra241-cmdqv.h | 18 ++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 38 ++++++++++++++++++++++++++++++++++++-- 3 files changed, 55 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index f82a7112d8..49c10535cf 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -62,6 +62,7 @@ typedef struct SMMUv3AccelState { bool auto_mode; bool auto_finalised; const SMMUv3AccelCmdqvOps *cmdqv_ops; + void *cmdqv; /* vendor specific CMDQV state */ } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 38c8b27b4d..030f5758d5 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -14,6 +14,24 @@ #define CMDQV_NUM_CMDQ_LOG2 1 #define CMDQV_NUM_SID_PER_VI_LOG2 4 =20 +/* + * Tegra241 CMDQV MMIO layout (64KB pages) + * + * 0x00000 (CMDQ-V Config page) + * 0x10000 (CMDQ-V CMDQ Page0) + * 0x20000 (CMDQ-V CMDQ Page1) + * 0x30000 (Virtual Interface Page0) + * 0x40000 (Virtual Interface Page1) + */ +#define TEGRA241_CMDQV_IO_LEN 0x50000 + +typedef struct Tegra241CMDQV { + struct iommu_viommu_tegra241_cmdqv cmdqv_data; + SMMUv3AccelState *s_accel; + MemoryRegion mmio_cmdqv; + qemu_irq irq; +} Tegra241CMDQV; + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 3a19a1af56..298671e0ce 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -13,6 +13,16 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset, unsi= gned size) +{ + return 0; +} + +static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, uint64_= t value, + unsigned size) +{ +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { } @@ -29,10 +39,34 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) { } =20 +static const MemoryRegionOps mmio_cmdqv_ops =3D { + .read =3D tegra241_cmdqv_read_mmio, + .write =3D tegra241_cmdqv_write_mmio, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, +}; + static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(OBJECT(s)); + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv; + + cmdqv =3D g_new0(Tegra241CMDQV, 1); + memory_region_init_io(&cmdqv->mmio_cmdqv, OBJECT(s), &mmio_cmdqv_ops, = cmdqv, + "tegra241-cmdqv", TEGRA241_CMDQV_IO_LEN); + sysbus_init_mmio(sbd, &cmdqv->mmio_cmdqv); + sysbus_init_irq(sbd, &cmdqv->irq); + cmdqv->s_accel =3D accel; + accel->cmdqv =3D cmdqv; + return true; } =20 static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187189328849.6785412899012; Tue, 19 May 2026 03:39:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrF-0008K3-5f; Tue, 19 May 2026 06:39:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHr8-0008Bo-GE; Tue, 19 May 2026 06:39:24 -0400 Received: from mail-southcentralusazlp170120001.outbound.protection.outlook.com ([2a01:111:f403:c10d::1] helo=SN4PR2101CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHr7-0006SI-2Y; Tue, 19 May 2026 06:39:22 -0400 Received: from BL1PR13CA0394.namprd13.prod.outlook.com (2603:10b6:208:2c2::9) by MN2PR12MB4256.namprd12.prod.outlook.com (2603:10b6:208:1d2::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.24; Tue, 19 May 2026 10:39:15 +0000 Received: from BL02EPF0001A108.namprd05.prod.outlook.com (2603:10b6:208:2c2:cafe::37) by BL1PR13CA0394.outlook.office365.com (2603:10b6:208:2c2::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:15 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A108.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:02 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:38:59 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=i4uS3X1q9tBrHZBSCHa662O9RsxTFNLni2qESmtx983B/9eBED02bK81iWdDJiBXudSyJDCc+RsiMV2EMdffWu9ax/07tV4tT0XiX6aLM2rXpkxBJRjpVD+Qluxl+87969fniQzffb034M2/s1TFEDMu4RjH7Dkd3Eb6wnpBqvy4ZQLiGBsnAm60Ho21oaM3iddYTJBaIWLea2DLIDOHZImejUt7dWnd51mVt0+2JeyMcvaxssn1dghVqr09i9snPgs1Dc8t4IYGplhx+JKM7n5ZC+SeJme9Ps8N70G/ZA7S8PyUdCShu0Ihj9gIsNAfQxiiRqdboSyGgO4vs0RaTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xhNrQCihf+DjDeMqIVYm4bXU+bGz60NlRZq+evYtsNs=; b=lrB/5Ak2bqGXtB2F7LNi/XVJhevASgvvw6sWfWLnxqSHX4wPrB77O5TpBgNtit/tzjj0Gdk0MFefAA39fx+iSv6dHtzmiyUezQYBIptzlaDtJwsrY6Yctx5Jd28F+9QwM98jQ6Yn/KMgN2bmxQTTCaieA9bRmabDIt1LSq7tqHzfh4uYQ0E8Mm/YBhQLhmr/orSJgp4szY8yKZUTHZ1C1vWkSQ9qUmtunDm6WKPeBj+6U3hb3zUUjubdfoCXlOjRNHN/OM6JL1MhouIu394074x2kNlHt05NYX1aALXYG31AcTifbGDiridrxiIDoaye1KZt7OOB+542B7STte2r1A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xhNrQCihf+DjDeMqIVYm4bXU+bGz60NlRZq+evYtsNs=; b=LE/l/BYBl8ufh3WimlcyYo/MugfweiU0OIE+uQPUYE9oCimdmC8nDyEdQm6t4LlElcd/rP7A/aoWlrNLVSQR4YqqJP9MAEkqgwkPuBAV1p3Ur4a8tH/Tbmq0jGwc3jSxAqVD4lxUPkIUp+KewFlsMg9fqYpUlaJ+9kNJpcuT24tshc3z31GsDnlzvbecVB5C1DNQQVjejIAXgY8zjCpLCvV68WUMFTPnwdAhDngub/V6cM5JMn9r4IHdY065dt7vLPGSRbxjy0Pfezah4Y9EZ7cgOZyZMYjdI2A1iDUPB0eeE5SaLYwm6JtA2DeY6Du0p98LlVOCbRBvW1AnIVG3QA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 12/32] hw/arm/virt: Link SMMUv3 CMDQV resources to platform bus Date: Tue, 19 May 2026 11:36:50 +0100 Message-ID: <20260519103727.899332-13-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A108:EE_|MN2PR12MB4256:EE_ X-MS-Office365-Filtering-Correlation-Id: af624a78-4566-4b14-2fea-08deb592df7c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|376014|1800799024|11063799006|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: KVsWcBio2TmHnBtpmbjkyk3gj9+ekfj8ci3zLzIg2uARzSJtr0o6kKh5Xpz/oG0dtLLZHDIeGuIvfnZcC3t3NXszUNblzVw9bOJdZC8n2QIsmGlfrzVLBANnYrqavANCCvAx4TB/Z4gmw5S7Latbnm16LfAhB8YQRCPEdwHm2KFUt9esUicdpi34ll5VR21lr9X5CLpKAM+sZ9JoQOa8oPTwoJ07Y1e5zwPGIV9fkRwYrjDxNqrm8Vn27iV0o9RYQy9ttklSrSWMm6SwnoInW+fHXWmmtnBscAN860GyGOpMUiVirokNd6s2fCjjFJ4OkfHIl2fgdAk8r1LzOSYPwj6bphUQG7X3yTZzkJTA/vJfLoksRhx2tyj7ZoPntWma10646wrFsi+xZwLg8kewp7Ymco9aNGzHgj9yURbGdbMRZzL+S8OiuSQ32uqxr+L7Yo5M2v1v+8mehPuDV0hSF4Lh5lyNPqGtHJl+6REUCASLil4KuCC8Xf+aywDydhROFRJqD5uoZHFp/CqF3LfoAAjcpoHn0MRMikkmIlFp9VJP4hFg9o7md3gHtmZC5lrUu6IicKiD+DKylxeUAZEguCtghaIpqdX5AKfcCn+jJ+enrtwH1JnKshfGthnewiD8LGQ2PTcWM+oPjE75u9/w9Cp+SPwsFzSzVDv1MN94dJ4LkLATn/NvdiWEl0HNxwZpWqOBWdasyNyqgbYwBwdsCigFpvFvCxV7F3JfknxgqOU= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(11063799006)(22082099003)(56012099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sBjil5EzyR9nb/TwgTQQXQ+w1nnKmpUk4MxZ3GkjqQgcwaXo9NxLo/iFPLTTP8uSD4NsZ+c3Usu/jex2nK9/ZMq7Is0+qmGge6S/aDO/T9QblU6VKm7gmcgzPUOUcT9XtUzmM3iQIgA/cCQugxixkyg23i6WLG2MYjx1s+J1Pi2oAKh6FtFqFpgCvhz84WlVJ9XrfzYmphlz3k1XRPG3UZHK0f7vY5m9PXdUcDGFvp/lQN6aPtLUxhCK2VEoPuiXVGJFuws1vUHdZNEEDr0mk1Cr9sOAWBy4Xk3p2df+6+EaYWWEMUZzRNmI99jG6ht8Q/pS/zsZjWJ91GkWmt7f7nA1OQsleOZuUvekCf8l/e9Ue8bu9ouGhAascoze9NHI0dVDB0e6hKJacTnQDisBAR2NYHhsPnIX5vqVdJUpCp2MT/4l9UhX0YXEUHCQCVkt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:15.0668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af624a78-4566-4b14-2fea-08deb592df7c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A108.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4256 Received-SPF: permerror client-ip=2a01:111:f403:c10d::1; envelope-from=skolothumtho@nvidia.com; helo=SN4PR2101CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187191633158500 Content-Type: text/plain; charset="utf-8" SMMUv3 devices with acceleration may enable CMDQV extensions after device realize. In that case, additional MMIO regions and IRQ lines may be registered but not yet mapped to the platform bus. Ensure SMMUv3 device resources are linked to the platform bus during machine_done(). This is safe to do unconditionally since the platform bus helpers skip resources that are already mapped. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac0606fe87..2add7401a1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2361,6 +2361,25 @@ static void virt_build_smbios(VirtMachineState *vms) } } =20 +/* + * SMMUv3 devices with acceleration may enable CMDQV extensions + * after device realize. In that case, additional MMIO regions and + * IRQ lines may be registered but not yet mapped to the platform bus. + * + * Ensure all resources are linked to the platform bus before final + * machine setup. + */ + +static void virt_smmuv3_dev_link_cmdqv(VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + DeviceState *dev =3D g_ptr_array_index(vms->smmuv3_devices, i); + + platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev= ), + SYS_BUS_DEVICE(dev)); + } +} + static void virt_machine_done(Notifier *notifier, void *data) { @@ -2377,6 +2396,9 @@ void virt_machine_done(Notifier *notifier, void *data) if (vms->cxl_devices_state.is_enabled) { cxl_fmws_link_targets(&error_fatal); } + + virt_smmuv3_dev_link_cmdqv(vms); + /* * If the user provided a dtb, we assume the dynamic sysbus nodes * already are integrated there. This corresponds to a use case where --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187200394556.3362696310103; Tue, 19 May 2026 03:40:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrM-0000B6-KU; Tue, 19 May 2026 06:39:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrJ-0008UN-PV; Tue, 19 May 2026 06:39:33 -0400 Received: from mail-westcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c112::7] helo=CY3PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrI-0006Tp-5F; Tue, 19 May 2026 06:39:33 -0400 Received: from DS7PR03CA0041.namprd03.prod.outlook.com (2603:10b6:5:3b5::16) by IA1PR12MB8335.namprd12.prod.outlook.com (2603:10b6:208:3fa::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.19; Tue, 19 May 2026 10:39:24 +0000 Received: from CY4PEPF0000EE37.namprd05.prod.outlook.com (2603:10b6:5:3b5:cafe::e1) by DS7PR03CA0041.outlook.office365.com (2603:10b6:5:3b5::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:24 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE37.mail.protection.outlook.com (10.167.242.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:06 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:03 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Mqi4T5a+EeSCIrGTQC0cRrADd7dluBg0KukYDMLfW3YpTbGkueNq80ZGHBSVIVrS6tkvN/gbXLDGNZp/NvLeww/q8Zm+y4g2BaSciyXuZi9m5AkhnCyFn0KeByD+4XXMRyPCrAj4fxodr2f6LLr8reAtec+mAq8a2dlg+gty912/d90N8Z2QFSub9Hi+qiM21csUcSnu2pPwXBnpcYUjtM6RLDjlUtT5syvRzsAXJB8SismJZSPgwyyTpfwrQUvE1pCTcBrlt4f+3AvytH3R9rGhc0EjPZGpkCRm3U35AyP9nxgYIpQ6YmwZaiMOUM4i8qkbIamItOo0b4qFfSbOHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/89rafBFmrGVNq+LSE0RCDjpUAewpVShKXNpokral3g=; b=aNuSPCKC2BHMj4pDogcxoStQ3HY++xS2KRbTqmaDenKFKok/sSszCAJrpiBVUMsrLy510+tXNIyOfqdm75ClrnzLa5cuVTCouBBgSIjB0MumCtTGLSzlFcrszGsg0CZLfCz/qqvZ7qS3Rf1hWBLHlTdlI0UyR1TmxCdQOjNZ5P+5pov7kUq4Zrotwih7OGFtKbjbdlh4RhsIujKnAcw6jGL2xz9bSQPfJh3Qll4wcf4fmVuR5FzGcy99v5qWohlrWGSctxIr9oKzZeEDb9MMdH/F0WIh55DKiEocXToV0IZ/lhkK6oO5/8D+KP+Omhu5OOZcVrKwSjfDmOXdAjgpoQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/89rafBFmrGVNq+LSE0RCDjpUAewpVShKXNpokral3g=; b=MJJuGCgGPePdIsYr3/ZhxBdpCGD933yZNot45aAKL+9dwrvY6dSPYZiSZKzZ6b2/o1RwJc445Qf88mXLuXgE2MsH17WsqvDJOQEpye8QEFJnrpmdMrB3r3yP4oX6e8+C4AofQixHEGUv+VmvqpuPIN1lyUlgf6xugMXdi3wfVHp0EQnYfpMty3f5tlvtE7GsD4y65suqwLbL/BhptKXvT7t02VU7kPpc/QEsNiNYzEI+3rxtGNMHfABUqm0uCR+hkMbDFHTImGWBGqmkCsYbJh4sle/0uYzS22H5/InzpHSetyJ179+/qm/gzf9LRIkaSvwlKOIqfPCmJVSo082oQQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 13/32] hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU alloc/free Date: Tue, 19 May 2026 11:36:51 +0100 Message-ID: <20260519103727.899332-14-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|IA1PR12MB8335:EE_ X-MS-Office365-Filtering-Correlation-Id: bf3534f6-ac7f-435d-79e2-08deb592e50f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|82310400026|1800799024|11063799006|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: BVT7sEYhi3YroWSgzJw2B7myhu9kQzG2PKuhKep9WBOrwIS1JvJ9+8DS/p0nOknkkDfiFNSgxG1TcUVerx8SmVyC+kvIaZNWXjOlhm/STGqvarrali9qAt+RLpV4nUXSpFCwdyzmrigO0+t7nWJ2ptK26E8039UHRP93nqn+6nyhWboJZzsPM1HBktQB7ET7tUUsdcE9RHocwlvVLVLEtkSimhKua04heRdxNc8vXlKGMF7eH87hUAjlJp8udRAsCtZ10c1Olc/Yv16vHNk2afkVVPYHA5VM12Y7/ppD/CgQltyF/BIafN+ZBlQjCdZELvyNHrciGw4RAzH/Xp5zE2tZ61Hr4R1M5HQqxxF88muT1OHGwQmSzQiqJgM02vQtMAqA4c3oQcpjFIdePxew5cwo7gTBBKlFuRGVO/6RNaMy4FXEkdAlxANyV/LL2mzL7Jb9usb83sqbe5aMchJQarhod89T3E+9wJE7KxUdqdTJbtETUSgtAOH1ACg8K4WW3DshnrVRwaHgTNf+NGrc3McXLyobU4feThLSLZ6tmkOwwRbD5k7hKMpXXeLFeKZVrFnKcgIJXF52LOIwvB5+5vRLtfPOO0z5hB3Hm46ZXoLtTqrGbuFRRuoyxJOqjz2uyTPuzomWWSmXxL/qF0Th5hifARM9p/f+F0R0UcOPPZkTLGNzmtic42jj9fMeXHibBZySvXGXqfD49bPK0deks9MqkXLA+dtk0o/5oYmJ1Qk= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(11063799006)(22082099003)(56012099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Y+Kg2JStNiC+hnEYgPJSQTJgvR0RJsgUZfjgu89xa7eeriSB3qw5oPhnm1yea/bkkcMj0Wpgnp7dorfZrZIw7Rs+N5Hr98KyfuoAtLkrgjFax8GjmqeOpydOPNgqmXkQcwCskVecKNos7zlbQKtQ8Xg+OVrbFvXynbWu1wsltrstlUgi+GwcdHVTAGCmnoMJ+39F1GmXXtTt5xygA9/8aoc9eX5+VIw0ihLyCWzyKTE71esG8oAW5sR3O7vm3/BiCmfujMVfuODQByZZksErO2VNXWfEM13TwbNIV7yE9SNUgMzPsnc3/jVuk1s+7Fz9IZRAMfkdkdBb+x5MLbrrsznTS4koZROsiuiLzG3qwUTFE6oJQtHOsqXnOF17INV6aGpvf+OrliIoKhY9r8oupU/bTe5c0Xue/eOsDshHBypFfMQk7JZislD6OGuxSXbN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:24.4729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf3534f6-ac7f-435d-79e2-08deb592e50f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8335 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=skolothumtho@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187201646158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Replace the stub implementation with real vIOMMU allocation for Tegra241 CMDQV. Allocate a matching vEVENTQ together with the vIOMMU, since it is specific to the Tegra241 CMDQV vIOMMU and used to receive CMDQV events. Free both objects on teardown. Reviewed-by: Eric Auger Co-developed-by: Shameer Kolothum Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 1 + hw/arm/tegra241-cmdqv.c | 48 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 030f5758d5..54854421f2 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -30,6 +30,7 @@ typedef struct Tegra241CMDQV { SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; + IOMMUFDVeventq *veventq; } Tegra241CMDQV; =20 const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 298671e0ce..6a6cfc2f71 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/arm/smmuv3-common.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 @@ -25,13 +26,58 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, uint64_t valu =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + + if (!viommu) { + return; + } + if (veventq) { + close(veventq->veventq_fd); + iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id); + g_free(veventq); + cmdqv->veventq =3D NULL; + } + iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id); } =20 static bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, uint32_t *out_viommu_id, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; + uint32_t viommu_id, veventq_id, veventq_fd; + IOMMUFDVeventq *veventq; + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, + idev->hwpt_id, &cmdqv->cmdqv_data, + sizeof(cmdqv->cmdqv_data), &viommu_i= d, + errp)) { + return false; + } + + if (!iommufd_backend_alloc_veventq(idev->iommufd, viommu_id, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + 1 << SMMU_EVENTQS, &veventq_id, + &veventq_fd, + errp)) { + error_append_hint(errp, "Tegra241 CMDQV: failed to alloc veventq"); + goto free_viommu; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + cmdqv->veventq =3D veventq; + + *out_viommu_id =3D viommu_id; + return true; + +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu_id); return false; } =20 --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187219803849.1573251567762; Tue, 19 May 2026 03:40:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrP-0000JO-QA; Tue, 19 May 2026 06:39:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrN-0000CZ-C1; Tue, 19 May 2026 06:39:37 -0400 Received: from mail-westus2azlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c005::5] helo=CO1PR03CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrK-0006U1-SV; Tue, 19 May 2026 06:39:36 -0400 Received: from BL1PR13CA0436.namprd13.prod.outlook.com (2603:10b6:208:2c3::21) by DS4PR12MB9747.namprd12.prod.outlook.com (2603:10b6:8:2a5::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Tue, 19 May 2026 10:39:26 +0000 Received: from BL02EPF0001A102.namprd05.prod.outlook.com (2603:10b6:208:2c3:cafe::45) by BL1PR13CA0436.outlook.office365.com (2603:10b6:208:2c3::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:26 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A102.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:26 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:11 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:07 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nNOJB+np65h66ZeNQRXv6F+9oSGpVej2tkwp3ChINXpYyn4LikFe4eOH5LKVoGmpURkEYMWPRYGwrrk4igItdU28kTlqEQ9/5v3hHm0x2pVbc/W7nInIbs1eozdVFxrSOBZDy7OBKRLwHHP248H+7xnV4PQBtxE8CQGSLGk+eKgXhidVLEv1/lezA/6lIM7CXbwpKckMWtpCMP71YAg7mmwamZmNwcITb6/uY4Ev+aXEHKuiRDNOFH18Z5ZgAM5XXWSNCqbp7uvTxFa2x4capIpxx0a8n+KeVOuyU5Ur1MW0jw9utal/Ec8TiWYdQ0Ae3iKLC32gaLgpsKuzYM0DKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GvkGxTMk8aoCUfcq09feR88Zhd50ZbIufr7RfujBjBY=; b=QkuCv7GuJz0RdMHipbBfj/w2pvFHDF+O5MPamJzI7ByPWrKY/JCtJzDslvLbfkN1CrEq7kB9TaRiYhPmLOZKANm+nsEVuFK7VhkfVkSs9J1BwnSy+WXzVlq7i5RSekLmr+k7kDtV7lUr2OmiGF7b1cNQQi6Kq7YzuXnaBMVDwXCRyNhMGWxgwSJcRSVdZ5pAlBaFtTyr77m2klWCE+xYKWRiehNNuqYUcHQk+y827tK/6DAHt/h8XlLRvl775ww69iehLa5HSlev06WxnCDhpSvbKm92zjw9D9LAm11R6+w7uvLXbjtfWaz9Wyw9a4ZqKmqYKOAi8mZD9QmXc8JmfQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GvkGxTMk8aoCUfcq09feR88Zhd50ZbIufr7RfujBjBY=; b=IH8O/LCwlY5p53iGI0o55krekwwMOS47B9gGNY+DzbSYWGvN9A6BAJawOgOhyDs1I1MbQ5RHTZUKgO2VkwGx7961NDJmXViQjs6rEychEctglq8yoywHGEx9IDkFnB5kkplScNATBr9jXOU4rqor+cZmtFpQyPzmMu6t4jgp1Ew/ZD/VUSpge/94w7BVKS9pv7RWx5PyRZTaGImRBgGqebsgyaYaFRTd3uiydoAfH0WVexDJaGZ2njWgS1AvfW/eN4dOeMuu926icfu0ilFdHRQ37v4oKMMc7BsNbz1mp2N6/B48fG51RSYlwklKIfdVyWlpMSO2pyu/Rds6l5IdSQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 14/32] hw/arm/tegra241-cmdqv: Emulate CMDQ-V Config region Date: Tue, 19 May 2026 11:36:52 +0100 Message-ID: <20260519103727.899332-15-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|DS4PR12MB9747:EE_ X-MS-Office365-Filtering-Correlation-Id: acf5f563-f6f7-4822-3334-08deb592e604 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700016|376014|1800799024|3023799003|11063799006|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: iBflSCzrvKyLXh7TrF6YZoXvSs08Q41SEAxzME1s/wmOEFA8IKwEXcjg+2BHgea1Nt3mo8zFPple0HRcAii0MS0sHCGN8NQn1MBzkSPGGphnBv3s9zcMUnOoLs0raQ9DcUiJn9hM8BXHjqf39Mo7qI5vrc9prrZnIi8gye1R52jlxG2KOffegwYPPYQEdHdrCLJQGPSGg3kEHMiDcRLkPtlGSSB1j6Y5hVmSM3uYDPRPZXSrL+aC9KYLb5NZjzM7CYY4uIAJJCcU9aNxnBZJGKaF/Yw8tXJvFEHrR5FchcMlTx44S9+ONTcQFqUOU4Ow7BXrE6X+CBlNPCM2f5dV8Eh4FR+1moXakSABtVXXoyLioZSstNyg04l1/9n5EpjEOCRZT6ZvKdBMGqgcaCZ+KIRoyZGlI4Wznn1sgHgYKqfKppcZLVMDP/uVFaRGNDvI6GT6qzwJYkHvH+aamqIAoCnYcwlz93K0qIf1QX+72jInX/wxXjhazD3ByL7lSNyw0Lsee8apRz9Q4KFu99AbXXTQjI3NI2y6cnDc8KSGCyzE2N28RApuxzjfe9RY7Kg19HSFnzPEwR/e67H8IL0rBUYpxiGE4QffCSwUbGnECT5oDLXVoSFcZEPprmwuqVGoGtUSqutw6VhC5bWYIC6Ap3CFHRG7G5PMsvuL6A34En50asY7wiqf9nHCAPgftny5pW/RNaYeOOdbNl3daO6n8nBS3awUB59rm/y/ogw7G8Q= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(3023799003)(11063799006)(18002099003)(22082099003)(56012099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YT3awyR/DI7i4voiwFFDi3/JOY/GVFvwiHyKTCHXFppbDh52RGJ4NZesIjgpplo5JUR0qItD9af/+VVBgZHxhzAjvTxIOf2+HjFsK2BiRdPYfMDlHtTCXtPT0zIGeSnyikypmaBswF4+01ewTTZVi0O6FBalB0CyZe/VdHqbtKo+m/UK4/mLlKn10qoddyNKXscxku2YyXECrBZJgzLvseimxhm4oHHQBLFKYHxk4rW6wffiWEHuhhRBNuiyznGzOpJbDO3W7mfDhpVb3LOrqaNTo3in7MqiJCSqWZ2eQXQ+b93s8V970G+f/00M4jHW4wn6brisb6uQqrdtMf5FCFMVd198Q/WvaFcE5pefxLEfqpVcbuWT2okzC5aq4MvmUiI9Rg4J9VXcbbRrrAXriC2iB4eKqG92mfn/1zNn1SBoDxD7DaShcIT7tuhbNi16 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:26.0223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acf5f563-f6f7-4822-3334-08deb592e604 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9747 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187221683158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes control and status registers in the CMDQ-V Config page (offset [0x0, 0x10000)) used to configure virtual command queue allocation and interrupt behavior. Add read/write emulation for the CMDQ-V Config region ([CMDQV_BASE, CMDQV_CMDQ_BASE]), backed by a simple register cache. This includes CONFIG, PARAM, STATUS, VI error and interrupt maps, CMDQ allocation map and the VINTF0 related registers defined in the CMDQ-V Config space. Only VINTF0 is supported; VINTF1-63 are not. Dispatch writes on access size: Introduced writel_mmio for 4-byte and writell_mmio for 8-byte. Reads need no split as the MMIO framework masks the returned value to the access size. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/tegra241-cmdqv.h | 110 +++++++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 188 +++++++++++++++++++++++++++++++++++++++- hw/arm/trace-events | 4 + 3 files changed, 298 insertions(+), 4 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 54854421f2..ace327443a 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,10 +10,15 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#include "hw/core/registerfields.h" + #define CMDQV_VER 1 #define CMDQV_NUM_CMDQ_LOG2 1 #define CMDQV_NUM_SID_PER_VI_LOG2 4 =20 +#define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2) +#define TEGRA241_CMDQV_MAX_NUM_SID (1U << CMDQV_NUM_SID_PER_VI_LOG2) + /* * Tegra241 CMDQV MMIO layout (64KB pages) * @@ -31,8 +36,113 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + + /* CMDQ-V Config page register cache */ + uint32_t config; + uint32_t param; + uint32_t status; + uint32_t vi_err_map[2]; + uint32_t vi_int_mask[2]; + uint32_t cmdq_err_map[4]; + uint32_t cmdq_alloc_map[TEGRA241_CMDQV_MAX_CMDQ]; + + /* VINTF0 register cache (within CMDQ-V Config page) */ + uint32_t vintf_config; + uint32_t vintf_status; + uint32_t vintf_sid_match[TEGRA241_CMDQV_MAX_NUM_SID]; + uint32_t vintf_sid_replace[TEGRA241_CMDQV_MAX_NUM_SID]; + uint32_t vintf_cmdq_err_map[4]; } Tegra241CMDQV; =20 +/* CMDQ-V Config page registers (offset 0x00000) */ +REG32(CONFIG, 0x0) +FIELD(CONFIG, CMDQV_EN, 0, 1) +FIELD(CONFIG, CMDQV_PER_CMD_OFFSET, 1, 3) +FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) +FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) +FIELD(CONFIG, CONS_DRAM_EN, 20, 1) + +REG32(PARAM, 0x4) +FIELD(PARAM, CMDQV_VER, 0, 4) +FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) +FIELD(PARAM, CMDQV_NUM_VI_LOG2, 8, 4) +FIELD(PARAM, CMDQV_NUM_SID_PER_VI_LOG2, 12, 4) + +REG32(STATUS, 0x8) +FIELD(STATUS, CMDQV_ENABLED, 0, 1) + +/* SMMU_CMDQV_VI_ERR_MAP_0/1 definitions */ +#define A_VI_ERR_MAP_0 0x14 +#define A_VI_ERR_MAP_1 0x18 +#define V_VI_ERR_MAP_NO_ERROR (0) +#define V_VI_ERR_MAP_ERROR (1) + +/* SMMU_CMDQV_VI_INT_MASK_0/1 definitions */ +#define A_VI_INT_MASK_0 0x1c +#define A_VI_INT_MASK_1 0x20 +#define V_VI_INT_MASK_NOT_MASKED (0) +#define V_VI_INT_MASK_MASKED (1) + +/* SMMU_CMDQV_CMDQ_ERR_MAP_0-3 definitions */ +#define A_CMDQ_ERR_MAP_0 0x24 +#define A_CMDQ_ERR_MAP_1 0x28 +#define A_CMDQ_ERR_MAP_2 0x2c +#define A_CMDQ_ERR_MAP_3 0x30 + +/* + * CMDQ_ALLOC_MAP: one entry per physical VCMDQ. Hardware supports up to 1= 28 + * entries (CMDQV_NUM_CMDQ_LOG2=3D7), but QEMU only exposes + * TEGRA241_CMDQV_MAX_CMDQ (=3D2) VCMDQs per VM so only entries 0 and 1 are + * defined here. + */ +/* 2 identical register entries */ +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_(i) \ + REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \ + FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \ + FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \ + FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6) + +SMMU_CMDQV_CMDQ_ALLOC_MAP_(0) +SMMU_CMDQV_CMDQ_ALLOC_MAP_(1) + +/* SMMU_CMDQV_VINTF0 registers (only VINTF0 is exposed to the guest) */ +REG32(VINTF0_CONFIG, 0x1000) +FIELD(VINTF0_CONFIG, ENABLE, 0, 1) +FIELD(VINTF0_CONFIG, VMID, 1, 16) +FIELD(VINTF0_CONFIG, HYP_OWN, 17, 1) + +REG32(VINTF0_STATUS, 0x1004) +FIELD(VINTF0_STATUS, ENABLE_OK, 0, 1) +FIELD(VINTF0_STATUS, STATUS, 1, 3) +FIELD(VINTF0_STATUS, VI_NUM_LVCMDQ, 16, 8) + +#define V_VINTF_STATUS_NO_ERROR (0 << 1) +#define V_VINTF_STATUS_VCMDQ_ERROR (1 << 1) + +/* + * SMMU_CMDQV_VINTF0_SID_MATCH/_REPLACE: 16 entries per VINTF + * (CMDQV_NUM_SID_PER_VI_LOG2=3D4). Only _0 and _15 are defined, + * used as switch case range bounds. + */ +REG32(VINTF0_SID_MATCH_0, 0x1040) +FIELD(VINTF0_SID_MATCH_0, ENABLE, 0, 1) +FIELD(VINTF0_SID_MATCH_0, VIRT_SID, 1, 20) +#define A_VINTF0_SID_MATCH_15 (A_VINTF0_SID_MATCH_0 + 15 * 4) + +REG32(VINTF0_SID_REPLACE_0, 0x1080) +FIELD(VINTF0_SID_REPLACE_0, PHYS_SID, 0, 20) +#define A_VINTF0_SID_REPLACE_15 (A_VINTF0_SID_REPLACE_0 + 15 * 4) + +/* + * SMMU_CMDQV_VINTF0_LVCMDQ_ERR_MAP: 4 registers per VINTF covering 32 log= ical + * VCMDQs each. With TEGRA241_CMDQV_MAX_CMDQ=3D2, only MAP_0 bits [1:0] ca= rry + * error state. MAP_1..MAP_3 always read as 0. Only _0 and _3 are defined, + * used as switch case range bounds. + */ +REG32(VINTF0_LVCMDQ_ERR_MAP_0, 0x10c0) +FIELD(VINTF0_LVCMDQ_ERR_MAP_0, LVCMDQ_ERR_MAP, 0, 32) +#define A_VINTF0_LVCMDQ_ERR_MAP_3 (A_VINTF0_LVCMDQ_ERR_MAP_0 + 3 * 4) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 6a6cfc2f71..813b9a61ce 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,20 +8,200 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" =20 #include "hw/arm/smmuv3.h" #include "hw/arm/smmuv3-common.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" +#include "trace.h" =20 -static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset, unsi= gned size) +static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, + hwaddr offset) { - return 0; + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + return cmdqv->vintf_config; + case A_VINTF0_STATUS: + return cmdqv->vintf_status; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + return cmdqv->vintf_sid_match[i]; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + return cmdqv->vintf_sid_replace[i]; + case A_VINTF0_LVCMDQ_ERR_MAP_0 ... A_VINTF0_LVCMDQ_ERR_MAP_3: + i =3D (offset - A_VINTF0_LVCMDQ_ERR_MAP_0) / 4; + return cmdqv->vintf_cmdq_err_map[i]; + default: + /* + * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) a= re + * filter config and filter data registers. They are not required = for + * normal VINTF operation and are not emulated. + */ + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + return 0; + } +} + +static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, + hwaddr offset, uint64_t valu= e) +{ + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + /* + * Mask out HYP_OWN on guest writes. This bit selects Hypervisor (= 1) vs + * Guest (0) ownership of the CMDQ. Force it to 0 so the VINTF alw= ays + * remains guest-owned. + */ + value &=3D ~R_VINTF0_CONFIG_HYP_OWN_MASK; + + cmdqv->vintf_config =3D value; + if (value & R_VINTF0_CONFIG_ENABLE_MASK) { + cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + } else { + cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; + } + break; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + cmdqv->vintf_sid_match[i] =3D value; + break; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + cmdqv->vintf_sid_replace[i] =3D value; + break; + default: + /* + * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) a= re + * filter config and filter data registers. They are not required = for + * normal VINTF operation and are not emulated. + */ + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + return; + } } =20 -static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, uint64_= t value, - unsigned size) +static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset, + unsigned size) { + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + uint64_t val =3D 0; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x%x)\n", __func= __, + offset, TEGRA241_CMDQV_IO_LEN); + goto out; + } + + switch (offset) { + case A_CONFIG: + val =3D cmdqv->config; + break; + case A_PARAM: + val =3D cmdqv->param; + break; + case A_STATUS: + val =3D cmdqv->status; + break; + case A_VI_ERR_MAP_0 ... A_VI_ERR_MAP_1: + val =3D cmdqv->vi_err_map[(offset - A_VI_ERR_MAP_0) / 4]; + break; + case A_VI_INT_MASK_0 ... A_VI_INT_MASK_1: + val =3D cmdqv->vi_int_mask[(offset - A_VI_INT_MASK_0) / 4]; + break; + case A_CMDQ_ERR_MAP_0 ... A_CMDQ_ERR_MAP_3: + val =3D cmdqv->cmdq_err_map[(offset - A_CMDQ_ERR_MAP_0) / 4]; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + val =3D cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4]; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + val =3D tegra241_cmdqv_config_vintf_read(cmdqv, offset); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + } + +out: + trace_tegra241_cmdqv_read_mmio(offset, val, size); + return val; +} + +/* 4-byte MMIO write handler. */ +static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *cmdqv, hwaddr offset, + uint32_t value) +{ + switch (offset) { + case A_CONFIG: + cmdqv->config =3D value; + if (value & R_CONFIG_CMDQV_EN_MASK) { + cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; + } else { + cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; + } + break; + case A_VI_INT_MASK_0 ... A_VI_INT_MASK_1: + cmdqv->vi_int_mask[(offset - A_VI_INT_MASK_0) / 4] =3D value; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + } +} + +/* + * 8-byte MMIO write handler. + */ +static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV *cmdqv, hwaddr offse= t, + uint64_t value) +{ + qemu_log_mask(LOG_UNIMP, + "%s unhandled 64-bit write at 0x%" PRIx64 " (WI)\n", + __func__, offset); +} + +static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x%x)\n", __func= __, + offset, TEGRA241_CMDQV_IO_LEN); + goto out; + } + + switch (size) { + case 4: + tegra241_cmdqv_writel_mmio(cmdqv, offset, value); + break; + case 8: + tegra241_cmdqv_writell_mmio(cmdqv, offset, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s bad write size %u at 0x%" PRIx64 "\n", + __func__, size, offset); + } + +out: + trace_tegra241_cmdqv_write_mmio(offset, value, size); } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3457536fb0..8c61d66a26 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -72,6 +72,10 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devi= d) "devfn=3D0x%x (idev dev smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 +# tegra241-cmdqv +tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187344202513.9905311968417; Tue, 19 May 2026 03:42:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrQ-0000Nw-Cf; Tue, 19 May 2026 06:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrO-0000Gc-6m; Tue, 19 May 2026 06:39:38 -0400 Received: from mail-westcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c112::7] helo=CY3PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrL-0006UI-G9; Tue, 19 May 2026 06:39:37 -0400 Received: from BL1PR13CA0232.namprd13.prod.outlook.com (2603:10b6:208:2bf::27) by LV5PR12MB9778.namprd12.prod.outlook.com (2603:10b6:408:300::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.24; Tue, 19 May 2026 10:39:31 +0000 Received: from BL02EPF0001A107.namprd05.prod.outlook.com (2603:10b6:208:2bf:cafe::26) by BL1PR13CA0232.outlook.office365.com (2603:10b6:208:2bf::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:31 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A107.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:30 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:15 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:11 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=TI9hhkkNGR8DxW0dC/vnKncXgbOppAa4fOiyTfgvsGUeMRnOIT2gD46mQ93zxKttcDraQxthRRxbBq/m0ytZDX9ORcAa5imflRWy2YrC/oVE3flbtGWr7U4OFN+x8NR4XQvMWlQ8VzG5ZkzdvNE2+VugOtZwf9iWmPNsBcimSGSKa7Bbjskf0d7jJ9QLvwEIU/Sz1TNhrDvf9uwyZGsHqQ9s1JUboksqIhQA1dOf2LAQFS5PoNxK0WrjI9sqBE+aGr+oLQABW1724lV6FvSOTN99HaobbSVspkFwZPVnL63ikXeUKnfRuuCxGWeZJ07nIeCT64Nr0EcmlW3poOspsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=h+c1bRcNIojrQHkQqgm6dO9/tMFDCirHUjw24Cng/Ng=; b=EuPiMS/rt5jSabKtEDTBG4GnAnVLn9bVh7628NcZRBBrTyPuaQ7SaDK8KN/gUImqRHUnJGaFeEuoGFw1rFqYA1RnGxTookvo3uxNTVc1TMCW1VHhKJ7x1+u632YBCewfJ2uJRDvQE5ev16jvpEf1c6PXCtGHNCsjda/mgFct+nnS8VTdNEXMxcbgHFewbb3oxB+WoKDTCovKxhnNc+fRpnF3G6di1K+TgmXj3wxYGfwTkZzkVfTys9YaDCgjbkqUAaGVQAM4M+X6Gqif73yQp7xgg2rD0bbQcoFvdz7lABcitW5djUsFDMU1+opdgDDXh5L6dde/FLtwwWHbgY8QYw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h+c1bRcNIojrQHkQqgm6dO9/tMFDCirHUjw24Cng/Ng=; b=afVaR1Ur3g3r0d8QKBB7cnTUawLZHw48LUIEaoHFLJnjd9I0z2qB00jjxkfGzZnppSgYXDhgFT+dcNBQPU4eaeCyam5u6chhAiZv5rwECBV9yF1OaocRlJl/GbVFNw6qJakTQEps5kPu2V/CaE8+ecxXdMNZ2ezyGE76UwmeIFz+pXSlVYl5tBSHYxcpBOc5+zxk211kTYeaD6bjWkBEV3zch06eobMM27DtZZ3M/LRx/vB39tIOj5eU4ADKDmNwfoqnG+AXKqYT4Qrf6NXIKnf4SnInvD6G9C0yhDRroOCDrZd/viDcMwb3fLWOGWoY5aKjUlAygFwfExCpS9cluw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 15/32] hw/arm/tegra241-cmdqv: Emulate VCMDQ register reads Date: Tue, 19 May 2026 11:36:53 +0100 Message-ID: <20260519103727.899332-16-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|LV5PR12MB9778:EE_ X-MS-Office365-Filtering-Correlation-Id: fce1bfd0-c9e5-4240-93dc-08deb592e8fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700016|376014|3023799003|18002099003|22082099003|56012099003|11063799006; X-Microsoft-Antispam-Message-Info: LOJVvH8DgnLw7nTwuTNbYjBrCRklzPEs169wepCfxVnkneEIoXPmBx4ZpVTTB2+7oYUVV0bBDSsHmqmn1MmxT9h01UyXTYO2KGT6yooSpovfiri4id+91D4wu4uC2xZ1O7akdEyMYA3z1FvaLZmuJ/1Y8YJ5Y82mPYd03EHe2UZVYGmOAfpxL0Dy2jUI+/esjjVkS6VvkGxTEzj3jxJInd13PnDht5mmv2ZZLiOBmEZ+2WIXLdAplhfzEQf1jGQSYll3cGTHU8v8rb11kvwdK97421qgwKKSGD/RxBrjt9kFOnYR9ThrqEnqip91XcrShDpCK9iB5UaMhXiVSJ/O4YPq4cqHA/HH05RoPJgYkVWoAN7H54I70hwHIzChn2LwWehipPvt21ihxnXhzj0/tMxUWgQ5egxGV5r+UVRJhbw0/eRirLpKODMLR/MZoQngyGoDpzxaNQGA6Jp1AfC2PcUYUMwfDgD0UT+RTcwKCJe2qcWjEbYjXjimCA9eVgAPjrYaXnDx09k3IGFTPV9KeciE1n0CoH5Jf4Zqj+nUJDU/5mbMaV+iDUDmauT9CxUu7VL1xp7B7sxrO905OsO3mSKLu3EB9fbUU4dqOe2ply/n19vPWMeRBNnabP6KamcxI8CtqukUVzrxdhKz9evM1G9j+fGpQwrL790+7CglRZ4vpEDGhY48HZ3TeemUtFd3a+tNueDrFCSyfpx1asnWLBKY/4VmcIGhI/ZxT7eyHVA= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(3023799003)(18002099003)(22082099003)(56012099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eqDIieuisWUy7mGNMDwrYv/K57cK1jjEE1SWhW9NtEWMxDEOyaIOdkrOSFA1/fDYetp87BJA7X6rsTAqma1Afj2sUYvaX8rYhEMPipbL0U1XPao39IiBSuQn9JfCg8jdn3bbt2uisWHaB6yfLlYnK2rRQNP+kas/JMTg/8WGdzpI5m4dO8dVlNZtIAuEVY9e/nFEtF76X0zTG2HzfIqXKdE6k3oV3XRCQ5Xb4xg45Ft3BOMG+/NCPCnnTIs3E8x50d3cPWwkahn9+SxZ7qltRZhbZYVM+/mki6AidOKJUcsM9Aejt0MzVIMEIXoCNHvTsb/p1Wv04Gz+GdO+Q/0WIaeqjfEBupejL3zGu5pmmxvM55X0e44xmL6mBiGmcchIjEPD6qGvZn48Kpx3HPERUxO3aB7ZaXie4ClIQrQdoiazOfjjjKdMADX/bWIxo+Pr X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:30.9985 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fce1bfd0-c9e5-4240-93dc-08deb592e8fc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9778 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=skolothumtho@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187346776154100 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes per-VCMDQ register windows through two MMIO apertures: Direct VCMDQ aperture (0x10000/0x20000): VCMDQ Page0/Page1 VINTF logical aperture (0x30000/0x40000): VINTF0 LVCMDQ Page0/Page1 Both apertures are hardware aliases of the same underlying registers: Page 0 (control/status): CONS_INDX, PROD_INDX, CONFIG, STATUS, GERROR, GERRORN Page 1 (base/DRAM): BASE_L/H, CONS_INDX_BASE_DRAM_L/H The direct aperture Page 0 is programmable at any time so long as CMDQV_EN is enabled. The VINTF (logical) aperture Page 0 is programmable only once SW has mapped a VCMDQ to a VINTF; the "logical" view is local to that VINTF. Add read emulation for both apertures, backed by a single per-VCMDQ register cache. VINTF aperture reads are translated to their equivalent direct-aperture offset and served from the same cached state. Once IOMMU_HW_QUEUE_ALLOC and viommu_mmap are wired up in a subsequent patch, Page 0 reads will be served directly from the hardware-backed mmap'd page instead of the cache. Page 1 is also a hardware alias, but the kernel only exposes mmap for Page 0, so Page 1 reads always trap to QEMU and are served from cache. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/tegra241-cmdqv.h | 215 ++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 95 ++++++++++++++++++ hw/arm/trace-events | 2 + 3 files changed, 312 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index ace327443a..6b21a407af 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -30,6 +30,13 @@ */ #define TEGRA241_CMDQV_IO_LEN 0x50000 =20 +/* CMDQV MMIO aperture bases and VCMDQ stride */ +#define CMDQV_VCMDQ_PAGE0_BASE 0x10000 /* CMDQV_CMDQ_BASE */ +#define CMDQV_VCMDQ_PAGE1_BASE 0x20000 +#define CMDQV_VINTF_PAGE0_BASE 0x30000 /* CMDQV_VI_CMDQ_BASE */ +#define CMDQV_VINTF_PAGE1_BASE 0x40000 +#define CMDQV_VCMDQ_STRIDE 0x80 + typedef struct Tegra241CMDQV { struct iommu_viommu_tegra241_cmdqv cmdqv_data; SMMUv3AccelState *s_accel; @@ -52,6 +59,19 @@ typedef struct Tegra241CMDQV { uint32_t vintf_sid_match[TEGRA241_CMDQV_MAX_NUM_SID]; uint32_t vintf_sid_replace[TEGRA241_CMDQV_MAX_NUM_SID]; uint32_t vintf_cmdq_err_map[4]; + /* + * VCMDQ register cache. The direct (VCMDQ aperture) and logical + * (VINTF aperture) views are hardware aliases; both are served from + * this single cached copy. + */ + uint32_t vcmdq_cons_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_prod_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_config[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_status[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerror[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerrorn[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_base[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_cons_indx_base[TEGRA241_CMDQV_MAX_CMDQ]; } Tegra241CMDQV; =20 /* CMDQ-V Config page registers (offset 0x00000) */ @@ -143,6 +163,201 @@ REG32(VINTF0_LVCMDQ_ERR_MAP_0, 0x10c0) FIELD(VINTF0_LVCMDQ_ERR_MAP_0, LVCMDQ_ERR_MAP, 0, 32) #define A_VINTF0_LVCMDQ_ERR_MAP_3 (A_VINTF0_LVCMDQ_ERR_MAP_0 + 3 * 4) =20 +/* + * VCMDQ Page 0 register window @ CMDQV_VCMDQ_PAGE0_BASE. + * Direct VCMDQ aperture; control and status registers. + */ +#define SMMU_CMDQV_VCMDQi_CONS_INDX_(i) \ + REG32(VCMDQ##i##_CONS_INDX, \ + CMDQV_VCMDQ_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +SMMU_CMDQV_VCMDQi_CONS_INDX_(0) +SMMU_CMDQV_VCMDQi_CONS_INDX_(1) + +#define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4 + +#define SMMU_CMDQV_VCMDQi_PROD_INDX_(i) \ + REG32(VCMDQ##i##_PROD_INDX, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20) + +SMMU_CMDQV_VCMDQi_PROD_INDX_(0) +SMMU_CMDQV_VCMDQi_PROD_INDX_(1) + +#define SMMU_CMDQV_VCMDQi_CONFIG_(i) \ + REG32(VCMDQ##i##_CONFIG, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +SMMU_CMDQV_VCMDQi_CONFIG_(0) +SMMU_CMDQV_VCMDQi_CONFIG_(1) + +#define SMMU_CMDQV_VCMDQi_STATUS_(i) \ + REG32(VCMDQ##i##_STATUS, \ + CMDQV_VCMDQ_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +SMMU_CMDQV_VCMDQi_STATUS_(0) +SMMU_CMDQV_VCMDQi_STATUS_(1) + +#define SMMU_CMDQV_VCMDQi_GERROR_(i) \ + REG32(VCMDQ##i##_GERROR, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +SMMU_CMDQV_VCMDQi_GERROR_(0) +SMMU_CMDQV_VCMDQi_GERROR_(1) + +#define SMMU_CMDQV_VCMDQi_GERRORN_(i) \ + REG32(VCMDQ##i##_GERRORN, \ + CMDQV_VCMDQ_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +SMMU_CMDQV_VCMDQi_GERRORN_(0) +SMMU_CMDQV_VCMDQi_GERRORN_(1) + +/* + * VCMDQ Page 1 register window @ CMDQV_VCMDQ_PAGE1_BASE. + * Direct VCMDQ aperture; base and DRAM address registers. + */ +#define SMMU_CMDQV_VCMDQi_BASE_L_(i) = \ + REG32(VCMDQ##i##_BASE_L, CMDQV_VCMDQ_PAGE1_BASE + i * CMDQV_VCMDQ_STRI= DE) \ + FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) = \ + FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27) + +SMMU_CMDQV_VCMDQi_BASE_L_(0) +SMMU_CMDQV_VCMDQi_BASE_L_(1) + +#define SMMU_CMDQV_VCMDQi_BASE_H_(i) \ + REG32(VCMDQ##i##_BASE_H, \ + CMDQV_VCMDQ_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16) + +SMMU_CMDQV_VCMDQi_BASE_H_(0) +SMMU_CMDQV_VCMDQi_BASE_H_(1) + +#define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \ + CMDQV_VCMDQ_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(0) +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) + +#define SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \ + CMDQV_VCMDQ_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(0) +SMMU_CMDQV_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) + +/* + * VINTF0 LVCMDQ Page 0 register window @ CMDQV_VINTF_PAGE0_BASE. + * Logical VCMDQ aperture (VCMDQs mapped via VINTF); control and + * status registers. Hardware alias of VCMDQ Page 0 above. + */ +#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX, \ + CMDQV_VINTF_PAGE0_BASE + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(0) +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_(1) + +#define SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(i) \ + REG32(VI_VCMDQ##i##_PROD_INDX, \ + CMDQV_VINTF_PAGE0_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20) + +SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(0) +SMMU_CMDQV_VI_VCMDQi_PROD_INDX_(1) + +#define SMMU_CMDQV_VI_VCMDQi_CONFIG_(i) \ + REG32(VI_VCMDQ##i##_CONFIG, \ + CMDQV_VINTF_PAGE0_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +SMMU_CMDQV_VI_VCMDQi_CONFIG_(0) +SMMU_CMDQV_VI_VCMDQi_CONFIG_(1) + +#define SMMU_CMDQV_VI_VCMDQi_STATUS_(i) \ + REG32(VI_VCMDQ##i##_STATUS, \ + CMDQV_VINTF_PAGE0_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +SMMU_CMDQV_VI_VCMDQi_STATUS_(0) +SMMU_CMDQV_VI_VCMDQi_STATUS_(1) + +#define SMMU_CMDQV_VI_VCMDQi_GERROR_(i) \ + REG32(VI_VCMDQ##i##_GERROR, \ + CMDQV_VINTF_PAGE0_BASE + 0x10 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +SMMU_CMDQV_VI_VCMDQi_GERROR_(0) +SMMU_CMDQV_VI_VCMDQi_GERROR_(1) + +#define SMMU_CMDQV_VI_VCMDQi_GERRORN_(i) \ + REG32(VI_VCMDQ##i##_GERRORN, \ + CMDQV_VINTF_PAGE0_BASE + 0x14 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +SMMU_CMDQV_VI_VCMDQi_GERRORN_(0) +SMMU_CMDQV_VI_VCMDQi_GERRORN_(1) + +/* + * VINTF0 LVCMDQ Page 1 register window @ CMDQV_VINTF_PAGE1_BASE. + * Logical VCMDQ aperture (VCMDQs mapped via VINTF); base and DRAM + * address registers. Hardware alias of VCMDQ Page 1 above. + */ +#define SMMU_CMDQV_VI_VCMDQi_BASE_L_(i) \ + REG32(VI_VCMDQ##i##_BASE_L, \ + CMDQV_VINTF_PAGE1_BASE + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27) + +SMMU_CMDQV_VI_VCMDQi_BASE_L_(0) +SMMU_CMDQV_VI_VCMDQi_BASE_L_(1) + +#define SMMU_CMDQV_VI_VCMDQi_BASE_H_(i) \ + REG32(VI_VCMDQ##i##_BASE_H, \ + CMDQV_VINTF_PAGE1_BASE + 0x4 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16) + +SMMU_CMDQV_VI_VCMDQi_BASE_H_(0) +SMMU_CMDQV_VI_VCMDQi_BASE_H_(1) + +#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, \ + CMDQV_VINTF_PAGE1_BASE + 0x8 + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(0) +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) + +#define SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, \ + CMDQV_VINTF_PAGE1_BASE + 0xc + i * CMDQV_VCMDQ_STRIDE) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(0) +SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 813b9a61ce..f859126ad6 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -16,6 +16,75 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +/* + * Read a VCMDQ Page 0 register (control/status) using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + */ +static uint64_t tegra241_cmdqv_read_vcmdq_page0(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index) +{ + uint64_t val =3D 0; + + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + val =3D cmdqv->vcmdq_cons_indx[index]; + break; + case A_VCMDQ0_PROD_INDX: + val =3D cmdqv->vcmdq_prod_indx[index]; + break; + case A_VCMDQ0_CONFIG: + val =3D cmdqv->vcmdq_config[index]; + break; + case A_VCMDQ0_STATUS: + val =3D cmdqv->vcmdq_status[index]; + break; + case A_VCMDQ0_GERROR: + val =3D cmdqv->vcmdq_gerror[index]; + break; + case A_VCMDQ0_GERRORN: + val =3D cmdqv->vcmdq_gerrorn[index]; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled read access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_read_vcmdq_page0(index, offset0, val); + return val; +} + +/* + * Read a VCMDQ Page 1 register (base / DRAM address) using VCMDQ0_* offse= ts. + */ +static uint64_t tegra241_cmdqv_read_vcmdq_page1(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index) +{ + uint64_t val =3D 0; + + switch (offset0) { + case A_VCMDQ0_BASE_L: + val =3D cmdqv->vcmdq_base[index]; + break; + case A_VCMDQ0_BASE_H: + val =3D cmdqv->vcmdq_base[index] >> 32; + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + val =3D cmdqv->vcmdq_cons_indx_base[index]; + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + val =3D cmdqv->vcmdq_cons_indx_base[index] >> 32; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled read access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_read_vcmdq_page1(index, offset0, val); + return val; +} + static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, hwaddr offset) { @@ -93,6 +162,7 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque, h= waddr offset, { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; uint64_t val =3D 0; + int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { qemu_log_mask(LOG_UNIMP, @@ -126,6 +196,31 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque,= hwaddr offset, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: val =3D tegra241_cmdqv_config_vintf_read(cmdqv, offset); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* + * VINTF Page0 registers are hardware aliases of VCMDQ Page0 regis= ters. + * Translate the VINTF aperture offset to its VCMDQ Page0 equivale= nt + * and fall through to the Page0 dispatch below. + */ + offset -=3D CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + /* + * Decode a per-VCMDQ Page 0 access. Each VCMDQ occupies a + * CMDQV_VCMDQ_STRIDE-byte window; extract the index and normalize + * to the VCMDQ0_* offset before calling the Page 0 helper. + */ + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq_page0(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index); + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above. */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq_page1(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index); default: qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", __func__, offset); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 8c61d66a26..8c34a04b24 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -75,6 +75,8 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS # tegra241-cmdqv tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_read_vcmdq_page0(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page0 offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_read_vcmdq_page1(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page1 offset0: 0x%"PRIx64" val: 0x%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187230809720.6783389553625; Tue, 19 May 2026 03:40:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHrh-0000xx-7J; Tue, 19 May 2026 06:39:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrZ-0000sE-5R; Tue, 19 May 2026 06:39:49 -0400 Received: from mail-westus3azlp170100009.outbound.protection.outlook.com ([2a01:111:f403:c107::9] helo=PH7PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrW-0006VV-QJ; Tue, 19 May 2026 06:39:48 -0400 Received: from BL1PR13CA0170.namprd13.prod.outlook.com (2603:10b6:208:2bd::25) by PH7PR12MB7017.namprd12.prod.outlook.com (2603:10b6:510:1b7::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Tue, 19 May 2026 10:39:36 +0000 Received: from BL02EPF0001A103.namprd05.prod.outlook.com (2603:10b6:208:2bd:cafe::45) by BL1PR13CA0170.outlook.office365.com (2603:10b6:208:2bd::25) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.15 via Frontend Transport; Tue, 19 May 2026 10:39:35 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A103.mail.protection.outlook.com (10.167.241.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:35 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:19 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:15 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DoZCwZew2GanEj32NmmtXAoUlYwzXrI6I7PqHXc783d0+hIUdpybQCzmfoTBQDn6Q87KcoGID87LW/IeUyAGofvQXfJ8EFEItX35KS6WiX563jAKkcxwVJeHMNVT1n/RSD9dMecDT9sIs4MKzChQtst5iJqreW9NxU21NOrsiV5duU6xMQxRL/ehkJ8rmFd2f/1SQdyme8cJSCp4gGBNkowb4ASgPFiQXk+eg33BCaAr11aoHT+m4wmGqtECHR7kipVK4HTNAaSdBUZQ9IbrDjipypn+XqU64Hq2ATQkavIOp5fMzXDeCkduLRrUjTxCgtxTTWwPVsEcIVDrxRp5fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fwdcdo9aVAUVCjZ9NEdw2HC9u+IoRqsxLjcTMtWkl74=; b=Lin9Gmk1hnLnY2dWxdnkXsa06oiMGmucTDYv3bN3fUdaXfAZyicyh5ATTfSOg10IWn0MZ5dpeS5Hvvw1ekxDkwvxRsZdOEg60Xq7Up0EWz8hpkpXx0tCxFOAFvVVFDyybJt6KaOSAh9399Jz5m472OVwaMgCvmhuP3UTxOz6KEZg2xnJmXobGFQTtCEKqAeau3KEOIvodx56ALlD6rwEnIiy4G8WDzTbNtStzn75BkI7Y/widZExAHCDIDvxcXUi3TNd+OuMRue+/afvjCKDyYxWuaB002xcdsZPiRv+id9vCQdIeSf7Qam6EsEuyvhZkTZS36rh90I+k3cgspLOCQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fwdcdo9aVAUVCjZ9NEdw2HC9u+IoRqsxLjcTMtWkl74=; b=KI+hMEk+1Pdco3octvipYRHE90yoZXTznXzX9QR98Pfsv86+cx17vJsR8gdZAeZpVf660isvo39EygrmEqFasIReTW9EQ3Dr/sqNzRjZqk8rLKhjACa/mRySCeU5DgL9Nbe0c0dClkc8bqcB/O7XqcIeHteWoqbIBKq+LmfG40gSdWcfJKaXzcadrZb10EX1jlmpywVDyVK/DMYGPtVDTVNvf99r++xNsk/u57QdWuEuLYU45LRBuoyD48ux46g+I4d8GfftqoOl4sfjwVv8tS9PQQEhnmQLerqlWQKRvsq2Z8t23xU1pE4vSGxYjzP+YwZo+smAh07yg/y2HDTouQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 16/32] hw/arm/tegra241-cmdqv: Emulate VCMDQ register writes Date: Tue, 19 May 2026 11:36:54 +0100 Message-ID: <20260519103727.899332-17-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|PH7PR12MB7017:EE_ X-MS-Office365-Filtering-Correlation-Id: 69b5ad91-49cb-431b-3ce0-08deb592ebd4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700016|376014|22082099003|11063799006|18002099003|56012099003|3023799003; X-Microsoft-Antispam-Message-Info: 2pIimYyymbPXf6iTVJjUFRhk8CPoVM0KY7OM0q0rIxPibiYjARO2oXjok9NJBfHzbUu91WTu/7eUA4nYdIyZ+Qw5/ub5E0wsQlf9+lVcVBCkDU+ZpfZNyYMbT8J9fOoA7jJ9ngn/sfCPTaDwfHs9ROVyvk8jZlEX0nkSeO8EPKOM6KCM86/UIdeI5lXHgphkE8vORXzyJuCHDSXgp/Kof9OIn5PV33I19FjsKzm77G64qqzgr0XHviWHVaJ8gd/TMRxiueUWJ5cLdLD+lf88yCp4CpReRLQ9GmWBbhdXdpyehcNV0fvJ5JOSqgabJkAIt10nYbi0bzrCAiX8jREyEHDVu6a2iQU1uHwthW9Qb6xOP2osBhEk9+CGY+CRokZtHxFFoHRMaXlF9MVG+bP9Q2Wfr9dcvBABpzmdpGCp0xq9h8vsE9rxNM0xkdNvCe+gwXNmxKY5J+ol+pSu3/IEA00/z76zoUvYOxtPMWd8x39JltPz+PBLAn/TQQQAyPQHsK73e5rqqF1sdpyfNUlufSLqr7Rb9MYAzx/WiJ2D3fSmxZW0deZj26quJcB6RwqwuA6NfYLhhyLrzhwXMqEFUT0a7+dhXxXdESvP6KEMdNMKer1oVuhEVth7QTsNbWEeYZyKoKnNCRhrdMcZQTzAkx+9YoHXomYzUDn3oaRH7vabFVy8cpUP1epDLQTcFbBiIjIvp62e4jyvI61g7mAhGKf1MYRLhCfQmVIUwD7xwVo= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(22082099003)(11063799006)(18002099003)(56012099003)(3023799003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XGwUbjl8DI+EOfhHNzzUxiwdXuF3X5SPg+8c6Zi0VOFws5NkoeQQxiI8hRqW4nxfIHIPBeT6BpgsFgsZlXweRvMO5YPIBhTqYBd1IpxLOaMWvyTwIyCS7MQS8cWXnRMnCfLjzaA4En2rGOtoq/6mnW2BYqVvbhFt/lpX49KgAJKPoTlrJMl5T8w4pyrBvnnDHO2A+X7gF/cc5Xg5WB/eAM5hJ2gNxOXQsVwpQEde6S0TQx7aPoBybl1Olkt6HscilaZZnqFYypY7hDlWIgXRBol/RuKkuYa+cGNE8/QZC7+s926wL1ebLOIgaJ7xagNUjbLadiIUro3BuSZLvGvDmVWIHT53f3z/P9+/eqVtXfuA46tndVmIwG/y4xMl3hoGuMLCh8nUWnRHUyWjMWI2pn2iVGsPm5jDJyXwYnHRzOhFmkHsE1kHbzIgFKrb/vse X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:35.7654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69b5ad91-49cb-431b-3ce0-08deb592ebd4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7017 Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=skolothumtho@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187231913158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen This is the write side counterpart of the VCMDQ read emulation. Add write handling for both the direct VCMDQ aperture and the VINTF logical aperture using the same index decoding and VINTF-to-VCMDQ translation logic as the read path. VINTF aperture writes are translated to their direct-aperture equivalent and update the same cached state. Page 1 registers (BASE, CONS_INDX_BASE) always update the cache. Once IOMMU_HW_QUEUE_ALLOC and viommu_mmap are wired up in a subsequent patch, Page 0 register writes will be forwarded to the hardware- backed mmap'd page. Ignore VCMDQ BASE writes if the VCMDQ is already enabled. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 164 +++++++++++++++++++++++++++++++++++++++- hw/arm/trace-events | 2 + 2 files changed, 164 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index f859126ad6..5d2d9d2e26 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -16,6 +16,16 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +/* + * Returns true if the per-VCMDQ CMDQ_EN_OK bit is set. + */ +static bool tegra241_vcmdq_enabled(Tegra241CMDQV *cmdqv, int index) +{ + uint32_t status =3D cmdqv->vcmdq_status[index]; + + return status & R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK; +} + /* * Read a VCMDQ Page 0 register (control/status) using VCMDQ0_* offsets. * @@ -116,6 +126,108 @@ static uint64_t tegra241_cmdqv_config_vintf_read(Tegr= a241CMDQV *cmdqv, } } =20 +/* + * Write a VCMDQ Page 0 register (control/status) using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * Page 0 registers are all 32-bit; this helper is only called for 4-byte + * writes. + */ +static void tegra241_cmdqv_write_vcmdq_page0(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + uint32_t value) +{ + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + cmdqv->vcmdq_cons_indx[index] =3D value; + break; + case A_VCMDQ0_PROD_INDX: + cmdqv->vcmdq_prod_indx[index] =3D value; + break; + case A_VCMDQ0_CONFIG: + if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) { + cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MAS= K; + } else { + cmdqv->vcmdq_status[index] &=3D ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MA= SK; + } + cmdqv->vcmdq_config[index] =3D value; + break; + case A_VCMDQ0_GERRORN: + cmdqv->vcmdq_gerrorn[index] =3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled write access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_write_vcmdq_page0(index, offset0, value); +} + +/* + * Write a VCMDQ Page 1 register (base / DRAM address) - 4-byte access. + */ +static void tegra241_cmdqv_write_vcmdq_page1(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + uint32_t value) +{ + switch (offset0) { + case A_VCMDQ0_BASE_L: + if (tegra241_vcmdq_enabled(cmdqv, index)) { + return; + } + cmdqv->vcmdq_base[index] =3D + deposit64(cmdqv->vcmdq_base[index], 0, 32, value); + break; + case A_VCMDQ0_BASE_H: + if (tegra241_vcmdq_enabled(cmdqv, index)) { + return; + } + cmdqv->vcmdq_base[index] =3D + deposit64(cmdqv->vcmdq_base[index], 32, 32, value); + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + cmdqv->vcmdq_cons_indx_base[index] =3D + deposit64(cmdqv->vcmdq_cons_indx_base[index], 0, 32, value); + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + cmdqv->vcmdq_cons_indx_base[index] =3D + deposit64(cmdqv->vcmdq_cons_indx_base[index], 32, 32, value); + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled write access at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_write_vcmdq_page1(index, offset0, value); +} + +/* + * Write a VCMDQ Page 1 register - 8-byte access at BASE_L or DRAM_L. + */ +static void tegra241_cmdqv_write_vcmdq_page1_64(Tegra241CMDQV *cmdqv, + hwaddr offset0, int index, + uint64_t value) +{ + switch (offset0) { + case A_VCMDQ0_BASE_L: + if (tegra241_vcmdq_enabled(cmdqv, index)) { + return; + } + cmdqv->vcmdq_base[index] =3D value; + break; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + cmdqv->vcmdq_cons_indx_base[index] =3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled 64-bit write at 0x%" PRIx64 "\n", + __func__, offset0); + } + trace_tegra241_cmdqv_write_vcmdq_page1(index, offset0, value); +} + static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, hwaddr offset, uint64_t valu= e) { @@ -235,6 +347,8 @@ out: static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *cmdqv, hwaddr offset, uint32_t value) { + int index; + switch (offset) { case A_CONFIG: cmdqv->config =3D value; @@ -253,6 +367,33 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *= cmdqv, hwaddr offset, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* + * VINTF Page0 registers are hardware aliases of VCMDQ Page0 regis= ters. + * Translate the VINTF aperture offset to its VCMDQ Page0 equivale= nt + * and fall through to the Page0 dispatch below. + */ + offset -=3D CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + /* + * Decode a per-VCMDQ Page 0 access. Each VCMDQ occupies a + * CMDQV_VCMDQ_STRIDE-byte window; extract the index and normalize + * to the VCMDQ0_* offset before calling the Page 0 helper. + */ + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page0(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value); + break; + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above. */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page1(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value); + break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); @@ -260,14 +401,33 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV = *cmdqv, hwaddr offset, } =20 /* - * 8-byte MMIO write handler. + * 8-byte MMIO write handler. Only Page 1 BASE / CONS_INDX_BASE_DRAM accept + * full 64-bit writes; other offsets are write-ignored. */ static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV *cmdqv, hwaddr offse= t, uint64_t value) { - qemu_log_mask(LOG_UNIMP, + int index; + + switch (offset) { + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* + * VINTF Page1 registers are hardware aliases of VCMDQ Page1 regis= ters. + * Translate the VINTF aperture offset to its VCMDQ Page1 equivale= nt + * and fall through to the Page1 dispatch below. + */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq_page1_64(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index, value); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled 64-bit write at 0x%" PRIx64 " (WI)\n", __func__, offset); + } } =20 static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 8c34a04b24..c4262bb2be 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -77,6 +77,8 @@ tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, u= nsigned size) "offset: tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_read_vcmdq_page0(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page0 offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_read_vcmdq_page1(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page1 offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_write_vcmdq_page0(int index, uint64_t offset0, uint64_t val= ) "vcmdq[%d] page0 offset0: 0x%"PRIx64" val: 0x%"PRIx64 +tegra241_cmdqv_write_vcmdq_page1(int index, uint64_t offset0, uint64_t val= ) "vcmdq[%d] page1 offset0: 0x%"PRIx64" val: 0x%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187336904515.7761245720601; Tue, 19 May 2026 03:42:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHs8-0001WW-Lz; Tue, 19 May 2026 06:40:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHra-0000wE-Ho; Tue, 19 May 2026 06:39:50 -0400 Received: from mail-eastusazlp17011000f.outbound.protection.outlook.com ([2a01:111:f403:c100::f] helo=BL2PR02CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrY-0006X8-GO; Tue, 19 May 2026 06:39:50 -0400 Received: from CYXP220CA0011.NAMP220.PROD.OUTLOOK.COM (2603:10b6:930:ee::14) by MN2PR12MB4453.namprd12.prod.outlook.com (2603:10b6:208:260::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.19; Tue, 19 May 2026 10:39:41 +0000 Received: from CY4PEPF0000EE35.namprd05.prod.outlook.com (2603:10b6:930:ee:cafe::3a) by CYXP220CA0011.outlook.office365.com (2603:10b6:930:ee::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:39:40 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE35.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:23 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:20 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WHEoMaPFoTsbtXOxqSg8a2CS/lSV8sy42xNtUe7yLiuM2AISCwXYfs1f+bQcMKsCdAEaCtuarFJK3fZ9b5aHJKCKZ4fS/rdfgtVOz510EWpa2n3tpNUu+zhfHPGfTgUUOIpKMtKXspPOjY+/mAW+5bkAp9LntafE7lB493KTa00uTxClRlZLdscxJKW9gjfc54y1ey1X4NglDJLG84OK8goufC2XjeRDBEAR8fSS0/W79Q9kUHk511LMEGwq8bf8btgk/6BbjJ79jm7g856XnC0uy4HtN3XoPw3DPfaBlJuf/Hrcj+9wXFut+TJ4JbTWSltT+83gwmE77Ywds2G3/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aKJ5F83CG6vTH5hm5T71otbSXOhpWgu4KbUTZ8vkB6U=; b=CiEABkrCrSBzYenk5VAAmCKWbSAdINq3GUHCTP2FB3wyu4mRM1OW0XbTNHDKCDjXbnRryIbIYsJcQVz0H75hQL83fVl19cahs/ZxMqbFX/8KmDOIyB3aHvxgxLu3oNb7hinym4bLlyZ1AqWtVDi+/QcgWMWZdihNvoIsl8tb9NvgDFs5N65E0BJ6RfbZdoNm+YMu3aZjUSXXwXuA4rKBDOPALAkzhmII6dJNx4naWZIwhPtPtwGecoDdM+fo/QrmrGUBYFAsE9JfueCcT3mxH6Ngs+H0uB8P4zvfkkrDw8swWnFdaF14pBQU9BAguB0GKSe5mfGlgkqf18M9k5mHhQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aKJ5F83CG6vTH5hm5T71otbSXOhpWgu4KbUTZ8vkB6U=; b=UiKBTJy+S+CnOIHlgc8jjIs4JGWgMm3l4gSvcAX7tRnw0G9K7OWfkf1HB0keDHWdBShbk4bVbw2btBt7gT/xkKcsFTJM5yORDGubepwfNPE7+jEyTpn+HXx7wDV695l62KfTlnLigYCO+78f8qD87xbvk8SVQeJ6+OBuV31GrUcXe+CqECUlTt2QG0qKWhL/ePEDVkDG0STVLsw80TImX4O13eRg+2Ewv5h0YQUUTklkiTEsdNxfzYKKu6b0CsSH5wk4NR5mM+vMuu2EFe0EwkdZrbMlDm4p09DVcB0AZG4HiWVYJubMHArsALDvnMV068oSfG1LBZ2fVXJNd2HWbg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 17/32] hw/arm/tegra241-cmdqv: mmap VINTF Page0 for CMDQV Date: Tue, 19 May 2026 11:36:55 +0100 Message-ID: <20260519103727.899332-18-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|MN2PR12MB4453:EE_ X-MS-Office365-Filtering-Correlation-Id: d24acd36-03d2-49c3-0226-08deb592eea7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|82310400026|1800799024|11063799006|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: yrcxn935+TjOUP6H1WiiifTVEEmJ4UQ3lDdeFRZ3HX8FVoicv9uHG0Rz7caTa318jJXSl8BdixfgJkbD6IigoPMfYtXN/0+WleDdYpdo9/Icl4t29khRmaZuztXp83sWL3cFLbS0zYhEJx6ikJsTEu2IJ/G62VvZDILIhrbbfGcz6wJJGR09DQVvUZIEalFv9e3yhuYDafZ8/s7SAHpqjVeDeEUE7RXrdcP1nC5Vkiacj8/M6Pu4KevRt6jVShADuQautNF2eMywvH6tXFGS//qc70cTXgrJvH2pckfKyu2PJWMppscTydXRCTkbkCs46E6UfCMzcX7rnknuz0r5xJ46CF9Ce+odoDf3jTNZjdvYpFttJe+jnNjiPjICGbbHbLyhciUl/seJhea+jLCTlc2mLQmTv++oSiCDxqOxYzeOABIVbtCzJpWZ49zLgCiGjTt1rB912KUHF55s9mnvgFs6OWYF2z+OU7nD/oACLnaNFT3WdIDv51OycOCoBQz6NrdUx5xqwFneFzId9LP5uKZ1wlXOGLMsT5EkH50UOKhl/3bToFx4+wwhwiA0+/rOURdDlWZ7fWfFr2ER1ajEjG2ABPyEZmLJSC3FlubZ3c20r/VmkdRsrZJqlnGHhYUvaxzSrMtGta+1g/wFdnWci2xfWi7B5Z5pmhmfjlxtGJPVaLTcRO8//D9P02kAfti9R76K8rPwBhOXffXrK+J2V2xN/1U1htBDXlDZ1Onob98= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(11063799006)(18002099003)(56012099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZubwBjjyjVfbbNNRbJA1Z08jpMhOtW4KTDy8nM4Io+cI+H4huXghKTHhfOP7E5Xh+4T2/wjZL/NKCV201DNVcRYUn+4bhiRtTFm3lqA6x2dsP7SNplwzoAQ8eE9x31ClfmtnWnyKzVtml2R1gublG8irrgMpNd8AVlXwquYhWDKKgEVg79r5PRX8++vJh3IjwHHBJVjL9iHaa2ltDu+nEqyYoGhGQKMjI5D6m8hC6dyGjA3abyCfOlsytGaIqdzQfK6ajWuexL8vFCkobKlOaJlKU7HtbumOufpgLbsqXub7Tv8Y4AOXp+m0XVk1Bz6CZiOBoW1qrCCbe7g+DcGCqjgVIsWB68jPhvn0favlo5/rmdi1pSv289FRVzCPpyRI4i4uMgJzy/Xfza6vNx51GtWGzF/2nq2EqzP1zDjZw6RgSvlR/2KK4dmLA1geb9uQ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:40.6037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d24acd36-03d2-49c3-0226-08deb592eea7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4453 Received-SPF: permerror client-ip=2a01:111:f403:c100::f; envelope-from=skolothumtho@nvidia.com; helo=BL2PR02CU003.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187338726154100 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The CMDQ-V CMDQ pages provide a VM wide view of all VCMDQs, while the VINTF pages expose a logical view local to a given VINTF. Although real hardware may support multiple VINTFs, the kernel currently exposes a single VINTF per VM. The kernel provides an mmap offset for the VINTF Page0 region during vIOMMU allocation. However, the logical-to-physical association between VCMDQs and a VINTF is only established after HW_QUEUE allocation. Prior to that, the mapped Page0 does not back any real VCMDQ state. When VINTF is enabled, mmap the kernel provided Page0 region and set ENABLE_OK only if the mmap succeeds. Unmap it when VINTF is disabled. This prepares the VINTF mapping in advance of subsequent patches that add VCMDQ allocation support. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 3 +++ hw/arm/tegra241-cmdqv.c | 50 ++++++++++++++++++++++++++++++++++++++--- 2 files changed, 50 insertions(+), 3 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 6b21a407af..f0b031b4dc 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -37,12 +37,15 @@ #define CMDQV_VINTF_PAGE1_BASE 0x40000 #define CMDQV_VCMDQ_STRIDE 0x80 =20 +#define VINTF_PAGE_SIZE 0x10000 + typedef struct Tegra241CMDQV { struct iommu_viommu_tegra241_cmdqv cmdqv_data; SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + void *vintf_page0; =20 /* CMDQ-V Config page register cache */ uint32_t config; diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 5d2d9d2e26..4d9f094b2a 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -9,6 +9,8 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" +#include "qapi/error.h" =20 #include "hw/arm/smmuv3.h" #include "hw/arm/smmuv3-common.h" @@ -228,8 +230,42 @@ static void tegra241_cmdqv_write_vcmdq_page1_64(Tegra2= 41CMDQV *cmdqv, trace_tegra241_cmdqv_write_vcmdq_page1(index, offset0, value); } =20 +static bool +tegra241_cmdqv_munmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **errp) +{ + if (!cmdqv->vintf_page0) { + return true; + } + + if (munmap(cmdqv->vintf_page0, VINTF_PAGE_SIZE) < 0) { + error_setg_errno(errp, errno, "Failed to unmap VINTF page0"); + return false; + } + cmdqv->vintf_page0 =3D NULL; + return true; +} + +static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **= errp) +{ + IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; + + if (cmdqv->vintf_page0) { + return true; + } + + if (!iommufd_backend_viommu_mmap(viommu->iommufd, viommu->viommu_id, + VINTF_PAGE_SIZE, + cmdqv->cmdqv_data.out_vintf_mmap_offs= et, + &cmdqv->vintf_page0, errp)) { + return false; + } + + return true; +} + static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, - hwaddr offset, uint64_t valu= e) + hwaddr offset, uint64_t valu= e, + Error **errp) { int i; =20 @@ -244,8 +280,11 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241= CMDQV *cmdqv, =20 cmdqv->vintf_config =3D value; if (value & R_VINTF0_CONFIG_ENABLE_MASK) { - cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + if (tegra241_cmdqv_mmap_vintf_page0(cmdqv, errp)) { + cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + } } else { + tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } break; @@ -347,6 +386,7 @@ out: static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *cmdqv, hwaddr offset, uint32_t value) { + Error *local_err =3D NULL; int index; =20 switch (offset) { @@ -365,7 +405,7 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *c= mdqv, hwaddr offset, cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; break; case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: - tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); + tegra241_cmdqv_config_vintf_write(cmdqv, offset, value, &local_err= ); break; case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: /* @@ -398,6 +438,10 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *= cmdqv, hwaddr offset, qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); } + + if (local_err) { + error_report_err(local_err); + } } =20 /* --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187303018761.2881875585823; Tue, 19 May 2026 03:41:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsA-0001mr-HF; Tue, 19 May 2026 06:40:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrd-0000yU-RK; Tue, 19 May 2026 06:39:55 -0400 Received: from mail-westus3azlp170120001.outbound.protection.outlook.com ([2a01:111:f403:c107::1] helo=PH8PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrb-0006Xl-I8; Tue, 19 May 2026 06:39:52 -0400 Received: from BL1P222CA0005.NAMP222.PROD.OUTLOOK.COM (2603:10b6:208:2c7::10) by DM4PR12MB7717.namprd12.prod.outlook.com (2603:10b6:8:103::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Tue, 19 May 2026 10:39:43 +0000 Received: from BL02EPF0001A101.namprd05.prod.outlook.com (2603:10b6:208:2c7:cafe::d0) by BL1P222CA0005.outlook.office365.com (2603:10b6:208:2c7::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.25.23 via Frontend Transport; Tue, 19 May 2026 10:39:42 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A101.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:42 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:27 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:24 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QcLaML0SuSTPr4z+7TOSFXb3IibRtQ/N3ZW+mFxGebxF7zVdGBD5a3S+X9AjAp0zxd9eTnQJSMXXKTZYuE7dXNG1g5fmVSGZfL1tXjHI4B1gyFIy3oDlsygL9RSrfBTG6y6xj6a5KfkeC4Vc2/pHo1IDExSACTZiHtNw0ys7j/hUkeskp2DjJkAaCov4wR7gu8SjOrhkk+muCMgtBObjpd3/gOZs2yiZmLE7oQ4qeYCevBdpikSmLxQIkVfU7eSL4eD/XgY/nY4DoU+/xcbJFAxQKwkIdm8HEjlOnTZrgMaoioLEGmIOnUnKnPQ3vnJzyrPXerdMl0BtJgd1E+WL8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1Va96SirhYRknJ1P+tBvn4cGX70lMspwMPqcIzl+VFQ=; b=Mhfw70ZDlq58I6Xt9R8vjvQjnKIhE9/tjuc6W8K0NZHe77JyHa75RpkRQdaWDqNYDgVXv5a9uEPdmwt+puofQyh7yTeOQbsR6E3wzjKYLSr2WKrtSyvRfbE0J1Q9fZIMl/Mu76xz0iDvIKyRYyze5DhZ/A+02a00bo9vEj5fX3NuuEzLoWL/HvBmdHL8UopQHniEaO1jC9VKNcx3nmyIyNmy6txrQVrJGfVo0WFAJVIkYfaPiJU2Pjo5l0eHTVSwKidwJws6Vbd4UVNNE+X+XZEikD1ojrvWWhut/0LkZj8oEuhyjqywxU50wMUX1XHvMn150wsfujCTMB2JstP87w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1Va96SirhYRknJ1P+tBvn4cGX70lMspwMPqcIzl+VFQ=; b=FBxjHi9OR5WgC0i/k7cJBZmgNtWjmzcBDm3JKIbDPn920yy9GxOrXTLcfImij4FB6OKjwe2T7X5P37yF5dzDaFQzXMYlGFjN4ggDUH1x6Co/1H5AXoJHbS+Y7HYlP+Chee5KshVyl3UeR+qeAqOLyf0qeTAqpbx5lPopP+tgvbwDj1yJEUqXi9IqKislnfB87XTRSIEMqcRL/d+dARl2COkGL/P+dHy7+R8ux9izSiK/eGYGqVqwxVybJZlRj3pFxza6wyTxsZCZOie3Sz4n3nbkuOJHzCMkrDWX2NR8oTQOtMT/VnnTyA/T1hThs5oOsaexyaoanfYaOEM77apKhQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 18/32] system/physmem: Add address_space_range_is_ram() helper Date: Tue, 19 May 2026 11:36:56 +0100 Message-ID: <20260519103727.899332-19-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A101:EE_|DM4PR12MB7717:EE_ X-MS-Office365-Filtering-Correlation-Id: 697e067b-6a4a-414e-2161-08deb592efed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700016|376014|82310400026|11063799006|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: ERH5Jp+udi77AN93bZdAVxY0U3mAACUR3iuyYEJJsniI5LWvlg5bv+WEywdi8yp0wJ6Qjt4yYqu22Qe4JmWBFrKNKyPqSWe2y6acZSHMoso4RwKSBM3Temgp2Dhvv63vhRhVqRBu3QdHW9ATyurCSaR2rJ3000GV3MqcJhC3JcH3fsgduYG06vi1KmPQPwR8mPCHFLRr3aYTjNmuKD5sKXvLaCWnTfyADhWBloKtVuCKv0M2+e+j8QNItsbrKoEbPaTW9FQ/6+sExRiwpSBsxsg/QgudjxultwWds+dXam0MpyDPNlFwCcl7BDQr7FlYkb+Os7f8x1RIU4ZnwTUa/09QJps8kD/Ig3yWtZVkmZ9b3z2YiOHm38zhRyOYSPqEkCAHRum6Xx9fJ9fvvqf8kgszOlyJrP6YQVHHs5t4XWUnLAnm1I4y/6IYX32rBugpCI4IQcUrcsc2z8E1DZqNVYlk4dScN63PIn7jqctVJY7DolcQgrVUgofq8W+Oy9PqWJaH8AldTB1O2j4U5WanmrmalA20h5CGvVuDNj8XK+da/6qsO45cbC+rTnQcdSwmWntRDfnnPwnjEQ65iB0eYq0vc4asUmFYQhn5SlbZ8RLzI2XPybmZSyB2vst9BKgmCIvz2jfalN1d2qUi7qfY4cGMY3U+mB+6j93C6SST+wtfRfkVJZ0A1nj4HEGh+UlLbnl12jz/yLQVoL072v9lazCvW8jVeMhxkbqmfTYYpeY= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(11063799006)(18002099003)(56012099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VQhOZmUd1aZUNN7LvZ8hnKjUEgY6BlWn8CZkFWvxZtKSUOUNCRBXn3E8yhoPcj6umxLdE9TSMMK+EU/h6aGrLAqzukqDf6bEtH6vIeKdpXg1sm/RxpyN0XwCu7sl7ZVe1rypP46p8Jl3lMO+Vj02pKccD/BKfEDmGOemn3qOZhQjgYpzNNYqa5Yw3hjYG4fUzRlAj1g6h2dNM6+ynHGEF1LzuS0CsdJjwcJH1FW64wwDZky8NXbZmHnihCHboDAq+En/jdHYXQUg3/F4z8EmX2TEF2n/VHJYpg9XbWF8SqUx7AdDI9CL7yo2M7C946asadpqF1DVxBY+fzNlZpPKYNZjLhANefxnGIFkcr5BOtSzgW8Fop86bq+nNMunNavco87ijI6+9+rvRb20uot2IIRYX7VKOQ2DHkYHAH1UY8OubLVDuHobUaBE6e4RDOKW X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:42.6487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 697e067b-6a4a-414e-2161-08deb592efed X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A101.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7717 Received-SPF: permerror client-ip=2a01:111:f403:c107::1; envelope-from=skolothumtho@nvidia.com; helo=PH8PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187304287158500 Content-Type: text/plain; charset="utf-8" Introduce address_space_range_is_ram(), a helper to determine whether a guest physical address range within an AddressSpace resolves entirely to RAM-backed MemoryRegions. The range is walked using address_space_translate() so contiguous RAM-only ranges return true even when they cross multiple MemoryRegion boundaries; any byte backed by non-RAM (MMIO, ROM device, hole) returns false. Signed-off-by: Shameer Kolothum --- include/system/memory.h | 13 +++++++++++++ system/physmem.c | 19 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/include/system/memory.h b/include/system/memory.h index 1417132f6d..af5f96f6ff 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -2841,6 +2841,19 @@ bool address_space_access_valid(AddressSpace *as, hw= addr addr, hwaddr len, */ bool address_space_is_io(AddressSpace *as, hwaddr addr); =20 +/** + * address_space_range_is_ram: check whether a guest physical address range + * within an address space resolves entirely t= o RAM. + * + * @as: #AddressSpace to be accessed + * @addr: address within that address space + * @size: number of bytes in the range starting at @addr + * + * Returns true if every byte in [@addr, @addr + @size) maps to a RAM + * MemoryRegion, false otherwise. + */ +bool address_space_range_is_ram(AddressSpace *as, hwaddr addr, hwaddr size= ); + /* address_space_map: map a physical memory region into a host virtual add= ress * * May map a subset of the requested range, given by and returned in @plen. diff --git a/system/physmem.c b/system/physmem.c index 7bcbf87573..46b36c7b10 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3668,6 +3668,25 @@ bool address_space_is_io(AddressSpace *as, hwaddr ad= dr) return !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); } =20 +bool address_space_range_is_ram(AddressSpace *as, hwaddr addr, hwaddr size) +{ + MemoryRegion *mr; + hwaddr xlat, l; + + RCU_READ_LOCK_GUARD(); + while (size > 0) { + l =3D size; + mr =3D address_space_translate(as, addr, &xlat, &l, false, + MEMTXATTRS_UNSPECIFIED); + if (!memory_region_is_ram(mr)) { + return false; + } + size -=3D l; + addr +=3D l; + } + return true; +} + static hwaddr flatview_extend_translation(FlatView *fv, hwaddr addr, hwaddr target_len, --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187284425278.18836271062787; Tue, 19 May 2026 03:41:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsN-00030M-Lv; Tue, 19 May 2026 06:40:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrn-0001BY-H0; Tue, 19 May 2026 06:40:12 -0400 Received: from mail-northcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c105::7] helo=CH4PR04CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrk-0006Ym-Ps; Tue, 19 May 2026 06:40:02 -0400 Received: from BLAPR05CA0013.namprd05.prod.outlook.com (2603:10b6:208:36e::28) by LV3PR12MB9144.namprd12.prod.outlook.com (2603:10b6:408:19d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Tue, 19 May 2026 10:39:47 +0000 Received: from BL02EPF0001A107.namprd05.prod.outlook.com (2603:10b6:208:36e:cafe::44) by BLAPR05CA0013.outlook.office365.com (2603:10b6:208:36e::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.15 via Frontend Transport; Tue, 19 May 2026 10:39:47 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A107.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:46 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:31 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:28 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LaOJDpqq3wO6KfYBtfa4nqccKj3C0I3AY4wmd8MhxK3cGA2B8prm8WKL+pwIuUM936RgCmqgUG2okoQIcuSE+XlBvYClpVdDzyTyVe47szfMRj7Tw3zFDZiof58Q6Ft8OwT5OzfaGsKzkmneJ8E8GFa2M+vYqjc1n4e9/r2nZBdKzh4l6I6DSACV2w2X5x0uVWXh0pK4SeIHEbaq78H9ulEmOx+eV3QU2Jh7RTme2UHp7q7x8ca6tYdepTjeIw86Yixe39PQjHlAsqjt9Ji7HHjvdAwRJEvmb6riTsd4KsdavxXMwisamo7AkDsqT0hJCYhkbrTtvK1yGRgr0zc8wQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=W2uMUnF1cRosH1w3Fn/DgzMuSdgaO+BRkRcabgUjd8U=; b=Ca9nUxXpPo3q7iZ90T7nCFr4Q7LW15+QGoKLGtBRtbCzTeKk6AvnRo7tFu6CyBTu5IdeQhWGj8MxuAvLKENqqHizfAa20h/lRaETSBSK7DefYCsejA+8pdn1uO1i6ubJo2FqHp9OReW7k1GGTDbLIFYmb9mAOz/Qv0IwyP9ZCc0r2WyKxtA70HvTm96sCn4zHcIvdM2XHBxSHKzin3lDkfn+r0QcWNUR7CTnpDI8+0ncC8vY3l1LFC+ahCQvz2fBx+tw7TRo3p1Dz33rAxK+R9I486uiqW0zcdVKJDkntUJdmw/I4XRceJMrH4Z3pYklEoo8X+yqiozz82qLom7Ang== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W2uMUnF1cRosH1w3Fn/DgzMuSdgaO+BRkRcabgUjd8U=; b=oXqkL/jZsj9q36l9L172pO+rMD2H6B6yGmOMwUitUPHxsBYtq03IOPnBP3OU4Ht/SCCfAVr93s/ccXq5zjFl5LY8xC0R+XxCPMM1T5Xv1wzw7u7pL/H+TFyiD5SRTxHUzaE4rRwCG1RNsHHFCOmsIFbkFJBVUDg1oJJwAHcglDQlvdsdOfBHEuY2Vq+uhPkqBWmPpsz/5dL3r5K/LAFoc9ZmneNiz5DMyRbd+6C6PpDPBSMudSI2FXBq56zpBqkSHMTFkugVTlVSLsBtgAj2n3IYCzoK6SiWDgKUGwquk4yfCLiCzB1EexSChVYLqTyoNqZLpRKtlB/dNRmb3P6zwQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 19/32] hw/arm/tegra241-cmdqv: Allocate HW VCMDQs once configured Date: Tue, 19 May 2026 11:36:57 +0100 Message-ID: <20260519103727.899332-20-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|LV3PR12MB9144:EE_ X-MS-Office365-Filtering-Correlation-Id: 982088f6-6919-4ec3-e470-08deb592f26e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700016|376014|56012099003|18002099003|22082099003|11063799006; X-Microsoft-Antispam-Message-Info: 334/qH1Qj31GIxgXpcUtn5gHWneIKs6rYq5bwAnMleXwZNFCcYe8CknzTW49ezRZkxYI69dkFFK71rCq90l3YZ2rJlX2V8YYNyUNNrNqHLBO62DhNh63Zuh+ixkwR4hMzgOqrE4bdqDoMs0/tH4F9J0QnF2k/+JNxdHUJQ/q2NPHKjFMlNyEMqk7Cu8ulbatdRcxB+ZOV/iM+T+FNlr/h6goPYG5WDZx9Zgkapg3jk3lU84ZXjVHtVFIhBdDsTFtNTu7EBgZ4S4ilnaoqJGsFwtOD/5wqTWKG+GwVmb1HIdIe9NgKazWlo1beBZkpN0J7tQQMwdQsn/iFxvByzrvWelpK/NCChRjJAGaDqO4lwq+9QQfrEDbLnbpsn4ehwBxsAqL6qWltCJoqtZmWsYe6gpPRr/B8XHw9/r2clf/4zO6WeesuMYuQiWYQceq9kjY5Hf1ccleJKRnyUB3KoPBo+pqvVamcr5SlzqSLrRiT9xvTg2ODc0YL94sAX65MIHKK5lIYs0C5D5Bftz3+/zqGoPTogd9Pq4cqUq8Gp8qxU5YUw363HfBw65J0CW+JA5u57IG2eucoZ1P9NtIrq4E2EKjA8eefMy4o3mXYFM6uTqu/lyWp6+Zy8u5FuVgC7UmP6pfXBDFb2SUb07r8NjU8aAQBgMOdUkA7FgbpS3OlTSTPULRXmso7qZY5OvJyffPk1xkp+GSCBOCj17eo5fuILb12U2NqEW6izn9ZSc8MZs= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(56012099003)(18002099003)(22082099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5eG080n09WW/aPUgzT4PReoQXv+7ecIpBsdEUp1zZTwHqH00PILyeNe8/7a4B0EBObeHrYkasTljBpmiDGTS2U5PR4hSz9SZ9qGUJ3csSKvI4fHMh1gSxFevTDXi+4P01t2D/1Z+p559kEQycPyCvVPVFTB9Wy6Gov/Z+ecFf2F9ZvPFMG4SbthDrHZAfVO6kMdLi1R7IQ3L+Xsj8er1s0qHAzzDdJVTNsYbHoAf/+mc445z/9BK5vZVs+t+w+M8fB0tFCCPfNAFqh7/lHRS6t2DtxS8xjDkr/ox6MSjkiVm7hfgHJuNXeCEHtPAa2SUAIZ6ApZLZINzfJRcIVGkCunl/g1brPDDf0FcRa8iZppEUian2RTEma+EbRzleAAvBTJT7C8/0rrFxUZo+9N0345XfnoPvJtsJiwnckt1Sf5nuqtmSRCga6ck4Z4C3JBq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:46.8524 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 982088f6-6919-4ec3-e470-08deb592f26e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9144 Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=skolothumtho@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187286269158500 From: Nicolin Chen Add support for allocating IOMMUFD hardware queues when the guest programs the VCMDQ BASE registers. VCMDQ_EN lives in VCMDQ_CONFIG, which is on the VINTF Page0 region that a later patch maps directly into the guest =E2=80=94 so QEMU won't trap its writes. Allocate the hardware queue instead once all of these are set: a RAM-backed BASE, CMDQ_ALLOC_MAP.ALLOC, and CMDQV / VINTF enabled. Each precondition write retries the allocation, so the guest may program them in any order. If a hardware queue was previously allocated for the same VCMDQ, free it before reallocation. Writes with invalid addresses are ignored. All allocated VCMDQs are freed when CMDQV or VINTF is disabled, or when the ALLOC bit is cleared. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 11 ++++ hw/arm/tegra241-cmdqv.c | 138 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 143 insertions(+), 6 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index f0b031b4dc..7a8cb2ebc7 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -45,6 +45,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; =20 /* CMDQ-V Config page register cache */ @@ -361,6 +362,16 @@ SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_L_(1) SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(0) SMMU_CMDQV_VI_VCMDQi_CONS_INDX_BASE_DRAM_H_(1) =20 +static inline bool tegra241_cmdqv_enabled(Tegra241CMDQV *cmdqv) +{ + return cmdqv->status & R_STATUS_CMDQV_ENABLED_MASK; +} + +static inline bool tegra241_vintf_enabled(Tegra241CMDQV *cmdqv) +{ + return cmdqv->vintf_status & R_VINTF0_STATUS_ENABLE_OK_MASK; +} + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 4d9f094b2a..f4968520f3 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -18,6 +18,95 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) +{ + IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; + IOMMUFDHWqueue *vcmdq =3D cmdqv->vcmdq[index]; + + if (!vcmdq) { + return; + } + iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id); + g_free(vcmdq); + cmdqv->vcmdq[index] =3D NULL; +} + +static void tegra241_cmdqv_free_all_vcmdq(Tegra241CMDQV *cmdqv) +{ + /* uapi/linux/iommufd.h: hw_queue destroy must be in descending @index= . */ + for (int i =3D (TEGRA241_CMDQV_MAX_CMDQ - 1); i >=3D 0; i--) { + tegra241_cmdqv_free_vcmdq(cmdqv, i); + } +} + +/* + * Allocate a host HW VCMDQ from the current cached BASE / size for @index. + * + * Setup is a no-op (returns true) when any of the following preconditions + * isn't met yet: + * - BASE not prgrammed yet. + * - VCMDQ is not mapped to a VINTF (CMDQ_ALLOC_MAP.ALLOC =3D=3D 0) + * - BASE / size don't resolve to a RAM region + * - CMDQV global enable or VINTF enable is not yet asserted + */ +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, + Error **errp) +{ + SMMUv3AccelState *accel =3D cmdqv->s_accel; + uint64_t base_mask =3D (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK | + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32; + uint64_t addr =3D cmdqv->vcmdq_base[index] & base_mask; + uint64_t log2 =3D cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_= MASK; + uint64_t size =3D 1ULL << (log2 + 4); + IOMMUFDViommu *viommu =3D accel->viommu; + IOMMUFDHWqueue *hw_queue; + uint32_t hw_queue_id; + + /* BASE not programmed yet. */ + if (!cmdqv->vcmdq_base[index]) { + return true; + } + + /* VCMDQ not yet mapped to a VINTF. */ + if (!(cmdqv->cmdq_alloc_map[index] & R_CMDQ_ALLOC_MAP_0_ALLOC_MASK)) { + return true; + } + + /* Ignore any invalid address. This may come as part of reset etc. */ + if (!address_space_range_is_ram(&address_space_memory, addr, size)) { + return true; + } + + if (!tegra241_cmdqv_enabled(cmdqv) || !tegra241_vintf_enabled(cmdqv)) { + return true; + } + + tegra241_cmdqv_free_vcmdq(cmdqv, index); + + if (!iommufd_backend_alloc_hw_queue(viommu->iommufd, viommu->viommu_id, + IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV, + index, addr, size, &hw_queue_id, + errp)) { + return false; + } + hw_queue =3D g_new(IOMMUFDHWqueue, 1); + hw_queue->hw_queue_id =3D hw_queue_id; + hw_queue->viommu =3D viommu; + cmdqv->vcmdq[index] =3D hw_queue; + + return true; +} + +static void tegra241_cmdqv_setup_all_vcmdq(Tegra241CMDQV *cmdqv, + Error **errp) +{ + for (int i =3D 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) { + if (!tegra241_cmdqv_setup_vcmdq(cmdqv, i, errp)) { + return; + } + } +} + /* * Returns true if the per-VCMDQ CMDQ_EN_OK bit is set. */ @@ -172,7 +261,7 @@ static void tegra241_cmdqv_write_vcmdq_page0(Tegra241CM= DQV *cmdqv, */ static void tegra241_cmdqv_write_vcmdq_page1(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, - uint32_t value) + uint32_t value, Error **errp) { switch (offset0) { case A_VCMDQ0_BASE_L: @@ -181,6 +270,7 @@ static void tegra241_cmdqv_write_vcmdq_page1(Tegra241CM= DQV *cmdqv, } cmdqv->vcmdq_base[index] =3D deposit64(cmdqv->vcmdq_base[index], 0, 32, value); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); break; case A_VCMDQ0_BASE_H: if (tegra241_vcmdq_enabled(cmdqv, index)) { @@ -188,6 +278,7 @@ static void tegra241_cmdqv_write_vcmdq_page1(Tegra241CM= DQV *cmdqv, } cmdqv->vcmdq_base[index] =3D deposit64(cmdqv->vcmdq_base[index], 32, 32, value); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); break; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: cmdqv->vcmdq_cons_indx_base[index] =3D @@ -210,7 +301,7 @@ static void tegra241_cmdqv_write_vcmdq_page1(Tegra241CM= DQV *cmdqv, */ static void tegra241_cmdqv_write_vcmdq_page1_64(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, - uint64_t value) + uint64_t value, Error **er= rp) { switch (offset0) { case A_VCMDQ0_BASE_L: @@ -218,6 +309,7 @@ static void tegra241_cmdqv_write_vcmdq_page1_64(Tegra24= 1CMDQV *cmdqv, return; } cmdqv->vcmdq_base[index] =3D value; + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); break; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: cmdqv->vcmdq_cons_indx_base[index] =3D value; @@ -282,8 +374,14 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241= CMDQV *cmdqv, if (value & R_VINTF0_CONFIG_ENABLE_MASK) { if (tegra241_cmdqv_mmap_vintf_page0(cmdqv, errp)) { cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + /* + * VCMDQs whose BASE was programmed before VINTF was + * enabled need their hw_queue allocated now. + */ + tegra241_cmdqv_setup_all_vcmdq(cmdqv, errp); } } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } @@ -394,16 +492,37 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV = *cmdqv, hwaddr offset, cmdqv->config =3D value; if (value & R_CONFIG_CMDQV_EN_MASK) { cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; + /* + * VCMDQs whose BASE was programmed before CMDQV was enabled + * need their hw_queue allocated now. + */ + tegra241_cmdqv_setup_all_vcmdq(cmdqv, &local_err); } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; } break; case A_VI_INT_MASK_0 ... A_VI_INT_MASK_1: cmdqv->vi_int_mask[(offset - A_VI_INT_MASK_0) / 4] =3D value; break; - case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: - cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: { + int idx =3D (offset - A_CMDQ_ALLOC_MAP_0) / 4; + bool was_alloc =3D cmdqv->cmdq_alloc_map[idx] & + R_CMDQ_ALLOC_MAP_0_ALLOC_MASK; + bool now_alloc =3D value & R_CMDQ_ALLOC_MAP_0_ALLOC_MASK; + + cmdqv->cmdq_alloc_map[idx] =3D value; + /* + * If the VCMDQ was already programmed (BASE) before mapping, fire + * setup on the ALLOC 0->1 transition; tear down on 1->0. + */ + if (!was_alloc && now_alloc) { + tegra241_cmdqv_setup_vcmdq(cmdqv, idx, &local_err); + } else if (was_alloc && !now_alloc) { + tegra241_cmdqv_free_vcmdq(cmdqv, idx); + } break; + } case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: tegra241_cmdqv_config_vintf_write(cmdqv, offset, value, &local_err= ); break; @@ -432,7 +551,8 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *c= mdqv, hwaddr offset, case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; tegra241_cmdqv_write_vcmdq_page1(cmdqv, - offset - index * CMDQV_VCMDQ_STRIDE, index, value); + offset - index * CMDQV_VCMDQ_STRIDE, index, value, + &local_err); break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", @@ -451,6 +571,7 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *c= mdqv, hwaddr offset, static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV *cmdqv, hwaddr offse= t, uint64_t value) { + Error *local_err =3D NULL; int index; =20 switch (offset) { @@ -465,13 +586,18 @@ static void tegra241_cmdqv_writell_mmio(Tegra241CMDQV= *cmdqv, hwaddr offset, case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; tegra241_cmdqv_write_vcmdq_page1_64(cmdqv, - offset - index * CMDQV_VCMDQ_STRIDE, index, value); + offset - index * CMDQV_VCMDQ_STRIDE, index, value, + &local_err); break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled 64-bit write at 0x%" PRIx64 " (WI)\n", __func__, offset); } + + if (local_err) { + error_report_err(local_err); + } } =20 static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1779187298; cv=pass; d=zohomail.com; s=zohoarc; b=R9QkgBeCS77OJg+m14squ7AwLD4G51UYYmZTkWz508m1ajBobZvO6hBtNKN35c7rJxkRxpYaxDXouyr8NpvX5qdit4M/rtHtNj7xNHsXYsdG7noEJDo7lrhwxybNOP7fnAXAUmAPErDuPpQbV7KUtKIe160JdZvnIFgKB/BRrwg= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779187298; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wUR2lS78GUxpYMKWHRg+EZzYom5CedXG3O4P2ADPmeo=; b=XX318VNDQU9Z7PnlLh9MQAusCs+o86DtktQT5SIp/XA4tgaMp5kya/hu3LGzgvU/NA29VkFP110WdnPsIMtUIDrhKD8M6c1oFJRJClwVYSRUs3kGcmCY0IFmMNJSbxUY5vmhl+dCkW6+qzVGrJcYCht+Z7ZN6DLWd/EDVavrWNw= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187298207978.3125915292242; Tue, 19 May 2026 03:41:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsE-0002CA-Px; Tue, 19 May 2026 06:40:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrn-0001Ba-Gc; Tue, 19 May 2026 06:40:09 -0400 Received: from mail-northcentralusazlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c105::1] helo=CH1PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrl-0006Z1-2K; Tue, 19 May 2026 06:40:02 -0400 Received: from BL1P222CA0007.NAMP222.PROD.OUTLOOK.COM (2603:10b6:208:2c7::12) by SJ5PPF0170DF9F2.namprd12.prod.outlook.com (2603:10b6:a0f:fc02::985) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.20; Tue, 19 May 2026 10:39:53 +0000 Received: from BL02EPF0001A101.namprd05.prod.outlook.com (2603:10b6:208:2c7:cafe::f3) by BL1P222CA0007.outlook.office365.com (2603:10b6:208:2c7::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.25.23 via Frontend Transport; Tue, 19 May 2026 10:39:51 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A101.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:50 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:35 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:32 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=UQ3nJvpNG0JntQi/CB7hAtQD7uDFdNRFoFxTvPWVfM48lfClgMkHkxGPTlir5jIcQ+Y965i/x5tEc+r+joon8abdpUoy37/hFBz8D28PMlHl/XRD8jS9Wfe19qg9reYbhClLwTPSQex2tBD4IFXXxtIIgQOKjyXYpPGMKp/vc5OtbtCtl/bA81Dhgn4KW124Ah3uvMpFuToSqqh/0DDtgfxa7KaDFOmhYAh/VE/f0+IbVrFE8Ei7y384+y8zfNs6H3XG3ZZWtPIufY4RNJEchM1Nj9hToN1EWYqTUTqitcJYKhhQqIBPM82fH3S1GVhPwQ0rQJNpVL+qrLSFFjRGEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=wUR2lS78GUxpYMKWHRg+EZzYom5CedXG3O4P2ADPmeo=; b=mkfQGBIaSBYkj91uTp53PkAFGb25kZ8wpQtdrKF7Khq1J8nMjWNWeE/eqmTDc33mVo4QoB6+NqmUGuV1p0fB1yY6KRPD9YgDzGFpY8YyR2BGWGg4b/99/wVmF5Z/IKMgJtz773rmTisdx/Gz0VoNSCdTE0/HhJcr0X4LsT6d8h9V8ools17X54363I3/G6zkxNuuktzOT0mhRyS5TFruwGGBHiGk9rDx6a1BQS5EF1eI3wDCmJd57b8TaCn6Zh35JrOny5JZWiqYUVERodBxUK1tqNPH5bdbR4qBEu+lJmPautjiRVOHV1CeLIbUX/8Z1AzPFaicWk8L6DnLSDgFUw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wUR2lS78GUxpYMKWHRg+EZzYom5CedXG3O4P2ADPmeo=; b=uP6k6GF89D1cEn4Bh3Cz+5RH5D866Hix6M1tg3rzXJKywSjArsoDkfD5PtQOfkcNGP0D7cKZdmJx7dNBH8fBIygX4QTjukp5MfOOPCmaCoyc01/gR0Zm987BQVa7SXP6oUYX9lFciLIsoNEY5q+uXiW63U9hqB8STeZ3QRUIpK6OgMhgBBrHROBHL2DBhrRH5lEVfF6J0zFtYYwgII2lRa4OAnga8I1YoWWB6kbI8v7LeLnl0Zvh2VJLGbbTyrG47Z3p6xk3kxQrGKYf/XB60ydtE22OJZMs0PY+oxaOARdh/dW1sXvKK2i23chmRlP7XlM9fIkdnb/TjUt3pO+Qtw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 20/32] hw/arm/tegra241-cmdqv: Use mmap'd VINTF page0 as VCMDQ backing Date: Tue, 19 May 2026 11:36:58 +0100 Message-ID: <20260519103727.899332-21-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A101:EE_|SJ5PPF0170DF9F2:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b0bef40-bf5b-4f71-1e88-08deb592f4e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|22082099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: Xyfl6idzYMxowVXJk4OWeeQYtOduK5/MNkLaaUpfPF7X6aug3WffW54RhjN65TbMN+r4mQ8ls2wawp4nlgzz/f0b9xIV+4x6NqwmgnwyfnhX9/1MSBGjFSYo+a3L92rP13IV+nYxe/FqZaYY+8ZrZdEnyv2nGoFylsg4Q/yTv3/0hknMcWl+AuWQgLYnzrQ6FeesJZwgg0AUpq/hPVCj8X5Yl8BOniOYLhEsF/x4tARnvFMC7RBbGRZJXuN0zsAO3KpTTK5gydmsoo912VunPOgGtObleztSqqB/YEMHm44VJ9n9Jfyt5lMTTN8DiEGvqaM4Q6If7gma2F7VbYu0LhVEPNZ6iPABsFzhC66VMr5gxfjgssFMY6oZNkvViZvfPA/lUL8dvyYVgt+tcxmhWFkYouwDNnOEwPJLK7pO/0lmF0Cw/9Rr+dbkY1sivtinl5eqs+hY7fZjuC+kP/PX4hyQqTX3KBekeDtsskHR0gmjldax8VOZlhYilfcW7MT9S+ktWMwGrHTzOhCKifAozrG/hMYwB0OZhHSj5pDeTkhEXz7WILcDX5ykQ/CjBQTwTMj3dYf4ZBBgeEDrjZwKwboD7PaSFMP/UIVV0E667a4vRo1TMbAmEJt6SHhrHO6aC3HfBJPmqfILjPwfNa+ep/wf5RkaNp6/dHEg8avkuOSSWPUKdS3PHgCwGwbHKgpQ109rc6HqcwYwpu2PqL3mzoPzO+HN4CO82EEYffSigMQ= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(56012099003)(22082099003)(18002099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /HODXMUE+dsUr3A+j658Hh2kMNANvaZ+r6464b3p5HBOFoxJT5wKygpyGQc7W6emXQAwFjWwuectsYr1jVrzXKGDnKg24wV6vGQyTRZO+UMZRD2W4cKRgnT/2o6B9uPaKkGoKJcRXpeVr2UVZorsYWiA1T7cwpay3xrkuUjWEKnP5QZjYB5TzPYe1992y6gW9U28VvLuG7Nw15qsgfCszLahwQBpPY5tAT+WU3DxUKgfzHQVaHXCk5LzUHBZazzcgxxUKo3Pzb6xFgkE/A9aFAJUPwNOxkqA/NFnR0Wr3pwaVJkjPJ7ghhuSlcoRa9Z5d2k6HSjZPDk1cY+fFPNNCFNNYtXbTTQYVnFyw7Y6grFrMoH7wv5mjnAiYVgoEhUDQgB82lEm4ZcvShewAO6v4fdvz0m42nmYfIZAwjYOZ4fTu72tkZ3QFkhtSnaAqPbg X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:50.9764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b0bef40-bf5b-4f71-1e88-08deb592f4e3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A101.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF0170DF9F2 Received-SPF: permerror client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187300366158500 Content-Type: text/plain; charset="utf-8" Introduce tegra241_cmdqv_vintf_ptr() to route VCMDQ Page0 register accesses through the mmap'd VINTF page0 backing once a hardware queue has been allocated. There are two QEMU trapped MMIO apertures for VCMDQ Page0 registers: - Direct VCMDQ Page0 aperture (offset 0x10000) - VINTF Page0 (offset 0x30000) These are hardware aliases: they address the same underlying registers. A subsequent patch maps the VINTF aperture as a guest-direct RAM region; in this patch both remain QEMU-trapped. VCMDQ Page0 accesses operate in one of two mutually exclusive modes, depending on whether a hardware queue (IOMMU_HW_QUEUE_ALLOC) has been allocated for the VCMDQ: Pre-alloc: vintf_ptr is NULL. Both apertures use QEMU's register cache. Hardware is not yet engaged. Post-alloc: vintf_ptr is valid. Both QEMU trapped apertures access registers directly via the mmap'd vintf_page0 pointer, bypassing the cache. Hardware is the single source of truth. The pre-to-post-alloc transition is triggered by the IOMMUFD hardware queue allocation. The tegra241_cmdqv_sync_vcmdq() copies any pre-alloc cached writes (CONS_INDX, PROD_INDX, CONFIG, GERRORN) into the mmap'd page so the guest's view survives the transition. CMDQV acceleration only becomes active once the guest enables VINTF and the corresponding HW QUEUE is allocated through IOMMUFD. Until then, all VCMDQ accesses are served from the emulated register cache with no real hardware command processing. This matches the CMDQV hardware specification: if the logical CMDQ index does not map to any allocated Virtual CMDQ, "the access is dropped with no Fault/Interrupt". Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 72 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index f4968520f3..a7e89905df 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -39,6 +39,39 @@ static void tegra241_cmdqv_free_all_vcmdq(Tegra241CMDQV = *cmdqv) } } =20 +/* Pointer into the mmap'd VINTF page0 slot for @index, or NULL. */ +static inline uint32_t *tegra241_cmdqv_vintf_ptr(Tegra241CMDQV *cmdqv, + int index, hwaddr offset0) +{ + if (!cmdqv->vcmdq[index] || !cmdqv->vintf_page0) { + return NULL; + } + return (uint32_t *)(cmdqv->vintf_page0 + + (index * CMDQV_VCMDQ_STRIDE) + + (offset0 - CMDQV_VCMDQ_PAGE0_BASE)); +} + +/* Flush cached pre-alloc writes into the mmap'd VINTF page0 slot. */ +static void tegra241_cmdqv_sync_vcmdq(Tegra241CMDQV *cmdqv, int index) +{ + uint32_t *ptr; + + ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, A_VCMDQ0_CONS_INDX); + if (!ptr) { + return; + } + *ptr =3D cmdqv->vcmdq_cons_indx[index]; + + ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, A_VCMDQ0_PROD_INDX); + *ptr =3D cmdqv->vcmdq_prod_indx[index]; + + ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, A_VCMDQ0_CONFIG); + *ptr =3D cmdqv->vcmdq_config[index]; + + ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, A_VCMDQ0_GERRORN); + *ptr =3D cmdqv->vcmdq_gerrorn[index]; +} + /* * Allocate a host HW VCMDQ from the current cached BASE / size for @index. * @@ -94,6 +127,9 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cm= dqv, int index, hw_queue->viommu =3D viommu; cmdqv->vcmdq[index] =3D hw_queue; =20 + /* Pre-alloc cached writes survive the cache-to-hardware transition. */ + tegra241_cmdqv_sync_vcmdq(cmdqv, index); + return true; } =20 @@ -108,11 +144,14 @@ static void tegra241_cmdqv_setup_all_vcmdq(Tegra241CM= DQV *cmdqv, } =20 /* - * Returns true if the per-VCMDQ CMDQ_EN_OK bit is set. + * Returns true if the per-VCMDQ CMDQ_EN_OK bit is set. Reads from the + * mmap'd VINTF page0 when the VCMDQ is allocated (HW is the source of + * truth post-alloc); otherwise reads from the register cache. */ static bool tegra241_vcmdq_enabled(Tegra241CMDQV *cmdqv, int index) { - uint32_t status =3D cmdqv->vcmdq_status[index]; + uint32_t *ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, A_VCMDQ0_STAT= US); + uint32_t status =3D ptr ? *ptr : cmdqv->vcmdq_status[index]; =20 return status & R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK; } @@ -122,12 +161,21 @@ static bool tegra241_vcmdq_enabled(Tegra241CMDQV *cmd= qv, int index) * * The caller normalizes the MMIO offset such that @offset0 always refers * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * If the VCMDQ is allocated and VINTF page0 is mmap'd, read directly + * from the VINTF page0 backing. Otherwise, fall back to the cache. */ static uint64_t tegra241_cmdqv_read_vcmdq_page0(Tegra241CMDQV *cmdqv, hwaddr offset0, int index) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0); uint64_t val =3D 0; =20 + if (ptr) { + val =3D *ptr; + goto out; + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: val =3D cmdqv->vcmdq_cons_indx[index]; @@ -152,6 +200,7 @@ static uint64_t tegra241_cmdqv_read_vcmdq_page0(Tegra24= 1CMDQV *cmdqv, "%s unhandled read access at 0x%" PRIx64 "\n", __func__, offset0); } +out: trace_tegra241_cmdqv_read_vcmdq_page0(index, offset0, val); return val; } @@ -225,11 +274,29 @@ static uint64_t tegra241_cmdqv_config_vintf_read(Tegr= a241CMDQV *cmdqv, * * Page 0 registers are all 32-bit; this helper is only called for 4-byte * writes. + * + * If the VCMDQ is allocated and VINTF page0 is mmap'd, write directly + * to the VINTF page0 backing. Otherwise, update the cache. */ static void tegra241_cmdqv_write_vcmdq_page0(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, uint32_t value) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0); + + if (ptr) { + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_GERRORN: + *ptr =3D value; + goto out; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: cmdqv->vcmdq_cons_indx[index] =3D value; @@ -253,6 +320,7 @@ static void tegra241_cmdqv_write_vcmdq_page0(Tegra241CM= DQV *cmdqv, "%s unhandled write access at 0x%" PRIx64 "\n", __func__, offset0); } +out: trace_tegra241_cmdqv_write_vcmdq_page0(index, offset0, value); } =20 --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187284222585.3516623345685; Tue, 19 May 2026 03:41:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsD-00023l-BT; Tue, 19 May 2026 06:40:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrp-0001DY-LB; Tue, 19 May 2026 06:40:12 -0400 Received: from mail-southcentralusazlp170110003.outbound.protection.outlook.com ([2a01:111:f403:c10d::3] helo=SN4PR0501CU005.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrm-0006Z3-Ld; Tue, 19 May 2026 06:40:04 -0400 Received: from BL1P222CA0021.NAMP222.PROD.OUTLOOK.COM (2603:10b6:208:2c7::26) by LV2PR12MB5751.namprd12.prod.outlook.com (2603:10b6:408:17d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.23; Tue, 19 May 2026 10:39:54 +0000 Received: from BL02EPF0001A101.namprd05.prod.outlook.com (2603:10b6:208:2c7:cafe::9f) by BL1P222CA0021.outlook.office365.com (2603:10b6:208:2c7::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.25.23 via Frontend Transport; Tue, 19 May 2026 10:39:54 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A101.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:39:54 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:39 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:36 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YbQ+zas8w6pZEgnX4C5qaF4+6OSsf1CljdYk6D+wcf9uEMyCVyMCRwk0nBmSLXI7OaEfaDxPouroB42BcFdzoDcvd61tCExrsTcxfNQk4SuGVnw+yzjF5a0FCIzzU14fSG8bxucpFxQ3PgbFhbZn0ozFYDOsF6O7wlf3+MBsXSthvKxLJAV0fQGnSGX2CN+Fu+W1QDHkz9BTNSyyQTcyvpM62zqnAVhZ07bE0D5EZ30GYervBHK5VDUjQYpEtbXBtSGxuP57DpquZUuiP1nnSP7ljk+9NQlSZv0btu/WQwO/k/n55m7HcpOhMC8E4x8DxhBEDq52aIJDuQ9FYIdSyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nRt38x4FhRYCtELyHTxGMV6x9z0Hw34kUIQW9+UYBG0=; b=WqcSMRgs6kAETGKnyj5/n/3+wX/c4G8pCVppSeuFxOXH2VXqhMw4iguH0KzimemyOeCE2qnHpRx5PlTDLCkGwlE7eruLaIUNIjrf4i2Xe76rp+n5YmUKFBrWBAeT9Xu4W2GPRxBmLADjxi2rTJSY0fknI9AVH1H89kuDpBeJNwEh0cTNSkCopKOqL0IXsfasZVhYdfSGVoRk8aqfZbomvqMidjqj8sxaOaB60H537LsieFqEIf2VE/lpqn6SaqbQVsvFpjRFYqJ7GIpZUt2SgjGwVi2fbH+aT80KFZMqXrpbhtA/Bla3MyKs2a3kOOIdSRCFlQVe19v5XFvcsfhK/w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nRt38x4FhRYCtELyHTxGMV6x9z0Hw34kUIQW9+UYBG0=; b=L0n1eYlhgecimantcUNKbjlQgkjmvC6T0u+orMDfpk1ZabiOOYe7e14EjqC1UhR84k39XGrTCquh9YeztCC75ArE6UjTzFvH8sbuMFH+5Ds2USyy3QmLiEB+7Mchi4544w4kyV8nbsvwBvN6gYYGdluHzCBh4llxNVang0EgC39+pW56m7o3HDYwRzHfsvEs7dhdSFwdHpMF9Z+4TmPUvXouhkwgtxcSMwX/6/9guicpNLoZvmqrXpXY+BRS456SVl/j2BzT9PU1Qszt9d7cFx72jo2/bf8zum5iEDtGa8kE2IJRVZHek4HTERmnNGc+4f0Pv5CMdBh7gnNweVdSIg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 21/32] memory: Allow RAM device regions to skip IOMMU mapping Date: Tue, 19 May 2026 11:36:59 +0100 Message-ID: <20260519103727.899332-22-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A101:EE_|LV2PR12MB5751:EE_ X-MS-Office365-Filtering-Correlation-Id: 58e819ca-6086-4064-f332-08deb592f700 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|1800799024|82310400026|22082099003|18002099003|56012099003|11063799006; X-Microsoft-Antispam-Message-Info: vAx5vdqP7n5K2hOg+xtBcOp/jb2SUX2aXhGN5lAhBTOnyQ4/moGoSfvk5sHhX/GfnKhhSR6w0pZmtF7zkKmw34Dkhmoh1VtnIK8ue1Tlc9PXeFvvnvOsEhhG0cuBsnamMlJmuwsPRWSkjJTHVqh4hcQupCwXD5Q5/ElkwvsxLsKl5ULcdGZQKKpMlYBNW8uxz6nPWgalXRUtkZe556Atv93GmaZZ442L3yeTNS6PH2A51UB1EF16B6pDKvWblZl7L83KCkaq6KoZQVB5keBUNMX5/mFxwlboSQJn6r4Y9IzXl1CjIh4kpvLoxN5cb6qRiOTZ43WTl3W8kUIGlgeo87YqHB5BocW++h7aiMItcb6FO56gBZF5AcSK28DTjNc0L2W5ANL0dy1ShpMXOm2s3GI0KtjhhUmTOTwQS5uKhWlxptMWJoKV+n8rJhDRAeo0OuUSj+chRE1HNFYHRj/dfvHwLap9R8ulRQqXUvckz0DsyirT2tQaQ/nOJPSIucCoGeWVlvpK2/HnputajEoOVzGSdko4tTTrmiJF7Hwa5/fPTMDwwcKwM06pl0kBt71FJk5Ucoe4JshcHB2zA55h0kjCfVqvSGDghJHKqcOJbkt8wNOtMmfQJfy4XIuyGoFExurci2mVCbx47O4XU0FemTBJefcnkTlUrKFSH4XtW0P9W6LQuRoVI0DBPtHy9ZsYePSdS8mYrZyZmWV5NktCQ6fwZ3CeaAWkJRhN0OeOuMg= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(22082099003)(18002099003)(56012099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: d0fxa5Hmga8YLZ5qfJvoHlaj7EPHqEqSfzafEzcpEPFC+4F60k7q9QXY0achGM6BGsE4OHklMkA6apmujpBs1vhmnR+R7F9wLNMw6VsQG6LWTZ5SWYXnF8DwUR/lDcRon5AxfjM2WNxNMjm1iWnGXYrIpdR8dFD4ggrHE9+w/MyA+QYChjNkgFQ/jb+yy8Uao+YwiJ0bivnQosn2QzZVZVhR9ohkA4UN8d0HLl8Qctxidl9OW5D26IOfAJqDbVlcZV/4l+S0hnOoIAJ15WfOGnodP+xWC5+A4CAJ1Fx2PzX2XQglWTGEird2RJXgkC9MtfKriKkZCmI9rXgvLQJlN12+gbow3gy+ab5qSgXrycxhkfk9tuZ0h320IgrdAnh80Tuxg3QLpcDcBq5LdEPCvkhFoeHXjehazZ+Mk4oki5Fp/RfkRcT2yeCUrWtrjysj X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:39:54.5131 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58e819ca-6086-4064-f332-08deb592f700 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A101.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5751 Received-SPF: permerror client-ip=2a01:111:f403:c10d::3; envelope-from=skolothumtho@nvidia.com; helo=SN4PR0501CU005.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187286191158500 Content-Type: text/plain; charset="utf-8" Some RAM device regions created with memory_region_init_ram_device_ptr() are not intended to be P2P DMA targets. The VFIO listener currently treats all RAM device regions as DMA capable and attempts to map them into the IOMMU. For regions without dma-buf backing this fails and prints warnings such as: IOMMU_IOAS_MAP failed: Bad address, PCI BAR? Introduce a MemoryRegion flag (ram_device_skip_iommu_map) to mark RAM device regions that should not be IOMMU mapped, paired with memory_region_skip_iommu_map() / memory_region_set_skip_iommu_map() accessors. When the flag is set, the VFIO listener skips DMA mapping for that region. Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Tested-by: Eric Auger --- include/system/memory.h | 21 +++++++++++++++++++++ hw/vfio/listener.c | 4 ++++ system/memory.c | 10 ++++++++++ 3 files changed, 35 insertions(+) diff --git a/include/system/memory.h b/include/system/memory.h index af5f96f6ff..b11d6bf07f 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -864,6 +864,8 @@ struct MemoryRegion { =20 /* For devices designed to perform re-entrant IO into their own IO MRs= */ bool disable_reentrancy_guard; + /* RAM device region that does not require IOMMU mapping for P2P */ + bool ram_device_skip_iommu_map; }; =20 struct IOMMUMemoryRegion { @@ -1743,6 +1745,25 @@ static inline bool memory_region_is_romd(const Memor= yRegion *mr) */ bool memory_region_is_protected(const MemoryRegion *mr); =20 +/** + * memory_region_skip_iommu_map: check whether a memory region is excluded + * from IOMMU mapping + * + * Returns %true if @mr is a RAM device region marked to skip IOMMU mappin= g. + * + * @mr: the memory region being queried + */ +bool memory_region_skip_iommu_map(const MemoryRegion *mr); + +/** + * memory_region_set_skip_iommu_map: mark a RAM device region to skip IOMMU + * mapping + * + * @mr: the memory region being modified + * @skip: %true to skip IOMMU mapping, %false to allow it + */ +void memory_region_set_skip_iommu_map(MemoryRegion *mr, bool skip); + /** * memory_region_has_guest_memfd: check whether a memory region has guest_= memfd * associated diff --git a/hw/vfio/listener.c b/hw/vfio/listener.c index 0b72a2cf5e..18100e9897 100644 --- a/hw/vfio/listener.c +++ b/hw/vfio/listener.c @@ -610,6 +610,10 @@ void vfio_container_region_add(VFIOContainer *bcontain= er, } } =20 + if (memory_region_skip_iommu_map(section->mr)) { + return; + } + ret =3D vfio_container_dma_map(bcontainer, iova, int128_get64(llsize), vaddr, section->readonly, section->mr); if (ret) { diff --git a/system/memory.c b/system/memory.c index 739ba11da6..48245fd01b 100644 --- a/system/memory.c +++ b/system/memory.c @@ -1814,6 +1814,16 @@ bool memory_region_is_protected(const MemoryRegion *= mr) return mr->ram && (mr->ram_block->flags & RAM_PROTECTED); } =20 +bool memory_region_skip_iommu_map(const MemoryRegion *mr) +{ + return memory_region_is_ram_device(mr) && mr->ram_device_skip_iommu_ma= p; +} + +void memory_region_set_skip_iommu_map(MemoryRegion *mr, bool skip) +{ + mr->ram_device_skip_iommu_map =3D skip; +} + bool memory_region_has_guest_memfd(const MemoryRegion *mr) { return mr->ram_block && mr->ram_block->guest_memfd >=3D 0; --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1779187275; cv=pass; d=zohomail.com; s=zohoarc; b=g++Gn8Z3P0QVzTOJ9ITuFewO8ijziJWJ1ouxpDt+oxFfuhi80onoLXNR2aTkpKf8V+yQT7P7kGy182qByGXMkbQKygyqG5wbd3IJCjum2PYUTjeM8Dq/xNujEmIu8ujOMu7kZ4+WDSurGFdXA0RXP5h5gmJJiFITUHT1OxewUVM= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779187275; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EhF/QX4xj1OQsXu41GlLIgRbvTOFQM1Y3CBA5ZRtNmg=; b=cnLdjHUdaPrYv8WJqbO60xiqcd6iKuN199mpT+EJcHHt2EnZBbGBsqfrKKsTmcxUm7cwgsFCx/VkK+acC8+0/Ytr6aUpNLHHStwfNhqC/m+15nn8Hm2GZaVl32UaCrcdv9Mh2PkNVUU0M31XbZGqM+MvsdVbIZbDEsKD95wYq9U= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187275938931.5027186791746; Tue, 19 May 2026 03:41:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsJ-0002Zv-9o; Tue, 19 May 2026 06:40:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrx-0001Mg-FB; Tue, 19 May 2026 06:40:19 -0400 Received: from mail-westus2azlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c005::5] helo=CO1PR03CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHru-0006lx-Jo; Tue, 19 May 2026 06:40:12 -0400 Received: from DS7PR05CA0066.namprd05.prod.outlook.com (2603:10b6:8:57::11) by MW6PR12MB8899.namprd12.prod.outlook.com (2603:10b6:303:248::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9913.11; Tue, 19 May 2026 10:40:02 +0000 Received: from CY4PEPF0000EE33.namprd05.prod.outlook.com (2603:10b6:8:57:cafe::27) by DS7PR05CA0066.outlook.office365.com (2603:10b6:8:57::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.15 via Frontend Transport; Tue, 19 May 2026 10:40:01 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE33.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:43 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:40 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VCYT+/mVABjUxawclGTmgeLvepw1NBvseenq4kC+gIqsgESWH3KkBB8UPEFAtFfILE4UAXYSyD8ESobHzOxFuivZFnuSc2LbaE7d/6N22ledWtCNlmCNZvU04WxbpAZsE9FbTjvFm54OTcckFYNWy4tagia8xTjpwt5pvL4tE3b73Wp3H3DWSSWA/hK1E2oZPsuzkr8KOVcxqLHDx8TiJ/Siiom56q3E1VXkfUuJbb+Wc8d3xVpgW9zZWTCj3pOB5TbEfW9biw8qDmgsci9kgG38xmonvr+moV5nX204j8BYHb7pZMBZbXigpDsOdH5nZur6G0AnbNmChwwLYoCkkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=EhF/QX4xj1OQsXu41GlLIgRbvTOFQM1Y3CBA5ZRtNmg=; b=wp3jr6EOjbki39IOIDGjjH6F2StEL5AcRyDyZe2BEfrzZyC+tXlQG+OX+Ble6pIhBUOOETys17zSed4Q6BJQrJzSkWaW2E8t6bi705Xqzniz/IShQKVXVnnolLQlDQIWrZkGBLDfQ9dyDpk0pEH/iLwuDasMKrHhQK2JQ4kZd0GCkt1GcmJiSHLEwpXtXvAah+5RlCZv/g3bc0SXuQw/3I8w/ntsA3eViunYGU5eghvnubFRoTt58i3wpNDtIXVBd2dziS3AeX80OPoYx1zlVDB19e5BBYprLyOFAJqVYBe2vSITt5NXr7t6KT6MPN2bbQSOBuMw5UbSRsx2tLZSbg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EhF/QX4xj1OQsXu41GlLIgRbvTOFQM1Y3CBA5ZRtNmg=; b=YnPSX1CmxpWm9A8uLmIWLuQhoiMtRw9GI3TL7vYz1XoqkVPGPPcDqfSpip5Rb1bluEG9nlhqVS2oEr+rDBQRV6x+ZoIDVw/N5jAxKedT/RVMOy6t+GBB+o3+Dn6ZnKlcaZCO2CqfkbdAj+Jm5JzIHtDdx6jjFeIrGSS9689jKWh8GtJ0yU7C5ojdmJccY8bE2nXAcsEsgTDA6Upi+1AtUi6i1IbR3BhbnrcMU6jPVmBKmqraHjvC6mCNybKip3M6ZxEDDfhmvBuv6Jy01E2gxnc5LcFNv0W+3GvPp1Kaoi3qzvNO5cSayQvz0Z4DBmX83fdE6F/BnWyDiKg4ZsQgDA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 22/32] hw/arm/tegra241-cmdqv: Map VINTF page0 into guest MMIO space Date: Tue, 19 May 2026 11:37:00 +0100 Message-ID: <20260519103727.899332-23-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|MW6PR12MB8899:EE_ X-MS-Office365-Filtering-Correlation-Id: 01309a7d-9873-4574-7aa1-08deb592fb51 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|82310400026|376014|11063799006|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: BwasscSwL8nf7VB6JnEFL+0yY+qv+VDP8mpL7xAHzIEjic1Kwtm48NeQT2GlkwW4RMhQC25hFrj00/IzrmZGQauiqg7af+v92XwU8iyvzq3nd+mlyy4S68fYZ63iCCGG6JBMmSiYeq5a1gnbtRSjEg6avcVfrLA1bVYr3mpFuNHSz4G3Aj+Cm0nu+900dK/qg3qpbOFIAsJKt9XvuJsKYdAJlrnPaxe8n9KxIaca3LOhuK6pLa2oYt39xGL4xIvW4vEapE3apLirYr0Y0B1xY+LLuDCi9KiQ2pMA4JWxZDDQxK/X16su5KLvBPa1E2gwUMVLArmWfL9f/F01PElXmf6H1hrZDrBe6ftwBivv+ytKL0Z4omljByJdNM0CIa51+X+6h9k7bphbgUU6cgvrBTiDefN8aW6CF5zDpWoKQfgLTx2bGi7RfEWEOjF7qufj1K8iaSFgG9DroDjlWy2rK8NsNhWOEb/FOnRL/o/cEnQ/fo7tPEaO7V1W1uq0isqCJXzZlADxZ0Evu6tSqU1s2oUaHtSipbRf6kiefndsbP7ZOzddGvezEW0CcBmkiXllc8B9R1TraBEex8hPjYyoynB81Cf4PtpUGzzLnM4qOU+/cVvlzv2Sq8yhce+CeJbseMEoOtxuZVUs7+yr4QjGeijGd6mXINQaP9267q9Q9g4jhbsg5QQo0zTXxF9KCyl8qbC6jteMIQHpcQYkewR6YB5Wz5d0qoLLYjFYMpcOaY8= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(11063799006)(22082099003)(56012099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FQxqi33g0299i0xFCjrjW0Xkc6AUmE9GoT2zlZEOSjq3gF9BpRyzocQM9f06VCbs1WD/YTfXRgLNY+9Puqpo0JKiq5TP5XkWjJQ1y8k76D0BAuZUBBNFF4sHbfSiYDmg1KYRgkuyTHxioHwalGp28R+dDMWaXpXZNkjg/FzjEf0Du5wW5WJvtl0jFyZuYC64Lft4DZ7WyX9yTCkyEhluhKCxgYx65QwwOEGbClVZI3+b+Gn9qHzjitLAiO12CKuCr8Xt3F4zQxGtUKJtu0bQwp7zVPforW7jKpu1i1xaEyNbRhoYYFF+3HS4t/7pgdvneCUlpOGFSEhkV9ONz76j0/nZsgzCFhMlUt6L8T8NltroR96MVTt2RmprqE/t7VJKYAHNwL3nluyiZtAN0mSC3KO9PAMsylsmRrlHV3fQBu+2VpYnJl3Qj3theilwrEdJ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:01.8028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01309a7d-9873-4574-7aa1-08deb592fb51 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8899 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187276162158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Once a VCMDQ is allocated, map the mmap'd vintf_page0 region directly into the guest-visible MMIO space at offset 0x30000 as a RAM-backed MemoryRegion. This eliminates QEMU trapping for hot-path CONS/PROD index updates. After this patch, the two VCMDQ apertures use different access paths: the direct aperture (0x10000) remains QEMU-trapped and writes via vintf_ptr, while the VI aperture (0x30000) is a direct guest RAM mapping. Both paths write to the same underlying vintf_page0 memory, so no synchronisation between the apertures is needed. The mapping is installed lazily on first successful VCMDQ hardware queue allocation and removed when CMDQV or VINTF is disabled. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 1 + hw/arm/tegra241-cmdqv.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 7a8cb2ebc7..e9e1933a19 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -47,6 +47,7 @@ typedef struct Tegra241CMDQV { IOMMUFDVeventq *veventq; IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; + MemoryRegion *mr_vintf_page0; =20 /* CMDQ-V Config page register cache */ uint32_t config; diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index a7e89905df..853c548e58 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -18,6 +18,40 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +static void tegra241_cmdqv_guest_unmap_vintf_page0(Tegra241CMDQV *cmdqv) +{ + if (!cmdqv->mr_vintf_page0) { + return; + } + + memory_region_del_subregion(&cmdqv->mmio_cmdqv, cmdqv->mr_vintf_page0); + object_unparent(OBJECT(cmdqv->mr_vintf_page0)); + g_free(cmdqv->mr_vintf_page0); + cmdqv->mr_vintf_page0 =3D NULL; +} + +static void tegra241_cmdqv_guest_map_vintf_page0(Tegra241CMDQV *cmdqv) +{ + char *name; + + if (cmdqv->mr_vintf_page0) { + return; + } + + name =3D g_strdup_printf("%s vintf-page0", + memory_region_name(&cmdqv->mmio_cmdqv)); + cmdqv->mr_vintf_page0 =3D g_malloc0(sizeof(*cmdqv->mr_vintf_page0)); + memory_region_init_ram_device_ptr(cmdqv->mr_vintf_page0, + memory_region_owner(&cmdqv->mmio_cmd= qv), + name, VINTF_PAGE_SIZE, + cmdqv->vintf_page0); + memory_region_set_skip_iommu_map(cmdqv->mr_vintf_page0, true); + memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv, + CMDQV_VINTF_PAGE0_BASE, + cmdqv->mr_vintf_page0, 1); + g_free(name); +} + static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) { IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; @@ -130,6 +164,9 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *c= mdqv, int index, /* Pre-alloc cached writes survive the cache-to-hardware transition. */ tegra241_cmdqv_sync_vcmdq(cmdqv, index); =20 + /* Map the mmap'd VINTF page0 into guest MMIO space. */ + tegra241_cmdqv_guest_map_vintf_page0(cmdqv); + return true; } =20 @@ -449,6 +486,7 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241C= MDQV *cmdqv, tegra241_cmdqv_setup_all_vcmdq(cmdqv, errp); } } else { + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; @@ -566,6 +604,7 @@ static void tegra241_cmdqv_writel_mmio(Tegra241CMDQV *c= mdqv, hwaddr offset, */ tegra241_cmdqv_setup_all_vcmdq(cmdqv, &local_err); } else { + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; } --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187265098568.1683687623315; Tue, 19 May 2026 03:41:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsL-0002mo-62; Tue, 19 May 2026 06:40:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrz-0001Pi-5K; Tue, 19 May 2026 06:40:19 -0400 Received: from mail-centralusazlp170110009.outbound.protection.outlook.com ([2a01:111:f403:c111::9] helo=DM5PR21CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHrw-0006m4-Cs; Tue, 19 May 2026 06:40:14 -0400 Received: from PH7P220CA0087.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:32c::35) by SA0PR12MB4431.namprd12.prod.outlook.com (2603:10b6:806:95::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.20; Tue, 19 May 2026 10:40:06 +0000 Received: from CY4PEPF0000EE31.namprd05.prod.outlook.com (2603:10b6:510:32c:cafe::16) by PH7P220CA0087.outlook.office365.com (2603:10b6:510:32c::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:06 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE31.mail.protection.outlook.com (10.167.242.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:05 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:48 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:45 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IQbTNg6vuxo6m/Cn8jrFvX9F/vD+CYEcP0ldYZ5c67mernBsfedmcRV8g4leq1Hg5vx9odU/e8ME4iiZq8l7aoa5EDtk1ZuZd+PZgOhl0gAAybnWve5dD+pPy0k9AdF20Jmo7HRrPAzFHT50x/QaGO+/EIJEhBjRYW/S/LwaZtuloSWc4A2jEfnxUlaVAFsn41MoC6cNvE8bmkrTZhsifPPqXNGgU2xvQ/+6y3vqCYMsAubeP5ShhXiK65wajs270dhPLzWWPlgj5mQXfVmDXImikCIjPidxofX2ur50qe8SBpXJL5QVEsicxbrwTLdHc+Slr+i2q6gMHCmMnnLqhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=epxiku7ZWiB4qpaX3a0yXA8UDG6iVgNHB+Tl2WHrTfM=; b=WgSdZbapb1wGOqtjMC2fPKU1Cdr+qtgzYp1CcVaCU4/H6x5fLoZ0mQL6TiOLuM9+HgNNve5xWBHPokW8Eth9C4GFTtbJE5SfIDtLBqrKmKg7yzyLuezDXFnOyTDX/PbHJAYBTkMP+BzIBCuGbShdHqSdv5RkRHPP9QpqH0v5J2ChH8u6OvctJ5VmKO/IQD4Vs5Ol/I6BoFmt7+NSWijCEtYgHGi9mhm2IztWOEhJvOezGlXF09gxvB8PT3ID/ZV6G1NW6V7viU/OZR66Ck9deLJEzi2JP7V83SFDMoDPfaADr/Wz/6HFKCcWAIgSfPx5YbACwDarty131PzseAR4dg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=epxiku7ZWiB4qpaX3a0yXA8UDG6iVgNHB+Tl2WHrTfM=; b=NfqYGtk/7ILxmhUt8/+hMWLrNNUxLe1eePL3zoEItIX0uN+fBowCKU/lMfB6p5OT7w2iguuNp4Wdxw10OpWXCq7CUq2kXrf8ZGxLrO9begZHGOTNOyVZkjBz5034GEUsw5bJYiC+sKlNK4gbfjCyzm7RwKPXSmR/ZtnoS9IGXWFkeEvE+tqPz+C8XxKyJLAJqyxKEICkT7scZ367hnf2YNdZBAFXvPCYhQl0MD7jYQx72P4gMXmv3/zovg7dvrlzSlegOlZOzdd8159Q25CMwzsmLGVdYMAtXzGMaqi+apydfUVnCpUJdOGL4NXtcLEhNUoPfPJ/dMDi12MeUppEEA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 23/32] hw/arm/smmuv3-accel: Introduce common helper for veventq read Date: Tue, 19 May 2026 11:37:01 +0100 Message-ID: <20260519103727.899332-24-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE31:EE_|SA0PR12MB4431:EE_ X-MS-Office365-Filtering-Correlation-Id: 5dd94279-49b3-417d-35d3-08deb592fdc6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|1800799024|36860700016|18002099003|3023799003|56012099003|22082099003|11063799006; X-Microsoft-Antispam-Message-Info: 0LhHb7szm2DeE8P2tdAJsElpx4NfTv/lr0vQgNN/t3geR9p1BIR+DqhLQm9frJZCTGp2Z9uf3fOf6mUehmWsh+bm6NgMP6axEOT8iGOQfio+Mnt0qinmnkaF1AGxEYKA93abdp0GIDca1Q0pqttN9jehECLcjrNhGUhSVC4MF5g8C5YP25wHiqxVDJaQ6OVGdoOFS/oV2JgTKCnq/wN8nfBxhmJRceEM3fz/JA8bme4ElCsl6IKwt/Ztks9vcdElwm+3iUPtTiabBh9DfsLYsHqluyBRBa1rq+rJ20D04NG9qnfcerGNnP+hYUFftfUvg0RtlQ4WBDqCDNqo5AUMuWAn11kCbVcM/GkttAn8CHWh67U3LOIR72hVT374L/9PU+cJ4PjqsdJh/1LmLXomRHDx20bPAWRzj5hIGJoUFyPg5rvsLOaJATBTLFqsThEUBEleIdE0zTBpNRkqS2x+kSw9/n5nXHbDfo67QbYv9bEiHKa7KpW5Hu3gCfaSAygNm5PTPXowG/e2S/nchAWMenQy5s9CkyxmYjJkH5OygVD3eobK9A/rc7c8+sj+PB3Ky8Sfzglbv9yH2kOTLtC9SPfuJLZq79UBlY1Su7M3wY4DR6Xqy7Or4OSAZyg5igRHAschTmhB342Uqs59iaykGvEypvgsxWvHA548yah56KclreT2MpwxHbc/L7Bwe9ctmwznmh7Sy+F95R/W24B+uwuSgBKUjBTsX7nhApmBdpk= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(1800799024)(36860700016)(18002099003)(3023799003)(56012099003)(22082099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: h35ZVrkP8eNkCTDabbVyJs2y1v8LEu04l9XczUy4mYFX0O7sjmunehfjOOPoyFNIxassoStTUGEO/WtoBqCR4R3zYqlDlz3rKsicT+XZ5/rj1o9yGiFu6ZNbKTbwHbJ+YACmAr5SblT8mqqCMtHXfdeCyXaVQvCwVCJK7T7QQsFx+t15NQU+959POpqx7y3WFfCGcS01ZjIkDycoq5ufGnF/8x1oq2u5O8GEoz1C8hgs1Uj0uFYU1cNJNF1yHmQOx7f9psCJc0ksoezOv8r9Zj0YY2RUZCUDMnfMz79VfVNpyJa8w1ZDZAk2I+vr0sp9WLNVRefPNKwm1Enu/kzl5ZZZm9Bh/yTkLtFVAkze0TdmSoNGV8NUdFBZoRgXaJJI76M7bCTPj/N9D17uY9hMt0SMUYhEtJG6KI8y7ahVg6poQmunWS8B4eNTSYPjC54w X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:05.8938 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5dd94279-49b3-417d-35d3-08deb592fdc6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4431 Received-SPF: permerror client-ip=2a01:111:f403:c111::9; envelope-from=skolothumtho@nvidia.com; helo=DM5PR21CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187267447154100 Content-Type: text/plain; charset="utf-8" Move the vEVENTQ read and validation logic into a common helper smmuv3_accel_event_read_validate(). The helper performs the read(), checks for overflow and short reads, validates the sequence number, and updates the sequence state. This helper can be reused for Tegra241 CMDQV vEVENTQ support in a subsequent patch. Error handling is slightly adjusted: instead of reporting errors directly in the read handler, the helper now returns errors via Error **. Sequence gaps are reported as warnings. Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 2 ++ hw/arm/smmuv3-accel-stubs.c | 7 ++++ hw/arm/smmuv3-accel.c | 67 ++++++++++++++++++++++--------------- 3 files changed, 49 insertions(+), 27 deletions(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 49c10535cf..241639ec8e 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -88,6 +88,8 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, Error **errp); void smmuv3_accel_idr_override(SMMUv3State *s); bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index 70cef66966..9e6c44a282 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -47,6 +47,13 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **= errp) return true; } =20 +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) +{ + return true; +} + + void smmuv3_accel_reset(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 202b1aedd9..acc0ca5251 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -440,47 +440,60 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void= *cmd, SMMUDevice *sdev, sizeof(Cmd), &entry_num, cmd, errp); } =20 -static void smmuv3_accel_event_read(void *opaque) +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) { - SMMUv3State *s =3D opaque; - IOMMUFDVeventq *veventq =3D s->s_accel->veventq; - struct { - struct iommufd_vevent_header hdr; - struct iommu_vevent_arm_smmuv3 vevent; - } buf; - enum iommu_veventq_type type =3D IOMMU_VEVENTQ_TYPE_ARM_SMMUV3; - uint32_t id =3D veventq->veventq_id; uint32_t last_seq =3D veventq->last_event_seq; + uint32_t id =3D veventq->veventq_id; + struct iommufd_vevent_header *hdr; ssize_t bytes; =20 - bytes =3D read(veventq->veventq_fd, &buf, sizeof(buf)); + bytes =3D read(veventq->veventq_fd, buf, size); if (bytes <=3D 0) { if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { - return; + return true; } - error_report_once("vEVENTQ(type %u id %u): read failed (%m)", type= , id); - return; + error_setg(errp, "vEVENTQ(type %u id %u): read failed (%m)", type,= id); + return false; } - - if (bytes =3D=3D sizeof(buf.hdr) && - (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { - error_report_once("vEVENTQ(type %u id %u): overflowed", type, id); + hdr =3D (struct iommufd_vevent_header *)buf; + if (bytes =3D=3D sizeof(*hdr) && + (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { + error_setg(errp, "vEVENTQ(type %u id %u): overflowed", type, id); veventq->event_start =3D false; - return; + return false; } - if (bytes < sizeof(buf)) { - error_report_once("vEVENTQ(type %u id %u): short read(%zd/%zd byte= s)", - type, id, bytes, sizeof(buf)); - return; + if (bytes < size) { + error_setg(errp, "vEVENTQ(type %u id %u): short read(%zd/%zd bytes= )", + type, id, bytes, size); + return false; } - /* Check sequence in hdr for lost events if any */ - if (veventq->event_start && (buf.hdr.sequence - last_seq !=3D 1)) { - error_report_once("vEVENTQ(type %u id %u): lost %u event(s)", - type, id, buf.hdr.sequence - last_seq - 1); + if (veventq->event_start && (hdr->sequence - last_seq !=3D 1)) { + warn_report("vEVENTQ(type %u id %u): lost %u event(s)", + type, id, hdr->sequence - last_seq - 1); } - veventq->last_event_seq =3D buf.hdr.sequence; + veventq->last_event_seq =3D hdr->sequence; veventq->event_start =3D true; + return true; +} + +static void smmuv3_accel_event_read(void *opaque) +{ + SMMUv3State *s =3D opaque; + IOMMUFDVeventq *veventq =3D s->s_accel->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_arm_smmuv3 vevent; + } buf; + Error *local_err =3D NULL; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, &= buf, + sizeof(buf), &local_err)) { + warn_report_err_once(local_err); + return; + } smmuv3_propagate_event(s, (Evt *)&buf.vevent); } =20 --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187277821699.0206631301858; Tue, 19 May 2026 03:41:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsD-00025q-LD; Tue, 19 May 2026 06:40:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHs5-0001Xy-61; Tue, 19 May 2026 06:40:24 -0400 Received: from mail-eastus2azlp170110003.outbound.protection.outlook.com ([2a01:111:f403:c110::3] helo=BN8PR05CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHs3-0006os-2i; Tue, 19 May 2026 06:40:20 -0400 Received: from PH8P221CA0065.NAMP221.PROD.OUTLOOK.COM (2603:10b6:510:349::13) by SA1PR12MB8641.namprd12.prod.outlook.com (2603:10b6:806:388::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Tue, 19 May 2026 10:40:10 +0000 Received: from CY4PEPF0000EE34.namprd05.prod.outlook.com (2603:10b6:510:349:cafe::4f) by PH8P221CA0065.outlook.office365.com (2603:10b6:510:349::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:10 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE34.mail.protection.outlook.com (10.167.242.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:54 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:50 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=RDy2p/5oriD0Z6kOIcVTnSPJfww9Jqhlbtgu5T+DD0+WGaehwkf+PF8ysIi17WtUDxBBvuWgb99T5TyEFTK9r24TgRAZEcL+Kg9HTdtwSvrz1VdjnFsEQlOhTgVA88WVC46k5sZSK1weymi+dbSnwoDHhHGE1YFsnGPIhERd20qjJ9FvVcwcOAl5Fahw38rbcbmdYJ9bS9NoHCzSwqLpURCohyIm18KEHsmPfwLgOjLvmUjKxsem1cofmNz7/1TGOPhb0BbuZPpzMfu6f4NZZWwByJeunSObSU2RV9Y3g74qjK82BmwfS3OmhYIaqAc5HGiHDV/FsvlQhWdFC9/OOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iDAPFbAwQn10+HRzAiO1cVUV7k+stA7dzwN9jGpVpew=; b=UyGVWIcSMmqckxMn0y1GgG4uAdwTdhuB6M8TRDEAwU6HCFiCTvwoDRusLAw2Sg8Pae9JnRkfbtQy4POa8FoCJ6veU3l5PkpHq5mMCoPOBvMYTPdjPz6CravNp9J7iYb+qlkGUp1GewynxpCAg+LBake/ctgvwNQiNL47EAzINmjtJJEsJUfCUQzVo4TnPq8+9owJrQveNsHvXAirJAYhbRH0dhSWcgb1RePGD46hLUU3JcKPh1IhMjNlFSd919zobsf7ZtXvCU0rs22ZLTlMWo45hUPIBz0oqNgbkYT2lPHkMw5umk/slZkGcCYUOqv8rjWG15Nsxe+sIcePYQupuw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iDAPFbAwQn10+HRzAiO1cVUV7k+stA7dzwN9jGpVpew=; b=aNB7wmwUXVj/Y2P/INxRbEuxPWlQEYd+3HItwF107Esfo/fwLK5m3kHVy+L7mZs9Dw5m99Pf3NR1Ey/p3H9Fs11WmiJZAiqU/9uZ7lsiORwqGI14x5txaUx4pHWXtZlsOWNgl42AGJEPDF3GtQN747aLGEXdWDkIrcpu863mxUugmxlJLrdC5FP/OfpWPaj3eKZ24/VPlQT+yTwUCAC1viPepDNsMRLGOZ1xoZOVjSi+W6z9QNlqQ+tIGYIwO1DMmWcPD0eKTASbXb80/2e4GhKzNkLBv6uAwCpptKArhgm3ejXllZ3vBTENRvZXO+0VDrcu46RwpIhAwPJomzZwdQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 24/32] hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors Date: Tue, 19 May 2026 11:37:02 +0100 Message-ID: <20260519103727.899332-25-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE34:EE_|SA1PR12MB8641:EE_ X-MS-Office365-Filtering-Correlation-Id: 39403801-4ab0-46fe-15e5-08deb593005a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700016|376014|11063799006|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: ImNjWAgwT7tBV7DKGg2/+QtxbH/sgF0RFrWPnRHVcm0uQDWvcENQjWV4EtJC7y0ZMVxDlSqn1uLaCqaBKhkiarxFL3ikQ8gbglY9+tfUKv60rG+8yPvptyuRSBgUiF2CkHY3UXsFzEOmOIJV78mEdmAONtPV2/jDEGhXCQKSrkE3PSqN0Z34Hk1BejRuSpmy/ZpRlv/dGa/6bAMmD6Hm/7wktW0PWTOkfeztdm2I1Ci4Lmew3aeWFtF4sXmL6R6Pqn/uM9uJdqzjYZMtbKuKtnmohGziisKprWXCSy2loyRTr2UyfqQqHeKVMs25IunU2u/DeDQK3NE4sd0jOQRXvY1pRe5vZSUNH87A2ir//3Kei12w9pXgaku0rrpmTUey88W9wRZ79rzIpDHsKNDQZE8MP23nQPjatE81RozCxpckuk68Tv7x5gZVKny8/DWlJVNff8OOpqofSa4RkM8FZ/ySMRz70jTneWBeji2JshJyalZqevQ6oIELcJgFBZQYn8Pfb9Lb/0LJnRfmOq7UGOojdOJ/n03cWiI16pIteeB14N8x+gvHz3qTtYPEHznI4louro3zQUEG3NRAkI+myQB3Vp07N400RJbhnZeC/q1PvQNvqJcPhq1hM8WHz0/dGVLXTsXSvlj7Gwj5lqVC+1To3idn6x2jxBDL20IFjiyi1uTvzVv5mu2S9JAavjfzjUHvxqXexqzAedhZUACCvhoAUbMNzg06BX03tDLabJ4= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(11063799006)(56012099003)(22082099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kQUmXAjuJeDZ8H22GKgD/X94K9Wyqh9LNaT0XlWyWLkRUQQKvBfnRw6W7nsL6V+JTt014kfMcDL2M1HH4jD+J8UY32Ffu7cFokcKlqG5cOzMuEYJGTmEVZi1PBG9hfBoZGmAw1l7Qik1ceRRd1Su2aVDraudqAUGE4WQRJPTkK1qiFskOc2X10KJASi63n9WntXBEZRKnsIIKMa2KLqtYZfLFE4quPJ+nXpg4oz8zT0PMlQ/Pdo0P5ezid14LEwES4yesFiJYX/4BX8nb5LEkiGRYHWzfRMTOXAYuSLRUT2VwKUgUgcFX2Jinvz4QXt8CPkt2aWx7sJIfZh6kC3nDUgdIynTo5DcVFCvSdkD09Tev/fbqtIXf4bfFGpkg6piPYhCL2Zk+slksRZmPWDUZHZy+78AYDooXVCll23nvZuo7yXLzuQmvZbTsOEXYwnk X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:10.2503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39403801-4ab0-46fe-15e5-08deb593005a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE34.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8641 Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=skolothumtho@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187278110158500 Content-Type: text/plain; charset="utf-8" Install an event handler on the CMDQV vEVENTQ fd to read and propagate host received CMDQV errors to the guest. The handler runs in QEMU's main loop, using a non-blocking fd registered via qemu_set_fd_handler(). Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 60 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 2 files changed, 61 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 853c548e58..0bba2c1801 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -14,6 +14,7 @@ =20 #include "hw/arm/smmuv3.h" #include "hw/arm/smmuv3-common.h" +#include "hw/core/irq.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" #include "trace.h" @@ -736,6 +737,48 @@ out: trace_tegra241_cmdqv_write_mmio(offset, value, size); } =20 +static void tegra241_cmdqv_event_read(void *opaque) +{ + Tegra241CMDQV *cmdqv =3D opaque; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_tegra241_cmdqv vevent; + } buf; + Error *local_err =3D NULL; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQ= V, + &buf, sizeof(buf), &local_err)) { + warn_report_err_once(local_err); + return; + } + + if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) { + cmdqv->vintf_cmdq_err_map[0] =3D + extract64(buf.vevent.lvcmdq_err_map[0], 0, 32); + cmdqv->vintf_cmdq_err_map[1] =3D + extract64(buf.vevent.lvcmdq_err_map[0], 32, 32); + cmdqv->vintf_cmdq_err_map[2] =3D + extract64(buf.vevent.lvcmdq_err_map[1], 0, 32); + cmdqv->vintf_cmdq_err_map[3] =3D + extract64(buf.vevent.lvcmdq_err_map[1], 32, 32); + /* + * CMDQV_CMDQ_ERR_MAP and VINTF0_LVCMDQ_ERR_MAP are distinct + * registers (different MMIO offsets). With only VINTF0 exposed + * they carry the same data, so mirror. + */ + for (int i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D cmdqv->vintf_cmdq_err_map[i]; + } + cmdqv->vi_err_map[0] |=3D 0x1; + qemu_irq_pulse(cmdqv->irq); + trace_tegra241_cmdqv_err_map( + cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2], + cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]); + } +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { SMMUv3AccelState *accel =3D s->s_accel; @@ -747,6 +790,7 @@ static void tegra241_cmdqv_free_viommu(SMMUv3State *s) return; } if (veventq) { + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); close(veventq->veventq_fd); iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id); g_free(veventq); @@ -762,6 +806,7 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; uint32_t viommu_id, veventq_id, veventq_fd; IOMMUFDVeventq *veventq; + int flags; =20 if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, @@ -780,14 +825,29 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMU= DeviceIOMMUFD *idev, goto free_viommu; } =20 + flags =3D fcntl(veventq_fd, F_GETFL); + if (flags < 0) { + error_setg(errp, "Failed to get flags for vEVENTQ fd"); + goto free_veventq; + } + if (fcntl(veventq_fd, F_SETFL, O_NONBLOCK | flags) < 0) { + error_setg(errp, "Failed to set O_NONBLOCK on vEVENTQ fd"); + goto free_veventq; + } + veventq =3D g_new(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; cmdqv->veventq =3D veventq; =20 + /* Set up event handler for veventq fd */ + qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, cmdqv= ); *out_viommu_id =3D viommu_id; return true; =20 +free_veventq: + close(veventq_fd); + iommufd_backend_free_id(idev->iommufd, veventq_id); free_viommu: iommufd_backend_free_id(idev->iommufd, viommu_id); return false; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c4262bb2be..5afbceee83 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -75,6 +75,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS # tegra241-cmdqv tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" tegra241_cmdqv_read_vcmdq_page0(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page0 offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_read_vcmdq_page1(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page1 offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_write_vcmdq_page0(int index, uint64_t offset0, uint64_t val= ) "vcmdq[%d] page0 offset0: 0x%"PRIx64" val: 0x%"PRIx64 --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187269561625.4694783953411; Tue, 19 May 2026 03:41:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsD-00027P-QF; Tue, 19 May 2026 06:40:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHs5-0001Z0-JA; Tue, 19 May 2026 06:40:24 -0400 Received: from mail-northcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c105::7] helo=CH4PR04CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHs3-0006py-Nx; Tue, 19 May 2026 06:40:21 -0400 Received: from PH8PR07CA0025.namprd07.prod.outlook.com (2603:10b6:510:2cf::13) by DS0PR12MB8573.namprd12.prod.outlook.com (2603:10b6:8:162::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Tue, 19 May 2026 10:40:12 +0000 Received: from CY4PEPF0000EE36.namprd05.prod.outlook.com (2603:10b6:510:2cf:cafe::9b) by PH8PR07CA0025.outlook.office365.com (2603:10b6:510:2cf::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.25.25 via Frontend Transport; Tue, 19 May 2026 10:40:12 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:12 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:58 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:55 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EWR+dGEUAKrMgjHAgQB+n71vYEnqnKPk6xb4K4slvUEuJR/E7acRyKy+1ruCtNG5hOyJ6IJqmr5ko3jDbZd5xhVbUa97lK9DOpl/uRKvssvfDO0Gf29QesS7j0/SU4CkaUMK3dlaOkq30cYPbO3B6Id9KSnB5f7tg6rE3Ols1tG6C6N9kNFPLoK6cY1p4QQpBQgL3r9MIFDzBXDwhNCh1e4ZCeMHCGlKb1U3eVw9XPV+bpYpxnNCezPfOaarMTOXC/LOwil7XbvUdob5KSeezZT6m9u1kKZjt/6EEkcDdCH4JZB8EdHEcje7ajAGzOazAEUYa4xJqgYUlo7E4bVD6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0/8Cs8dQH28IaPOUtRU0YY97g0cieILZpAHtOk5Kwzs=; b=LANHgP0FbklhtLTPfpHxl4O9hKZvzdCkyGwc2bsIkI0VJTBzQ8jHFa0YpRGs4UPip1CJybv9sXOC0dd9H32AWHhhU/vdBGfvTClXWYJHZ71gNRIbh4WzTCs5nPOUC9NrtRzg2+6ZjuH73CzOQKo7OAUOoeKpX3qLwN9RTGwI06VLfS+FY2ewwSWmbogpnB9nSlzFsECSCqqwOrAqjyZzQh8Oy0ULcnzP4DcSo2klmhGLNubtkq2O6Hj+rQPU1xSwbR3dsxGdkAZiJbzzi/v32x+FV3WBIvabK170ZunsTYssaOXmJMESib0lyaYHe0A784TXA6wwXSw3GQkE44JMwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0/8Cs8dQH28IaPOUtRU0YY97g0cieILZpAHtOk5Kwzs=; b=hi7r7vKlzd2xqWjHp5A7cqJmOe6JCEaP/mO1pyzKzklbA4Yp5Xl1ROpTvi8u7vzoALDGSAI1WgOJXd6RU0tccvDy3r+NMhnOR3iK2TvdowxpTQsGQj9VKbhRP2QI0uaF0dEtZk1kAzuskqJaOYrV9B84E/mM+78xw5+SzaY5thSwbzUs/V2OHB832/YF5gohgFtNYITQEunpE7WqWFWQCPA3FtKGePJkO1MYOw/bTs8ZbaWtwC/ST3SV0E01P54pIW2/E6P7+msdIXgTMdUT59NG+2DHZ4NaytoF4t3KoeKb8e69veSlmBKK4BfWNSslaPmY4JvueVkh4Uo6+D8zwQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 25/32] hw/arm/tegra241-cmdqv: Add reset handler Date: Tue, 19 May 2026 11:37:03 +0100 Message-ID: <20260519103727.899332-26-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|DS0PR12MB8573:EE_ X-MS-Office365-Filtering-Correlation-Id: be661d41-e175-4d88-2805-08deb59301b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700016|22082099003|56012099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: 0QDzhWZ5FuigErRyQ0HUqcQTQl72RrzDM53Qa1PZTwoifLpqWZtW+qRTCzLtJYeSgQ0des/UwuDLqBCg7qCMHeL48NhBP67cwK+aWbkRsNlJYs6x+09sWIElgDB/6/a/1NRDr6SHPnO5fjIPBzCo7zQh1286edigPFnTI1Tr57yOSi1Uol21Bb4pAD50u0m4Fz9xp/pXE00uu8tt2mdxuPrPLdgoftOi+4GSz6scTedfw0jYG73BJTOOPw+HsSRu+2UqSolS3r4raTvenpbqYnmXb6mik92r5EjNmJdyYNAyXVhPbXaOweJHFG797zyxSv3+T/CRrsOfnLZ/2xADMO0T3lH9WvWnBLfNeifZCOkYwBNOVzj/nMziZrGrenvcKDbjad3g3aqxqimgxZgeAJayd4LbPXLV4pv7w6/VP3R1k/IqIAAblJMm65YCpus2tUXc5m5U8P1f0MdvEbwJ06vKb3QFCE35ZETLquCd1p4lrwfJn8J8Odta66PSD2zpedKuH+hugzQ07fa9bOtJ1N4wYSSRF6HD9nmzNYuV/gBlyVahcAmdscVYDG5vLWpncGsQ1NnDinp3SDqtDAqfIoZAxcHgDmDtxBtrY1uPHZ+w584+87KNNXnr9OBZobR3AxVYaf3njkP9Gw3hQkY9hCevHjRq/924M+FMVgntaPIGIOHQ508knKKSq0x4LTeV02g/MURoZ8Jjyvn608KhZABqO36f3RxE0NJKBpqRbA0= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(22082099003)(56012099003)(18002099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jzYGpGkjS35wJOBdQW16sR8lg3+cAhzxfJlKZ4c+Vbl/MRPPKqxaig9EEYqQgBk+j/VDE+7EJmKOZbKRrvt2V74d3Ye2q+dAdBrFAw9jhZStryx/L5hkf8lMtbeYTymtNT3dgn8Ezz6iyIVbfsX2TFPZOECKobqwLaGXMk3Rgag8jqBgbQxHGoexkj2OiSL94qW2F+qM+E6ESEgBieqEyolxoBeKdbRGe1peg4xxMUAkwolP7iKLOo7cVXVnoKtQF/GB5wTMtfXkIIAw+2KVW2W4I7p8Llcr/kdIlVfFeCBydd99aujIDl5HQKAu8bEZiUS9YhMOhuS6MfX9ONWGObbODmUgBKA9xl6tuWzlt4YAmY0iyfYfuRxoICm2oi6iT24G53xVkytgSZW3H240ziq5DIRzW00TrBbQv0WPKvyS75vE3NyAvLCo123dZT5L X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:12.5413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be661d41-e175-4d88-2805-08deb59301b6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8573 Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=skolothumtho@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187271410154100 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Introduce a reset handler for the Tegra241 CMDQV and initialize its register state. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/tegra241-cmdqv.h | 3 +++ hw/arm/tegra241-cmdqv.c | 48 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 3 files changed, 52 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index e9e1933a19..34cb5efb84 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -87,6 +87,9 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) FIELD(CONFIG, CONS_DRAM_EN, 20, 1) =20 +/* CMDQV_EN=3D1, PER_CMD_OFFSET=3D16B, CLK_BATCH=3D256, CMD_BATCH=3D32. */ +#define V_CONFIG_RESET 0x00020083 + REG32(PARAM, 0x4) FIELD(PARAM, CMDQV_VER, 0, 4) FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 0bba2c1801..ad64f06260 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -853,8 +853,56 @@ free_viommu: return false; } =20 +static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) +{ + int i; + + cmdqv->config =3D V_CONFIG_RESET; + cmdqv->param =3D FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2, + CMDQV_NUM_CMDQ_LOG2); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VI_= LOG2, + CMDQV_NUM_SID_PER_VI_LOG2); + trace_tegra241_cmdqv_init_regs(cmdqv->param); + cmdqv->status =3D R_STATUS_CMDQV_ENABLED_MASK; + + for (i =3D 0; i < 2; i++) { + cmdqv->vi_err_map[i] =3D 0; + cmdqv->vi_int_mask[i] =3D 0; + } + for (i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D 0; + cmdqv->vintf_cmdq_err_map[i] =3D 0; + } + cmdqv->vintf_config =3D 0; + cmdqv->vintf_status =3D 0; + for (i =3D 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) { + cmdqv->cmdq_alloc_map[i] =3D 0; + cmdqv->vcmdq_cons_indx[i] =3D 0; + cmdqv->vcmdq_prod_indx[i] =3D 0; + cmdqv->vcmdq_config[i] =3D 0; + cmdqv->vcmdq_status[i] =3D 0; + cmdqv->vcmdq_gerror[i] =3D 0; + cmdqv->vcmdq_gerrorn[i] =3D 0; + cmdqv->vcmdq_base[i] =3D 0; + cmdqv->vcmdq_cons_indx_base[i] =3D 0; + } +} + static void tegra241_cmdqv_reset(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + + if (!cmdqv) { + return; + } + + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); + tegra241_cmdqv_munmap_vintf_page0(cmdqv, NULL); + tegra241_cmdqv_free_all_vcmdq(cmdqv); + + tegra241_cmdqv_init_regs(s, cmdqv); } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 5afbceee83..5ebb3dc9ea 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -76,6 +76,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" +tegra241_cmdqv_init_regs(uint32_t param) "hw info received. param: 0x%04X" tegra241_cmdqv_read_vcmdq_page0(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page0 offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_read_vcmdq_page1(int index, uint64_t offset0, uint64_t val)= "vcmdq[%d] page1 offset0: 0x%"PRIx64" val: 0x%"PRIx64 tegra241_cmdqv_write_vcmdq_page0(int index, uint64_t offset0, uint64_t val= ) "vcmdq[%d] page0 offset0: 0x%"PRIx64" val: 0x%"PRIx64 --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1779187334; cv=pass; d=zohomail.com; s=zohoarc; b=N7u+l7ExURLeoe+HvOa2eMac04U3U9ohk2l11fdO+MJ6GNn1WT+b7gB96vM0fHMULMKKgefYKeY6VFDc/LDuml7xSbuIfC95YWupf8WN4YKfvoYa4olV7Nl9eDT4OHWVtmX6Gs0zsF3+MquRNnOU5RwfXcVaZo1CwBKdUwYjgO4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779187334; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Nyy6Xt3WmzNihqPvcBrs0beIQDu+ENLonfXJsLABu/U=; b=CziBilVcCdor4lp16oB3g8lTdcNGYXSCiCkT5mI6RZ72krj9VFZJDMV9oUFgJem9TvA8cnZTgAtJykLJKwXVOGgO7+1VSZrPj8bD/Ta6Cw11oTjLZ//9lHuwfmlMB0w5u9AraPkM69aqBr4kpTRpQ2qHUnbsY10xwcdt4a4nMbc= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187334896390.4881222123935; Tue, 19 May 2026 03:42:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsK-0002ic-NF; Tue, 19 May 2026 06:40:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsE-0002EG-Qc; Tue, 19 May 2026 06:40:30 -0400 Received: from mail-southcentralusazlp170110003.outbound.protection.outlook.com ([2a01:111:f403:c10d::3] helo=SN4PR0501CU005.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsC-0006rg-Qk; Tue, 19 May 2026 06:40:30 -0400 Received: from PH7PR02CA0016.namprd02.prod.outlook.com (2603:10b6:510:33d::15) by MN0PR12MB5787.namprd12.prod.outlook.com (2603:10b6:208:376::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.22; Tue, 19 May 2026 10:40:17 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:33d:cafe::fd) by PH7PR02CA0016.outlook.office365.com (2603:10b6:510:33d::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:17 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:17 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:03 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:39:59 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=s5VFTn0LdUAU1fX66NO+hIUZ7cClayaL4bFTJMCOUOBkV2rpKFgsZD2dhhVUFaNx43CJh8nN0MoQ6994jLxU3g8Dgrb7roZBkQNiotso4BeQmk+UlkKimFJEHJK7RkVCpkCnx/qjFPvK+6gwHRzDlwtZz+G7R4Hw8R0FPtYq08wBE2hGwDBlESDNNSGCLJwOpwOAqNYW16UwXkQJwFCSoUEQOly6Tk42SfWTcEv8F2e/6yHERLhf19cwc0Rqw+8p85nP0uEkya3J4cOT7IAGfmYNREz3hC4o6Xst4RDWV6eZfB7k1qZA1ivP89thjo+UFkSKl3aTwFHdenr3stMMrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Nyy6Xt3WmzNihqPvcBrs0beIQDu+ENLonfXJsLABu/U=; b=WJwQcrXoYxaV1vw+EVbGDZ/FAi3W4VUjh1Y+N90KjAMSZq0yqIKDUlhsaB1WPbRF1h19yLQEdiY2eJJtz5UvP46p1/WuCZjWGGePbCmAIU3dfKjY3eDnRG6U6ZPOA+2UxIKxPKlFmwP74TxAM3NRFwEj7gpIgrWQVwy2viXVq2WbP8nbOcIOuUzCTfUwdJMNnPNsHrGIoZKTlsxBpL8TQMOXZvYUoOtT+KI37JjAIETgczUBO+2/jCieQq7QY+bRcpr+VgldKPkM7y6bY93IqowtEWITFHAXzckvcQTfjxCRUO/GaVv9DFngKNJp5i6p02d3gJVvXew26nz70IfQxg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Nyy6Xt3WmzNihqPvcBrs0beIQDu+ENLonfXJsLABu/U=; b=ShcqTWZVeqPi0vXLmHC6iJk/ddp6IpLH3YzN5SKJqBtDmGaRfePjMH7qGOL2d5yrw6rg8jRnSZoXHzWR3xMia5WEJkaur6B7FYRfDOkxQP6QVZ0aZaW7RGbC9+07w7cb0uWvg5ehTxlmYpegP+3GcwZooYB2ZPfIADGddfZFKD9+9ezQAYsvRq/1vf2Keg0t18rAgebGOAZE7tm3bnTducy17jIEip9RCIDO5hlD7fcqmu6842fMZjKCl/9VrorP+NLE9uaJmWA6pxR42HHPgUl0endbTVMy7uL9H1NeAm1MvR1Mzrt/lkly8cJQL0wHACFH8BLt7T4fgS2x4l3e3g== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , Peter Xu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 26/32] system/physmem: Add qemu_ram_backend_pagesize_min() helper Date: Tue, 19 May 2026 11:37:04 +0100 Message-ID: <20260519103727.899332-27-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|MN0PR12MB5787:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f37f408-9eec-4e52-eb46-08deb593045d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|7416014|36860700016|22082099003|56012099003|11063799006|18002099003; X-Microsoft-Antispam-Message-Info: fkhKHeo8GGbihgb1Y+baU+9yL9zhFH84DkxeWueyKAKyjFlghk9Ksy6Dk7L8qPdcIqDUpL2i41/G1wkd5iOWgMdRcGGvZlJyJHuu7g1XJJ3HlJBSqbQKUKHXI+KR3iXKvATheZIX+PXVxpA9bLPwlgQEpzH87vB1y2d/IpmS+PAFeoJyTgZV0H79hminS+iqcSEMCa75IiFKNO9OET5RJMFPV/DuaMzfYEaMS4QLnN3QEjMWejoTdypRHrrWzZVWIHjKq2+ktwAB9wUqxN4X530nu0vFYStxA/xJywXnZrOGKKpxI62KVjkTrSkL6iRt6xhj7zyF2iYTv1Joj/eXWfqcYupSLNM196pkgC6HaxSYBigFeftupB7ZKDZnuFuoS6YXXYeaXTcCWClzaMstfFfLwAvu8wKZnfHboUEVBhGwcw+cOR1lb7dm1vhhj6cwUA8PB1Td5lzZoY1sjBwgrFZ9YCkveJiadcFJB+6DEq7ImatlAnlO2nQlLQIvOpqPIEl/gIBRooy2+rAK3mW++02w0vWCf8UuvtSMXdcs/NxbEXTwecSJaMfc0kMpceR5QLVdPvXErkNHWfVoVbmWNcYbyt4zUzWEHV2CkjrDpHp1pDL4qNdh8IPQru/5d8LNC6QBJYYZDEhwCMa0EHI0Ec1aat1tgLkIJy7uE/vh7anLG3epi/LWUmkDIQWykeKpPNO62MK5+4QyjVqDdGa/Cx34W2K6fjrTdmREv5Y2spM= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700016)(22082099003)(56012099003)(11063799006)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4NGoBM4IK+LFeA/qA60mD1RYqEjTjnunX/HAn+5bYcto1A9Y8V3et5ox3TLypLxuTMLctVw61S8S5iuPHVVf8Bq20JFimEODTDUkQilvN76XTvM2MMuuI/To3fJoigd8t73idGIbnq1YcehgVi56UgpznqnndIkeAojsLDPUmqhPZKhjqc1dUjiMcq/mcjY9lVrbLTB9xuxUpgZTv+OLZ2/t8tPeY6BCVaL1JmEYOtvN7lV7+pweyYXCmDsSuolSC4k4w/Bhpzw4/nz8erul5Bxnq2OUK4zkS/f92vda31d5T8Y46zd1KIUq6W2XzbDYZ07WpBhElcKelvHYZ3ObxAQ5pa8Hf6QhkBZK9Qoeiov+6sR8j3qwFoG5ec8t78LJDd9WxG05jH4wrZ3RNLIV7QrIKxu2KzO7HhdHPNVMEu5kb01v94a43LJ++NxADV7J X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:17.0346 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f37f408-9eec-4e52-eb46-08deb593045d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5787 Received-SPF: permerror client-ip=2a01:111:f403:c10d::3; envelope-from=skolothumtho@nvidia.com; helo=SN4PR0501CU005.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187336699154100 Some hardware accelerators DMA directly to the host physical address of a guest-resident buffer (e.g. set up via IOMMUFD). The HPA is contiguous only within a single host backing page; a buffer larger than the smallest backing page in use may span non-contiguous host pages and fault. Introduce qemu_ram_backend_pagesize_min(), which returns the smallest page size among RAM regions backed by a memory-backend object. Falls back to qemu_real_host_page_size() if no memory-backend RAM blocks are found. Callers can use this to bound the size of buffers that must remain host-physically contiguous. A subsequent Tegra241 CMDQV support patch will use this to bound the command queue size exposed to the guest. Cc: Peter Xu Cc: "Philippe Mathieu-Daud=C3=A9" Signed-off-by: Shameer Kolothum --- include/system/ramblock.h | 1 + system/physmem.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/system/ramblock.h b/include/system/ramblock.h index 4435f8d55f..7f7ea53557 100644 --- a/include/system/ramblock.h +++ b/include/system/ramblock.h @@ -175,6 +175,7 @@ int qemu_ram_get_fd(const RAMBlock *rb); =20 size_t qemu_ram_pagesize(const RAMBlock *block); size_t qemu_ram_pagesize_largest(void); +size_t qemu_ram_backend_pagesize_min(void); #include "exec/target_page.h" #include "exec/hwaddr.h" =20 diff --git a/system/physmem.c b/system/physmem.c index 46b36c7b10..7ccec52aa2 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -1999,6 +1999,35 @@ size_t qemu_ram_pagesize_largest(void) return largest; } =20 +/* + * Returns the smallest page size among RAM regions backed by a + * memory-backend object. Falls back to qemu_real_host_page_size() if no + * memory-backend RAM blocks are found. + */ +size_t qemu_ram_backend_pagesize_min(void) +{ + RAMBlock *rb; + size_t pg, min_pg =3D SIZE_MAX; + + RAMBLOCK_FOREACH(rb) { + MemoryRegion *mr =3D rb->mr; + + if (!mr || !memory_region_is_ram(mr)) { + continue; + } + if (!object_dynamic_cast(mr->owner, TYPE_MEMORY_BACKEND)) { + continue; + } + + pg =3D qemu_ram_pagesize(rb); + if (pg && pg < min_pg) { + min_pg =3D pg; + } + } + + return (min_pg =3D=3D SIZE_MAX) ? qemu_real_host_page_size() : min_pg; +} + static int memory_try_enable_merging(void *addr, size_t len) { if (!machine_mem_merge(current_machine)) { --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187351867949.5216489586845; Tue, 19 May 2026 03:42:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsQ-0003L8-OS; Tue, 19 May 2026 06:40:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsO-00035b-64; Tue, 19 May 2026 06:40:40 -0400 Received: from mail-eastusazlp170120007.outbound.protection.outlook.com ([2a01:111:f403:c101::7] helo=BL0PR03CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsK-0006zp-Bd; Tue, 19 May 2026 06:40:39 -0400 Received: from BL1PR13CA0412.namprd13.prod.outlook.com (2603:10b6:208:2c2::27) by DM4PR12MB9071.namprd12.prod.outlook.com (2603:10b6:8:bd::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.21; Tue, 19 May 2026 10:40:28 +0000 Received: from BL02EPF0001A104.namprd05.prod.outlook.com (2603:10b6:208:2c2:cafe::5e) by BL1PR13CA0412.outlook.office365.com (2603:10b6:208:2c2::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.15 via Frontend Transport; Tue, 19 May 2026 10:40:28 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A104.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:28 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:12 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:09 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jU4O7ocqfVVFRCeIdT7o1FG43IDyDfSb71S8d33QqueY0X8FFtB/GcfSSmhegEkLa53s9oya5PbkSLEgkNbw07ipzK15Riq6VIjEiGBiVXKVE4C6TR6SNDdvA9kvC/dGgLvBp4htfRyTn797Vb6qX2h/SR3a7MIzNpGv3MDU1Rd2g4cm2v/g0kvi9C2/HteMIzPaunaOKkq19Cf+Gsk2X6J6id04SksB5Le9dlf30moRZrwQsfC/rMbFAlY9AS7TM5Wp65adyq/Y3OUvYlioa77spI099CRgSia/OPfwS1ALvvtMLbQLCTkgWhE20DFqxH9OO6rmoGUpPom1jONhFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SSaGvrM8fYfRhbGGYEAfBvuAcXdrUP/9EQaZx+Shsdk=; b=FSWxoYjoXYmaU1w38/FVnET5/ibPBGJYBsbWu2f8a9ZLs9t8ttB+5m37ACA37qOUkBmpTTmDCDbLUyvT08cgjWOAJLL7D3YJpqY1nSuCU2zNJ5rM5AWKT5xbeZLPyLFuGiuREeSWBY/7qE1O+/CGiXYT0sO4p43/3xpRgeltjzlb+KS6M/5gN4FFPM54NIctpXoLwt1MletntC4LFpwD/Qa4tIL+8DnzyjoFIfOI62sUF8ZFl/pDABya4JIsfkHXSNrHk4DPT46vJ6dcQuxE5Sg6KW1k5BvE8WW4z3DVfjqfvQjhYSp+AZX1KDJJQdolzR8yyXxcLDHmDqxYA2CLkA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SSaGvrM8fYfRhbGGYEAfBvuAcXdrUP/9EQaZx+Shsdk=; b=Gh6Wsmc6XSPb9WgsqJ0L2YHLeUpXxGq0fNvgkdtNBeA9b7Rfg1uzRtMizK8EPZrFjCYT8UWv7SImY3qit0ne6I7JaY3yWeMU98zcnFHDt8InpKiHwZFHwwbSnjLOL6uqBx1NN22wJ1Zm1ABgGdYjCuVwYTAyvjcZkgWKzn53BCk+DOIKREoER61rKk6uNleiB/9P0k+cKjQRhKJ/7KHeSMJ4hNFkmNTlgR25+YhMtKt0iuU6M4uz+/fuvGpzyApY4m+XGIOeKNoqOHHdM3uNPgI9/w1qk+vHvVot/37Pequ+iQsVDz+m7qY7icuSDU7XYDXFf/yFqZRQKezmreBuYA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 27/32] hw/arm/tegra241-cmdqv: Limit queue size based on backend page size Date: Tue, 19 May 2026 11:37:05 +0100 Message-ID: <20260519103727.899332-28-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|DM4PR12MB9071:EE_ X-MS-Office365-Filtering-Correlation-Id: f3f6fd75-66e3-4069-722c-08deb5930b18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|56012099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: fcXT46zhGDRp5e1gtcDajozqesB+wzx0w5Pugmw2aBq4IUctl+e1rwbreUMtTQ6ZUDdgi+6EtH/mD/4RPIPjy+iolNUfHMxbKsnHYRu6DazvjGsW+FRHgrvxC3bOfYjH529QShok99LcmjosMh5kh14zabB7VRbCN8NnXz6eaHHeYeGlUwAsrVBqf6NKy6YQTByj/kr1oHbAyuwHveyNfsyCU4t8Yo5aRwZux7/8pmsreADLPtJZAntzZHoX9Jo4bZ6WC0vim2SkaZuw49DonnXPGYph3T2wvKak+CNTATwaqO6sbEpED+1f81/izFtSGAxMk+5Rh24NcEhrIU0Qiu8yJFiGF9LqmpfcnfSfl4HaLa+LqPK21YVDLk1VFAJTIMErzI0ulRweZfr7rwk48GHxhkLMnlPsFjN3AZxtWRfghviid3blL3djeOicQMKCxUdOu2HomIfMNIMXOSm8QvDqI13C+BJqzODE28FmabyQ4mvL9h/0Y564k706eKXRoSS/TGU/x5QaeIFYzJnLctOh/pbSXY5d9vD/EK1vypcKrCqU2oggjdVD9ub2VGXpauN5Yuphvco1VU9RkLWLMYN5Hlud9ilTsW1GogYwOxkYSESIx827kpDf6JBiPbPWznN13HPRVqrqFgl5rpGBFTGnxaZtE4sljLEQXThUMAMD98JM+BPYj8aRi3CV+LYbFkU3sVjBCFFt2IRdyVbFyxPw6IEF6kgUFlRsH/zpjWo= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(56012099003)(18002099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: o+4EIp69DlnSKepy6LWH3LHNSKTObhsxhcVSksPOfgRrHqlCZ6Bf2h6WFOwGWDD4LNiAqOIIeli1wmFUJ/hdfSKYcDq1ni/pxlkWyvYBX83hBzgTs+4Wll8HfjPjcvIkhMr7uduDW8mvasWtosXXr6e4yFEV5yCeZvkc1EMjNiyy//nUh12HwjiTsTL89Q+s84TJtK6QHJPQ7mkLG4mx+OqBKkidTbUt7KNnmEy/BAuz3XHh60gPsbndXyAF/sQydMI/3D9rstUEUkHenWbgqJ6jp8sD9Jf4OeMXRY4yvphxBdEPnRJ0FOGNvn3g/p/6deo/pnalv0HF1XKo6E/0nlKwjRxUeEKkfhD/leDb2JHhEhyrXqrjoxlvdKGUPunGvVhVpTeec2C+5Tp21KdPA/FKyu2Yhdt1pFHB10Yl+raf2SqAkXpRk/t4/BP3vpjQ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:28.2202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3f6fd75-66e3-4069-722c-08deb5930b18 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB9071 Received-SPF: permerror client-ip=2a01:111:f403:c101::7; envelope-from=skolothumtho@nvidia.com; helo=BL0PR03CU003.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187352533158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen CMDQV HW reads guest queue memory by its host physical address set up via IOMMUFD. This requires the guest queue to be contiguous in both guest PA and host PA space. With Tegra241 CMDQV enabled, we must only advertise a command queue size (CMDQS) that the host can safely back with physically contiguous memory. Allowing a queue size larger than the host page size could cause the hardware to DMA across page boundaries, leading to faults. Use qemu_ram_backend_pagesize_min() to find the smallest memory- backend page size in use, then cap IDR1.CMDQS so the guest cannot configure a command queue that exceeds that contiguous backing. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ad64f06260..7f617bcc97 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -16,6 +16,8 @@ #include "hw/arm/smmuv3-common.h" #include "hw/core/irq.h" #include "smmuv3-accel.h" +#include "smmuv3-internal.h" +#include "system/ramblock.h" #include "tegra241-cmdqv.h" #include "trace.h" =20 @@ -856,6 +858,8 @@ free_viommu: static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) { int i; + size_t pgsize; + uint32_t val; =20 cmdqv->config =3D V_CONFIG_RESET; cmdqv->param =3D FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER); @@ -887,6 +891,19 @@ static void tegra241_cmdqv_init_regs(SMMUv3State *s, T= egra241CMDQV *cmdqv) cmdqv->vcmdq_base[i] =3D 0; cmdqv->vcmdq_cons_indx_base[i] =3D 0; } + + /* + * CMDQ must not cross a physical RAM backend page. Adjust CMDQS so the + * queue fits entirely within the smallest backend page size, ensuring + * the command queue is physically contiguous in host memory. + * + * IDR1.CMDQS =3D log2(max_qsz) - entry_shift + * + * where entry_shift =3D 4 (each CMDQ entry is 16 bytes =3D 2^4). + */ + pgsize =3D qemu_ram_backend_pagesize_min(); + val =3D FIELD_EX32(s->idr[1], IDR1, CMDQS); + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, MIN(ctz64(pgsize) - 4= , val)); } =20 static void tegra241_cmdqv_reset(SMMUv3State *s) --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187266964476.0528068460484; Tue, 19 May 2026 03:41:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsf-0004QV-LW; Tue, 19 May 2026 06:40:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsT-0003cQ-A1; Tue, 19 May 2026 06:40:47 -0400 Received: from mail-centralusazlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c111::5] helo=DM1PR04CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsQ-00079D-OW; Tue, 19 May 2026 06:40:44 -0400 Received: from BL0PR0102CA0062.prod.exchangelabs.com (2603:10b6:208:25::39) by DS0PR12MB8573.namprd12.prod.outlook.com (2603:10b6:8:162::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Tue, 19 May 2026 10:40:35 +0000 Received: from BL02EPF0001A106.namprd05.prod.outlook.com (2603:10b6:208:25:cafe::6) by BL0PR0102CA0062.outlook.office365.com (2603:10b6:208:25::39) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:34 +0000 Received: from mail.nvidia.com (216.228.117.161) by BL02EPF0001A106.mail.protection.outlook.com (10.167.241.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:34 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:17 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:14 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=STLJDIzIG3LpbWooWBTVExxx/+R7f63uvZ2u+USiP2ruREAEL5NfqO2Guyc6d2t/iem4syhiIQ2FY9bcDjgAonM3Uh7BiyZzkbfEq7PUc0Bpd8JSusnh8lHRrRB+kPzwcsNfj1bm91TjUM60hzv+2KUK/oN+3niZNAItV3/rKjYuYjB+sFhRxFuzl/L2qwfuAp+JDseVPpxD6LW4hJB+kc/QGXoK47qaanc56DRPOsdpqQfEWNk2T8sFtrz8AE8GljNNM8vtCuXdkBSmRE6Sen/zc2hyXdWtAFqp1NVT5cK7Au742ngZpalh9NaXURt6JdvWY8Sj3m9QlSz73nq/Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9FPth/J5ZGFeEsP4pYdNaqbTjB3ZaQrOotMzkOox/HM=; b=h958LBvhBMsCOAOeJxy/NYIjlkwtG2v1SVyMhI7942vz3fyotsk3xQup+odx+EyVHMLefiVs5HGpM7oNvR9t7rImZHoduGRxjWyTqOmrwh9E74KpNESXMnR2AqPsXVlGYiyEaVoNexOGX+7lgYEa9+HqoheD9C0wfedqEkBd9E4ULmv/fyPFBPq6/n4QhDe6ctUH+XYKMfZ5REyZ+o2tkEBZyA61jll2Pi4/+e63pG1RqQvLpX4zh+Ojt6m50vawE4n3oyATS82FeBLTM+YXg31uCvXDPlWBRN63ZaUNa/pA7WNgaSp1RIbNcFZ9fiasJV4mi/mVLV5QQUrRHGmMmA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9FPth/J5ZGFeEsP4pYdNaqbTjB3ZaQrOotMzkOox/HM=; b=ZML+9sAbjKfn7C8j/2lgLwdQS9ua9tR0jf6SdT5POeu81YXvBrbvm2mX9Y7OOkYRImI/GJxEqZV5R95gFjJmmkxDbe8ZBHm5ags9BhxYhz9kUvUhdjVIYMl0giixxmJV2ozaiD3dmIcCdDjs+c8EstpKeTLH7xEZnPQR6NIreBADcj75b4owGr4gRcBOH2WuDtfVEInaI5p0zWbKCDuCGRUzK8bX8Bo3txJ3YywMDE4yhioNChl4v1kKqPvI3ie4TEWOKT3Q4ub5SjcKTs6rEyuy0LCod6KSLZY4D+3T4Dfs/x7CbzILj7a4BQOScnS/lNJ309KBrdF2pV6u3qE/zw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 28/32] hw/arm/smmuv3: Add per-device identifier property Date: Tue, 19 May 2026 11:37:06 +0100 Message-ID: <20260519103727.899332-29-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A106:EE_|DS0PR12MB8573:EE_ X-MS-Office365-Filtering-Correlation-Id: edc90e19-a1c8-4697-c3bd-08deb5930ee5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700016|22082099003|56012099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: XCkpE2dx+wIt2SeP7kibASjOkn2X2yuEMwU+biz9kkmC/hZj7lW81XReBsWpuDY00KQYQn+zqjV3GdbwFPOGAa6bP4gL3Crpp48SqbJltFWHJ5+87IB2KtgX0izFJaM8GVow+8YY/wwwufNqbXm3aK3rWcaWYUOLER272WKMkiviVBNTfqSUS9qjqA5bGRee9CqSTHew0ljfBHJ2tCgrLa9xfJ45cva0eAzwEWzLnDi2MZEzqtrWjDP/cwW9RphmYxKT3WAfdEP9oxOepJRo8zpGchpTbPu60FvMcuyOGn5ZdlrSm0QGR4XlFgAWkqKf1Hg76WYNxMLdqMxPzbYoDQjZmbrjSw9zZhzh3pzFK//Cof3tgm3Rp2cn+1L08eD8fPh6zdI3ezoJ3BEOj90OK7ZdTx1t7eiMLQm8gcZUa/XRdYShWe7X+vk9a1lBnHQppboIfaSZVKGXsVrvdU2HaqMyRef0mLawJ1eJLYMo/fXVDjdo2a2Y23+5RTeCRcekMi4rJmtrXtK2qMAb51Mz3CfDJLXHw8IknU23R2c84l4lcWPwVL4yuLu0yenkJ24yZBXNWUVJYb3PIZsrzjl87oI9gC5MHNsI+p90719CbFX0M2jCgFpRAP/TD0JbxcdH8Go6lW+RB6gMFc0EBt5TmnfXdiV4AyLSGZu/i37cT57Jff9UJQ7kHS74ejNKjxfk34AvVlypGTU+rFlJ0VgJi6NVFB1CDksnMu4SXObUKSw= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(22082099003)(56012099003)(18002099003)(11063799006); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +wyBYbA0dFFHNPij81zFfMMNR8emOldaQqg49Y+zmX+Hs5P0rBVrJBj+eBhLpDogdy+xkVxajPdFmH8ba/ZJZgWRfj/Krd1RCC40agnXdLAiN4OYwdr70/Z2shnUVoc/rBn7UA+kw5jGPHrFlW3EcsQ09G+bltXwx0M86Gk/mzQqKNPoU6lb3Q6K4ybio5qJ2tSsk3jWq6DRpCZLY+MqZZ/GrOa98hkH7XppGyjSb2M480c0JZQDcavnpA+Dnp6+UTeVVdmF7+qNHgRharUeUj6m0WcmUEgGPfx0Wy7s3cxeNtrRu5AH07aD1Zc/5M+jqyOH7VTR+aeAWVCTbJ79hRFaiehMAMKpYSc6qMBTEJehW2ZCTQoeIupVy9usKu7mfxozwVdOzTQLwQrndSj7z1fdKCHSOPUMhm0qNouD1X0Lo+lHMLUaMj8L7iBmUP3v X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:34.6049 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: edc90e19-a1c8-4697-c3bd-08deb5930ee5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A106.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8573 Received-SPF: permerror client-ip=2a01:111:f403:c111::5; envelope-from=skolothumtho@nvidia.com; helo=DM1PR04CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187268118158500 Content-Type: text/plain; charset="utf-8" Add an "identifier" property to the SMMUv3 device and use it when building the ACPI IORT SMMUv3 node Identifier field. This avoids relying on device enumeration order and provides a stable per-device identifier. A subsequent patch will use the same identifier when generating the DSDT description for Tegra241 CMDQV, ensuring that the IORT and DSDT entries refer to the same SMMUv3 instance. The identifier is assigned at pre-plug time, accounting for the ITS Group node that build_iort() places before SMMUv3 nodes in the IORT table, so that identifiers are globally unique across all IORT nodes. No functional change: IORT blob content for bios-tables qtest is identical to before. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- include/hw/arm/smmuv3.h | 1 + hw/arm/smmuv3.c | 2 ++ hw/arm/virt-acpi-build.c | 5 ++++- hw/arm/virt.c | 12 ++++++++++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index aa6a79237a..0fce564619 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -64,6 +64,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + uint8_t identifier; =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 665e6a2538..763b86c417 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2126,6 +2126,8 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* Identifier used for ACPI IORT SMMUv3 (and DSDT for CMDQV) generatio= n */ + DEFINE_PROP_UINT8("identifier", SMMUv3State, identifier, 0), DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b00f3477ca..9d05982137 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -349,6 +349,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpo= inter b) typedef struct AcpiIortSMMUv3Dev { int irq; hwaddr base; + uint8_t id; GArray *rc_smmu_idmaps; /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; @@ -411,6 +412,7 @@ static int populate_smmuv3_dev(VirtMachineState *vms, G= Array *sdev_blob) &error_abort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); + sdev.id =3D object_property_get_uint(obj, "identifier", &error_abo= rt); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -637,7 +639,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); build_append_int_noprefix(table_data, node_size, 2); /* Length */ build_append_int_noprefix(table_data, 4, 1); /* Revision */ - build_append_int_noprefix(table_data, id++, 4); /* Identifier */ + build_append_int_noprefix(table_data, sdev->id, 4); /* Identifier = */ + id++; /* advance shared counter for RC/RMR node uniqueness */ /* Number of ID mappings */ build_append_int_noprefix(table_data, smmu_mapping_count, 4); /* Reference to ID Array */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2add7401a1..d8d27f2ef6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -254,6 +254,9 @@ static MemMapEntry extended_memmap[] =3D { /* Any CXL Fixed memory windows come here */ }; =20 +/* Counts SMMUv3 devices plugged; used to assign stable IORT identifiers */ +static uint8_t smmuv3_dev_id; + static const int a15irqmap[] =3D { [VIRT_UART0] =3D 1, [VIRT_RTC] =3D 2, @@ -3830,6 +3833,15 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, OBJECT(vms->sysmem), NULL); object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem), NULL); + /* + * In build_iort(), the ITS node(id=3D0) precedes SMMUv3 nodes + * when present. Account for it so this SMMUv3's identifier + * is globally unique across all IORT nodes. + */ + uint8_t its_offset =3D (vms->msi_controller =3D=3D VIRT_MSI_CT= RL_ITS) + ? 1 : 0; + object_property_set_uint(OBJECT(dev), "identifier", + its_offset + smmuv3_dev_id++, NULL); } if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { hwaddr db_start =3D 0; --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187290808201.40694608826732; Tue, 19 May 2026 03:41:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsi-0004oq-Ha; Tue, 19 May 2026 06:41:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsc-0004IR-Nm; Tue, 19 May 2026 06:40:56 -0400 Received: from mail-westcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c112::7] helo=CY3PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsa-0007Nl-5Z; Tue, 19 May 2026 06:40:54 -0400 Received: from PH8PR07CA0034.namprd07.prod.outlook.com (2603:10b6:510:2cf::15) by DM4PR12MB6039.namprd12.prod.outlook.com (2603:10b6:8:aa::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Tue, 19 May 2026 10:40:42 +0000 Received: from CY4PEPF0000EE36.namprd05.prod.outlook.com (2603:10b6:510:2cf:cafe::bd) by PH8PR07CA0034.outlook.office365.com (2603:10b6:510:2cf::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:41 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:22 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:18 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=YuoSGpOJfnqCqy3pe/o4KfRGxsWsk/lJuZ8ALoB47gjv/tI0O5ocjvzmY7H28706VxjpJkhud8syPfmiOioiRlCnMxAjZyG/L1Pyc8/IghkSLVcVpKJ9lutxse7oIKeXLOjIeuxojVzgFAfBPJlo4a0qGs1QCO/aS/5QIu/wfJ6KRS8BhoaIEqfCHBxaADOvM3ZCIRzkkR9dxhBURdpP6mfTJJXylmE/3u/SexUIdgeGmtebUnEWZ9CZYINwJnQZfIzRDZut17L7uLazGRVBB07ypgHRiVQR26QTCUqd+oadWRXhf09qomm7+Ow8ipl+H4LRtu+C91F6cu0TjRpOkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=csnaU1L1lmT41Vlcpt1LTf0U7LQSrClrSWBlpVr47Gw=; b=COevizZLYwX6iISpL4qv6DxZCROAL5xwu63CaYvVdo5NfZMu2v7ma/70Ux/0CGldEfwEsHIM7SWaEdX389/p7jjatbJ4dXmlSunRpnVHu6gTZSvSk51X4T55LpKsl1cRPOOoYfG+ofQUPx2iB6naAp5Emr9/14O3gqt9J6O7KGghKPDERCwjpIMqC63Fqh8Te7A88O/8ueQPR1mT6JVN9OwChINQ6rX13meAn93jBS4dRq4063Faj3D0ClII7f+IYSL5ejy4sb8+xz7J2GylBhgfZYYRzCpGl/LJw1oRdVTMLbDC7kguJWhjbk2aM7XMvsGT122cYVdTWzbeVsdbxA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=csnaU1L1lmT41Vlcpt1LTf0U7LQSrClrSWBlpVr47Gw=; b=eeyK2la5cAQBiO3+rd+DP5One8YEzXULLAKZRh44Zt88BA0UBPq8Uxbhyf+zDoSho6pWtf3nnloJiYD4TI2GybOzlhgf6aim4s84UXk/nRNq7TC/UbwamZeex9AIIF7NbJ+VtWpiIVqPaYP515zc9PbzVfuthAOyCBmVTOldoK3xp3/pNpVhHSFV4amJiHVmN4s2ZY/vBbh1MihH4/H0EwvKQmSIRltoeNnCcka2RjicKCJMD+aohft5dw+oxkSoSgq1UBqFVG7RQ+K0QepLcYJ8FLmH5wsyudApVbOYv5F2VS2iVwTkFz18ON5yfXwQuQhasBgpufR5sHhzkawS/A== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 29/32] hw/arm/smmuv3-accel: Introduce helper to query CMDQV type Date: Tue, 19 May 2026 11:37:07 +0100 Message-ID: <20260519103727.899332-30-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|DM4PR12MB6039:EE_ X-MS-Office365-Filtering-Correlation-Id: c648c5c4-3ebc-4f2e-de03-08deb593131e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|376014|82310400026|11063799006|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: 0TyooU6VO8eiL7oRq0Q7dtkUANrxB2NXM+gAeb0NL06hlWNgo+7En5iJc+aEfBrUgsTTqnnohdM2aqQCWLYQpEHc82N7b7NKfL/Pw1cXGsQ2pUG+HahNv1h9zzXn1rr84rNw3KEVs6QqUrIHIIqiqMxmiu0Uybh7bMvrQVr4p38bsJ0sRAMSFiFWk82N5VU/zEOS3WsFYzyYhvL9IAC4PENg235TCYFWawMMXJs91AkOcja043qXr89oCvrx2hR0W5rcXGkl7GceeR6SRmnK5qwf8cJGQvvDKkuMqE2sgL2z+/6+TgqpAHOdMNfSrvu7JDKnfXtV7iT0aOQQcP00UApvQyYRYEkQIvMHfl5xEhS/WadTzk5LRgb2URNmX8DiISXjuegrzk4epjQr2kbnvHeO/mtDUNfPwpmW0sO/J7W10DWaXNOxAe2RyjO36fJ5hAbrSeqV0kntnJvrkXtZr8QYFhsiHTY0O0aZlxlL+q+rvcXe+4daIAPbdZCgjxaX9mEdTeTSyujfbinkScNMtlzVwCWLn80Y23UlhSqR6o2/7vs4OHglRM/mDnBn7hvBQNXDlPlmd2F6Nq+y7XD6x6OMgqE4SdyrfUNKQgIZGSfDA73lV5RnFCjnPoK5YuBisWfwroi2U2AV3L+s+s+DsoNRC2ZUM37QZtOl9CBabKYVZetLdwPVU12iXdoHgUz30Qv09hWB3t0hKaDKTcwDhHi+eBCFZZJduumpb5zw2ao= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700016)(1800799024)(376014)(82310400026)(11063799006)(18002099003)(22082099003)(56012099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: X+AiB2c6r0QGzd5bEERDJT2ZvQcTH8ickMyGnMr/J7Gy1U4hdlxOeWf+ONaW2GTkjnum0kmn3OzoUMyfQzGSWkapE17iiB3Qw2UJbx3wOcjIlW4cSsLjMxnXjMMA6Co5GDfEEZd5ej5zWmGm3EfobyaWH4/v5h02F7wmv2oGTWMMmGz0r60ocB5XjRQLr3tP+apWjUl1BW0ZYgPcxWtK/Wqw6MRUiaPo5MamkdOYpT2LiZklOLZsqwHyK4jFi/RSxZITTwOXW2TcT4mR20bxLZ2fv2f0UWJOdG0TIo4sig9TZprZMUU9D9IFkyGu/kzkE2oSyxs83t979yMuzG3bLmL6oeWFVudf5Q64IHvRAJWDBf16O/Z296hE9DcxF81ZXW3A9YgAHWToXUSFXZhFJYBOrJoro1DBp28/G7XlIKsbMgTKY2IH9EWdfZIqmrSR X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:41.7407 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c648c5c4-3ebc-4f2e-de03-08deb593131e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6039 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=skolothumtho@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187291931154100 Content-Type: text/plain; charset="utf-8" Introduce a SMMUv3AccelCmdqvType enum and a helper to query the CMDQV implementation type associated with an accelerated SMMUv3 instance. A subsequent patch will use this helper when generating the Tegra241 CMDQV DSDT. Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 10 ++++++++++ hw/arm/smmuv3-accel-stubs.c | 5 +++++ hw/arm/smmuv3-accel.c | 12 ++++++++++++ hw/arm/tegra241-cmdqv.c | 6 ++++++ 4 files changed, 33 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 241639ec8e..8cf35c2936 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -16,6 +16,11 @@ #include #endif =20 +typedef enum SMMUv3AccelCmdqvType { + SMMUV3_CMDQV_NONE =3D 0, + SMMUV3_CMDQV_TEGRA241, +} SMMUv3AccelCmdqvType; + /* * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to * support multiple VCMDQs with virtualization capabilities. @@ -43,6 +48,10 @@ typedef struct SMMUv3AccelCmdqvOps { * If NULL, the viommu_id is freed directly via iommufd_backend_free_i= d(). */ void (*free_viommu)(SMMUv3State *s); + /** + * @get_type: Optional callback. Return the CMDQV implementation type. + */ + SMMUv3AccelCmdqvType (*get_type)(void); /** * @reset: Optional callback. Reset CMDQV state. */ @@ -91,5 +100,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **= errp); bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index 9e6c44a282..147ae06163 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -57,3 +57,8 @@ bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *vev= entq, uint32_t type, void smmuv3_accel_reset(SMMUv3State *s) { } + +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + return SMMUV3_CMDQV_NONE; +} diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index acc0ca5251..dbb50d1795 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -1062,6 +1062,18 @@ static void smmuv3_accel_as_init(SMMUv3State *s) address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); } =20 +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + SMMUv3State *s =3D ARM_SMMUV3(obj); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel || !accel->cmdqv_ops || !accel->cmdqv_ops->get_type) { + return SMMUV3_CMDQV_NONE; + } + + return accel->cmdqv_ops->get_type(); +} + static void smmuv3_machine_done(Notifier *notifier, void *data) { SMMUv3State *s =3D container_of(notifier, SMMUv3State, machine_done); diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 7f617bcc97..fb4301aa7d 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -952,6 +952,11 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error = **errp) return true; } =20 +static SMMUv3AccelCmdqvType tegra241_cmdqv_get_type(void) +{ + return SMMUV3_CMDQV_TEGRA241; +} + static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { @@ -992,6 +997,7 @@ static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D= { .init =3D tegra241_cmdqv_init, .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, .free_viommu =3D tegra241_cmdqv_free_viommu, + .get_type =3D tegra241_cmdqv_get_type, .reset =3D tegra241_cmdqv_reset, }; =20 --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187281184513.8639838165675; Tue, 19 May 2026 03:41:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsp-0005ka-Mb; Tue, 19 May 2026 06:41:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsk-0005C5-Su; Tue, 19 May 2026 06:41:03 -0400 Received: from mail-southcentralusazlp170130001.outbound.protection.outlook.com ([2a01:111:f403:c10c::1] helo=SA9PR02CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHse-0007Qu-GQ; Tue, 19 May 2026 06:41:02 -0400 Received: from PH7PR02CA0013.namprd02.prod.outlook.com (2603:10b6:510:33d::21) by MW6PR12MB8662.namprd12.prod.outlook.com (2603:10b6:303:243::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Tue, 19 May 2026 10:40:47 +0000 Received: from CY4PEPF0000EE30.namprd05.prod.outlook.com (2603:10b6:510:33d:cafe::6b) by PH7PR02CA0013.outlook.office365.com (2603:10b6:510:33d::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:46 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE30.mail.protection.outlook.com (10.167.242.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:46 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:26 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:22 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=F2Krd3/3oYfJffN8C13hnn+WvadK03RlntybwGfzZDdfKBwqLNeew79kgDVIspdkKrgD8xxCg+py7Y5a2a6hqIhz8C603vOxK8J55KmSpXxgT2DlvuoaecPzqqX4zHAcsDLKDBdRL7JzMBW3wAVrKj3lZiUehv6ws+ijuj2lLxklTt3XWs4V2Vif6IxM5ZVlHS7E5ITiJdxhd3ASA74Kmcykr+3QMA7bi0KvUuG5m1cE5YhpfvChMSmGH18S8iZBJcy9bXtrFHqPbmN0LP4G+7+1LgUuQsJQ+kPvWDREqlwjGeIJMANIevQx8Y4QvUd9ND7PD2agQMBSpNgshkFUrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=eeZ+bu+V6j1ip99x3YYyHAtjX7prKsiGal4S/AoTflI=; b=f8XNwthcRDIgBP8mOx8eSIBB1waJzHcgTSZxPOlaHaQJeP4WhzStRCpnn2MVbGY4bpdtqguZKuaSjkA6h242tf118RL5j9i9/7AgcNySQTFdYRah45WjBbZUBRz+UBDg0gDojzaLXsK9k/6rpFqAgcCViies2FXrmzxtAagT6vqqRUc/y5WWOgKRq3uJkJ/IRt1/9s1CI5UUx5La6jJs/RMzu/htQ0P6iGbkLgbIz4fCJ5cTfmrQWuZtM4sDikJhvgGvhXOqahcDM8AqcC7aQC0yWDlgfRYye5slIkil4kPVUykOHAtvoFldHt2TtAicTz9DEi0MMiF45Un9FKKo5g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eeZ+bu+V6j1ip99x3YYyHAtjX7prKsiGal4S/AoTflI=; b=IFYsPaPOl0vDtzzBi8bG0wIvYPa3OLgHJMhss8Spo2+sgNEDB2iHiqXNKbxfsL0/920ZllNbX8JJjM36CbFELhq8PH24vPwnJgXNTzGAKRuMmzypW5buIAAm+/AUtKO1lB62oXm1+ToThfbnPmPc9f9RK7T/kpR/ozeBLILR2adt5yziuUSqhMH40D5txhlniQNzpufs4L6c8q0ALcLYcK+Gp0jIT4fFhlFa775zw+w98AwEW7eeaUjoe58MqWD6yoXryeAzmk4YuF0on71axUxxw4rxiCe4Kk7fUruN35hzAd6NmfQ9bL9C0GLQ9OxFCC9QwcsMW/J7GxNc67TLSg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 30/32] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT Date: Tue, 19 May 2026 11:37:08 +0100 Message-ID: <20260519103727.899332-31-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE30:EE_|MW6PR12MB8662:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ea6190a-b184-4a8e-f2a0-08deb59315f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|82310400026|36860700016|11063799006|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: jFg8w+kIt2QOng/qG4Cm0rzO664gnn9CF/HD8Jre9SeIkx2gaBu2JOgBxweyi2PFwSKD/CuwuQUutIBX99f1acV96ctXy61KJ8IZukhQp6+1jwB1LhGE57bAhlAr3t4fjaD73EiqQczDPcs6+Cy7msneHR8ozyrdYQ0bjZCnygXqh0Mw9aZcdsTvXa2vCaWaVzuiPEGfXYCegf+nZVrsVcj3nomZAzuh5YlOpYOnZTTHfhicA47JnB+Q4neCq9vjdkKcz8IvlZ0XsfQfZeZQofL3qvwbKzQEmgYSXSjs6U4BqDsXP3yE0q4K47qEgXepNr6a1uySdKzzG/VPm7rT3y1HbygteSFXDfC172u2WbxOfDHDlQ5C5GXGcT1cJv3DfSNNtrZ6XsMQ8K8R+IYuNLeCl8pFMfzDOKKdLfe92SLrLFUTour/9c5whw4VyO4MhXnEV1dE1/q2jhlxmoV2fizvtn4iByXBcdu6jREKl8mfjZjNDUjihg2NLH3P0LwvDogd7qbpTc2ePm5eD1nSyG5esAPvYrMJboM+Q0rP0E0iME5ev78jg5azGjFUGuTmy+vUZW+YtMofyiIsXfPRGBddNlyld1tmIGgGjs1Css6QvRlPvp02z4iNFnjqjOxDpPnJ6WA6Z4YQYlUegpTdxIYaaDSU3PBiTYPge132FltWk4aJq+TPo3AolgDXfEh6c6Otbc0zp2pxr+uAr++0CWHj4u3kXVWK9KvV5xky6gU= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(11063799006)(56012099003)(18002099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uAAk9S59J95IOACtyDLEAVg9K1iY47OF6s7K/96Co3D2xDe0SdBYNePhm+hWdkBszy+wEYECPSqS7pzJ8ZRCcoKCvZGo2ktEoP3sPMb88PE73B6XhmEHY835tilKj5tin3eAzxLLiDyO8mgvAE5LSF66r3rlo32knex4gyMvlNGPWMwf60Wbt80g0wSRXCRhtV4VcKNmhwj3vdckKN/0dBqxGG/knslD/vJsJRbpms4b/TM5rJOYUG0qRGIMCvTNZUydP+10TPR1qx+7F64dGQQy3nLmkrzCHnHER2DNPHgRK5TGlifUbfvYIejCbX2yJCfbWrglbLIltj4s/Lh868RRUSmoRfRZTbaQ/Fuz/zDRCg5j/4aGg4CJDkkNOLroc8HtU3VPJIu2l3Q5K2xSOTIpJ9liljOktTrkigFJA+pjP35AvQ9WBewOVN+ETApF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:46.4805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ea6190a-b184-4a8e-f2a0-08deb59315f1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8662 Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=skolothumtho@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187282212158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is created with tegra241-cmdqv. For each accelerated SMMUv3 instance, add a Tegra241 CMDQV device object under the DSDT \_SB namespace, with HID "NVDA200C" and a UID that matches the Identifier of the corresponding SMMUv3 IORT node, so the guest OS can associate the DSDT device with the right SMMU. The _CRS covers the CMDQV MMIO aperture plus its interrupt, and _CCA declares I/O cache coherency. See ACPI Specification 6.5, Section 6 (Device Configuration) for _HID/_UID/_CCA/_CRS. Generated DSDT entry for a CMDQV instance paired with SMMUv3 Identifier=3D1: ... Device (CV01) { Name (_HID, "NVDA200C") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cac= heable, ReadWrite, 0x0000000000000000, // Granularity 0x000000000C080000, // Range Minimum 0x000000000C0CFFFF, // Range Maximum 0x0000000000000000, // Translation Offset 0x0000000000050000, // Length ,, , AddressRangeMemory, TypeStatic) Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) { 0x00000094, } }) } ... Generated IORT SMMUv3 node (Identifier =3D 1): ... [048h 0072 001h] Type : 04 [049h 0073 002h] Length : 0058 [04Bh 0075 001h] Revision : 04 [04Ch 0076 004h] Identifier : 00000001 [050h 0080 004h] Mapping Count : 00000001 [054h 0084 004h] Mapping Offset : 00000044 ... Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/virt-acpi-build.c | 52 ++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 2 files changed, 53 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9d05982137..99490aa7b1 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -65,6 +65,9 @@ #include "target/arm/cpu.h" #include "target/arm/multiprocessing.h" =20 +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + #define ARM_SPI_BASE 32 =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -1121,6 +1124,51 @@ static void build_fadt_rev6(GArray *table_data, BIOS= Linker *linker, build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); } =20 +static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + PlatformBusDevice *pbus; + Aml *dev, *crs, *addr; + SysBusDevice *sbdev; + hwaddr base; + uint32_t id; + int irq; + + if (smmuv3_accel_cmdqv_type(obj) !=3D SMMUV3_CMDQV_TEGRA241) { + continue; + } + id =3D object_property_get_uint(obj, "identifier", &error_abort); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + base =3D platform_bus_get_mmio_addr(pbus, sbdev, 1); + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq =3D platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS); + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + irq +=3D ARM_SPI_BASE; + + dev =3D aml_device("CV%.02u", id); + aml_append(dev, aml_name_decl("_HID", aml_string("NVDA200C"))); + aml_append(dev, aml_name_decl("_UID", aml_int(id))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + crs =3D aml_resource_template(); + addr =3D aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_F= IXED, + AML_CACHEABLE, AML_READ_WRITE, 0x0, base, + base + TEGRA241_CMDQV_IO_LEN - 0x1, 0x0, + TEGRA241_CMDQV_IO_LEN); + aml_append(crs, addr); + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE, + AML_ACTIVE_HIGH, AML_EXCLUSIVE, + (uint32_t *)&irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + + trace_virt_acpi_dsdt_tegra241_cmdqv(id, base, irq); + } +} + /* DSDT */ static void build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -1185,6 +1233,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, V= irtMachineState *vms) acpi_dsdt_add_tpm(scope, vms); #endif =20 + if (!vms->legacy_smmuv3_present) { + acpi_dsdt_add_tegra241_cmdqv(scope, vms); + } + aml_append(dsdt, scope); =20 pci0_scope =3D aml_scope("\\_SB.PCI0"); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 5ebb3dc9ea..e49a2b324d 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -9,6 +9,7 @@ omap1_lpg_led(const char *onoff) "omap1 LPG: LED is %s" =20 # virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." +virt_acpi_dsdt_tegra241_cmdqv(int smmu_id, uint64_t base, uint32_t irq) "D= SDT: add cmdqv node for (id=3D%d), base=3D0x%" PRIx64 ", irq=3D%d" =20 # smmu-common.c smmu_add_mr(const char *name) "%s" --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187297483275.60417042611266; Tue, 19 May 2026 03:41:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHso-0005Wf-6A; Tue, 19 May 2026 06:41:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsk-000599-H0; Tue, 19 May 2026 06:41:02 -0400 Received: from mail-westus2azlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c005::5] helo=CO1PR03CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsf-0007T1-3y; Tue, 19 May 2026 06:41:02 -0400 Received: from CYXP220CA0011.NAMP220.PROD.OUTLOOK.COM (2603:10b6:930:ee::14) by SA1PR12MB7442.namprd12.prod.outlook.com (2603:10b6:806:2b5::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.21; Tue, 19 May 2026 10:40:50 +0000 Received: from CY4PEPF0000EE35.namprd05.prod.outlook.com (2603:10b6:930:ee:cafe::d6) by CYXP220CA0011.outlook.office365.com (2603:10b6:930:ee::14) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:50 +0000 Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE35.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:50 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:30 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:26 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=eyfRkDWXzk0oLm4oXKx7oGOv6G1uZ7wbceKOWLg7yx3lXbCQU3imUUGknQkswRNr4cowv5hbJ4/ppHgox2SuDuOk71QrNaQkbclyc0AJaAlWYNzqRaKl1H9iqcYgp+Sz5OGleXl/Y/0HmFAy/Cg4L+JZ9+ouqBMRVfKw9NjkhfxCbJqbjWJ7MihHg41N9laauMeQuonsJVOxPcKNB1hJ3lLAT56EWVRz2E/YmPRKfRtUb21UN361ZsxIOG76JQmqv2Wo5mkj2vJ03VpdKFU10o91kDaEcKdLEggMju6MbS13T6hHt5Yei22NzXihM26vPEhHHLjVlOi5PzmuvQ7lkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QN0D18HZCD69yGnIKM2WtBzzjkDTLY++aS7GScREmzw=; b=iTyFp08TUsWFWlltzR416Mi12GUsw0AQGwfFHuGUnLQS53JGJOMrxpJx1/cuLuY9bGveq8j3YGH9kZhOUi31GSmjip+qjtmI+F80botbXyucE5v0UutIATQdRAEw9PBSZTeki9oowqPkIZya7/XEDlgVXqAOmYXWyOip4n3CrpWQ6W04j3dQKcOWHwCWxioWnGGliYmMu6wQBNEkTP9POV9DnN6GdNrSi+zDnOZacy31UdJKSwU5krdUpDHuJgHIjsp4aDFX9YBfnglye0aJ+oUkLHgATMbkU6zpi8rIqwKXNjqjZYwql3sQ557aIqshPv9opoUXSGhDEXPGQOYDYA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QN0D18HZCD69yGnIKM2WtBzzjkDTLY++aS7GScREmzw=; b=iHezbeV6Wav+sWU6klWXITxwa2qqDI3LRIxlfwPAWkdN8gAYCO2ANoCfwjOnHOBPe6jzeBAIq+6tEJi6h8PdQv64SYNckCkpXyxJnX/9OpQEdb6j7PsXie3cuByjFMttv/1/RmikFO9Q6u4l36y8Ng5v6pW3F9vBVPHl6YVXbsvppOXMryWyyTWGATYGxPcM3DO43WAYmJKHGSKbf1ow7W8G9NEJbk4wj5d8V4jUO5KlAjJWYdKMNP6w/GqDN97p/+uY9GDt1DaAhmJaNmUmirQBvBTcAXh7BH1bVJxw1J2U5jjYd1yhZBDMBThWoatpcg4Gacjh+CgfyYFl1cbccA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 31/32] hw/arm/smmuv3-accel: Enforce viommu association when CMDQV is active Date: Tue, 19 May 2026 11:37:09 +0100 Message-ID: <20260519103727.899332-32-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE35:EE_|SA1PR12MB7442:EE_ X-MS-Office365-Filtering-Correlation-Id: b6d64f71-a660-4735-af7d-08deb5931862 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700016|82310400026|11063799006|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: mdEbbz5exxRp1My4Jx6kzErpqHlEC6a+t52xM1tTV26doajSSUh/tChOTBxVuxSa2v2G6u+wk3PtsAl5agHIwumCnmOki5lipYxvdVuipx/giprwZtNiSX8WlFLYztHQu6tItZYnzQ5wYriyrWVllW3HQrnbMOYLmHqOPCk7jvC5MB+gGn4KamgHd7xNRH99axNu18T9ip1q5U5ZZPJFh0yaaAI13ZVDCe8Sj9YtFRetPjhcwvEQ3Q4Jn4WRdscyDkFMrW5MmdxjpgwUNMOB/a1sxe4v12Hqi9rq4AoKOQIvLfuNI3ZOQmNeb+Tebq7fJ86A3azBtYE6T5BWaEOmniwDC9+nGxY3hsrxWpZn0IAaNJFzi6w8c95SS8N7FU59zFKixrE9eAVpYwYMl9rLAOiirU9kqhTC2EJJTRMJAUA2/5OXlZYZ5QZaK1/7sZVseS2SEPrDrlzjImGGBQLqdiBogfUmzlAEWGPXhAcPoivR71c7l851xRohKH2qfFA37e7/aOjpjTfQxffFmhAwKqu/O3+QbL6jGWBwY2LM2EbxzmdosygxehlIBUe4ZgMykwOuCOt5V5gf4i5WIz33ZlGizj93verjNojZauorMbOeSTuGX9Xmy/Nq7YLw77eacTPJvMbjuIFFtgqWWIcWrd7QfgY4MktFxhFisLunrOJigy7GyHT4Vm/2DpAV5ZOfKVgYo/jb4MFXmvW/jGVK50ZkiqRCebOciMkKpPEOROQ= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(11063799006)(56012099003)(18002099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8/PYkDLiOE4+4A0Q1f/O4rOQi0YueAPEJl8MPZmVV4JEftBfL9inC3Nydd+XKV+7xdnMCCk5wISbvCuoXqfZKIXg/148sZ3+1TPPw06LMZnQBeL+dGkIvTfdw0EefuxN3do33/2lf1CVcpK7Z7I8I1xtdk5Ab8kmtHcXxz/VhRL6Un7oItGULmsp3+VULeG+Bk1VHfalO9kUUwIKdWdOrdoEAJ9r767mLHWis/leJiBFktTdjuTo2S4ArXBQkahiI3gNJDWRUrA6PzCwN2M9yQAfsYlLNGnqZsNMjN1BfwHRrr8bnD+l3ZbFxA1dWaWOVVN9S+MZk54gqarhpHSdsnpzYEvyooQyFpgRz6FOhaBvBXFCwmmKySLy3bUKQZ9A6yVN2fgwAxk7mNlhuqKHvjivyEumzfitiXQjnLXhlehL2ayA+s0IwdeDSHvT7C/M X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:50.5769 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6d64f71-a660-4735-af7d-08deb5931862 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7442 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187299987154100 Content-Type: text/plain; charset="utf-8" When CMDQV is active, the first cold-plugged VFIO device establishes the viommu to host SMMUv3 association. Block its hot-unplug to preserve this association and the guest's boot time CMDQV configuration. Also abort at machine_done if cmdqv=3Don is requested but no cold-plugged VFIO device was present to initialize it. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 1 + hw/arm/smmuv3-accel.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 8cf35c2936..4d05eb100a 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -85,6 +85,7 @@ typedef struct SMMUv3AccelDevice { IOMMUFDVdev *vdev; QLIST_ENTRY(SMMUv3AccelDevice) next; SMMUv3AccelState *s_accel; + Error *unplug_blocker; /* set when CMDQV is active to block hot-unplug= */ } SMMUv3AccelDevice; =20 bool smmuv3_accel_init(SMMUv3State *s, Error **errp); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index dbb50d1795..03575808b3 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -761,6 +761,18 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, return false; } =20 + /* + * CMDQV is active: block hot-unplug of the device that established the + * viommu association. Removing it would cause the vIOMMU to host SMMU= v3 + * association be changed via device hot-plug. + */ + if (s->s_accel->cmdqv_ops) { + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); + error_setg(&accel_dev->unplug_blocker, + "CMDQV is active: removing the device that established = the " + "viommu association would break the guest CMDQV"); + qdev_add_unplug_blocker(DEVICE(pdev), accel_dev->unplug_blocker); + } done: accel_dev->hiodi =3D hiodi; accel_dev->s_accel =3D s->s_accel; @@ -1088,6 +1100,12 @@ static void smmuv3_machine_done(Notifier *notifier, = void *data) "at least one cold-plugged VFIO device"); exit(1); } + + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON && !accel->cmdqv) { + error_report("arm-smmuv3 cmdqv=3Don requires at least one cold-plu= gged " + "VFIO device"); + exit(1); + } } =20 bool smmuv3_accel_init(SMMUv3State *s, Error **errp) --=20 2.43.0 From nobody Sat May 30 18:34:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=pass(p=reject dis=none) header.from=nvidia.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779187287932167.22334763823255; Tue, 19 May 2026 03:41:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPHsr-000614-GH; Tue, 19 May 2026 06:41:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHso-0005as-7d; Tue, 19 May 2026 06:41:06 -0400 Received: from mail-northcentralusazlp170120005.outbound.protection.outlook.com ([2a01:111:f403:c105::5] helo=CH5PR02CU005.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPHsj-0007XC-6d; Tue, 19 May 2026 06:41:05 -0400 Received: from BN9PR03CA0359.namprd03.prod.outlook.com (2603:10b6:408:f6::34) by DS0PR12MB6485.namprd12.prod.outlook.com (2603:10b6:8:c6::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.25.18; Tue, 19 May 2026 10:40:53 +0000 Received: from BN1PEPF00004685.namprd03.prod.outlook.com (2603:10b6:408:f6:cafe::98) by BN9PR03CA0359.outlook.office365.com (2603:10b6:408:f6::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Tue, 19 May 2026 10:40:53 +0000 Received: from mail.nvidia.com (216.228.117.160) by BN1PEPF00004685.mail.protection.outlook.com (10.167.243.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Tue, 19 May 2026 10:40:53 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:34 -0700 Received: from NV-2Y5XW94.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 19 May 2026 03:40:31 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nPYek8X9P4Dhe8sGfKooBkyW77o+Es4w7kyvcRTIO4/paxeBzFaSi2sv8e4UxoaQ6LYouFEV5tgSdM541fmgNH1a8BxhT8uythH6iduh1Xkyr1zK8YF9yBCUyFhkg28XtIbDvmM1fsedKfPll2RE9WlapFtZM5iRE18pu4d8B3am+WVxY+XNNo4rXt7I7UHTJCLJSc/3/shjE3ZIXw7F3PDurd6BEeOc3cxokHv0gVWhsCzFxWmYq4d/V0nQo2IBHwMiQqHqLYcL3SI+fwIWzvWEAvxFV6Ea6uxIfarGsowG568z4dkp9FCQHWe/1R5YLHuyUjVNSuO5pBZeU//+Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PJ2yh4zHfmZpub68KH2s9iOe8W332c0T3nuuiUcrwsQ=; b=UJaNN8ni140s0f58uj3nQcmmu6Qj+zrFmfwGO29xs4qeXcO5U6k5RTCS0VkPlMoGlR5p5MsqfVn15zeP9KkH4GZlC+Fa8f8ogRGMt08SgXnOx1nM25y5rDIqR/TDDx1HU6wvdgRZZvGPlmpRy2gQ+k1FGl19HO03EdMGxUAWhxMk7P7xclFVwuxqzk+SYooxHrB0MNcwWuUEkJ1BkxXLBIABj+YUW4Er9jiat11t+licJ7krMs5haqy8DsD7IUsMwwcXiuGnorYJRK1XAr4ULRESLS21upxa+xHRZlqbcEEW2IP5cJpuphXmlzob5F9kwpOacaeXsHlEf65IirR+ag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PJ2yh4zHfmZpub68KH2s9iOe8W332c0T3nuuiUcrwsQ=; b=Dxa2R8sxFBU5SdzNB4L6t8eO6JP8Vld1bHZ8lNeFoLU9LDnxroxjoNse7CPGcwkJL9h9YHt5qEdDZOVJGGh4emgbYo6hVRfYi1CS9BmDB8FuncDsYTouS1X7Fpc+8moY61avitkAYShoi5WOvKeCggzQcRBLcLUBpKqYXurqZLxEh/NfImStOXnBmJwMT93AwgreAUNCmKbNDvHkJzJpg74S1VQ2FVigzOa9RTilF61TiRTncTQMjzaRDROXzIYOAM82IhuPMz4g8sZ6A5O8SlGx9KNr87aTvIs4jhXScuG/DLS83RGwqame5JzY7Tgywx0+ZcAn3NHroK5ACOed6g== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 32/32] hw/arm/smmuv3: Add cmdqv property for SMMUv3 device Date: Tue, 19 May 2026 11:37:10 +0100 Message-ID: <20260519103727.899332-33-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519103727.899332-1-skolothumtho@nvidia.com> References: <20260519103727.899332-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|DS0PR12MB6485:EE_ X-MS-Office365-Filtering-Correlation-Id: 38e0810f-056c-4958-9ddf-08deb5931a03 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700016|82310400026|11063799006|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: gAJyzfynLaNM0UBR3msCxXCGidVo/G0sJJ9zCRsA7Em8cxvaSdSIzpgw6aTnr95skAi9ZkL151XoDHcmICJV2aB+YO1CKkfFk/KxxjBQE24R8w/0PLrzkidd3Wx69FfSRbgViIfe/nJDNgCW9a8iST8BZufzE3xOUKawtwGqNemuv0ChheevfvHAesaTcP4KHa2p6G4PxKEcrJhw2P4rKSBkqakDPVj5IAdEe4mxxhKh3ekGqE8olVs0+H/6nIBnDRq06XO3yL7XZdn93UkZ1WfDtBM7EW4bCgYrU+AzpjDVsjn5LU71+YOedUMRGLcgTPskxGmTaSehnpRGizxIuZrQml3FBdM7Xt7o64Y1Q80iicjmPxvMASS7TTVqnBuUnGxLoXe6nYY796bMItq5IRei9CaFiIyKwc7lWCaKLBRGVkJPQ3O9ysZax+g5P3TbrrV9T+ILCab801CWXa11IRNw3lxaFpmlgRxGMYFRDr3AekfDD4x6uI+BKbOWZZUe8A7balkBQ2KYnRrAIAYIGAxzuzh+pB40PAGv6hxmisEdR8lfMSOB3p8Q/5PjtUolu41SK0sBMdwoV4t+QSlaOVUyZ3n91eSZrlCJr/64N1RERg2t6iT7mP2OU/hCrRKfvEO576r8o2I7Q5+iABA9Y+kFYi5lelSx1DDtYqa/7hIYcb1ddCWvKyUEtSGArPoRHA2u/o+ksFAQl9af99SECnfV7fon46vacvqk+OaThZo= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(11063799006)(56012099003)(22082099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: u4y3yncRlRhSR9aagQjNZll2+HxWvRh48PB7BBn/ptlwv6TdVzaiY9Fi2aLdzuLNh/JpxulUt7oPC8LNQyFLrLlorsX3xaywjgHOAWwYCRCZY4agpTCkiRDw8B/YXZSDXme8f8NbG1+bsyEaff+cFlxe6yjNITL9DOaXX8LjgdaiVHBkBtabEP2HjSQG8g7XXHRT3Xyivxtva+or9B/c5WkZ2X+7Z5PNR4oEukwsZf3s1GOAxfqDQd/lwaBkBQ5O45beXdmjtmcjTtlcHjItUTjsM6Ys19vEabVHNooDmZuNslGts9WrflisZEXhpdzZRSi6fcWzzRv92JZG/vcNXkSXb5v4ISzaSXwSoSw6oWQC3L2YossVOMbjK+siB2XfhkSrhgvKMkB9u8n3GkRULDjnYdlIZq6Ym+QeE4ddaIxC+CIPamkFIGF2FZW6zo3s X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2026 10:40:53.2663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38e0810f-056c-4958-9ddf-08deb5931a03 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6485 Received-SPF: permerror client-ip=2a01:111:f403:c105::5; envelope-from=skolothumtho@nvidia.com; helo=CH5PR02CU005.outbound.protection.outlook.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1779187289787154100 Content-Type: text/plain; charset="utf-8" Introduce a "cmdqv" property to enable Tegra241 CMDQV support. This is only enabled for accelerated SMMUv3 devices. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger --- hw/arm/smmuv3.c | 8 ++++++++ qemu-options.hx | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 763b86c417..8c13489a5c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1994,6 +1994,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) "bits if accel=3Don"); return false; } + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON) { + error_setg(errp, "cmdqv can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2144,6 +2148,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_AUTO), + DEFINE_PROP_ON_OFF_AUTO("cmdqv", SMMUv3State, cmdqv, ON_OFF_AUTO_AUTO), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2188,6 +2193,9 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " "A value of 0 disables SubstreamID support. A value greater " "than 0 is required to enable PASID support."); + object_class_property_set_description(klass, "cmdqv", + "Enable/disable CMDQV support (for accel=3Don). " + "Valid values are on, off, and auto. Defaults to auto."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/qemu-options.hx b/qemu-options.hx index 46b02a1bb3..c8b8f4e69a 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1329,6 +1329,14 @@ SRST - With accel=3Don, auto means the value is automatically derived f= rom the host SMMU. - With accel=3Doff, auto is resolved to 0. =20 + ``cmdqv=3Don|off|auto`` (default: auto) + Enable hardware Command Queue Virtualization (CMDQV) for the + SMMUv3 command queue. Currently only the NVIDIA Tegra241 CMDQV + implementation is supported. + + - With accel=3Don, auto means the value is automatically derived f= rom the host SMMU. + - With accel=3Doff, auto is resolved to 'off'. + ``-device amd-iommu[,option=3D...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following option= s: --=20 2.43.0