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Mon, 18 May 2026 00:37:34 -0700 (PDT) From: khaled saleh To: mst@redhat.com Cc: qemu-devel@nongnu.org, khaled.saleh.req@gmail.com Subject: [PATCH] hw/pci/shpc: Enable 66MHz Bus Speed Support Date: Mon, 18 May 2026 09:37:14 +0200 Message-Id: <20260518073714.70571-1-khaled.saleh.req@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=khaled.saleh.req@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089958785158500 Content-Type: text/plain; charset="utf-8" The Standard Hot-Plug Controller (SHPC) specification (PI=3D1) defines 66MHz conventional PCI as a valid bus speed mode. While QEMU defined the relevant constants, it hardcoded the secondary bus speed to 33MHz and advertised 0 slots as 66MHz capable. This patch enables 66MHz support by: 1. Allowing SHPC_SEC_BUS_66 in shpc_set_sec_bus_speed(). 2. Advertising all slots as 66MHz capable in shpc_reset(). 3. Dynamically checking and reporting a slot's 66MHz capability based on the plugged PCI device's Status Register (PCI_STATUS_66MHZ). PCI-X speeds remain unsupported and will continue to trigger an INVALID_MODE command status error. Signed-off-by: khaled saleh --- hw/pci/shpc.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index 938602866d..3becde7f10 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -12,7 +12,7 @@ =20 /* TODO: model power only and disabled slot states. */ /* TODO: handle SERR and wakeups */ -/* TODO: consider enabling 66MHz support */ + =20 /* TODO: remove fully only on state DISABLED and LED off. * track state to properly record this. */ @@ -30,7 +30,7 @@ #define SHPC_PHYS_BUTTON 0x8000 #define SHPC_SEC_BUS 0x10 /* 2 bytes */ #define SHPC_SEC_BUS_33 0x0 -#define SHPC_SEC_BUS_66 0x1 /* Unused */ +#define SHPC_SEC_BUS_66 0x1 #define SHPC_SEC_BUS_MASK 0x7 #define SHPC_MSI_CTL 0x12 /* 1 byte */ #define SHPC_PROG_IFC 0x13 /* 1 byte */ @@ -169,6 +169,17 @@ static void shpc_set_status(SHPCDevice *shpc, pci_word_test_and_set_mask(status, value << ctz32(msk)); } =20 +static bool shpc_device_is_66mhz_capable(SHPCDevice *shpc, int slot) +{ + int pci_slot =3D SHPC_IDX_TO_PCI(slot); + PCIDevice *dev =3D shpc->sec_bus->devices[PCI_DEVFN(pci_slot, 0)]; + + if (!dev) { + return false; + } + return pci_get_word(dev->config + PCI_STATUS) & PCI_STATUS_66MHZ; +} + static void shpc_interrupt_update(PCIDevice *d) { SHPCDevice *shpc =3D d->shpc; @@ -203,6 +214,7 @@ static void shpc_set_sec_bus_speed(SHPCDevice *shpc, ui= nt8_t speed) { switch (speed) { case SHPC_SEC_BUS_33: + case SHPC_SEC_BUS_66: shpc->config[SHPC_SEC_BUS] &=3D ~SHPC_SEC_BUS_MASK; shpc->config[SHPC_SEC_BUS] |=3D speed; break; @@ -220,7 +232,7 @@ void shpc_reset(PCIDevice *d) memset(shpc->config, 0, SHPC_SIZEOF(d)); pci_set_byte(shpc->config + SHPC_NSLOTS, nslots); pci_set_long(shpc->config + SHPC_SLOTS_33, nslots); - pci_set_long(shpc->config + SHPC_SLOTS_66, 0); + pci_set_long(shpc->config + SHPC_SLOTS_66, nslots); pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0)); pci_set_word(shpc->config + SHPC_PHYS_SLOT, SHPC_IDX_TO_PHYSICAL(0) | @@ -256,7 +268,9 @@ void shpc_reset(PCIDevice *d) shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK); } shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_ATTN_LED_MASK); - shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66); + shpc_set_status(shpc, i, + shpc_device_is_66mhz_capable(shpc, i) ? 1 : 0, + SHPC_SLOT_STATUS_66); } shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33); shpc->msi_requested =3D 0; @@ -578,6 +592,9 @@ void shpc_device_plug_cb(HotplugHandler *hotplug_dev, D= eviceState *dev, shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN); shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W, SHPC_SLOT_STATUS_PRSNT_MASK); + shpc_set_status(shpc, slot, + shpc_device_is_66mhz_capable(shpc, slot) ? 1 : 0, + SHPC_SLOT_STATUS_66); return; } =20 @@ -596,7 +613,9 @@ void shpc_device_plug_cb(HotplugHandler *hotplug_dev, D= eviceState *dev, shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=3D SHPC_SLOT_EVENT_BUTTON; } - shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66); + shpc_set_status(shpc, slot, + shpc_device_is_66mhz_capable(shpc, slot) ? 1 : 0, + SHPC_SLOT_STATUS_66); shpc_interrupt_update(pci_hotplug_dev); } =20 --=20 2.34.1