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Mon, 18 May 2026 02:58:37 -0700 (PDT) From: Abdelrahman Elbehery Date: Mon, 18 May 2026 12:58:15 +0300 Subject: [PATCH] target/arm: replace cp_regs hashtable lookup with direct array index MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260518-enhance_arm_gdb_get_sysreg_performance-v1-1-f0a5b22003c0@gmail.com> X-B4-Tracking: v=1; b=H4sIALbiCmoC/x2N0QrCMBAEf6Xcs4EkxBr8FZGjNtuYh6blrohS+ u9GH2cHdnZSSIHStdtJ8CpaltrAnToan0PNMCU1Jm99b88uGtQ2j+BBZs7pwRkb60cFmVfItMj 80yb4GMMlBOtST+1sFUzl/Q/d7sfxBVbyI9J4AAAA X-Change-ID: 20260518-enhance_arm_gdb_get_sysreg_performance-4288474401d6 To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Abdelrahman Elbehery X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6908; i=elbeheri95@gmail.com; h=from:subject:message-id; bh=/wdbX57nyxVVoTtoLAbDqlJxwAOjWI4ITu9yT4WRpso=; b=owGbwMvMwCUm/fee8JG43+sYT6slMWRxPTqTGmzxk3Od2P7QjfaeBWFRfMLrhLpWnF3i/Ov/b 8akSW/rO0pZGMS4GGTFFFm+Jauyejmo7bE4dm8nzBxWJpAhDFycAjCR9tOMDOfE6hIMeAyM7x6S ar267GadN99lvqWCblt27mD4vff4z3JGhn2Cm7wXymsoXOR3uLQsa0l/UveKG2f8Poh+0+y0DDq /hR0A X-Developer-Key: i=elbeheri95@gmail.com; a=openpgp; fpr=F66325054A4026BC38C6DEB91BFDDE13C45EFBAE Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=elbeheri95@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 18 May 2026 09:29:20 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779110992858154100 Profiling showed g_hash_table_lookup as a hot spot when running TCG plugins that log all CPU registers (e.g. execlog with reg=3D*). Replace it with a direct array index to avoid lookup overhead. Signed-off-by: Abdelrahman Elbehery --- While profiling (via callgrind) a TCG plugin that logs all the CPU registers (very identical to execlog with reg=3D*) i noticed that arm_gdb_get_sysreg = is a hot spot, mostly while calling g_hash_table_lookup. Probably this is due to some hash= table collision that is handleded by glib internally. Currently each DynamicGDBFeatureInfo item holds keys for cp_regs, and the k= eys are always used to retrieve the ARMCPRegInfo pointer. By replacing the keys array with a GPtrArray, we now just access reg info d= irectly from the given index. The benchmarking was done on c2d-highcpu-16 (16 vCPUs, 32 GB memory) GCP Setup was to run qemu-system-aarch64 against a buildroot kernel and rootfs with and without the patch mostly using: --plugin contrib/plugins/libstoptrigger.so,icount=3D2000000 --plugin contrib/plugins/libexeclog.so,reg=3D* -M virt -cpu cortex-a710 -smp 1 Benchmark showed ~15% performance gain when hashtable is not used. For benchmarking, i used hyperfine with 3 warmup rounds and 10 iterations e= ach. --- target/arm/cpu.h | 6 +++--- target/arm/gdbstub.c | 28 ++++++++++++++++------------ 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 15a13b929276dad161032b61ba51ebbce7eeebc6..8816e94e3f8271ad403e77f6182= fdb8cee31c527 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -121,15 +121,15 @@ * DynamicGDBFeatureInfo: * @desc: Contains the feature descriptions. * @data: A union with data specific to the set of registers - * @cpregs_keys: Array that contains the corresponding Key of - * a given cpreg with the same order of the cpreg + * @cpregs_regs: Array that contains the corresponding Register info po= inter + * of a given cpreg with the same order of the cpreg * in the XML description. */ typedef struct DynamicGDBFeatureInfo { GDBFeature desc; union { struct { - uint32_t *keys; + GPtrArray *regs; } cpregs; } data; } DynamicGDBFeatureInfo; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index d6e29c4cf46745dc7851bc5f8339c8d7c6857b8c..e66af8207b436fe8f1dd27441a5= 87b1eb52ff928 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -238,19 +238,23 @@ static int arm_gdb_get_sysreg(CPUState *cs, GByteArra= y *buf, int reg) ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; const ARMCPRegInfo *ri; - uint32_t key; =20 - key =3D cpu->dyn_sysreg_feature.data.cpregs.keys[reg]; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); + ri =3D g_ptr_array_index(cpu->dyn_sysreg_feature.data.cpregs.regs, reg= ); if (ri) { switch (cpreg_field_type(ri)) { case MO_64: if (ri->vhe_redir_to_el2 && (arm_hcr_el2_eff(env) & HCR_E2H) && arm_current_el(env) =3D=3D 2) { - ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l2); + ri =3D g_ptr_array_index( + cpu->dyn_sysreg_feature.data.cpregs.regs, + ri->vhe_redir_to_el2 + ); } else if (ri->vhe_redir_to_el01) { - ri =3D get_arm_cp_reginfo(cpu->cp_regs, ri->vhe_redir_to_e= l01); + ri =3D g_ptr_array_index( + cpu->dyn_sysreg_feature.data.cpregs.regs, + ri->vhe_redir_to_el01 + ); } return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); case MO_32: @@ -269,19 +273,18 @@ static int arm_gdb_set_sysreg(CPUState *cs, uint8_t *= buf, int reg) =20 static void arm_gen_one_feature_sysreg(GDBFeatureBuilder *builder, DynamicGDBFeatureInfo *dyn_feature, - ARMCPRegInfo *ri, uint32_t ri_key, + ARMCPRegInfo *ri, int bitsize, int n) { gdb_feature_builder_append_reg(builder, ri->name, bitsize, n, "int", "cp_regs"); =20 - dyn_feature->data.cpregs.keys[n] =3D ri_key; + g_ptr_array_index(dyn_feature->data.cpregs.regs, n) =3D ri; } =20 static void arm_register_sysreg_for_feature(gpointer key, gpointer value, gpointer p) { - uint32_t ri_key =3D (uintptr_t)key; ARMCPRegInfo *ri =3D value; RegisterSysregFeatureParam *param =3D p; ARMCPU *cpu =3D ARM_CPU(param->cs); @@ -292,7 +295,7 @@ static void arm_register_sysreg_for_feature(gpointer ke= y, gpointer value, if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state =3D=3D ARM_CP_STATE_AA64) { arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, - ri, ri_key, 64, param->n++); + ri, 64, param->n++); } } else { if (ri->state =3D=3D ARM_CP_STATE_AA32) { @@ -302,10 +305,10 @@ static void arm_register_sysreg_for_feature(gpointer = key, gpointer value, } if (ri->type & ARM_CP_64BIT) { arm_gen_one_feature_sysreg(¶m->builder, dyn_featur= e, - ri, ri_key, 64, param->n++); + ri, 64, param->n++); } else { arm_gen_one_feature_sysreg(¶m->builder, dyn_featur= e, - ri, ri_key, 32, param->n++); + ri, 32, param->n++); } } } @@ -323,7 +326,8 @@ static GDBFeature *arm_gen_dynamic_sysreg_feature(CPUSt= ate *cs, int base_reg) "org.qemu.gdb.arm.sys.regs", "system-registers.xml", base_reg); - cpu->dyn_sysreg_feature.data.cpregs.keys =3D g_new(uint32_t, num_regs); + cpu->dyn_sysreg_feature.data.cpregs.regs =3D g_ptr_array_new(); + g_ptr_array_set_size(cpu->dyn_sysreg_feature.data.cpregs.regs, num_reg= s); g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_feature, &p= aram); gdb_feature_builder_end(¶m.builder); return &cpu->dyn_sysreg_feature.desc; --- base-commit: ac6721b88df944ade0048822b2b74210f543d656 change-id: 20260518-enhance_arm_gdb_get_sysreg_performance-4288474401d6 Best regards, --=20 Abdelrahman Elbehery