From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868087; cv=none; d=zohomail.com; s=zohoarc; b=kDHaOMEgHlIr9kU0bM8Xqv+2q8vKdBuv/RuZEZ2zO99DM4c8RgCgdQ9G77vc6SVdWK5jvqLiFlHFwQxTSXMJWWDaMiRVeXnid8Glr5jiCdvHsNXEyuA+qFOwLeHRDVB9P4cOH/PHm8NL7dXtZS9XZ77F7lTju2cgZJPtenr6Ams= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778868087; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=7+Akt3ctCQ8zFBK6g77Oimdobx/r4QnKsamSWwo94tA=; b=fmsooKqqwoP33mVIUYeE4k4AxngDBG3F/86qb5H8zon04IYJLPpezfnoe6JPIEyCrGqz41bsbxVLM5WPQBBIVZrTeDmzf1fVT8Z56GvtEN86fy06+tJrHmBdmxFo1IaG1HGgkSpHYZ+sDuDsB5JCpSWsn78L4q8Wdy8Y8I/DXsA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778868087006207.67669612616692; Fri, 15 May 2026 11:01:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wNwqL-0007KA-BE; Fri, 15 May 2026 14:01:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqB-0007Hm-Eb for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:52 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwq8-0001Gg-4L for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=7+Akt3ctCQ8zFBK6g77Oimdobx/r4QnKsamSWwo94tA=; b=qZDGJDiLgsxXgYg BKw8Ep7hgVEn9Uh8SSGSVYYAR20Qqdfo6O3bLLarfUxZAERjVwXd7NpyGrab/JZINoTH6Xco0Xe3v NVIFIIdBlqlpXPLyH2DOPLYIY6/ENinRktBZynPZVwjCRIqOnqba+cBWZ7xljz7HiVhYU7z7XV/yG co=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 01/27] target/riscv: Fix size of gpr and gprh Date: Fri, 15 May 2026 20:04:11 +0200 Message-ID: <20260515180437.23620-2-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868089918158500 Content-Type: text/plain; charset="utf-8" gprh is only needed for TARGET_RISCV64 when modeling 128-bit registers, fixing their size to 64 bits makes sense. gpr is also fixed to 64 bits since all direct uses of env->gpr correctly zero extend/truncate to/from target_ulong, meaning !TARGET_RISCV64 will behave as expected. We do however need to be a bit careful when mapping 64-bit fields to 32-bit TCGv globals on big endian hosts. Note, the cpu/rv128 VMSTATE version is bumped, breaking migration from older versions. Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 4 ++-- target/riscv/cpu.c | 2 +- target/riscv/machine.c | 8 ++++---- target/riscv/monitor.c | 2 +- target/riscv/translate.c | 16 ++++++++++++++-- 5 files changed, 22 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fae839cade..8891673054 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -213,8 +213,8 @@ typedef struct PMUFixedCtrState { } PMUFixedCtrState; =20 struct CPUArchState { - target_ulong gpr[32]; - target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ + uint64_t gpr[32]; + uint64_t gprh[32]; /* 64 top bits of the 128-bit registers */ =20 /* vector coprocessor state. */ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 506a018d52..f9b57914ee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -596,7 +596,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) #endif =20 for (i =3D 0; i < 32; i++) { - qemu_fprintf(f, " %-8s " TARGET_FMT_lx, + qemu_fprintf(f, " %-8s %" PRIx64, riscv_int_regnames[i], env->gpr[i]); if ((i & 3) =3D=3D 3) { qemu_fprintf(f, "\n"); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 09c032a879..7349383eab 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -177,11 +177,11 @@ static bool rv128_needed(void *opaque) =20 static const VMStateDescription vmstate_rv128 =3D { .name =3D "cpu/rv128", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D rv128_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), + VMSTATE_UINT64_ARRAY(env.gprh, RISCVCPU, 32), VMSTATE_UINT64(env.mscratchh, RISCVCPU), VMSTATE_UINT64(env.sscratchh, RISCVCPU), VMSTATE_END_OF_LIST() @@ -429,7 +429,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { .minimum_version_id =3D 11, .post_load =3D riscv_cpu_post_load, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), + VMSTATE_UINT64_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 6380600241..9edac0533c 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -248,7 +248,7 @@ static bool reg_is_ulong_integer(CPURISCVState *env, co= nst char *name, target_ulong *val, bool is_gprh) { const char * const *reg_names; - target_ulong *vals; + uint64_t *vals; =20 if (is_gprh) { reg_names =3D riscv_int_regnamesh; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1e4f340256..640691e1c5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1469,12 +1469,24 @@ void riscv_translate_init(void) */ cpu_gpr[0] =3D NULL; cpu_gprh[0] =3D NULL; + /* + * Be careful with big endian hosts when mapping 64-bit CPUArchState f= ields + * to 32-bit TCGv globals. An offset of 4 bytes is applied so the lea= st + * significant bytes are correctly written to. + */ +#if HOST_BIG_ENDIAN && !defined(TARGET_RISCV64) + size_t field_offset =3D 4; +#else + size_t field_offset =3D 0; +#endif =20 for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, - offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); + offsetof(CPURISCVState, gpr[i]) + field_offset, + riscv_int_regnames[i]); cpu_gprh[i] =3D tcg_global_mem_new(tcg_env, - offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); + offsetof(CPURISCVState, gprh[i]) + field_offset, + riscv_int_regnamesh[i]); } =20 for (i =3D 0; i < 32; i++) { --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177886822000623.653348791718486; Fri, 15 May 2026 11:03:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wNwqz-0007bX-Ep; Fri, 15 May 2026 14:01:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqE-0007Ii-QU for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:55 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwq8-0001Gi-4K for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=BwzQUOPl5hFJU1Bi2228EYkziJw3pOsSvaq9/Dykexk=; b=UlJZq1Aqj2hmPLC GYGro3bt+V0opfPou6fjDU2Ct1hGvrVdCm3p8QaB8CQ5JXJQ6wKcnzNlS7rjNkcyW3ctDoyU5vCrk 9giKtobX0BsacWi9cSU89Ya63/AlYQm9PY6vwTMnaYVY9zpm+1/0tlaOwGUlKDN4Vm/YdNuarOEk/ jY=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 02/27] target/riscv: Fix size of vector CSRs Date: Fri, 15 May 2026 20:04:12 +0200 Message-ID: <20260515180437.23620-3-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868220863158500 Content-Type: text/plain; charset="utf-8" According to version 20250508 of the unprivileged specification: - vtype: bits 0..7 used, bit XLEN-1 illegal, rest reserved =3D> fix to 64-bits. - vxsat: bit 0 used, vxrm which would occupy bits 1..2 is stored separately, and bits 3..31 are set to 0 =3D> fix to 8-bits. - vxrm: 2 lowest bits are used for rounding mode, rest set to 0 =3D> fix to 8-bits. - vstart: maximum value of VLMAX-1, where VLMAX is at most 2^16 =3D> fix to 32-bits as vstart is mapped to a TCG global. - vl: maximum value of VLEN which is at most 2^16 =3D> fix to 32-bits as vl is mapped to a TCG global. Fields are shuffled for reduced padding. Note, the cpu/vector VMSTATE version is bumped, breaking migration from older versions. Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 12 +-- target/riscv/machine.c | 14 +-- target/riscv/translate.c | 12 ++- target/riscv/vector_helper.c | 125 ++++++++++++++---------- target/riscv/insn_trans/trans_rvv.c.inc | 22 ++--- 5 files changed, 103 insertions(+), 82 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8891673054..d9771ef845 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -192,7 +192,7 @@ FIELD(VTYPE, VSEW, 3, 3) FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, ALTFMT, 8, 1) -FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10) +FIELD(VTYPE, RESERVED, 9, sizeof(uint64_t) * 8 - 10) =20 typedef struct PMUCTRState { /* Current value of a counter */ @@ -218,11 +218,11 @@ struct CPUArchState { =20 /* vector coprocessor state. */ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); - target_ulong vxrm; - target_ulong vxsat; - target_ulong vl; - target_ulong vstart; - target_ulong vtype; + uint64_t vtype; + uint32_t vl; + uint32_t vstart; + uint8_t vxrm; + uint8_t vxsat; bool vill; =20 target_ulong pc; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 7349383eab..440b09fc32 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -137,16 +137,16 @@ static bool vector_needed(void *opaque) =20 static const VMStateDescription vmstate_vector =3D { .name =3D "cpu/vector", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .needed =3D vector_needed, .fields =3D (const VMStateField[]) { VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), - VMSTATE_UINTTL(env.vxrm, RISCVCPU), - VMSTATE_UINTTL(env.vxsat, RISCVCPU), - VMSTATE_UINTTL(env.vl, RISCVCPU), - VMSTATE_UINTTL(env.vstart, RISCVCPU), - VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_UINT64(env.vtype, RISCVCPU), + VMSTATE_UINT32(env.vl, RISCVCPU), + VMSTATE_UINT32(env.vstart, RISCVCPU), + VMSTATE_UINT8(env.vxrm, RISCVCPU), + VMSTATE_UINT8(env.vxsat, RISCVCPU), VMSTATE_BOOL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 640691e1c5..4a557b4907 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -38,8 +38,9 @@ #include "tcg/tcg-cpu.h" =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ +static TCGv_i32 cpu_vl, cpu_vstart; static TCGv load_res; static TCGv load_val; =20 @@ -1480,6 +1481,10 @@ void riscv_translate_init(void) size_t field_offset =3D 0; #endif =20 + /* 32 bits in size, no offset needed */ + size_t vl_offset =3D offsetof(CPURISCVState, vl); + size_t vstart_offset =3D offsetof(CPURISCVState, vstart); + for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, gpr[i]) + field_offset, @@ -1495,9 +1500,8 @@ void riscv_translate_init(void) } =20 cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "p= c"); - cpu_vl =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "v= l"); - cpu_vstart =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vst= art), - "vstart"); + cpu_vl =3D tcg_global_mem_new_i32(tcg_env, vl_offset, "vl"); + cpu_vstart =3D tcg_global_mem_new_i32(tcg_env, vstart_offset, "vstart"= ); load_res =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= res), "load_res"); load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5a3554dd71..2073c04e41 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -285,7 +285,7 @@ vext_continuous_ldst_host(CPURISCVState *env, vext_ldst= _elem_fn_host *ldst_host, } } =20 -static void vext_set_tail_elems_1s(target_ulong vl, void *vd, +static void vext_set_tail_elems_1s(uint32_t vl, void *vd, uint32_t desc, uint32_t nf, uint32_t esz, uint32_t max_elems) { @@ -388,6 +388,12 @@ vext_page_ldst_us(CPURISCVState *env, void *vd, target= _ulong addr, uint32_t evl =3D env->vstart + elems; MMUAccessType access_type =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; =20 + /* + * Maximum vector length is VLMAX =3D=3D 2^16 =3D=3D LMUL * VL / SEW, = and + * occurs for LMUL =3D=3D 8, SEW =3D=3D 8, VL =3D=3D 2^16. + */ + g_assert(env->vstart < UINT16_MAX && UINT16_MAX - env->vstart >=3D ele= ms); + /* Check page permission/pmp/watchpoint/etc. */ probe_pages(env, addr, size, ra, access_type, mmu_index, &host, &flags, true); @@ -2206,12 +2212,12 @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8) * define common macros for fixed point here. */ typedef void opivv2_rm_fn(void *vd, void *vs1, void *vs2, int i, - CPURISCVState *env, int vxrm); + CPURISCVState *env, uint8_t vxrm); =20 #define OPIVV2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static inline void \ do_##NAME(void *vd, void *vs1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ + CPURISCVState *env, uint8_t vxrm) \ { \ TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ @@ -2221,7 +2227,7 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, = \ static inline void vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, int vxrm, + uint32_t vl, uint32_t vm, uint8_t vxrm, opivv2_rm_fn *fn, uint32_t vma, uint32_t esz) { for (uint32_t i =3D env->vstart; i < vl; i++) { @@ -2280,7 +2286,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ do_##NAME, ESZ); \ } =20 -static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, +static inline uint8_t saddu8(CPURISCVState *env, uint8_t vxrm, uint8_t a, uint8_t b) { uint8_t res =3D a + b; @@ -2291,7 +2297,7 @@ static inline uint8_t saddu8(CPURISCVState *env, int = vxrm, uint8_t a, return res; } =20 -static inline uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a, +static inline uint16_t saddu16(CPURISCVState *env, uint8_t vxrm, uint16_t = a, uint16_t b) { uint16_t res =3D a + b; @@ -2302,7 +2308,7 @@ static inline uint16_t saddu16(CPURISCVState *env, in= t vxrm, uint16_t a, return res; } =20 -static inline uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a, +static inline uint32_t saddu32(CPURISCVState *env, uint8_t vxrm, uint32_t = a, uint32_t b) { uint32_t res =3D a + b; @@ -2313,7 +2319,7 @@ static inline uint32_t saddu32(CPURISCVState *env, in= t vxrm, uint32_t a, return res; } =20 -static inline uint64_t saddu64(CPURISCVState *env, int vxrm, uint64_t a, +static inline uint64_t saddu64(CPURISCVState *env, uint8_t vxrm, uint64_t = a, uint64_t b) { uint64_t res =3D a + b; @@ -2334,12 +2340,12 @@ GEN_VEXT_VV_RM(vsaddu_vv_w, 4) GEN_VEXT_VV_RM(vsaddu_vv_d, 8) =20 typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i, - CPURISCVState *env, int vxrm); + CPURISCVState *env, uint8_t vxrm); =20 #define OPIVX2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static inline void \ do_##NAME(void *vd, target_long s1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ + CPURISCVState *env, uint8_t vxrm) \ { \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ *((TD *)vd + HD(i)) =3D OP(env, vxrm, s2, (TX1)(T1)s1); \ @@ -2348,7 +2354,7 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i,= \ static inline void vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, int vxrm, + uint32_t vl, uint32_t vm, uint8_t vxrm, opivx2_rm_fn *fn, uint32_t vma, uint32_t esz) { for (uint32_t i =3D env->vstart; i < vl; i++) { @@ -2417,7 +2423,8 @@ GEN_VEXT_VX_RM(vsaddu_vx_h, 2) GEN_VEXT_VX_RM(vsaddu_vx_w, 4) GEN_VEXT_VX_RM(vsaddu_vx_d, 8) =20 -static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t = b) +static inline int8_t sadd8(CPURISCVState *env, uint8_t vxrm, int8_t a, + int8_t b) { int8_t res =3D a + b; if ((res ^ a) & (res ^ b) & INT8_MIN) { @@ -2427,7 +2434,7 @@ static inline int8_t sadd8(CPURISCVState *env, int vx= rm, int8_t a, int8_t b) return res; } =20 -static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, +static inline int16_t sadd16(CPURISCVState *env, uint8_t vxrm, int16_t a, int16_t b) { int16_t res =3D a + b; @@ -2438,7 +2445,7 @@ static inline int16_t sadd16(CPURISCVState *env, int = vxrm, int16_t a, return res; } =20 -static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, +static inline int32_t sadd32(CPURISCVState *env, uint8_t vxrm, int32_t a, int32_t b) { int32_t res =3D a + b; @@ -2449,7 +2456,7 @@ static inline int32_t sadd32(CPURISCVState *env, int = vxrm, int32_t a, return res; } =20 -static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, +static inline int64_t sadd64(CPURISCVState *env, uint8_t vxrm, int64_t a, int64_t b) { int64_t res =3D a + b; @@ -2478,7 +2485,7 @@ GEN_VEXT_VX_RM(vsadd_vx_h, 2) GEN_VEXT_VX_RM(vsadd_vx_w, 4) GEN_VEXT_VX_RM(vsadd_vx_d, 8) =20 -static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, +static inline uint8_t ssubu8(CPURISCVState *env, uint8_t vxrm, uint8_t a, uint8_t b) { uint8_t res =3D a - b; @@ -2489,7 +2496,7 @@ static inline uint8_t ssubu8(CPURISCVState *env, int = vxrm, uint8_t a, return res; } =20 -static inline uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a, +static inline uint16_t ssubu16(CPURISCVState *env, uint8_t vxrm, uint16_t = a, uint16_t b) { uint16_t res =3D a - b; @@ -2500,7 +2507,7 @@ static inline uint16_t ssubu16(CPURISCVState *env, in= t vxrm, uint16_t a, return res; } =20 -static inline uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a, +static inline uint32_t ssubu32(CPURISCVState *env, uint8_t vxrm, uint32_t = a, uint32_t b) { uint32_t res =3D a - b; @@ -2511,7 +2518,7 @@ static inline uint32_t ssubu32(CPURISCVState *env, in= t vxrm, uint32_t a, return res; } =20 -static inline uint64_t ssubu64(CPURISCVState *env, int vxrm, uint64_t a, +static inline uint64_t ssubu64(CPURISCVState *env, uint8_t vxrm, uint64_t = a, uint64_t b) { uint64_t res =3D a - b; @@ -2540,7 +2547,8 @@ GEN_VEXT_VX_RM(vssubu_vx_h, 2) GEN_VEXT_VX_RM(vssubu_vx_w, 4) GEN_VEXT_VX_RM(vssubu_vx_d, 8) =20 -static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t = b) +static inline int8_t ssub8(CPURISCVState *env, uint8_t vxrm, int8_t a, + int8_t b) { int8_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT8_MIN) { @@ -2550,7 +2558,7 @@ static inline int8_t ssub8(CPURISCVState *env, int vx= rm, int8_t a, int8_t b) return res; } =20 -static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, +static inline int16_t ssub16(CPURISCVState *env, uint8_t vxrm, int16_t a, int16_t b) { int16_t res =3D a - b; @@ -2561,7 +2569,7 @@ static inline int16_t ssub16(CPURISCVState *env, int = vxrm, int16_t a, return res; } =20 -static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, +static inline int32_t ssub32(CPURISCVState *env, uint8_t vxrm, int32_t a, int32_t b) { int32_t res =3D a - b; @@ -2572,7 +2580,7 @@ static inline int32_t ssub32(CPURISCVState *env, int = vxrm, int32_t a, return res; } =20 -static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, +static inline int64_t ssub64(CPURISCVState *env, uint8_t vxrm, int64_t a, int64_t b) { int64_t res =3D a - b; @@ -2602,7 +2610,7 @@ GEN_VEXT_VX_RM(vssub_vx_w, 4) GEN_VEXT_VX_RM(vssub_vx_d, 8) =20 /* Vector Single-Width Averaging Add and Subtract */ -static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift) +static inline uint8_t get_round(uint8_t vxrm, uint64_t v, uint8_t shift) { uint8_t d =3D extract64(v, shift, 1); uint8_t d1; @@ -2614,22 +2622,30 @@ static inline uint8_t get_round(int vxrm, uint64_t = v, uint8_t shift) =20 d1 =3D extract64(v, shift - 1, 1); D1 =3D extract64(v, 0, shift); - if (vxrm =3D=3D 0) { /* round-to-nearest-up (add +0.5 LSB) */ + switch (vxrm) { + case 0: + /* round-to-nearest-up (add +0.5 LSB) */ return d1; - } else if (vxrm =3D=3D 1) { /* round-to-nearest-even */ + case 1: + /* round-to-nearest-even */ if (shift > 1) { D2 =3D extract64(v, 0, shift - 1); return d1 & ((D2 !=3D 0) | d); } else { return d1 & d; } - } else if (vxrm =3D=3D 3) { /* round-to-odd (OR bits into LSB, aka "ja= m") */ + case 2: + /* round-down (truncate) */ + return 0; + case 3: + /* round-to-odd (OR bits into LSB, aka "jam") */ return !d & (D1 !=3D 0); + default: + g_assert_not_reached(); } - return 0; /* round-down (truncate) */ } =20 -static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, +static inline int32_t aadd32(CPURISCVState *env, uint8_t vxrm, int32_t a, int32_t b) { int64_t res =3D (int64_t)a + b; @@ -2638,7 +2654,7 @@ static inline int32_t aadd32(CPURISCVState *env, int = vxrm, int32_t a, return (res >> 1) + round; } =20 -static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, +static inline int64_t aadd64(CPURISCVState *env, uint8_t vxrm, int64_t a, int64_t b) { int64_t res =3D a + b; @@ -2667,7 +2683,7 @@ GEN_VEXT_VX_RM(vaadd_vx_h, 2) GEN_VEXT_VX_RM(vaadd_vx_w, 4) GEN_VEXT_VX_RM(vaadd_vx_d, 8) =20 -static inline uint32_t aaddu32(CPURISCVState *env, int vxrm, +static inline uint32_t aaddu32(CPURISCVState *env, uint8_t vxrm, uint32_t a, uint32_t b) { uint64_t res =3D (uint64_t)a + b; @@ -2676,7 +2692,7 @@ static inline uint32_t aaddu32(CPURISCVState *env, in= t vxrm, return (res >> 1) + round; } =20 -static inline uint64_t aaddu64(CPURISCVState *env, int vxrm, +static inline uint64_t aaddu64(CPURISCVState *env, uint8_t vxrm, uint64_t a, uint64_t b) { uint64_t res =3D a + b; @@ -2704,7 +2720,7 @@ GEN_VEXT_VX_RM(vaaddu_vx_h, 2) GEN_VEXT_VX_RM(vaaddu_vx_w, 4) GEN_VEXT_VX_RM(vaaddu_vx_d, 8) =20 -static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, +static inline int32_t asub32(CPURISCVState *env, uint8_t vxrm, int32_t a, int32_t b) { int64_t res =3D (int64_t)a - b; @@ -2713,7 +2729,7 @@ static inline int32_t asub32(CPURISCVState *env, int = vxrm, int32_t a, return (res >> 1) + round; } =20 -static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, +static inline int64_t asub64(CPURISCVState *env, uint8_t vxrm, int64_t a, int64_t b) { int64_t res =3D (int64_t)a - b; @@ -2742,7 +2758,7 @@ GEN_VEXT_VX_RM(vasub_vx_h, 2) GEN_VEXT_VX_RM(vasub_vx_w, 4) GEN_VEXT_VX_RM(vasub_vx_d, 8) =20 -static inline uint32_t asubu32(CPURISCVState *env, int vxrm, +static inline uint32_t asubu32(CPURISCVState *env, uint8_t vxrm, uint32_t a, uint32_t b) { int64_t res =3D (int64_t)a - b; @@ -2751,7 +2767,7 @@ static inline uint32_t asubu32(CPURISCVState *env, in= t vxrm, return (res >> 1) + round; } =20 -static inline uint64_t asubu64(CPURISCVState *env, int vxrm, +static inline uint64_t asubu64(CPURISCVState *env, uint8_t vxrm, uint64_t a, uint64_t b) { uint64_t res =3D (uint64_t)a - b; @@ -2780,7 +2796,8 @@ GEN_VEXT_VX_RM(vasubu_vx_w, 4) GEN_VEXT_VX_RM(vasubu_vx_d, 8) =20 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ -static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t= b) +static inline int8_t vsmul8(CPURISCVState *env, uint8_t vxrm, int8_t a, + int8_t b) { uint8_t round; int16_t res; @@ -2800,7 +2817,7 @@ static inline int8_t vsmul8(CPURISCVState *env, int v= xrm, int8_t a, int8_t b) } } =20 -static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) +static int16_t vsmul16(CPURISCVState *env, uint8_t vxrm, int16_t a, int16_= t b) { uint8_t round; int32_t res; @@ -2820,7 +2837,7 @@ static int16_t vsmul16(CPURISCVState *env, int vxrm, = int16_t a, int16_t b) } } =20 -static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) +static int32_t vsmul32(CPURISCVState *env, uint8_t vxrm, int32_t a, int32_= t b) { uint8_t round; int64_t res; @@ -2840,7 +2857,7 @@ static int32_t vsmul32(CPURISCVState *env, int vxrm, = int32_t a, int32_t b) } } =20 -static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) +static int64_t vsmul64(CPURISCVState *env, uint8_t vxrm, int64_t a, int64_= t b) { uint8_t round; uint64_t hi_64, lo_64; @@ -2888,7 +2905,7 @@ GEN_VEXT_VX_RM(vsmul_vx_d, 8) =20 /* Vector Single-Width Scaling Shift Instructions */ static inline uint8_t -vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) +vssrl8(CPURISCVState *env, uint8_t vxrm, uint8_t a, uint8_t b) { uint8_t round, shift =3D b & 0x7; uint8_t res; @@ -2898,7 +2915,7 @@ vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8= _t b) return res; } static inline uint16_t -vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b) +vssrl16(CPURISCVState *env, uint8_t vxrm, uint16_t a, uint16_t b) { uint8_t round, shift =3D b & 0xf; =20 @@ -2906,7 +2923,7 @@ vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uin= t16_t b) return (a >> shift) + round; } static inline uint32_t -vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b) +vssrl32(CPURISCVState *env, uint8_t vxrm, uint32_t a, uint32_t b) { uint8_t round, shift =3D b & 0x1f; =20 @@ -2914,7 +2931,7 @@ vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uin= t32_t b) return (a >> shift) + round; } static inline uint64_t -vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b) +vssrl64(CPURISCVState *env, uint8_t vxrm, uint64_t a, uint64_t b) { uint8_t round, shift =3D b & 0x3f; =20 @@ -2940,7 +2957,7 @@ GEN_VEXT_VX_RM(vssrl_vx_w, 4) GEN_VEXT_VX_RM(vssrl_vx_d, 8) =20 static inline int8_t -vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) +vssra8(CPURISCVState *env, uint8_t vxrm, int8_t a, int8_t b) { uint8_t round, shift =3D b & 0x7; =20 @@ -2948,7 +2965,7 @@ vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t= b) return (a >> shift) + round; } static inline int16_t -vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) +vssra16(CPURISCVState *env, uint8_t vxrm, int16_t a, int16_t b) { uint8_t round, shift =3D b & 0xf; =20 @@ -2956,7 +2973,7 @@ vssra16(CPURISCVState *env, int vxrm, int16_t a, int1= 6_t b) return (a >> shift) + round; } static inline int32_t -vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) +vssra32(CPURISCVState *env, uint8_t vxrm, int32_t a, int32_t b) { uint8_t round, shift =3D b & 0x1f; =20 @@ -2964,7 +2981,7 @@ vssra32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) return (a >> shift) + round; } static inline int64_t -vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) +vssra64(CPURISCVState *env, uint8_t vxrm, int64_t a, int64_t b) { uint8_t round, shift =3D b & 0x3f; =20 @@ -2992,7 +3009,7 @@ GEN_VEXT_VX_RM(vssra_vx_d, 8) =20 /* Vector Narrowing Fixed-Point Clip Instructions */ static inline int8_t -vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8_t b) +vnclip8(CPURISCVState *env, uint8_t vxrm, int16_t a, int8_t b) { uint8_t round, shift =3D b & 0xf; int16_t res; @@ -3011,7 +3028,7 @@ vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8= _t b) } =20 static inline int16_t -vnclip16(CPURISCVState *env, int vxrm, int32_t a, int16_t b) +vnclip16(CPURISCVState *env, uint8_t vxrm, int32_t a, int16_t b) { uint8_t round, shift =3D b & 0x1f; int32_t res; @@ -3030,7 +3047,7 @@ vnclip16(CPURISCVState *env, int vxrm, int32_t a, int= 16_t b) } =20 static inline int32_t -vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b) +vnclip32(CPURISCVState *env, uint8_t vxrm, int64_t a, int32_t b) { uint8_t round, shift =3D b & 0x3f; int64_t res; @@ -3063,7 +3080,7 @@ GEN_VEXT_VX_RM(vnclip_wx_h, 2) GEN_VEXT_VX_RM(vnclip_wx_w, 4) =20 static inline uint8_t -vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b) +vnclipu8(CPURISCVState *env, uint8_t vxrm, uint16_t a, uint8_t b) { uint8_t round, shift =3D b & 0xf; uint16_t res; @@ -3079,7 +3096,7 @@ vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, ui= nt8_t b) } =20 static inline uint16_t -vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b) +vnclipu16(CPURISCVState *env, uint8_t vxrm, uint32_t a, uint16_t b) { uint8_t round, shift =3D b & 0x1f; uint32_t res; @@ -3095,7 +3112,7 @@ vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, u= int16_t b) } =20 static inline uint32_t -vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) +vnclipu32(CPURISCVState *env, uint8_t vxrm, uint64_t a, uint32_t b) { uint8_t round, shift =3D b & 0x3f; uint64_t res; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index e65356eb7c..a331fcaad8 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -203,7 +203,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2) =20 if (rd =3D=3D 0 && rs1 =3D=3D 0) { s1 =3D tcg_temp_new(); - tcg_gen_mov_tl(s1, cpu_vl); + tcg_gen_ext_i32_tl(s1, cpu_vl); } else if (rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_constant_tl(RV_VLEN_MAX); @@ -1213,9 +1213,9 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, tcg_gen_qemu_st_i64(t8, addr, s->mem_idx, MO_LEUQ | atomic= ity); } if (i =3D=3D size - 8) { - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); } else { - tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 8 >> log2_esz); + tcg_gen_addi_i32(cpu_vstart, cpu_vstart, 8 >> log2_esz); } } } else { @@ -2426,7 +2426,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ s->cfg_ptr->vlenb, data, \ (s->altfmt ? gen_helper_##BFA_HELPER : \ fns[s->sew - 1])); \ - tcg_gen_movi_tl(cpu_vstart, 0); \ + tcg_gen_movi_i32(cpu_vstart, 0); \ finalize_rvv_inst(s); \ \ return true; \ @@ -3656,7 +3656,7 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_= s *a) vec_element_loadi(s, t1, a->rs2, 0, true); tcg_gen_trunc_i64_tl(dest, t1); gen_set_gpr(s, a->rd, dest); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } @@ -3673,7 +3673,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) TCGv s1; TCGLabel *over =3D gen_new_label(); =20 - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + tcg_gen_brcond_i32(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); =20 @@ -3685,7 +3685,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); gen_set_label(over); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } @@ -3713,7 +3713,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_= f_s *a) } =20 mark_fs_dirty(s); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } @@ -3734,7 +3734,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) TCGLabel *over =3D gen_new_label(); =20 /* if vstart >=3D vl, skip vector register write back */ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + tcg_gen_brcond_i32(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 /* NaN-box f[rs1] */ t1 =3D tcg_temp_new_i64(); @@ -3743,7 +3743,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) vec_element_storei(s, a->rd, 0, t1); =20 gen_set_label(over); - tcg_gen_movi_tl(cpu_vstart, 0); + tcg_gen_movi_i32(cpu_vstart, 0); finalize_rvv_inst(s); return true; } @@ -3808,7 +3808,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ \ fns[s->sew](dest, mask, src1, src2, tcg_env, desc); \ \ - tcg_gen_movi_tl(cpu_vstart, 0); \ + tcg_gen_movi_i32(cpu_vstart, 0); \ finalize_rvv_inst(s); \ \ return true; \ --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868102; cv=none; d=zohomail.com; s=zohoarc; b=PtKMMKo0YcL50GXiCvvWRG2erzqD1eSWtCLr0oYOHXLOfzxwG0AqkUXHs/GkygUuoQC57UpmuPDSRDQx90PuuAWI1Hf2w2ZZh3g77bMjeV4yAsPKPdfYtQQDEC5jTXaUOUXPJ3AhveNu4CkQeIWD+jeLVDs2Hhl6vqVQHS4ZzuA= ARC-Message-Signature: i=1; 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To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 03/27] target/riscv: Fix size of pc, load_[val|res] Date: Fri, 15 May 2026 20:04:13 +0200 Message-ID: <20260515180437.23620-4-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868103534158500 Content-Type: text/plain; charset="utf-8" Fix to 64 bits in size and as these are mapped to TCG globals, be careful with host endianness when allocating globals. Casts are added to logging expressions to retain the correct size for TARGET_RISCV32. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 6 +++--- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 6 +++--- target/riscv/machine.c | 6 +++--- target/riscv/translate.c | 12 +++++++----- 5 files changed, 17 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d9771ef845..15c9f8b3a0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -225,9 +225,9 @@ struct CPUArchState { uint8_t vxsat; bool vill; =20 - target_ulong pc; - target_ulong load_res; - target_ulong load_val; + uint64_t pc; + uint64_t load_res; + uint64_t load_val; =20 /* Floating-Point state */ uint64_t fpr[32]; /* assume both F and D extensions */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f9b57914ee..27310a95d1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -569,7 +569,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) qemu_fprintf(f, " %s %d\n", "V =3D ", env->virt_enabled); } #endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); + qemu_fprintf(f, " %s %" PRIx64 "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY for (i =3D 0; i < ARRAY_SIZE(csr_ops); i++) { int csrno =3D i; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 17305e1bb7..6236f65ff8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -2334,9 +2334,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 qemu_log_mask(CPU_LOG_INT, "%s: hart:%"PRIu64", async:%d, cause:"TARGET_FMT_lx", " - "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=3D%= s\n", - __func__, env->mhartid, async, cause, env->pc, tval, - riscv_cpu_get_trap_name(cause, async)); + "epc:0x%"PRIx64", tval:0x"TARGET_FMT_lx", desc=3D%s\n", + __func__, env->mhartid, async, cause, env->pc, + tval, riscv_cpu_get_trap_name(cause, async)); =20 mode =3D env->priv <=3D PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 440b09fc32..66ed3f6504 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -433,9 +433,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64), VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64), - VMSTATE_UINTTL(env.pc, RISCVCPU), - VMSTATE_UINTTL(env.load_res, RISCVCPU), - VMSTATE_UINTTL(env.load_val, RISCVCPU), + VMSTATE_UINT64(env.pc, RISCVCPU), + VMSTATE_UINT64(env.load_res, RISCVCPU), + VMSTATE_UINT64(env.load_val, RISCVCPU), VMSTATE_UINTTL(env.frm, RISCVCPU), VMSTATE_UINTTL(env.badaddr, RISCVCPU), VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4a557b4907..b444fde3ef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1484,6 +1484,10 @@ void riscv_translate_init(void) /* 32 bits in size, no offset needed */ size_t vl_offset =3D offsetof(CPURISCVState, vl); size_t vstart_offset =3D offsetof(CPURISCVState, vstart); + /* 64 bits in size mapped to TCGv, needs offset */ + size_t pc_offset =3D offsetof(CPURISCVState, pc) + field_offset; + size_t res_offset =3D offsetof(CPURISCVState, load_res) + field_off= set; + size_t val_offset =3D offsetof(CPURISCVState, load_val) + field_off= set; =20 for (i =3D 1; i < 32; i++) { cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, @@ -1499,11 +1503,9 @@ void riscv_translate_init(void) offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); } =20 - cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "p= c"); + cpu_pc =3D tcg_global_mem_new(tcg_env, pc_offset, "pc"); cpu_vl =3D tcg_global_mem_new_i32(tcg_env, vl_offset, "vl"); cpu_vstart =3D tcg_global_mem_new_i32(tcg_env, vstart_offset, "vstart"= ); - load_res =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= res), - "load_res"); - load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), - "load_val"); + load_res =3D tcg_global_mem_new(tcg_env, res_offset, "load_res"); + load_val =3D tcg_global_mem_new(tcg_env, val_offset, "load_val"); } --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868168; cv=none; d=zohomail.com; s=zohoarc; b=LrCBpKdlEjvXg5xMuC3oHrzl4wtr0ZeUVGoZESrwBE1T21IrfsQtnaaJSKI+N6ablOVK6IAivUwXjhKnLxFEgdRXGRLdbrUtF44oBke0vGxnb78ajrSljA6OsyRmj/o15HSbyRhHh+ITku+r4y+JXtxWZuQSmEbTDSJs3SQWblI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778868168; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 15 May 2026 14:00:55 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwq8-0001H1-Md for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=2JICwj0wlF8zs/LeQRG6ti119Y7Tm2Wy6mCaaLd/K6Y=; b=UN3hhlYF33saOao feOr5KG2514AFrqx4hhMCSPmv3HWVFhmwYxgOQd8gTG5XedcWGarrP5YWWCob8c1qF7BWPVzq8M7V yYf4hZ2X9/vdHJWgnbMeFShPM6PNOjEXJzAXbxY2bygNguD/iaq/VziWsOwC3YOEHL8HphtmCjWL+ us=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 04/27] target/riscv: Fix size of frm and fflags Date: Fri, 15 May 2026 20:04:14 +0200 Message-ID: <20260515180437.23620-5-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868170365158500 Content-Type: text/plain; charset="utf-8" According to version 20250508 of the unprivileged specification the frm field of fcsr is 3-bits in size, fix it to 8-bits. Similarly fflags is 5 bits, fix to 8. Uses of frm is restricted to uint8_t where sensible, helpers still need 32-bit arguments and the DisasContext field is kept as int to represent -1 for an unknown rm. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 6 +++--- target/riscv/csr.c | 4 ++++ target/riscv/fpu_helper.c | 10 +++++----- target/riscv/machine.c | 2 +- target/riscv/translate.c | 4 ++-- 5 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 15c9f8b3a0..76c19902c6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -231,7 +231,7 @@ struct CPUArchState { =20 /* Floating-Point state */ uint64_t fpr[32]; /* assume both F and D extensions */ - target_ulong frm; + uint8_t frm; float_status fp_status; =20 target_ulong badaddr; @@ -665,8 +665,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, RISCVException exception, uintptr_t pc); =20 -target_ulong riscv_cpu_get_fflags(CPURISCVState *env); -void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); +uint8_t riscv_cpu_get_fflags(CPURISCVState *env); +void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t); =20 #ifndef CONFIG_USER_ONLY void cpu_set_exception_base(int vp_index, target_ulong address); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da366cf562..4f18e3ff0c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -907,6 +907,10 @@ static RISCVException write_frm(CPURISCVState *env, in= t csrno, static RISCVException read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { + /* + * This is an 8-bit operation, fflags make up the lower 5 bits and + * frm the upper 3 bits of fcsr. + */ *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); return RISCV_EXCP_NONE; diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index af40561b31..e6d1ffb1d6 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -23,10 +23,10 @@ #include "fpu/softfloat.h" #include "internals.h" =20 -target_ulong riscv_cpu_get_fflags(CPURISCVState *env) +uint8_t riscv_cpu_get_fflags(CPURISCVState *env) { int soft =3D get_float_exception_flags(&env->fp_status); - target_ulong hard =3D 0; + uint8_t hard =3D 0; =20 hard |=3D (soft & float_flag_inexact) ? FPEXC_NX : 0; hard |=3D (soft & float_flag_underflow) ? FPEXC_UF : 0; @@ -37,7 +37,7 @@ target_ulong riscv_cpu_get_fflags(CPURISCVState *env) return hard; } =20 -void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) +void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t hard) { int soft =3D 0; =20 @@ -52,7 +52,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulon= g hard) =20 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) { - int softrm; + FloatRoundMode softrm; =20 if (rm =3D=3D RISCV_FRM_DYN) { rm =3D env->frm; @@ -82,7 +82,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_= t rm) =20 void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) { - int softrm; + FloatRoundMode softrm; =20 /* Always validate frm, even if rm !=3D DYN. */ if (unlikely(env->frm >=3D 5)) { diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 66ed3f6504..07995fb303 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -436,7 +436,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.pc, RISCVCPU), VMSTATE_UINT64(env.load_res, RISCVCPU), VMSTATE_UINT64(env.load_val, RISCVCPU), - VMSTATE_UINTTL(env.frm, RISCVCPU), + VMSTATE_UINT8(env.frm, RISCVCPU), VMSTATE_UINTTL(env.badaddr, RISCVCPU), VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b444fde3ef..7c23996271 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -753,7 +753,7 @@ static void finalize_rvv_inst(DisasContext *ctx) ctx->vstart_eq_zero =3D true; } =20 -static void gen_set_rm(DisasContext *ctx, int rm) +static void gen_set_rm(DisasContext *ctx, uint8_t rm) { if (ctx->frm =3D=3D rm) { return; @@ -770,7 +770,7 @@ static void gen_set_rm(DisasContext *ctx, int rm) gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); } =20 -static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) +static void gen_set_rm_chkfrm(DisasContext *ctx, uint8_t rm) { if (ctx->frm =3D=3D rm && ctx->frm_valid) { return; --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868111; cv=none; d=zohomail.com; s=zohoarc; b=MAq1RmwHSps5RzjbwgX0GRjRj5VDq4kpeBi8lIg6TPLv/3mTfr3iZJGKFApqVl6AwiAWlaqPmRLyHoiEdPKJbuGH5oo0ap66TZzrTCmQ8fWZ6GgQa1XrGTHyW3YK1pBi+W4whTnIWSNGhpQaIWMtNWUsLFREf8F/1FfQjt7GRXk= ARC-Message-Signature: i=1; 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To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 05/27] target/riscv: Fix size of badaddr and bins Date: Fri, 15 May 2026 20:04:15 +0200 Message-ID: <20260515180437.23620-6-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868113363158500 Content-Type: text/plain; charset="utf-8" Fix these fields to 64 bits as they cannot be made smaller. Also make sure stores to these fields from TCG are 64 bits in size to avoid incorrect values on big endian hosts. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 4 ++-- target/riscv/machine.c | 2 +- target/riscv/translate.c | 6 ++++-- target/riscv/insn_trans/trans_privileged.c.inc | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 76c19902c6..3c7d4acff2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -234,8 +234,8 @@ struct CPUArchState { uint8_t frm; float_status fp_status; =20 - target_ulong badaddr; - target_ulong bins; + uint64_t badaddr; + uint64_t bins; =20 target_ulong guest_phys_fault_addr; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 07995fb303..b047321073 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -437,7 +437,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.load_res, RISCVCPU), VMSTATE_UINT64(env.load_val, RISCVCPU), VMSTATE_UINT8(env.frm, RISCVCPU), - VMSTATE_UINTTL(env.badaddr, RISCVCPU), + VMSTATE_UINT64(env.badaddr, RISCVCPU), VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7c23996271..1ea7faea4c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -273,7 +273,7 @@ static void generate_exception(DisasContext *ctx, RISCV= Exception excp) =20 static void gen_exception_illegal(DisasContext *ctx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, + tcg_gen_st_i64(tcg_constant_i64(ctx->opcode), tcg_env, offsetof(CPURISCVState, bins)); if (ctx->virt_inst_excp) { generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); @@ -284,7 +284,9 @@ static void gen_exception_illegal(DisasContext *ctx) =20 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) { - tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); + TCGv_i64 ext =3D tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(ext, target); + tcg_gen_st_i64(ext, tcg_env, offsetof(CPURISCVState, badaddr)); generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); } =20 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 8a62b4cfcd..a8eaccef67 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -68,7 +68,7 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) if (pre =3D=3D 0x01f01013 && ebreak =3D=3D 0x00100073 && post =3D=3D 0= x40705013) { generate_exception(ctx, RISCV_EXCP_SEMIHOST); } else { - tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, + tcg_gen_st_i64(tcg_constant_i64(ebreak_addr), tcg_env, offsetof(CPURISCVState, badaddr)); generate_exception(ctx, RISCV_EXCP_BREAKPOINT); } --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868131; cv=none; d=zohomail.com; s=zohoarc; b=gfVKcSM7CAEgjXY6Uc8xQuhD/ju5ixxIZEZ5+uKKguJtZcs7tactBqtilOu+pK9t7zOS4+D+NNp6l9PbfKCxegAl3IJJcF9j9tLZbn2RhYLq1QuUsniXv2nCS6oK6lLUctfUo1U8lDZClY0zttgoCCDZmDxC8RJGk5t9m8yFxOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778868131; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=1iruL33lAUwm3VAULC9tHN/eVySDMJCXDMHGEP/IDUI=; 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Fri, 15 May 2026 14:00:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=1iruL33lAUwm3VAULC9tHN/eVySDMJCXDMHGEP/IDUI=; b=HYXGu5HvGMck61E 1RL2oB+a/0c2HDmTJh1pBZFSpz1phmrmu1JnIc3Li44HwYgsu2T07AGJ2JHqOPh/TSPQcLfGmhTOm /0XcoXn9cvTvcFf2LC1BCvQT9O6ZY+cmjdF3x8f3P4l4rYS1+HTYjq/A6/TwYwy4tAyCORVZ4OGDk o4=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 06/27] target/riscv: Fix size of guest_phys_fault_addr Date: Fri, 15 May 2026 20:04:16 +0200 Message-ID: <20260515180437.23620-7-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868133615158500 Content-Type: text/plain; charset="utf-8" Widen to 64 bits, and use hwaddr as argument to get_physical_address(). Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 3 +-- target/riscv/machine.c | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3c7d4acff2..21f3400cd5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -237,7 +237,7 @@ struct CPUArchState { uint64_t badaddr; uint64_t bins; =20 - target_ulong guest_phys_fault_addr; + uint64_t guest_phys_fault_addr; =20 target_ulong priv_ver; target_ulong vext_ver; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6236f65ff8..752fb7c71d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1236,7 +1236,7 @@ static bool check_svukte_addr(CPURISCVState *env, vad= dr addr) */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, int *ret_prot, vaddr addr, - target_ulong *fault_pte_addr, + hwaddr *fault_pte_addr, int access_type, int mmu_idx, bool first_stage, bool two_stage, bool is_debug, bool is_probe) @@ -1840,7 +1840,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, mmu_idx, true, true, false, probe); - /* * A G-stage exception may be triggered during two state lookup. * And the env->guest_phys_fault_addr has already been set in diff --git a/target/riscv/machine.c b/target/riscv/machine.c index b047321073..27034180c4 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -438,7 +438,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.load_val, RISCVCPU), VMSTATE_UINT8(env.frm, RISCVCPU), VMSTATE_UINT64(env.badaddr, RISCVCPU), - VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), + VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU), VMSTATE_UINTTL(env.priv_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778868124680762.9629250389514; Fri, 15 May 2026 11:02:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wNwqx-0007Yd-TH; Fri, 15 May 2026 14:01:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqG-0007Ip-2h for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:57 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqD-0001HR-SL for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; 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charset="utf-8" Fix these fields to 32 bits, also update corresponding priv_ver field in DisasContext as well as function arguments. 32 bits was chosen since it's large enough to fit all stored values and int/int32_t is used in RISCVCPUDef and a few functions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 6 +++--- target/riscv/machine.c | 4 ++-- target/riscv/translate.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 21f3400cd5..feacf19a5e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -239,8 +239,8 @@ struct CPUArchState { =20 uint64_t guest_phys_fault_addr; =20 - target_ulong priv_ver; - target_ulong vext_ver; + uint32_t priv_ver; + uint32_t vext_ver; =20 /* RISCVMXL, but uint32_t for vmstate migration */ uint32_t misa_mxl; /* current mxl */ @@ -844,7 +844,7 @@ bool riscv_cpu_eff_priv(CPURISCVState *env, int *priv, = bool *virt) } =20 static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, - target_long priv_ver, + uint32_t priv_ver, uint32_t misa_ext) { /* In priv spec version 1.12 or newer, C always implies Zca */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 27034180c4..1cf744c5f0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -439,8 +439,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT8(env.frm, RISCVCPU), VMSTATE_UINT64(env.badaddr, RISCVCPU), VMSTATE_UINT64(env.guest_phys_fault_addr, RISCVCPU), - VMSTATE_UINTTL(env.priv_ver, RISCVCPU), - VMSTATE_UINTTL(env.vext_ver, RISCVCPU), + VMSTATE_UINT32(env.priv_ver, RISCVCPU), + VMSTATE_UINT32(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UNUSED(4), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1ea7faea4c..18a1e0ae99 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -59,7 +59,7 @@ typedef struct DisasContext { DisasContextBase base; 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Fri, 15 May 2026 14:01:01 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqI-0001JJ-6r for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Dif4F/JSwsFoirBfR0Og1xVgR07gWDZRmkt3nSiTV88=; b=Dae+XsDyOzUixdF DTuRSUw4a0s9CK2lwLKQ7/ZpL2KqwLzEblLF1vwftz2aoSRYxiBMwnsn3+Ztk7otCTvkVrfTH3nQT NGJNJRCizhZ9pDFQ5DEOA08WcVhXeFlJVl1LnRmYf3Z/XAyH44VbSENZO7XWpdp3eEjvWuh8uBuVz sE=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 08/27] target/riscv: Fix size of retxh Date: Fri, 15 May 2026 20:04:18 +0200 Message-ID: <20260515180437.23620-9-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868168338158500 Content-Type: text/plain; charset="utf-8" 128-bit helpers only make sense for MXL_RV128, TARGET_RISCV64, and TCGv =3D=3D TCGv_i64, therefore fix retxh to 64 bits. For the sake of being pedandic, update 128-bit instructions to access retxh via 64 bit TCG ops, even if they only make sense when TCGv =3D=3D TCGv_i64. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++++-- target/riscv/insn_trans/trans_rvm.c.inc | 16 ++++++++++++---- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index feacf19a5e..5ecae9b339 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -249,7 +249,7 @@ struct CPUArchState { uint32_t xl; /* current xlen */ =20 /* 128-bit helpers upper part return value */ - target_ulong retxh; + uint64_t retxh; =20 uint64_t jvt; =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 2c82ae41a7..ff450d46f8 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -1030,10 +1030,12 @@ static bool do_csrr_i128(DisasContext *ctx, int rd,= int rc) TCGv destl =3D dest_gpr(ctx, rd); TCGv desth =3D dest_gprh(ctx, rd); TCGv_i32 csr =3D tcg_constant_i32(rc); + TCGv_i64 wide_desth =3D tcg_temp_new_i64(); =20 translator_io_start(&ctx->base); gen_helper_csrr_i128(destl, tcg_env, csr); - tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_ld_i64(wide_desth, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_trunc_i64_tl(desth, wide_desth); gen_set_gpr128(ctx, rd, destl, desth); return do_csr_post(ctx); } @@ -1053,10 +1055,12 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd= , int rc, TCGv destl =3D dest_gpr(ctx, rd); TCGv desth =3D dest_gprh(ctx, rd); TCGv_i32 csr =3D tcg_constant_i32(rc); + TCGv_i64 wide_desth =3D tcg_temp_new_i64(); =20 translator_io_start(&ctx->base); gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh); - tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_ld_i64(wide_desth, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_trunc_i64_tl(desth, wide_desth); gen_set_gpr128(ctx, rd, destl, desth); return do_csr_post(ctx); } diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 795f0ccf14..0e2da5bed2 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -169,8 +169,10 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *= a) static void gen_div_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { + TCGv_i64 wide_rdh =3D tcg_temp_new_i64(); gen_helper_divs_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_trunc_i64_tl(rdh, wide_rdh); } =20 static void gen_div(TCGv ret, TCGv source1, TCGv source2) @@ -212,8 +214,10 @@ static bool trans_div(DisasContext *ctx, arg_div *a) static void gen_divu_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { + TCGv_i64 wide_rdh =3D tcg_temp_new_i64(); gen_helper_divu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_trunc_i64_tl(rdh, wide_rdh); } =20 static void gen_divu(TCGv ret, TCGv source1, TCGv source2) @@ -244,8 +248,10 @@ static bool trans_divu(DisasContext *ctx, arg_divu *a) static void gen_rem_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { + TCGv_i64 wide_rdh =3D tcg_temp_new_i64(); gen_helper_rems_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_trunc_i64_tl(rdh, wide_rdh); } =20 static void gen_rem(TCGv ret, TCGv source1, TCGv source2) @@ -289,8 +295,10 @@ static bool trans_rem(DisasContext *ctx, arg_rem *a) static void gen_remu_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { + TCGv_i64 wide_rdh =3D tcg_temp_new_i64(); gen_helper_remu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_ld_i64(wide_rdh, tcg_env, offsetof(CPURISCVState, retxh)); + tcg_gen_trunc_i64_tl(rdh, wide_rdh); } =20 static void gen_remu(TCGv ret, TCGv source1, TCGv source2) --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778868102060766.934443090602; Fri, 15 May 2026 11:01:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wNwqj-0007Mq-ME; Fri, 15 May 2026 14:01:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqB-0007Hl-2d for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:52 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwq8-0001KJ-4Y for qemu-devel@nongnu.org; Fri, 15 May 2026 14:00:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=qKPf3HvIHXxfyIDjOPh6sqbGcYuK4t1NrcQzAHS+fUg=; b=WJAUxEmPduKXcXr 6Qjc7xFeIXoyjVSa+XAQtKxNnZ/gAJeWbPQNJPxCPEir5YeUoEEVd2toYOs9oy/c/53aSP/fde6yZ gldP1jvK3d4onW0jkpFHO0TtVJsk95OQ4k1eZLiFGJw8N4U+nRzpZLWNF1pLMx5dq08xy7gAXGQDL I8=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 09/27] target/riscv: Fix size of ssp Date: Fri, 15 May 2026 20:04:19 +0200 Message-ID: <20260515180437.23620-10-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868103545158500 Content-Type: text/plain; charset="utf-8" As ssp holds a pointer, fix to 64 bits in size and make sure stores from TCG use the correct size to avoid problems on big endian hosts. Note, the cpu/ssp VMSTATE version is bumped, breaking migration from older versions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/machine.c | 6 +++--- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 18 +++++++++++++----- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5ecae9b339..c93c8e3617 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -256,7 +256,7 @@ struct CPUArchState { /* elp state for zicfilp extension */ bool elp; /* shadow stack register for zicfiss extension */ - target_ulong ssp; + uint64_t ssp; /* env place holder for extra word 2 during unwind */ target_ulong excp_uw2; /* sw check code for sw check exception */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 1cf744c5f0..c55794c554 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -390,11 +390,11 @@ static bool ssp_needed(void *opaque) =20 static const VMStateDescription vmstate_ssp =3D { .name =3D "cpu/ssp", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D ssp_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(env.ssp, RISCVCPU), + VMSTATE_UINT64(env.ssp, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index 0b6ad57965..40e5a1b7df 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -32,7 +32,9 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopch= k *a) TCGLabel *skip =3D gen_new_label(); uint32_t tmp =3D (get_xl(ctx) =3D=3D MXL_RV64) ? 8 : 4; TCGv data =3D tcg_temp_new(); - tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); + TCGv_i64 wide_addr =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp)); + tcg_gen_trunc_i64_tl(addr, wide_addr); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_qemu_ld_tl(data, addr, SS_MMU_INDEX(ctx), mxl_memop(ctx) | MO_ALIGN); @@ -45,7 +47,8 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopch= k *a) tcg_constant_i32(RISCV_EXCP_SW_CHECK)); gen_set_label(skip); tcg_gen_addi_tl(addr, addr, tmp); - tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); + tcg_gen_ext_tl_i64(wide_addr, addr); + tcg_gen_st_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp)); =20 return true; } @@ -59,12 +62,15 @@ static bool trans_sspush(DisasContext *ctx, arg_sspush = *a) TCGv addr =3D tcg_temp_new(); int tmp =3D (get_xl(ctx) =3D=3D MXL_RV64) ? -8 : -4; TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv_i64 wide_addr =3D tcg_temp_new_i64(); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); - tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); + tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp)); + tcg_gen_trunc_i64_tl(addr, wide_addr); tcg_gen_addi_tl(addr, addr, tmp); tcg_gen_qemu_st_tl(data, addr, SS_MMU_INDEX(ctx), mxl_memop(ctx) | MO_ALIGN); - tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); + tcg_gen_ext_tl_i64(wide_addr, addr); + tcg_gen_st_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp)); =20 return true; } @@ -76,7 +82,9 @@ static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a) } =20 TCGv dest =3D dest_gpr(ctx, a->rd); - tcg_gen_ld_tl(dest, tcg_env, offsetof(CPURISCVState, ssp)); + TCGv_i64 wide_addr =3D tcg_temp_new_i64(); + tcg_gen_ld_i64(wide_addr, tcg_env, offsetof(CPURISCVState, ssp)); + tcg_gen_trunc_i64_tl(dest, wide_addr); gen_set_gpr(ctx, a->rd, dest); =20 return true; --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868087; cv=none; d=zohomail.com; s=zohoarc; b=epTozjoNuyTgEee46467CMQqEtsI/v5oa8bytCUL8vv+MuV+s1Vqmc+ugDO88hYoZWQdOWNEUjszYEy+gRVopZJQ5EWM/g8ThSnvke8Svsn3FfvMQxvRPUIyKz2WF8o2nO3LxdthmIcQ8Xg19hTEQFx1jhoc29NcD18XBXXymf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778868087; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c93c8e3617..f4fcf65500 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -258,7 +258,7 @@ struct CPUArchState { /* shadow stack register for zicfiss extension */ uint64_t ssp; /* env place holder for extra word 2 during unwind */ - target_ulong excp_uw2; + uint64_t excp_uw2; /* sw check code for sw check exception */ target_ulong sw_check_code; #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18a1e0ae99..9a0fd700d2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -231,7 +231,7 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 i= n) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } =20 -static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2) +static void decode_save_opc(DisasContext *ctx, uint64_t excp_uw2) { assert(!ctx->insn_start_updated); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868103543158500 The field only holds values of 2 and 3, fix its size to 8 bits and update stores from TCG. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/translate.c | 4 ++-- target/riscv/insn_trans/trans_rvi.c.inc | 8 ++++---- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f4fcf65500..31eda139c6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -260,7 +260,7 @@ struct CPUArchState { /* env place holder for extra word 2 during unwind */ uint64_t excp_uw2; /* sw check code for sw check exception */ - target_ulong sw_check_code; + uint8_t sw_check_code; #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9a0fd700d2..6a1ae92e5a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1400,8 +1400,8 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) if (ctx->fcfi_lp_expected) { /* Emit after insn_start, i.e. before the op following insn_start.= */ tcg_ctx->emit_before_op =3D QTAILQ_NEXT(ctx->base.insn_start, link= ); - tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), - tcg_env, offsetof(CPURISCVState, sw_check_code)); + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_env, offsetof(CPURISCVState, sw_check_code)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); tcg_ctx->emit_before_op =3D NULL; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index ff450d46f8..fea05d02cc 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -53,8 +53,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) /* * misaligned, according to spec we should raise sw check exception */ - tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), - tcg_env, offsetof(CPURISCVState, sw_check_code)); + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_env, offsetof(CPURISCVState, sw_check_code)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); return true; @@ -66,8 +66,8 @@ static bool trans_lpad(DisasContext *ctx, arg_lpad *a) TCGv tmp =3D tcg_temp_new(); tcg_gen_extract_tl(tmp, get_gpr(ctx, xT2, EXT_NONE), 12, 20); tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, a->label, skip); - tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), - tcg_env, offsetof(CPURISCVState, sw_check_code)); + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_env, offsetof(CPURISCVState, sw_check_code)); gen_helper_raise_exception(tcg_env, tcg_constant_i32(RISCV_EXCP_SW_CHECK)); gen_set_label(skip); diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index 40e5a1b7df..cb9c5419fa 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -40,8 +40,8 @@ static bool trans_sspopchk(DisasContext *ctx, arg_sspopch= k *a) mxl_memop(ctx) | MO_ALIGN); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); 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To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 12/27] target/riscv: Fix size of priv Date: Fri, 15 May 2026 20:04:22 +0200 Message-ID: <20260515180437.23620-13-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868214802158500 Content-Type: text/plain; charset="utf-8" The priv field of CPUArchState only stores values in the range [0,3], fix to 8 bits in size and update relevant function arguments. Introduce a new privilege_mode_t typedef for passing around the privilege mode. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 27 +++++++++++++++++---------- target/riscv/internals.h | 4 ++-- target/riscv/pmu.h | 2 +- target/riscv/cpu_helper.c | 37 ++++++++++++++++++++----------------- target/riscv/csr.c | 10 ++++++---- target/riscv/gdbstub.c | 2 +- target/riscv/machine.c | 2 +- target/riscv/op_helper.c | 27 ++++++++++++++------------- target/riscv/pmu.c | 9 ++++++--- target/riscv/translate.c | 2 +- 10 files changed, 69 insertions(+), 53 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 31eda139c6..79d3e74b7a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -109,6 +109,12 @@ typedef struct riscv_cpu_profile { =20 extern RISCVCPUProfile *riscv_profiles[]; =20 +/* + * Type large enough to hold all PRV_* fields, update CPUArchState::priv + * migration field if changing this type. + */ +typedef uint8_t privilege_mode_t; + /* Privileged specification version */ #define PRIV_VER_1_10_0_STR "v1.10.0" #define PRIV_VER_1_11_0_STR "v1.11.0" @@ -265,7 +271,7 @@ struct CPUArchState { uint32_t elf_flags; #endif =20 - target_ulong priv; + privilege_mode_t priv; /* CSRs for execution environment configuration */ uint64_t menvcfg; uint64_t senvcfg; @@ -640,7 +646,7 @@ void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, privilege_mode_t pr= iv, int (*rmw_fn)(void *arg, target_ulong reg, target_ulong *val, @@ -651,10 +657,11 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env= , uint32_t priv, RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); #endif /* !CONFIG_USER_ONLY */ =20 -void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en); +void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv, + bool virt_en); =20 void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, - enum CTRType type, target_ulong prev_priv, bool prev_virt); + enum CTRType type, privilege_mode_t prev_priv, bool prev_virt); void riscv_ctr_clear(CPURISCVState *env); =20 void riscv_translate_init(void); @@ -722,9 +729,9 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURI= SCVState *env) } =20 #if !defined(CONFIG_USER_ONLY) -static inline int cpu_address_mode(CPURISCVState *env) +static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) { - int mode =3D env->priv; + privilege_mode_t mode =3D env->priv; =20 if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); @@ -732,7 +739,7 @@ static inline int cpu_address_mode(CPURISCVState *env) return mode; } =20 -static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) +static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mod= e) { RISCVMXL xl =3D env->misa_mxl; /* @@ -778,7 +785,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *en= v) #ifdef CONFIG_USER_ONLY return env->xl; #else - int mode =3D cpu_address_mode(env); + privilege_mode_t mode =3D cpu_address_mode(env); =20 return cpu_get_xl(env, mode); #endif @@ -816,9 +823,9 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) * Returns true if the effective privilege mode is modified. */ static inline QEMU_ALWAYS_INLINE -bool riscv_cpu_eff_priv(CPURISCVState *env, int *priv, bool *virt) +bool riscv_cpu_eff_priv(CPURISCVState *env, privilege_mode_t *priv, bool *= virt) { - int mode =3D env->priv; + privilege_mode_t mode =3D env->priv; bool virt_enabled =3D false; bool mode_modified =3D false; =20 diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 8c24af0d85..e143a86f97 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -43,9 +43,9 @@ #define MMU_2STAGE_BIT (1 << 2) #define MMU_IDX_SS_WRITE (1 << 3) =20 -static inline int mmuidx_priv(int mmu_idx) +static inline privilege_mode_t mmuidx_priv(int mmu_idx) { - int ret =3D mmu_idx & 3; + privilege_mode_t ret =3D mmu_idx & 3; if (ret =3D=3D MMUIdx_S_SUM) { ret =3D PRV_S; } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3853d0e262..b4f1e469a2 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -34,7 +34,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_even= t_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); -void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newp= riv, bool new_virt); RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, bool upper_half, uint32_t ctr_idx); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 752fb7c71d..ff4e941d94 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -44,7 +44,7 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) return 0; #else bool virt =3D env->virt_enabled; - int mode =3D env->priv; + privilege_mode_t mode =3D env->priv; bool mode_modified =3D false; =20 /* All priv -> mmu_idx mapping are here */ @@ -165,7 +165,7 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env,= bool virt) RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY - int priv_mode; + privilege_mode_t priv_mode; bool virt; =20 riscv_cpu_eff_priv(env, &priv_mode, &virt); @@ -217,7 +217,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY - int priv_mode; + privilege_mode_t priv_mode; =20 if (!riscv_cpu_cfg(env)->ext_ssnpm || get_field(env->mstatus, MSTATUS_MXR) || @@ -245,7 +245,7 @@ bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, boo= l is_vm_ldst) #ifndef CONFIG_USER_ONLY int satp_mode =3D 0; uint64_t satp; - int priv_mode; + privilege_mode_t priv_mode; bool virt =3D false; =20 if (!is_vm_ldst) { @@ -816,7 +816,7 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64= _t (*fn)(void *), env->rdtime_fn_arg =3D arg; } =20 -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, privilege_mode_t pr= iv, int (*rmw_fn)(void *arg, target_ulong reg, target_ulong *val, @@ -849,7 +849,7 @@ void riscv_ctr_clear(CPURISCVState *env) memset(env->ctr_data, 0x0, sizeof(env->ctr_data)); } =20 -static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt) +static uint64_t riscv_ctr_priv_to_mask(privilege_mode_t priv, bool virt) { switch (priv) { case PRV_M: @@ -869,7 +869,8 @@ static uint64_t riscv_ctr_priv_to_mask(target_ulong pri= v, bool virt) g_assert_not_reached(); } =20 -static uint64_t riscv_ctr_get_control(CPURISCVState *env, target_long priv, +static uint64_t riscv_ctr_get_control(CPURISCVState *env, + privilege_mode_t priv, bool virt) { switch (priv) { @@ -891,10 +892,11 @@ static uint64_t riscv_ctr_get_control(CPURISCVState *= env, target_long priv, * and src privilege is less than target privilege. This includes the virt= ual * state as well. */ -static bool riscv_ctr_check_xte(CPURISCVState *env, target_long src_prv, +static bool riscv_ctr_check_xte(CPURISCVState *env, + privilege_mode_t src_prv, bool src_virt) { - target_long tgt_prv =3D env->priv; + privilege_mode_t tgt_prv =3D env->priv; bool res =3D true; =20 /* @@ -980,7 +982,7 @@ static bool riscv_ctr_check_xte(CPURISCVState *env, tar= get_long src_prv, * idx =3D (sctrstatus.WRPTR - entry - 1) & (depth - 1); */ void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, - enum CTRType type, target_ulong src_priv, bool src_virt) + enum CTRType type, privilege_mode_t src_priv, bool src_virt) { bool tgt_virt =3D env->virt_enabled; uint64_t src_mask =3D riscv_ctr_priv_to_mask(src_priv, src_virt); @@ -1078,7 +1080,8 @@ void riscv_ctr_add_entry(CPURISCVState *env, target_l= ong src, target_long dst, env->sctrstatus =3D set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, = head); } =20 -void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool vir= t_en) +void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv, + bool virt_en) { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); =20 @@ -1141,7 +1144,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ul= ong newpriv, bool virt_en) */ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr = addr, int size, MMUAccessType access_type, - int mode) + privilege_mode_t mode) { pmp_priv_t pmp_priv; bool pmp_has_privs; @@ -1165,7 +1168,7 @@ static int get_physical_address_pmp(CPURISCVState *en= v, int *prot, hwaddr addr, =20 /* Returns 'true' if a svukte address check is needed */ static bool do_svukte_check(CPURISCVState *env, bool first_stage, - int mode, bool virt) + privilege_mode_t mode, bool virt) { /* Svukte extension depends on Sv39. */ if (!(env_archcpu(env)->cfg.ext_svukte || @@ -1248,7 +1251,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmuidx_priv(mmu_idx); + privilege_mode_t mode =3D mmuidx_priv(mmu_idx); bool virt =3D mmuidx_2stage(mmu_idx); bool use_background =3D false; hwaddr ppn; @@ -1825,7 +1828,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, bool two_stage_lookup =3D mmuidx_2stage(mmu_idx); bool two_stage_indirect_error =3D false; int ret =3D TRANSLATE_FAIL; - int mode =3D mmuidx_priv(mmu_idx); + privilege_mode_t mode =3D mmuidx_priv(mmu_idx); /* default TLB page size */ hwaddr tlb_size =3D TARGET_PAGE_SIZE; =20 @@ -2211,7 +2214,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool always_storeamo =3D (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); bool vsmode_exc; uint64_t s; - int mode; + privilege_mode_t mode; =20 /* * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -2227,7 +2230,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool smode_double_trap =3D false; uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; const bool prev_virt =3D env->virt_enabled; - const target_ulong prev_priv =3D env->priv; + const privilege_mode_t prev_priv =3D env->priv; uint64_t last_pc =3D env->pc; target_ulong tval =3D 0; target_ulong tinst =3D 0; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4f18e3ff0c..ec08fbddce 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -374,7 +374,7 @@ static RISCVException aia_smode(CPURISCVState *env, int= csrno) static RISCVException aia_smode32(CPURISCVState *env, int csrno) { int ret; - int csr_priv =3D get_field(csrno, 0x300); + privilege_mode_t csr_priv =3D get_field(csrno, 0x300); =20 if (csr_priv =3D=3D PRV_M && !riscv_cpu_cfg(env)->ext_smaia) { return RISCV_EXCP_ILLEGAL_INST; @@ -2653,7 +2653,8 @@ static RISCVException rmw_xireg_aia(CPURISCVState *en= v, int csrno, bool virt =3D false, isel_reserved =3D false; int ret =3D -EINVAL; uint8_t *iprio; - target_ulong priv, vgein; + privilege_mode_t priv; + uint32_t vgein; =20 /* VS-mode CSR number passed in has already been translated */ switch (csrno) { @@ -2938,7 +2939,8 @@ static RISCVException rmw_xtopei(CPURISCVState *env, = int csrno, { bool virt; int ret =3D -EINVAL; - target_ulong priv, vgein; + privilege_mode_t priv; + uint32_t vgein; =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -5612,7 +5614,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, } =20 #if !defined(CONFIG_USER_ONLY) - int csr_priv, effective_priv =3D env->priv; + privilege_mode_t csr_priv, effective_priv =3D env->priv; =20 if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S && !env->virt_enabled) { diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 2c6ccd4761..7abacd0e11 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -223,7 +223,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t = *mem_buf, int n) const unsigned regsz =3D riscv_cpu_is_32bit(cpu) ? 4 : 8; #ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; - uint64_t new_priv =3D ldn(env, mem_buf, regsz) & 0x3; + privilege_mode_t new_priv =3D ldn(env, mem_buf, regsz) & 0x3; bool new_virt =3D 0; =20 if (new_priv =3D=3D PRV_RESERVED) { diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c55794c554..ce5e44325d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -445,7 +445,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UNUSED(4), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), - VMSTATE_UINTTL(env.priv, RISCVCPU), + VMSTATE_UINT8(env.priv, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU), VMSTATE_UINT64(env.resetvec, RISCVCPU), VMSTATE_UINT64(env.mhartid, RISCVCPU), diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 81873014cb..c074b24bc9 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -286,8 +286,9 @@ void helper_sc_probe_write(CPURISCVState *env, target_u= long addr, target_ulong helper_sret(CPURISCVState *env) { uint64_t mstatus; - target_ulong prev_priv, prev_virt =3D env->virt_enabled; - const target_ulong src_priv =3D env->priv; + privilege_mode_t prev_priv; + bool prev_virt =3D env->virt_enabled; + const privilege_mode_t src_priv =3D env->priv; const bool src_virt =3D env->virt_enabled; =20 if (!(env->priv >=3D PRV_S)) { @@ -339,7 +340,7 @@ target_ulong helper_sret(CPURISCVState *env) /* We support Hypervisor extensions and virtulisation is disabled = */ target_ulong hstatus =3D env->hstatus; =20 - prev_virt =3D get_field(hstatus, HSTATUS_SPV); + prev_virt =3D !!(get_field(hstatus, HSTATUS_SPV)); hstatus =3D set_field(hstatus, HSTATUS_SPV, 0); =20 env->hstatus =3D hstatus; @@ -369,7 +370,7 @@ target_ulong helper_sret(CPURISCVState *env) } =20 static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc, - target_ulong prev_priv, + privilege_mode_t prev_priv, uintptr_t ra) { if (!(env->priv >=3D PRV_M)) { @@ -388,8 +389,8 @@ static void check_ret_from_m_mode(CPURISCVState *env, t= arget_ulong retpc, } } static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatu= s, - target_ulong prev_priv, - target_ulong prev_virt) + privilege_mode_t prev_priv, + bool prev_virt) { /* If returning to U, VS or VU, sstatus.sdt =3D 0 */ if (prev_priv =3D=3D PRV_U || (prev_virt && @@ -408,13 +409,13 @@ target_ulong helper_mret(CPURISCVState *env) { target_ulong retpc =3D env->mepc & get_xepc_mask(env); uint64_t mstatus =3D env->mstatus; - target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); + privilege_mode_t prev_priv =3D get_field(mstatus, MSTATUS_MPP); uintptr_t ra =3D GETPC(); =20 check_ret_from_m_mode(env, retpc, prev_priv, ra); =20 - target_ulong prev_virt =3D get_field(env->mstatus, MSTATUS_MPV) && - (prev_priv !=3D PRV_M); + bool prev_virt =3D !!(get_field(env->mstatus, MSTATUS_MPV) && + (prev_priv !=3D PRV_M)); mstatus =3D set_field(mstatus, MSTATUS_MIE, get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); @@ -457,14 +458,14 @@ target_ulong helper_mret(CPURISCVState *env) target_ulong helper_mnret(CPURISCVState *env) { target_ulong retpc =3D env->mnepc; - target_ulong prev_priv =3D get_field(env->mnstatus, MNSTATUS_MNPP); - target_ulong prev_virt; + privilege_mode_t prev_priv =3D get_field(env->mnstatus, MNSTATUS_MNPP); + bool prev_virt; uintptr_t ra =3D GETPC(); =20 check_ret_from_m_mode(env, retpc, prev_priv, ra); =20 - prev_virt =3D get_field(env->mnstatus, MNSTATUS_MNPV) && - (prev_priv !=3D PRV_M); + prev_virt =3D !!(get_field(env->mnstatus, MNSTATUS_MNPV) && + (prev_priv !=3D PRV_M)); env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, true); =20 /* diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 708f2ec7aa..3444400bd2 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -114,7 +114,8 @@ static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, ui= nt32_t ctr_idx) * new priv and new virt values are passed in as arguments. */ static void riscv_pmu_icount_update_priv(CPURISCVState *env, - target_ulong newpriv, bool new_vi= rt) + privilege_mode_t newpriv, + bool new_virt) { uint64_t *snapshot_prev, *snapshot_new; uint64_t current_icount; @@ -154,7 +155,8 @@ static void riscv_pmu_icount_update_priv(CPURISCVState = *env, } =20 static void riscv_pmu_cycle_update_priv(CPURISCVState *env, - target_ulong newpriv, bool new_vir= t) + privilege_mode_t newpriv, + bool new_virt) { uint64_t *snapshot_prev, *snapshot_new; uint64_t current_ticks; @@ -189,7 +191,8 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState *= env, counter_arr[env->priv] +=3D delta; } =20 -void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv, +void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, + privilege_mode_t newpriv, bool new_virt) { riscv_pmu_cycle_update_priv(env, newpriv, new_virt); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6a1ae92e5a..3132386801 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -68,7 +68,7 @@ typedef struct DisasContext { RISCVExtStatus mstatus_fs; RISCVExtStatus mstatus_vs; uint32_t mem_idx; - uint32_t priv; + privilege_mode_t priv; /* * Remember the rounding mode encoded in the previous fp instruction, * which we have already installed into env->fp_status. Or -1 for --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868247; cv=none; d=zohomail.com; s=zohoarc; b=mxlcR4YimFcq5uEV/eSR5gyPoEuopSbgHVJoRblv8DtgXeAVNshq+N0M0NVllAV3p2DLKXIJdfVXWbEbSw/hEiVeXH0bxqZJnKJzLB4A9WBqFR2Lvqmw6UUsDXiNWRkPx8y4+0lFsQcygbaiZx/Ltx0sd/65NgYx4qxy3KjZTDw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778868247; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=1I3Bgv0SQHY8SsYW832jIY3xIe6YZKMN3LWNdtZDkRc=; b=dXGy1wAH+KbeRKtgj1w2yYWBZRd82zU7yxurhUE0oi7STWbyeSGYP7r7xQFHSEAVCMQuYnnZAL/+LMnF6qcJi8fCXqkZGsar54xjvaWd0dkhE/Tzcv65LlmDC9jXJxbXicuWkSH0kW+z8EWaHFoas1xR2yXHeOluLttM/cB9u98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177886824701889.65159734964038; Fri, 15 May 2026 11:04:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wNwqx-0007YY-F3; Fri, 15 May 2026 14:01:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqL-0007Km-I1 for qemu-devel@nongnu.org; Fri, 15 May 2026 14:01:07 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqI-0001MA-7r for qemu-devel@nongnu.org; Fri, 15 May 2026 14:01:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=1I3Bgv0SQHY8SsYW832jIY3xIe6YZKMN3LWNdtZDkRc=; b=RzL/mX6+TKVos4K DmEgxAGgcaXGAyIRJz+ISEP563Gdub9S8oZKmcIzf98tdl+/Vz0pGcCG5hJlMSeQdWKJ+QBriK+gv sk3KOuu8/4Y6yG51jsi9VcyQmQFTgyPaZ1mi6Ge7qwW4RLJqK4aeJS7rimJG5Fl2uz6QOrypnGJSf FA=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 13/27] target/riscv: Fix size of gei fields Date: Fri, 15 May 2026 20:04:23 +0200 Message-ID: <20260515180437.23620-14-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868247195158500 Content-Type: text/plain; charset="utf-8" geilen takes the values 31 or 63, fix it to 8 bits. hgeie and hgeip are at most 64 bits in size, fix to 64. Update relevant function arguments and uses of hgeie and hgeip. Note, masking is widened to 64-bit as geilen is already verified to be smaller than the target long size, and an out-of-bounds shift would be UB anyway. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 10 +++++----- target/riscv/cpu.c | 4 ++-- target/riscv/cpu_helper.c | 4 ++-- target/riscv/csr.c | 4 ++-- target/riscv/machine.c | 4 ++-- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 79d3e74b7a..a2ba5bef60 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -279,7 +279,7 @@ struct CPUArchState { #ifndef CONFIG_USER_ONLY /* This contains QEMU specific information about the virt state. */ bool virt_enabled; - target_ulong geilen; + uint8_t geilen; uint64_t resetvec; =20 uint64_t mhartid; @@ -356,8 +356,8 @@ struct CPUArchState { uint64_t htval; uint64_t htinst; uint64_t hgatp; - target_ulong hgeie; - target_ulong hgeip; + uint64_t hgeie; + uint64_t hgeip; uint64_t htimedelta; uint64_t hvien; =20 @@ -609,8 +609,8 @@ int riscv_cpu_mirq_pending(CPURISCVState *env); int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); bool riscv_cpu_fp_enabled(CPURISCVState *env); -target_ulong riscv_cpu_get_geilen(CPURISCVState *env); -void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); +uint8_t riscv_cpu_get_geilen(CPURISCVState *env); +void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 27310a95d1..d7219edd87 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1064,9 +1064,9 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) } =20 /* Update HGEIP CSR */ - env->hgeip &=3D ~((target_ulong)1 << irq); + env->hgeip &=3D ~(1ULL << irq); if (level) { - env->hgeip |=3D (target_ulong)1 << irq; + env->hgeip |=3D 1ULL << irq; } =20 /* Update mip.SGEIP bit */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ff4e941d94..e7c0ff49d0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -712,7 +712,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) } } =20 -target_ulong riscv_cpu_get_geilen(CPURISCVState *env) +uint8_t riscv_cpu_get_geilen(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { return 0; @@ -721,7 +721,7 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env) return env->geilen; } =20 -void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) +void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen) { if (!riscv_has_ext(env, RVH)) { return; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ec08fbddce..0e84554f29 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3768,7 +3768,7 @@ static RISCVException rmw_mip64(CPURISCVState *env, i= nt csrno, =20 if (csrno !=3D CSR_HVIP) { gin =3D get_field(env->hstatus, HSTATUS_VGEIN); - old_mip |=3D (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP := 0; + old_mip |=3D (env->hgeip & (1ULL << gin)) ? MIP_VSEIP : 0; old_mip |=3D env->vstime_irq ? MIP_VSTIP : 0; } =20 @@ -4953,7 +4953,7 @@ static RISCVException write_hgeie(CPURISCVState *env,= int csrno, target_ulong val, uintptr_t ra) { /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ - val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; + val &=3D ((1ULL << env->geilen) - 1) << 1; env->hgeie =3D val; /* Update mip.SGEIP bit */ riscv_cpu_update_mip(env, MIP_SGEIP, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ce5e44325d..8a8f5be8d6 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -91,8 +91,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINT64(env.htval, RISCVCPU), VMSTATE_UINT64(env.htinst, RISCVCPU), VMSTATE_UINT64(env.hgatp, RISCVCPU), - VMSTATE_UINTTL(env.hgeie, RISCVCPU), - VMSTATE_UINTTL(env.hgeip, RISCVCPU), + VMSTATE_UINT64(env.hgeie, RISCVCPU), + VMSTATE_UINT64(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.hvien, RISCVCPU), VMSTATE_UINT64(env.hvip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Jy9nyZQyx6N5Xui1oQjtJJ4nKG3WCoXEYeMk56ZFPSQ=; b=T09XO0I/RGpjZ56 9axVHG4SQDidTWsssVucJzhcsINW7RPlE2AeHCpB3TYtX5FSagrK8wAupn26wj1qv2yVQK5rkIHr1 KafPIAMweVnPn76cWxnAwEhqE0WtX6yKp8JhCts8wB62k98GOT8f8iNhd6Kou52rcOblPcFIvhk5N /E=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 14/27] target/riscv: Fix size of [m|s|vs]iselect fields Date: Fri, 15 May 2026 20:04:24 +0200 Message-ID: <20260515180437.23620-15-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868194591158500 Content-Type: text/plain; charset="utf-8" [m|s|vs]iselect are defined in version 20250508 of the privileged specification to be XLEN in size, however QEMU only ever uses at most 16 bits of these fields, so fix them to 16. Update relevant function arguments. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 6 +++--- target/riscv/csr.c | 32 ++++++++++++++++---------------- target/riscv/machine.c | 6 +++--- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a2ba5bef60..0e925f4b0b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -343,8 +343,8 @@ struct CPUArchState { uint8_t siprio[64]; =20 /* AIA CSRs */ - target_ulong miselect; - target_ulong siselect; + uint16_t miselect; + uint16_t siselect; uint64_t mvien; uint64_t mvip; =20 @@ -390,7 +390,7 @@ struct CPUArchState { uint64_t vsatp; =20 /* AIA VS-mode CSRs */ - target_ulong vsiselect; + uint16_t vsiselect; =20 uint64_t mtval2; uint64_t mtinst; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0e84554f29..4bab7ec29f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2422,7 +2422,7 @@ static RISCVException rmw_xiselect(CPURISCVState *env= , int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - target_ulong *iselect; + uint16_t *iselect; int ret; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); @@ -2465,18 +2465,18 @@ static RISCVException rmw_xiselect(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static bool xiselect_aia_range(target_ulong isel) +static bool xiselect_aia_range(uint16_t isel) { return (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) || (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LAST); } =20 -static bool xiselect_cd_range(target_ulong isel) +static bool xiselect_cd_range(uint16_t isel) { return (ISELECT_CD_FIRST <=3D isel && isel <=3D ISELECT_CD_LAST); } =20 -static bool xiselect_ctr_range(int csrno, target_ulong isel) +static bool xiselect_ctr_range(int csrno, uint16_t isel) { /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */ return CTR_ENTRIES_FIRST <=3D isel && isel <=3D CTR_ENTRIES_LAST && @@ -2484,7 +2484,7 @@ static bool xiselect_ctr_range(int csrno, target_ulon= g isel) } =20 static int rmw_iprio(target_ulong xlen, - target_ulong iselect, uint8_t *iprio, + uint16_t iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, target_ulong wr_mask, int ext_irq_no) { @@ -2528,7 +2528,7 @@ static int rmw_iprio(target_ulong xlen, return 0; } =20 -static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val, +static int rmw_ctrsource(CPURISCVState *env, uint16_t isel, target_ulong *= val, target_ulong new_val, target_ulong wr_mask) { /* @@ -2567,7 +2567,7 @@ static int rmw_ctrsource(CPURISCVState *env, int isel= , target_ulong *val, return 0; } =20 -static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val, +static int rmw_ctrtarget(CPURISCVState *env, uint16_t isel, target_ulong *= val, target_ulong new_val, target_ulong wr_mask) { /* @@ -2606,7 +2606,7 @@ static int rmw_ctrtarget(CPURISCVState *env, int isel= , target_ulong *val, return 0; } =20 -static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val, +static int rmw_ctrdata(CPURISCVState *env, uint16_t isel, target_ulong *va= l, target_ulong new_val, target_ulong wr_mask) { /* @@ -2647,7 +2647,7 @@ static int rmw_ctrdata(CPURISCVState *env, int isel, = target_ulong *val, } =20 static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { bool virt =3D false, isel_reserved =3D false; @@ -2728,12 +2728,12 @@ done: } =20 static int rmw_xireg_cd(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { int ret =3D -EINVAL; - int ctr_index =3D isel - ISELECT_CD_FIRST; - int isel_hpm_start =3D ISELECT_CD_FIRST + 3; + uint16_t ctr_index =3D isel - ISELECT_CD_FIRST; + uint16_t isel_hpm_start =3D ISELECT_CD_FIRST + 3; =20 if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_sscc= fg) { ret =3D RISCV_EXCP_ILLEGAL_INST; @@ -2800,7 +2800,7 @@ done: } =20 static int rmw_xireg_ctr(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) { @@ -2828,7 +2828,7 @@ static int rmw_xireg_ctr(CPURISCVState *env, int csrn= o, * extension using csrind should be implemented here. */ static int rmw_xireg_csrind(CPURISCVState *env, int csrno, - target_ulong isel, target_ulong *val, + uint16_t isel, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { bool virt =3D csrno =3D=3D CSR_VSIREG ? true : false; @@ -2858,7 +2858,7 @@ static int rmw_xiregi(CPURISCVState *env, int csrno, = target_ulong *val, target_ulong new_val, target_ulong wr_mask) { int ret =3D -EINVAL; - target_ulong isel; + uint16_t isel; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); if (ret !=3D RISCV_EXCP_NONE) { @@ -2889,7 +2889,7 @@ static RISCVException rmw_xireg(CPURISCVState *env, i= nt csrno, target_ulong wr_mask) { int ret =3D -EINVAL; - target_ulong isel; + uint16_t isel; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); if (ret !=3D RISCV_EXCP_NONE) { diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8a8f5be8d6..376075b2bd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -108,7 +108,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINT64(env.vscause, RISCVCPU), VMSTATE_UINT64(env.vstval, RISCVCPU), VMSTATE_UINT64(env.vsatp, RISCVCPU), - VMSTATE_UINTTL(env.vsiselect, RISCVCPU), + VMSTATE_UINT16(env.vsiselect, RISCVCPU), VMSTATE_UINT64(env.vsie, RISCVCPU), =20 VMSTATE_UINT64(env.mtval2, RISCVCPU), @@ -467,8 +467,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.mepc, RISCVCPU), VMSTATE_UINT64(env.mcause, RISCVCPU), VMSTATE_UINT64(env.mtval, RISCVCPU), - VMSTATE_UINTTL(env.miselect, RISCVCPU), - VMSTATE_UINTTL(env.siselect, RISCVCPU), + VMSTATE_UINT16(env.miselect, RISCVCPU), + VMSTATE_UINT16(env.siselect, RISCVCPU), VMSTATE_UINT32(env.scounteren, RISCVCPU), VMSTATE_UINT32(env.mcounteren, RISCVCPU), VMSTATE_UINT32(env.scountinhibit, RISCVCPU), --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=0a5EFRy/YTIm7ekObM3W8nkrbiAxS2wuBFwwGZBTtm0=; b=VvvVWLKahdLVd5o yRtT39c1wT54mqid/v0AE0T1E3c2NAAHcYq6Hr9+wGMJD2RTFw+9XvBR2A4vzFds4uKZ9jYmXaLWD 6cw6aXg/R3o0b/Ao6ghGr9JE4UKfegChHts11avQxwPWt8RW9L4AUdlJbT2asimwPlHRf7NUqVFUo xQ=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 15/27] target/riscv: Fix arguments to board IMSIC emulation callbacks Date: Fri, 15 May 2026 20:04:25 +0200 Message-ID: <20260515180437.23620-16-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868143822158500 Content-Type: text/plain; charset="utf-8" In hw/ the relevant RISCVIMSICState fields eidelivery, eithreshold, eistate are uint32_t. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Acked-by: Alistair Francis --- target/riscv/cpu.h | 42 ++++++++++++++++++++------------------- hw/intc/riscv_imsic.c | 34 +++++++++++++++---------------- target/riscv/cpu_helper.c | 12 ++++------- target/riscv/csr.c | 24 ++++++++++++---------- 4 files changed, 57 insertions(+), 55 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0e925f4b0b..e9d3bed6f9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -200,6 +200,24 @@ FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, ALTFMT, 8, 1) FIELD(VTYPE, RESERVED, 9, sizeof(uint64_t) * 8 - 10) =20 +#ifndef CONFIG_USER_ONLY +/* machine specific AIA ireg read-modify-write callback */ +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) = \ + ((uint32_t)((((__xlen) & 0xff) << 24) | = \ + (((__vgein) & 0x3f) << 20) | = \ + (((__virt) & 0x1) << 18) | = \ + (((__priv) & 0x3) << 16) | = \ + (__isel & 0xffff))) +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) +#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) + +typedef int (*aia_ireg_rmw_fn)(void *arg, uint32_t reg, uint64_t *val, + uint64_t new_val, uint64_t write_mask); +#endif + typedef struct PMUCTRState { /* Current value of a counter */ uint64_t mhpmcounter_val; @@ -465,20 +483,8 @@ struct CPUArchState { void *rdtime_fn_arg; =20 /* machine specific AIA ireg read-modify-write callback */ -#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ - ((((__xlen) & 0xff) << 24) | \ - (((__vgein) & 0x3f) << 20) | \ - (((__virt) & 0x1) << 18) | \ - (((__priv) & 0x3) << 16) | \ - (__isel & 0xffff)) -#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) -#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) -#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) -#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) -#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) - int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, - target_ulong *val, target_ulong new_val, target_ulong write_mask); - void *aia_ireg_rmw_fn_arg[4]; + aia_ireg_rmw_fn aia_ireg_rmw_cb[4]; + void *aia_ireg_rmw_cb_arg[4]; =20 /* True if in debugger mode. */ bool debugger; @@ -646,12 +652,8 @@ void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, privilege_mode_t pr= iv, - int (*rmw_fn)(void *arg, - target_ulong reg, - target_ulong *val, - target_ulong new_val, - target_ulong write_mask), +void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t pr= iv, + aia_ireg_rmw_fn rmw_fn, void *rmw_fn_arg); =20 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 7c9a012033..3ce9f146c0 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -88,11 +88,11 @@ static void riscv_imsic_update(RISCVIMSICState *imsic, = uint32_t page) } =20 static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t pag= e, - target_ulong *val, - target_ulong new_val, - target_ulong wr_mask) + uint64_t *val, + uint64_t new_val, + uint64_t wr_mask) { - target_ulong old_val =3D imsic->eidelivery[page]; + uint32_t old_val =3D imsic->eidelivery[page]; =20 if (val) { *val =3D old_val; @@ -106,11 +106,11 @@ static int riscv_imsic_eidelivery_rmw(RISCVIMSICState= *imsic, uint32_t page, } =20 static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t pa= ge, - target_ulong *val, - target_ulong new_val, - target_ulong wr_mask) + uint64_t *val, + uint64_t new_val, + uint64_t wr_mask) { - target_ulong old_val =3D imsic->eithreshold[page]; + uint32_t old_val =3D imsic->eithreshold[page]; =20 if (val) { *val =3D old_val; @@ -124,8 +124,8 @@ static int riscv_imsic_eithreshold_rmw(RISCVIMSICState = *imsic, uint32_t page, } =20 static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page, - target_ulong *val, target_ulong new_val, - target_ulong wr_mask) + uint64_t *val, uint64_t new_val, + uint64_t wr_mask) { uint32_t base, topei =3D riscv_imsic_topei(imsic, page); =20 @@ -149,11 +149,11 @@ static int riscv_imsic_topei_rmw(RISCVIMSICState *ims= ic, uint32_t page, =20 static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, uint32_t xlen, uint32_t page, - uint32_t num, bool pend, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) + uint32_t num, bool pend, uint64_t *val, + uint64_t new_val, uint64_t wr_mask) { uint32_t i, base, prev; - target_ulong mask; + uint64_t mask; uint32_t state =3D (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENAB= LED; =20 if (xlen !=3D 32) { @@ -178,7 +178,7 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, continue; } =20 - mask =3D (target_ulong)1 << i; + mask =3D 1ull << i; if (wr_mask & mask) { if (new_val & mask) { prev =3D qatomic_fetch_or(&imsic->eistate[base + i], state= ); @@ -197,8 +197,8 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, return 0; } =20 -static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val, - target_ulong new_val, target_ulong wr_mask) +static int riscv_imsic_rmw(void *arg, uint32_t reg, uint64_t *val, + uint64_t new_val, uint64_t wr_mask) { RISCVIMSICState *imsic =3D arg; uint32_t isel, priv, virt, vgein, xlen, page; @@ -383,7 +383,7 @@ static void riscv_imsic_realize(DeviceState *dev, Error= **errp) } =20 if (!kvm_irqchip_in_kernel()) { - riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PR= V_S, + riscv_cpu_set_aia_ireg_rmw_cb(env, (imsic->mmode) ? PRV_M : PR= V_S, riscv_imsic_rmw, imsic); } } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e7c0ff49d0..90c126fdc2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -816,17 +816,13 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint= 64_t (*fn)(void *), env->rdtime_fn_arg =3D arg; } =20 -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, privilege_mode_t pr= iv, - int (*rmw_fn)(void *arg, - target_ulong reg, - target_ulong *val, - target_ulong new_val, - target_ulong write_mask), +void riscv_cpu_set_aia_ireg_rmw_cb(CPURISCVState *env, privilege_mode_t pr= iv, + aia_ireg_rmw_fn rmw_fn, void *rmw_fn_arg) { if (priv <=3D PRV_M) { - env->aia_ireg_rmw_fn[priv] =3D rmw_fn; - env->aia_ireg_rmw_fn_arg[priv] =3D rmw_fn_arg; + env->aia_ireg_rmw_cb[priv] =3D rmw_fn; + env->aia_ireg_rmw_cb_arg[priv] =3D rmw_fn_arg; } } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4bab7ec29f..837212b55f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2655,6 +2655,7 @@ static RISCVException rmw_xireg_aia(CPURISCVState *en= v, int csrno, uint8_t *iprio; privilege_mode_t priv; uint32_t vgein; + uint64_t wide_val; =20 /* VS-mode CSR number passed in has already been translated */ switch (csrno) { @@ -2699,16 +2700,17 @@ static RISCVException rmw_xireg_aia(CPURISCVState *= env, int csrno, } } else if (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LA= ST) { /* IMSIC registers only available when machine implements it. */ - if (env->aia_ireg_rmw_fn[priv]) { + if (env->aia_ireg_rmw_cb[priv]) { /* Selected guest interrupt file should not be zero */ if (virt && (!vgein || env->geilen < vgein)) { goto done; } /* Call machine specific IMSIC register emulation */ - ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[pr= iv], + ret =3D env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[pr= iv], AIA_MAKE_IREG(isel, priv, virt, vgein, riscv_cpu_mxl_bits(env)), - val, new_val, wr_mask); + &wide_val, new_val, wr_mask); + *val =3D wide_val; } } else { isel_reserved =3D true; @@ -2941,6 +2943,7 @@ static RISCVException rmw_xtopei(CPURISCVState *env, = int csrno, int ret =3D -EINVAL; privilege_mode_t priv; uint32_t vgein; + uint64_t wide_val; =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -2966,7 +2969,7 @@ static RISCVException rmw_xtopei(CPURISCVState *env, = int csrno, }; =20 /* IMSIC CSRs only available when machine implements IMSIC. */ - if (!env->aia_ireg_rmw_fn[priv]) { + if (!env->aia_ireg_rmw_cb[priv]) { goto done; } =20 @@ -2979,10 +2982,11 @@ static RISCVException rmw_xtopei(CPURISCVState *env= , int csrno, } =20 /* Call machine specific IMSIC register emulation for TOPEI */ - ret =3D env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], + ret =3D env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[priv], AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, riscv_cpu_mxl_bits(env)), - val, new_val, wr_mask); + &wide_val, new_val, wr_mask); + *val =3D wide_val; =20 done: if (ret) { @@ -4486,7 +4490,7 @@ static RISCVException read_vstopi(CPURISCVState *env,= int csrno, target_ulong *val) { int irq, ret; - target_ulong topei; + uint64_t topei =3D 0; uint64_t vseip, vsgein; uint32_t iid, iprio, hviid, hviprio, gein; uint32_t s, scount =3D 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRC= S]; @@ -4501,13 +4505,13 @@ static RISCVException read_vstopi(CPURISCVState *en= v, int csrno, if (gein <=3D env->geilen && vseip) { siid[scount] =3D IRQ_S_EXT; siprio[scount] =3D IPRIO_MMAXIPRIO + 1; - if (env->aia_ireg_rmw_fn[PRV_S]) { + if (env->aia_ireg_rmw_cb[PRV_S]) { /* * Call machine specific IMSIC register emulation for * reading TOPEI. */ - ret =3D env->aia_ireg_rmw_fn[PRV_S]( - env->aia_ireg_rmw_fn_arg[PRV_S], + ret =3D env->aia_ireg_rmw_cb[PRV_S]( + env->aia_ireg_rmw_cb_arg[PRV_S], AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, ge= in, riscv_cpu_mxl_bits(env)), &topei, 0, 0); --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=ah/1dICPkTg/6HRoUxIzNNJZpUruo0Yemrd/I+7gnns=; b=Gqv40g31Zyl+ao2 ZoIZqqVWutK1BlbDE/O7s7J6KC3ApeEsy0uB69tmJtQpm6NwWoFzw3Lj4kb3oukUwCNSx7JK/nSAm my4xyXE0kIcrNG2rbHbSMfYmmLbMwBfHBBo4q3ivgiVrf7Le8vXVmxz5bCD5PQhezcfcHHzfo/eWm Ew=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 16/27] target/riscv: Fix size of irq_overflow_left Date: Fri, 15 May 2026 20:04:26 +0200 Message-ID: <20260515180437.23620-17-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868208711158500 Fix to 64 bits to hold all relevant values. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e9d3bed6f9..269bc07e2d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -224,7 +224,7 @@ typedef struct PMUCTRState { /* Snapshot value of a counter */ uint64_t mhpmcounter_prev; /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ - target_ulong irq_overflow_left; + uint64_t irq_overflow_left; } PMUCTRState; =20 typedef struct PMUFixedCtrState { --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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=20 typedef struct PMUFixedCtrState { - /* Track cycle and icount for each privilege mode */ - uint64_t counter[4]; - uint64_t counter_prev[4]; - /* Track cycle and icount for each privilege mode when V =3D 1*/ - uint64_t counter_virt[2]; - uint64_t counter_virt_prev[2]; + /* Track cycle and icount for each privilege mode */ + uint64_t counter[4]; + uint64_t counter_prev[4]; + /* Track cycle and icount for each privilege mode when V =3D 1*/ + uint64_t counter_virt[2]; + uint64_t counter_virt_prev[2]; } PMUFixedCtrState; =20 struct CPUArchState { --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868141; cv=none; d=zohomail.com; s=zohoarc; b=Y+ff26R8IF3/5W4hjhuMQllGEWGX04kv4hhp3la8rTZ7GdQKO7QsW8JfEERVXUX9e2ZCLxIfW1wI9SduLHL7Hcz3Dutzy0LwxKKQJpufgtbnW+EqMe8kgp8BNHtPG9zgdhFbBeLNcLq8BktHzwNmCnIe2n6imxevAb3c9Jp4SxI= ARC-Message-Signature: i=1; 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To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 18/27] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Date: Fri, 15 May 2026 20:04:28 +0200 Message-ID: <20260515180437.23620-19-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868143690158500 Fix cause argument to 64 bit to match env->mcause. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2787bc0386..becf594fc7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -601,7 +601,7 @@ extern const char * const riscv_int_regnamesh[]; extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_rvv_regnames[]; =20 -const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); +const char *riscv_cpu_get_trap_name(uint64_t cause, bool async); int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d7219edd87..4cff10b0d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -370,7 +370,7 @@ static const char * const riscv_intr_names[] =3D { [IRQ_PMU_OVF] =3D "counter_overflow", }; =20 -const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) +const char *riscv_cpu_get_trap_name(uint64_t cause, bool async) { if (async) { if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cau= se]) { --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868217; cv=none; d=zohomail.com; s=zohoarc; b=kRc39T4D7FoVIOJymp7S0PH5l4AliF7gQUkaCkwRmBxYN7Uj81HaveQS+Cwcoj6rwBVOfdJWfEfNRDSMZ2/8wTy8fLi7v3rAWzT759dggZhlEeUZYuHp+DKVFgj/Rm1X57XybSQoI7Ldl9/yz/4IjafdfYT89Cfshy4benZciqE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778868217; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Fri, 15 May 2026 14:01:11 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqM-0001Nl-6h for qemu-devel@nongnu.org; Fri, 15 May 2026 14:01:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=EFxonNCNYzmhcDIwW9OqT1YlKlkJpgGTL8a4puX01t8=; b=uBzOSHDfaRNvIql ZZ9Jj0BKAuhBPVVEBfDj7PbmS1cq9hQCEkRpIKjiLfR0V9mKyNZs5qV6jkngCw35tRhA2LnnTMvsY Mb/ZBwd7+N5w+RTSuhlyjqP3pxVv++F26thWbLljDpio05gS/NLMbh87c6/dcMo4S9wJ7K+AYPVO3 eM=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 19/27] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Date: Fri, 15 May 2026 20:04:29 +0200 Message-ID: <20260515180437.23620-20-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868218927158500 Widen to 64 bits in size to hold all relevant values. Note: src and dst arguments change from signed to unsigned but no functional change is incurred. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu_helper.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index becf594fc7..032bcba025 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -662,8 +662,9 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int= index, uint64_t bit); void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv, bool virt_en); =20 -void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, - enum CTRType type, privilege_mode_t prev_priv, bool prev_virt); +void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst, + enum CTRType type, privilege_mode_t prev_priv, + bool prev_virt); void riscv_ctr_clear(CPURISCVState *env); =20 void riscv_translate_init(void); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 90c126fdc2..c4d396fa11 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -977,8 +977,9 @@ static bool riscv_ctr_check_xte(CPURISCVState *env, * entry =3D isel - CTR_ENTRIES_FIRST; * idx =3D (sctrstatus.WRPTR - entry - 1) & (depth - 1); */ -void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long = dst, - enum CTRType type, privilege_mode_t src_priv, bool src_virt) +void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst, + enum CTRType type, privilege_mode_t src_priv, + bool src_virt) { bool tgt_virt =3D env->virt_enabled; uint64_t src_mask =3D riscv_ctr_priv_to_mask(src_priv, src_virt); --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868186; cv=none; d=zohomail.com; s=zohoarc; b=lGba6tPHSA3bQlYqkbB2AUZNECSshfx7SwolYNysa+x2Howoukqyp/M3Y0ZT+CCjAwoEDdf3AXzFzqvR81yEfVC/AwcNujZ1SUC1lZL8M4ZWfNoTovuBxH33Fa3GA6sgYvWa6+BD3aBD22GthGfOHlPhpm+RXW8zYoyxSd0vCJk= ARC-Message-Signature: i=1; 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To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 20/27] target/riscv: Fix size of trigger data Date: Fri, 15 May 2026 20:04:30 +0200 Message-ID: <20260515180437.23620-21-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868188481158500 mcontext is at most 14 bits in size with the H extension, fix to 16 bits. trigger_cur indexes into tdata*[RV_MAX_TRIGGERS] which holds 2 elements, fix to 8 bits. This patch also adds a migration entry for mcontext which is used in tandem with other debug data that is already migrated. Note, the cpu/debug VMSTATE version is bumped, breaking migration from older versions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu.h | 10 +++++----- target/riscv/machine.c | 13 +++++++------ 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 032bcba025..f34b19470b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -467,11 +467,11 @@ struct CPUArchState { target_ulong mseccfg; =20 /* trigger module */ - target_ulong trigger_cur; - target_ulong tdata1[RV_MAX_TRIGGERS]; - target_ulong tdata2[RV_MAX_TRIGGERS]; - target_ulong tdata3[RV_MAX_TRIGGERS]; - target_ulong mcontext; + uint16_t mcontext; + uint8_t trigger_cur; + uint64_t tdata1[RV_MAX_TRIGGERS]; + uint64_t tdata2[RV_MAX_TRIGGERS]; + uint64_t tdata3[RV_MAX_TRIGGERS]; struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 376075b2bd..c6ebb58882 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -239,15 +239,16 @@ static int debug_post_load(void *opaque, int version_= id) =20 static const VMStateDescription vmstate_debug =3D { .name =3D "cpu/debug", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .needed =3D debug_needed, .post_load =3D debug_post_load, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), - VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINT16(env.mcontext, RISCVCPU), + VMSTATE_UINT8(env.trigger_cur, RISCVCPU), + VMSTATE_UINT64_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINT64_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINT64_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), VMSTATE_END_OF_LIST() } }; --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868160; cv=none; d=zohomail.com; s=zohoarc; b=bqLazxodXz4DXKLCE2LtSoJetPkEFrCtCQTwFEHyWsBHw1Kpd4aSDRlPxPpJAiR1yTr4HsItCl3MzO5KwcTrK/+dXd5T0CAuzuLuFcX6aRAO65uCKEXjGY7bEPosz2jT7PbHXEEOOwvF2mxLsy1+v5GmVhT+r3kywM4kNR1kCuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778868160; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=9am6gYHdbA5/081RdyVXNrSde+WPT2MqADZHWGGw6sA=; b=bxpAYOcF0QDqRIoYfwCbSASxeWL/z2KDBDS5qSIzuAyKcDGmOi8h1kUDM0ascadxlkaUSjoW/IA1+rOyaXFZ7nFMd8PKdDj1fNBpU9+WQsjPTT7Qj0+5PCXyaVKVx81XRuOpwoP52zw9x/+GBsChqnU0hvh6Tm86PtDlYt0Wh5Q= ARC-Authentication-Results: i=1; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=9am6gYHdbA5/081RdyVXNrSde+WPT2MqADZHWGGw6sA=; b=MHYqqxAYC30pjSD 8RNcaq1qbMmGwpaXMBInXMnQgfLMAoKa+JtdtWeww8mGgYqg5ImVYsweolN4LognRw64OeXZndDOX 2U5wzYMXHgeujGJzhDM2z618m9Mfwd3wIZI4FiBhZ2XJr895GIZAFpplPh4udRiD2mPTeteXgv1A6 dM=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 21/27] target/riscv: Fix size of mseccfg Date: Fri, 15 May 2026 20:04:31 +0200 Message-ID: <20260515180437.23620-22-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868162081158500 mseccfg is defined in version 20250508 of the privileged specification to be 64 bits in size. Update relevant function arguments. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/pmp.h | 4 ++-- target/riscv/pmp.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f34b19470b..126c4647c8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -464,7 +464,7 @@ struct CPUArchState { =20 /* physical memory protection */ pmp_table_t pmp_state; - target_ulong mseccfg; + uint64_t mseccfg; =20 /* trigger module */ uint16_t mcontext; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 17307ef88a..91130289d8 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -71,8 +71,8 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_in= dex, target_ulong val); target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); =20 -void mseccfg_csr_write(CPURISCVState *env, target_ulong val); -target_ulong mseccfg_csr_read(CPURISCVState *env); +void mseccfg_csr_write(CPURISCVState *env, uint64_t val); +uint64_t mseccfg_csr_read(CPURISCVState *env); =20 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, target_ulong val); diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 5391caa59c..bc4ab8ad15 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -659,7 +659,7 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint3= 2_t addr_index) /* * Handle a write to a mseccfg CSR */ -void mseccfg_csr_write(CPURISCVState *env, target_ulong val) +void mseccfg_csr_write(CPURISCVState *env, uint64_t val) { int i; uint64_t mask =3D MSECCFG_MMWP | MSECCFG_MML; @@ -705,7 +705,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) /* * Handle a read from a mseccfg CSR */ -target_ulong mseccfg_csr_read(CPURISCVState *env) +uint64_t mseccfg_csr_read(CPURISCVState *env) { trace_mseccfg_csr_read(env->mhartid, env->mseccfg); return env->mseccfg; --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=UhQ7BUV2gEIk4L+Yg+Zmpwk4sjAZt7rJjl4Kr3cUN+w=; b=btjkW/AO7EVn294 8r95dDCWSHklA4hy9xMH4y4JmnfHGRSgumtX7kaJECgK1Iru94h6SQLN/Go/jNd5ZMsuJ//v5Q49c jcPwvpSddOUhxHulN0dKCJWNBt4Q4mkWIcOcQNr+XhxQM4aDMueSCEgfqk4Eyct6hKGKDrvqcU4Nu wA=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 22/27] target/riscv: Move debug.h include away from cpu.h Date: Fri, 15 May 2026 20:04:32 +0200 Message-ID: <20260515180437.23620-23-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868147862158500 All debug.h definitions except for RV_MAX_TRIGGERS are internal to target/riscv. Move RV_MAX_TRIGGERS to cpu.h and include debug.h from all translation units which relied on the cpu.h include. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 2 +- target/riscv/debug.h | 2 -- target/riscv/cpu.c | 3 +++ target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 3 +++ target/riscv/debug.c | 1 + target/riscv/machine.c | 2 +- target/riscv/tcg/tcg-cpu.c | 1 + 8 files changed, 11 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 126c4647c8..d7a0b083d1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -186,12 +186,12 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_impli= ed_rules[]; =20 #if !defined(CONFIG_USER_ONLY) #include "pmp.h" -#include "debug.h" #endif =20 #define RV_VLEN_MAX 1024 #define RV_MAX_MHPMEVENTS 32 #define RV_MAX_MHPMCOUNTERS 32 +#define RV_MAX_TRIGGERS 2 =20 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 066e9c585f..55a3ac72e6 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -25,8 +25,6 @@ #include "exec/breakpoint.h" #include "exec/target_long.h" =20 -#define RV_MAX_TRIGGERS 2 - /* register index of tdata CSRs */ enum { TDATA1 =3D 0, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4cff10b0d3..133ec5cbc3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -37,6 +37,9 @@ #include "kvm/kvm_riscv.h" #include "tcg/tcg-cpu.h" #include "tcg/tcg.h" +#if !defined(CONFIG_USER_ONLY) +#include "target/riscv/debug.h" +#endif =20 /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] =3D "IEMAFDQCBPVH"; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c4d396fa11..1086c37690 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -34,7 +34,7 @@ #include "semihosting/common-semi.h" #include "exec/icount.h" #include "cpu_bits.h" -#include "debug.h" +#include "target/riscv/debug.h" #include "pmp.h" #include "qemu/plugin.h" =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 837212b55f..7908ea02a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -31,6 +31,9 @@ #include "qapi/error.h" #include "tcg/insn-start-words.h" #include "internals.h" +#if !defined(CONFIG_USER_ONLY) +#include "target/riscv/debug.h" +#endif =20 /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5664466749..30d39ee5cd 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "cpu.h" +#include "target/riscv/debug.h" #include "trace.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c6ebb58882..36f4c3251d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -22,7 +22,7 @@ #include "system/kvm.h" #include "migration/cpu.h" #include "exec/icount.h" -#include "debug.h" +#include "target/riscv/debug.h" =20 static bool pmp_needed(void *opaque) { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 02c98cc2db..90ed360648 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -37,6 +37,7 @@ #include "hw/core/boards.h" #include "system/tcg.h" #include "exec/icount.h" +#include "target/riscv/debug.h" #endif =20 /* Hash that stores user set extensions */ --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=W/DLWrRh5+Y4og+0LUFPAspmS8bfpYDPmYoWzEDDT+s=; b=f3O8NAV4SHM6ZM4 CKxeEq0zZFm8iWh8w1vaGR2tHx7xhit4xh86Recgp8biES9q60uSNIG8hu9mYyHxpEz4E53NpXJst Uzaf/7TcQJ/lic+s+D7lI/ZDa6mSodLs5+jZJedJqEIM+HR72O4UDoCJLOIziEjnCikgtrX4q7p8U xU=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 23/27] target/riscv: Move CSR declarations to separate csr.h header Date: Fri, 15 May 2026 20:04:33 +0200 Message-ID: <20260515180437.23620-24-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868257482158500 Most of these definitions save riscv_csrr, riscv_csrrw, riscv_csr_read, riscv_csr_write are only used in target/. Move declarations to a separate headers which will soon be made internal to target/. csr.h is temporarily included from cpu.h to not break includes from outside target/, this include will be removed in the following commit. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 87 +---------------------------- target/riscv/csr.h | 100 ++++++++++++++++++++++++++++++++++ target/riscv/cpu.c | 1 + target/riscv/csr.c | 1 + target/riscv/gdbstub.c | 1 + target/riscv/kvm/kvm-cpu.c | 1 + target/riscv/mips_csr.c | 1 + target/riscv/monitor.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/riscv-qmp-cmds.c | 1 + target/riscv/th_csr.c | 1 + 11 files changed, 110 insertions(+), 86 deletions(-) create mode 100644 target/riscv/csr.h diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d7a0b083d1..eb18e1f59f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -903,75 +903,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); =20 -RISCVException riscv_csrr(CPURISCVState *env, int csrno, - target_ulong *ret_value); - -RISCVException riscv_csrrw(CPURISCVState *env, int csrno, - target_ulong *ret_value, target_ulong new_value, - target_ulong write_mask, uintptr_t ra); -RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, - target_ulong write_mask); - -static inline void riscv_csr_write(CPURISCVState *env, int csrno, - target_ulong val) -{ - riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS= ), 0); -} - -static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) -{ - target_ulong val =3D 0; - riscv_csrr(env, csrno, &val); - return val; -} - -typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, - int csrno); -typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value); -typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, - target_ulong new_value, - uintptr_t ra); -typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, - target_ulong *ret_value, - target_ulong new_value, - target_ulong write_mask); - -RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, - Int128 *ret_value); -RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, - Int128 *ret_value, Int128 new_value, - Int128 write_mask, uintptr_t ra); - -typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csr= no, - Int128 *ret_value); -typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int cs= rno, - Int128 new_value); - -typedef struct { - const char *name; - riscv_csr_predicate_fn predicate; - riscv_csr_read_fn read; - riscv_csr_write_fn write; - riscv_csr_op_fn op; - riscv_csr_read128_fn read128; - riscv_csr_write128_fn write128; - /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0)= */ - uint32_t min_priv_ver; -} riscv_csr_operations; - -struct RISCVCSR { - int csrno; - bool (*insertion_test)(RISCVCPU *cpu); - riscv_csr_operations csr_ops; -}; - -/* CSR function table constants */ -enum { - CSR_TABLE_SIZE =3D 0x1000 -}; +#include "target/riscv/csr.h" =20 /* * The event id are encoded based on the encoding specified in the @@ -1015,28 +947,11 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Erro= r **errp); void riscv_add_satp_mode_properties(Object *obj); bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 -/* CSR function table */ -extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; -bool riscv_csr_is_fpu(int csrno); -bool riscv_csr_is_vpu(int csrno); - extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; =20 -void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); -void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops); - void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 -target_ulong riscv_new_csr_seed(target_ulong new_value, - target_ulong write_mask); - const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 -/* In th_csr.c */ -extern const RISCVCSR th_csr_list[]; - -/* Implemented in mips_csr.c */ -extern const RISCVCSR mips_csr_list[]; - const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.h b/target/riscv/csr.h new file mode 100644 index 0000000000..fef3cd34cb --- /dev/null +++ b/target/riscv/csr.h @@ -0,0 +1,100 @@ +/* + * QEMU RISC-V CSRs + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef RISCV_CSR_H +#define RISCV_CSR_H + +target_ulong riscv_new_csr_seed(target_ulong new_value, + target_ulong write_mask); + +RISCVException riscv_csrr(CPURISCVState *env, int csrno, + target_ulong *ret_value); + +RISCVException riscv_csrrw(CPURISCVState *env, int csrno, + target_ulong *ret_value, target_ulong new_value, + target_ulong write_mask, uintptr_t ra); +RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); + +static inline void riscv_csr_write(CPURISCVState *env, int csrno, + target_ulong val) +{ + riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS= ), 0); +} + +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) +{ + target_ulong val =3D 0; + riscv_csrr(env, csrno, &val); + return val; +} + +typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, + int csrno); +typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value); +typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, + target_ulong new_value, + uintptr_t ra); +typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, + target_ulong *ret_value, + target_ulong new_value, + target_ulong write_mask); + +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, + Int128 *ret_value); +RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, + Int128 *ret_value, Int128 new_value, + Int128 write_mask, uintptr_t ra); + +typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csr= no, + Int128 *ret_value); +typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int cs= rno, + Int128 new_value); + +typedef struct { + const char *name; + riscv_csr_predicate_fn predicate; + riscv_csr_read_fn read; + riscv_csr_write_fn write; + riscv_csr_op_fn op; + riscv_csr_read128_fn read128; + riscv_csr_write128_fn write128; + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0)= */ + uint32_t min_priv_ver; +} riscv_csr_operations; + +struct RISCVCSR { + int csrno; + bool (*insertion_test)(RISCVCPU *cpu); + riscv_csr_operations csr_ops; +}; + +/* CSR function table constants */ +enum { + CSR_TABLE_SIZE =3D 0x1000 +}; + +/* CSR function table */ +extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; + +bool riscv_csr_is_fpu(int csrno); +bool riscv_csr_is_vpu(int csrno); + +void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); +void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops); + +/* In th_csr.c */ +extern const RISCVCSR th_csr_list[]; + +/* Implemented in mips_csr.c */ +extern const RISCVCSR mips_csr_list[]; + +#endif /* RISCV_CSR_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 133ec5cbc3..daad317381 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "cpu_vendorid.h" +#include "target/riscv/csr.h" #include "internals.h" #include "qapi/error.h" #include "qapi/visitor.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7908ea02a5..6cc3fcd4e3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" +#include "target/riscv/csr.h" #include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 7abacd0e11..a2bbaf7f07 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -21,6 +21,7 @@ #include "gdbstub/helpers.h" #include "cpu.h" #include "internals.h" +#include "target/riscv/csr.h" =20 struct TypeSize { const char *gdb_type; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index b047ffa9c0..1f730f337e 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -31,6 +31,7 @@ #include "system/kvm.h" #include "system/kvm_int.h" #include "cpu.h" +#include "target/riscv/csr.h" #include "trace.h" #include "accel/accel-cpu-target.h" #include "hw/pci/pci.h" diff --git a/target/riscv/mips_csr.c b/target/riscv/mips_csr.c index 822e25e346..609718f288 100644 --- a/target/riscv/mips_csr.c +++ b/target/riscv/mips_csr.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "cpu_vendorid.h" +#include "target/riscv/csr.h" =20 /* Static MIPS CSR state storage */ static struct { diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 9edac0533c..3e89dcaf7c 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/qemu-print.h" #include "cpu.h" +#include "target/riscv/csr.h" #include "cpu_bits.h" #include "monitor/monitor.h" #include "monitor/hmp.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c074b24bc9..3dc8c4f6b3 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "target/riscv/csr.h" #include "internals.h" #include "exec/cputlb.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 8a1856c50e..d1c64c1e7f 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -35,6 +35,7 @@ #include "system/tcg.h" #include "cpu-qom.h" #include "cpu.h" +#include "target/riscv/csr.h" =20 static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c index 49eb7bbab5..a4ea4ce391 100644 --- a/target/riscv/th_csr.c +++ b/target/riscv/th_csr.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "cpu_vendorid.h" +#include "target/riscv/csr.h" =20 #define CSR_TH_SXSTATUS 0x5c0 =20 --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868239067158500 Content-Type: text/plain; charset="utf-8" Convert riscv_csr_[read|write]() into target_ulong angnostic CSR access functions that can be safely used from outside of target/ without knowledge of the target register size. Replace the 4 existing CSR accesses in hw/ and linux-user/. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 7 ++++++- target/riscv/csr.h | 13 ------------- hw/riscv/riscv_hart.c | 7 +++---- linux-user/riscv/signal.c | 5 +++-- target/riscv/csr.c | 17 +++++++++++++++++ 5 files changed, 29 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eb18e1f59f..3352409676 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -903,7 +903,12 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); =20 -#include "target/riscv/csr.h" +/* + * Externally facing CSR access functions, wrappers around riscv_csr*(). + */ + +int riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val); +int riscv_csr_read_i64(CPURISCVState *env, int csrn, uint64_t *res); =20 /* * The event id are encoded based on the encoding specified in the diff --git a/target/riscv/csr.h b/target/riscv/csr.h index fef3cd34cb..370da83a69 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -23,19 +23,6 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int= csrno, target_ulong new_value, target_ulong write_mask); =20 -static inline void riscv_csr_write(CPURISCVState *env, int csrno, - target_ulong val) -{ - riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS= ), 0); -} - -static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) -{ - target_ulong val =3D 0; - riscv_csrr(env, csrno, &val); - return val; -} - typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno); typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index e675358e1a..d1c7188369 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -67,12 +67,11 @@ static void csr_call(char *cmd, uint64_t cpu_num, int c= srno, uint64_t *val) RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(cpu_num)); CPURISCVState *env =3D &cpu->env; =20 - int ret =3D RISCV_EXCP_NONE; + RISCVException ret =3D RISCV_EXCP_NONE; if (strcmp(cmd, "get_csr") =3D=3D 0) { - ret =3D riscv_csrr(env, csrno, (target_ulong *)val); + ret =3D riscv_csr_read_i64(env, csrno, val); } else if (strcmp(cmd, "set_csr") =3D=3D 0) { - ret =3D riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, - MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); + ret =3D riscv_csr_write_i64(env, csrno, *val); } =20 g_assert(ret =3D=3D RISCV_EXCP_NONE); diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index 358fa1d82d..9d5ba300e4 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -90,7 +90,8 @@ static void setup_sigcontext(struct target_sigcontext *sc= , CPURISCVState *env) __put_user(env->fpr[i], &sc->fpr[i]); } =20 - uint32_t fcsr =3D riscv_csr_read(env, CSR_FCSR); + uint64_t fcsr; + riscv_csr_read_i64(env, CSR_FCSR, &fcsr); __put_user(fcsr, &sc->fcsr); } =20 @@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, stru= ct target_sigcontext *sc) =20 uint32_t fcsr; __get_user(fcsr, &sc->fcsr); - riscv_csr_write(env, CSR_FCSR, fcsr); + riscv_csr_write_i64(env, CSR_FCSR, fcsr); } =20 static void restore_ucontext(CPURISCVState *env, struct target_ucontext *u= c) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6cc3fcd4e3..3ffb56e938 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5716,6 +5716,23 @@ RISCVException riscv_csrrw(CPURISCVState *env, int c= srno, return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, = ra); } =20 +int riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val) +{ + RISCVException ret; + ret =3D riscv_csrrw(env, csrno, NULL, val, + MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); + return ret; +} + +int riscv_csr_read_i64(CPURISCVState *env, int csrno, uint64_t *res) +{ + RISCVException ret; + target_ulong val =3D 0; + ret =3D riscv_csrr(env, csrno, &val); + *res =3D val; + return ret; +} + static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1778868176; cv=none; d=zohomail.com; s=zohoarc; b=E/dnLdV3tRYWj5C1WXvne8agdkctMnq9APCHhrR+ynBgXDIsrKa8mC+Fhj5ztJVMkYHMNjBi5qJv/LFpjztxUZj6ipWVs66sYYHA+hbl9YYrvWpEhQrNKf8FEDYccuGS2RsKFJzztHHQGNkdHQ8X+4nobB9QB37BCf47TsNu33U= ARC-Message-Signature: i=1; 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To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 25/27] target/riscv: Make pmp.h target_ulong agnostic Date: Fri, 15 May 2026 20:04:35 +0200 Message-ID: <20260515180437.23620-26-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868178510158500 The pmp.h header is exposed through cpu.h. pmp_table_t is also used in CPUArchState. CSR declarations are only used in target/ and are moved to csr.h. In pmp.h, addr_reg is widened to 64 bits and the privilege mode parameter is fixed to 8 bits, similar to previous commits. Note, the cpu/pmp/entry and cpu/pmp VMSTATE versions are bumped, breaking migration from older versions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/csr.h | 12 ++++++++++++ target/riscv/pmp.h | 19 +++++-------------- target/riscv/machine.c | 10 +++++----- target/riscv/pmp.c | 10 ++++++---- 4 files changed, 28 insertions(+), 23 deletions(-) diff --git a/target/riscv/csr.h b/target/riscv/csr.h index 370da83a69..5ee3f38ac5 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -84,4 +84,16 @@ extern const RISCVCSR th_csr_list[]; /* Implemented in mips_csr.c */ extern const RISCVCSR mips_csr_list[]; =20 +/* PMP CSRs, defined in pmp.c */ +void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, + target_ulong val); +target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); + +void mseccfg_csr_write(CPURISCVState *env, uint64_t val); +uint64_t mseccfg_csr_read(CPURISCVState *env); + +void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, + target_ulong val); +target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); + #endif /* RISCV_CSR_H */ diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 91130289d8..eae305ac6f 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -22,7 +22,6 @@ #ifndef RISCV_PMP_H #define RISCV_PMP_H =20 -#include "exec/target_long.h" #include "cpu.h" =20 typedef enum { @@ -52,7 +51,7 @@ typedef enum { } mseccfg_field_t; =20 typedef struct { - target_ulong addr_reg; + uint64_t addr_reg; uint8_t cfg_reg; } pmp_entry_t; =20 @@ -67,21 +66,13 @@ typedef struct { uint32_t num_rules; } pmp_table_t; =20 -void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, - target_ulong val); -target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); +typedef struct CPUArchState CPURISCVState; =20 -void mseccfg_csr_write(CPURISCVState *env, uint64_t val); -uint64_t mseccfg_csr_read(CPURISCVState *env); - -void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, - target_ulong val); -target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, - target_ulong size, pmp_priv_t privs, + int size, pmp_priv_t privs, pmp_priv_t *allowed_privs, - target_ulong mode); -target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr); + privilege_mode_t mode); +uint64_t pmp_get_tlb_size(CPURISCVState *env, hwaddr addr); void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); void pmp_update_rule_nums(CPURISCVState *env); uint32_t pmp_get_num_rules(CPURISCVState *env); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 36f4c3251d..13eb292c4a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -48,10 +48,10 @@ static int pmp_post_load(void *opaque, int version_id) =20 static const VMStateDescription vmstate_pmp_entry =3D { .name =3D "cpu/pmp/entry", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (const VMStateField[]) { - VMSTATE_UINTTL(addr_reg, pmp_entry_t), + VMSTATE_UINT64(addr_reg, pmp_entry_t), VMSTATE_UINT8(cfg_reg, pmp_entry_t), VMSTATE_END_OF_LIST() } @@ -59,8 +59,8 @@ static const VMStateDescription vmstate_pmp_entry =3D { =20 static const VMStateDescription vmstate_pmp =3D { .name =3D "cpu/pmp", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D pmp_needed, .post_load =3D pmp_post_load, .fields =3D (const VMStateField[]) { diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index bc4ab8ad15..9b26a3c1b4 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "cpu.h" +#include "target/riscv/csr.h" #include "trace.h" #include "exec/cputlb.h" #include "exec/page-protection.h" @@ -310,7 +311,7 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_= index, hwaddr addr) */ static bool pmp_hart_has_privs_default(CPURISCVState *env, pmp_priv_t priv= s, pmp_priv_t *allowed_privs, - target_ulong mode) + privilege_mode_t mode) { bool ret; =20 @@ -373,8 +374,9 @@ static bool pmp_hart_has_privs_default(CPURISCVState *e= nv, pmp_priv_t privs, * have no functional impact in QEMU emulation. */ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, - target_ulong size, pmp_priv_t privs, - pmp_priv_t *allowed_privs, target_ulong mode) + int size, pmp_priv_t privs, + pmp_priv_t *allowed_privs, + privilege_mode_t mode) { int i =3D 0; int pmp_size =3D 0; @@ -724,7 +726,7 @@ uint64_t mseccfg_csr_read(CPURISCVState *env) * To avoid this we return a size of 1 (which means no caching) if the PMP * region only covers partial of the TLB page. */ -target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr) +uint64_t pmp_get_tlb_size(CPURISCVState *env, hwaddr addr) { hwaddr pmp_sa; hwaddr pmp_ea; --=20 2.52.0 From nobody Thu May 28 00:44:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778868125773286.4336998560907; Fri, 15 May 2026 11:02:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wNwr6-0007k4-MU; Fri, 15 May 2026 14:01:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqb-0007N1-Hv for qemu-devel@nongnu.org; Fri, 15 May 2026 14:01:21 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wNwqR-0001Rj-Gc for qemu-devel@nongnu.org; Fri, 15 May 2026 14:01:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; 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charset="utf-8" The corresponding field CPUArchState::resetvec is uint64_t anyway, no need to use target_ulong. Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3352409676..ad5d23ee6b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -679,7 +679,7 @@ uint8_t riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t); =20 #ifndef CONFIG_USER_ONLY -void cpu_set_exception_base(int vp_index, target_ulong address); +void cpu_set_exception_base(int vp_index, uint64_t address); #endif =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index daad317381..753f92307f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -79,7 +79,7 @@ bool riscv_cpu_option_set(const char *optname) =20 #ifndef CONFIG_USER_ONLY /* This is used in runtime only. */ -void cpu_set_exception_base(int vp_index, target_ulong address) +void cpu_set_exception_base(int vp_index, uint64_t address) { RISCVCPU *cpu; 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Fri, 15 May 2026 14:01:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=4copfV3KOUSGQI/wq6tJqErp7sDw4BebeHasptGS1lM=; b=WGHEM3MhkP6TFf/ iBKJ1eYTaD7jnU7W0hM2/m1i/UjJBcmuxQlNm126Bcn3mKtMntYOG5QovAnLovQM2TaGZbs7pD79O /eCIQyuYNThQgcW+JpP3xrgh5uphegVWuSTpw2znBQcX/tspkMnz1eXpDYqj9vuo0Hhai/t+ZeZy1 hA=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, Anton Johansson Subject: [PATCH v6 27/27] target/riscv: Fix pmp.h/cpu.h circular inclusion Date: Fri, 15 May 2026 20:04:37 +0200 Message-ID: <20260515180437.23620-28-anjo@rev.ng> In-Reply-To: <20260515180437.23620-1-anjo@rev.ng> References: <20260515180437.23620-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1778868176308158500 Content-Type: text/plain; charset="utf-8" pmp.h is only needed and included for system mode, however relevant macros (MAX_RISCV_PMPS, OLD_MAX_RISCV_PMPS, MIN_RISCV_PMP_GRANULARITY) are required unconditionally by cpu.c, and so are defined in cpu.h. pmp.h then defines pmp_table_t depending on these macros and so requires cpu.h, and cpu.h in turn uses pmp_table_t resulting in circular inclusion. Move PMP macros to pmp.h and only exose PMP properties in system mode. Signed-off-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 4 ---- target/riscv/pmp.h | 4 +++- target/riscv/cpu.c | 6 ++++++ 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad5d23ee6b..4bd24c15c5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -180,10 +180,6 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implie= d_rules[]; =20 #define MMU_USER_IDX 3 =20 -#define MAX_RISCV_PMPS (64) -#define OLD_MAX_RISCV_PMPS (16) -#define MIN_RISCV_PMP_GRANULARITY 4 - #if !defined(CONFIG_USER_ONLY) #include "pmp.h" #endif diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index eae305ac6f..4c95c2767a 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -22,7 +22,9 @@ #ifndef RISCV_PMP_H #define RISCV_PMP_H =20 -#include "cpu.h" +#define MAX_RISCV_PMPS (64) +#define OLD_MAX_RISCV_PMPS (16) +#define MIN_RISCV_PMP_GRANULARITY 4 =20 typedef enum { PMP_READ =3D 1 << 0, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 753f92307f..36f9570f2d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1127,7 +1127,9 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; cpu->cfg.pmp_regions =3D 16; +#ifndef CONFIG_USER_ONLY cpu->cfg.pmp_granularity =3D MIN_RISCV_PMP_GRANULARITY; +#endif cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; =20 @@ -1550,6 +1552,7 @@ static const PropertyInfo prop_mmu =3D { .set =3D prop_mmu_set, }; =20 +#ifndef CONFIG_USER_ONLY static void prop_pmp_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1658,6 +1661,7 @@ static const PropertyInfo prop_pmp_granularity =3D { .get =3D prop_pmp_granularity_get, .set =3D prop_pmp_granularity_set, }; +#endif /* !CONFIG_USER_ONLY */ =20 static int priv_spec_from_str(const char *priv_spec_str) { @@ -2666,9 +2670,11 @@ static const Property riscv_cpu_properties[] =3D { {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 {.name =3D "mmu", .info =3D &prop_mmu}, +#ifndef CONFIG_USER_ONLY {.name =3D "pmp", .info =3D &prop_pmp}, {.name =3D "num-pmp-regions", .info =3D &prop_num_pmp_regions}, {.name =3D "pmp-granularity", .info =3D &prop_pmp_granularity}, +#endif =20 {.name =3D "priv_spec", .info =3D &prop_priv_spec}, {.name =3D "vext_spec", .info =3D &prop_vext_spec}, --=20 2.52.0