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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fc8d69d0bsm16350635e9.13.2026.05.12.13.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2026 13:34:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1778618059; x=1779222859; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cEpKJWK5V6JDGRyw7DYJPQ9RxwfD1fQlpX/kpuDU7mw=; b=uqHUhGpEllQQWFqohi2RbiYU6QYP6zZrqTXgF+hEnSdxzir3KHsmbZY7OWewweIe7D sdemjkjskauCuweR0eREzA/DKhDFc4N8Nk1e8iv86xwCRKX/b2NIInIbujSB30wxaa3g XwW1sDM7ax0d559YnzDwRVtSgPTS3jj3YHibBvkHuOvukouFcRem+TVhK3L5rmZiR9/1 k0pzXZ2Kf4zW/nhjm/aXM8crdg9dXFERlTCK4nw2aw442N4LU1GYCynHta87CWzSxizv Ra0yAK3AANOanEH6q1h4Ij6xudUsUBlA6KtVVvFmQ0MF+/4NGl0k0r27MmADdpR+P/JJ QwYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778618059; x=1779222859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=cEpKJWK5V6JDGRyw7DYJPQ9RxwfD1fQlpX/kpuDU7mw=; b=fn2VTk0ZyGsgR95OrnH0Jccl5+tkKowJOpVH8+MKUYK9AdfM74b7BaJs3qn5nU4TCJ hUiQVIYtKgVO/0SeQBHYlttLTw/zTuSo7GOZnuDNw6YnDo+VnJRPF/juGCxQ8gRPNvDe dRNXqLq8XRbYirSI38GO59pAEQAo/0E85OjTGcWJG4cnPa3+QHrPJK2kxvcC4FnCVbCp s0mDYepkuKlAw9HFiSdxt+8i7gRt/i7V3sLlpnW+Z7TxjFnMafwbdkdr0niO2QCcJkma HmHR4pF/Q3usSirw3eXIAApbtvQfqJv4RXp6JQY22xqXJMi4SANJ5UXdX63OyS3hOJTg BRfg== X-Forwarded-Encrypted: i=1; AFNElJ9l6qcaQaEq+/heV8uJJ38MTxTUYKt8ybAYFe6AtnjhVNfAeAn0bOU77M062Be/wnwKqqmFZVspK9tS@nongnu.org X-Gm-Message-State: AOJu0YzEK4hnnitCGbiThoyf92bb3YWvmJVwalGbJiS8VTgei2R7dxyj 8mePGIxagYb9hG11r5HmzbKPkjj5rl7q0GdI9O1WwUCStfjxJdv3n/AIRdDsgCtKYHg5PMv81x1 jCuV6 X-Gm-Gg: Acq92OENVBkKLJle8Tpt9/UBRbTwCIxpUGi6ZMtYNpg3Vc9DcFYoQRlv+bU4lFlNkby qHKnFOhArP98zXtcc668fudjdeCr/wFxuuRFvQd7d1jsU+avuI76nwgyTUPI4o9vdjjamdmUiFM T55vOn1OEn9v1V5dtkP5c4vjJIReAumVoEippPhk5KOnCXkyfZS+QKYpa3o+Gaxth7PsY8FG5+I 6a4/Ju9tpb3uvDdrGwtGdCd/U4Mwx43RrdfNW7PR+pN78MifkDXs8jBPtXXoovtR98gs/1tZ9I7 WBSxN1CsbZ305dk6f2tWTQSuf3r4ynjjBbcqtfYZ9UCuMrGXe0zbkdr5pCr3BbEAEQVXJmfIVvW wvmsrPI9mvzDEPKGzqRQ/x/mmwhKopa74eXIyeg3yJuq9GJ1ePQfcsRdI8IQJFETsB8CAeP6V4F NHS8ubCSzP36qlU2aLMjc/AYSE7s0ENCa+RRiFXw5WkHJ4lVqj6APsLA9QvRsBZb9liXLyctUHd hVeaSQQkgDWmbygIDOh7vv1NRLlaenJAhdCbpbpfQ== X-Received: by 2002:a05:600c:1d03:b0:48a:906a:9050 with SMTP id 5b1f17b1804b1-48fc9a100damr6299365e9.10.1778618058987; Tue, 12 May 2026 13:34:18 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/12] hw/arm/omap: Remove omap_mpu_model remnants Date: Tue, 12 May 2026 21:34:03 +0100 Message-ID: <20260512203414.3633237-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512203414.3633237-1-peter.maydell@linaro.org> References: <20260512203414.3633237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778618136374154100 Content-Type: text/plain; charset="utf-8" The omap1.c code has handling for an mpu_model field which is an enum of which OMAP SoC model it is. We removed most of our OMAP support some time ago, and now the only OMAP SoC we implement is the OMAP310, which sets s->mpu_model =3D omap310 in omap310_mpu_init(). That makes all the handling for other settings of mpu_model dead code; remove them. This includes the omap GPIO device's mpu_model property which we set but which the device makes no use of, and the omap-id-e20 memory region (because the OMAP310 satisfies cpu_is_omap15xx(), so never executed the old if() block). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/omap1.c | 28 ++-------------------------- hw/gpio/omap_gpio.c | 6 ------ hw/misc/omap_clk.c | 9 +-------- include/hw/arm/omap.h | 18 ------------------ 4 files changed, 3 insertions(+), 58 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 980959166d..c9f9c3ef40 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -948,8 +948,6 @@ static void omap_pin_cfg_init(MemoryRegion *system_memo= ry, static uint64_t omap_id_read(void *opaque, hwaddr addr, unsigned size) { - struct omap_mpu_state_s *s =3D opaque; - if (size !=3D 4) { qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx " with bad width %d\n", __func__, addr, size); @@ -968,25 +966,10 @@ static uint64_t omap_id_read(void *opaque, hwaddr add= r, return 0xcafeb574; =20 case 0xfffed400: /* JTAG_ID_LSB */ - switch (s->mpu_model) { - case omap310: - return 0x03310315; - case omap1510: - return 0x03310115; - default: - hw_error("%s: bad mpu model\n", __func__); - } - break; + return 0x03310315; /* omap310 */ =20 case 0xfffed404: /* JTAG_ID_MSB */ - switch (s->mpu_model) { - case omap310: - return 0xfb57402f; - case omap1510: - return 0xfb47002f; - default: - hw_error("%s: bad mpu model\n", __func__); - } + return 0xfb57402f; /* omap310 */ break; } =20 @@ -1022,11 +1005,6 @@ static void omap_id_init(MemoryRegion *memory, struc= t omap_mpu_state_s *mpu) memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu= ->id_iomem, 0xfffed400, 0x100); memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); - if (!cpu_is_omap15xx(mpu)) { - memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", - &mpu->id_iomem, 0xfffe2000, 0x800); - memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20= ); - } } =20 /* MPUI Control (Dummy) */ @@ -3819,7 +3797,6 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegio= n *dram, MemoryRegion *system_memory =3D get_system_memory(); =20 /* Core */ - s->mpu_model =3D omap310; s->cpu =3D ARM_CPU(cpu_create(cpu_type)); s->sdram_size =3D memory_region_size(dram); s->sram_size =3D OMAP15XX_SRAM_SIZE; @@ -3974,7 +3951,6 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegio= n *dram, s->wakeup, omap_findclk(s, "clk32-kHz")); =20 s->gpio =3D qdev_new("omap-gpio"); - qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); sysbus_realize_and_unref(SYS_BUS_DEVICE(s->gpio), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index ee3ddb09e3..16da9a88d9 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -45,7 +45,6 @@ struct Omap1GpioState { SysBusDevice parent_obj; =20 MemoryRegion iomem; - int mpu_model; void *clk; struct omap_gpio_s omap1; }; @@ -228,17 +227,12 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk= clk) gpio->clk =3D clk; } =20 -static const Property omap_gpio_properties[] =3D { - DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0), -}; - static void omap_gpio_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D omap_gpio_realize; device_class_set_legacy_reset(dc, omap_gpif_reset); - device_class_set_props(dc, omap_gpio_properties); /* Reason: pointer property "clk" */ dc->user_creatable =3D false; } diff --git a/hw/misc/omap_clk.c b/hw/misc/omap_clk.c index e927ef22a0..dc398570ac 100644 --- a/hw/misc/omap_clk.c +++ b/hw/misc/omap_clk.c @@ -707,14 +707,7 @@ void omap_clk_init(struct omap_mpu_state_s *mpu) { struct clk **i, *j, *k; int count; - int flag; - - if (cpu_is_omap310(mpu)) - flag =3D CLOCK_IN_OMAP310; - else if (cpu_is_omap1510(mpu)) - flag =3D CLOCK_IN_OMAP1510; - else - return; + int flag =3D CLOCK_IN_OMAP310; =20 for (i =3D onchip_clks, count =3D 0; *i; i ++) if ((*i)->flags & flag) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 66a435a3d7..6ea47293a6 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -542,24 +542,7 @@ void omap_mmc_set_clk(DeviceState *dev, omap_clk clk); /* omap_i2c.c */ I2CBus *omap_i2c_bus(DeviceState *omap_i2c); =20 -#define cpu_is_omap310(cpu) (cpu->mpu_model =3D=3D omap310) -#define cpu_is_omap1510(cpu) (cpu->mpu_model =3D=3D omap1510) -#define cpu_is_omap1610(cpu) (cpu->mpu_model =3D=3D omap1610) -#define cpu_is_omap1710(cpu) (cpu->mpu_model =3D=3D omap1710) - -#define cpu_is_omap15xx(cpu) \ - (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) -#define cpu_is_omap16xx(cpu) \ - (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) - struct omap_mpu_state_s { - enum omap_mpu_model { - omap310, - omap1510, - omap1610, - omap1710, - } mpu_model; - ARMCPU *cpu; =20 qemu_irq *drq; @@ -571,7 +554,6 @@ struct omap_mpu_state_s { MemoryRegion id_iomem; MemoryRegion id_iomem_e18; MemoryRegion id_iomem_ed4; - MemoryRegion id_iomem_e20; MemoryRegion mpui_iomem; MemoryRegion tcmi_iomem; MemoryRegion clkm_iomem; --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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They have no callers, so we can delete them. This code was the last user of hw_error() in this file, so we can also remove the hw-error.h include. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/omap1.c | 26 -------------------------- include/hw/arm/omap.h | 3 --- 2 files changed, 29 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index c9f9c3ef40..15087ba03e 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -25,7 +25,6 @@ #include "target/arm/cpu.h" #include "system/address-spaces.h" #include "exec/cpu-common.h" -#include "hw/core/hw-error.h" #include "hw/core/irq.h" #include "hw/core/qdev-properties.h" #include "hw/arm/boot.h" @@ -2095,31 +2094,6 @@ static struct omap_mpuio_s *omap_mpuio_init(MemoryRe= gion *memory, return s; } =20 -qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) -{ - return s->in; -} - -void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) -{ - if (line >=3D 16 || line < 0) - hw_error("%s: No GPIO line %i\n", __func__, line); - s->handler[line] =3D handler; -} - -void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) -{ - if (row >=3D 5 || row < 0) - hw_error("%s: No key %i-%i\n", __func__, col, row); - - if (down) - s->buttons[row] |=3D 1 << col; - else - s->buttons[row] &=3D ~(1 << col); - - omap_mpuio_kbd_update(s); -} - /* MicroWire Interface */ struct omap_uwire_s { MemoryRegion iomem; diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 6ea47293a6..dc63323210 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -486,9 +486,6 @@ struct omap_uart_s *omap_uart_init(hwaddr base, void omap_uart_reset(struct omap_uart_s *s); =20 struct omap_mpuio_s; -qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); -void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler= ); -void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); =20 struct omap_uwire_s; =20 --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778618188; cv=none; d=zohomail.com; s=zohoarc; b=lZdsHjGsqZL3zNJL77mALGKfPsAoEcs5OkvJB1uRey0/VsGZUZdFMNmV92seldHFzKCtsvBbDtKnBpT7/T/5etYbmhnnFN9opXZij9J+Y0yg9zxuEfu+6hdf7Z+in8QrZPuVpwWWmRPbNBB53ULAR3fQXo1Lf+RHUmKEye8jsdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778618188; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=zpCSnTZDy0cXLQEkLxVTYXKV5hdeLG4LMCu3JIo7jKo=; b=kFE6QUXsjLvhXx9XuqV5AjN6chmebVtYvtNK62dW2R7vnAEXy4xIKefVuQi/gwRqrtxzgZ2sXRgyUGOxss4DaZvwYnPaciS2fF7xB3pRUbPS9qTFSEhj9asx5TKJDw5+P4Y6n9vnosd42eW3agZn3lLQZ/W8cNo/61kJbl7OqWg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778618188250282.8710502047511; Tue, 12 May 2026 13:36:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wMtoQ-0002SX-Ib; Tue, 12 May 2026 16:34:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wMtoD-0002Ns-W7 for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:35 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wMto8-0002MW-1y for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:28 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-488ba840146so53817475e9.1 for ; Tue, 12 May 2026 13:34:22 -0700 (PDT) Received: from lanath.. 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Delete it now. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/omap.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index dc63323210..96a52d280c 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -338,10 +338,6 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq = *irqs, MemoryRegion *sysmem, qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk c= lk, enum omap_dma_model model); -struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, - MemoryRegion *sysmem, - struct omap_mpu_state_s *mpu, int fifo, - int chans, omap_clk iclk, omap_clk fclk); void omap_dma_reset(struct soc_dma_s *s); =20 struct dma_irq_map { --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778618132; cv=none; d=zohomail.com; s=zohoarc; b=Y6Ckg/SlPUr6Gxl++FIlWMuhBwTypQcPualOAZo5S7YptHFuyaZ+vJ7zLaZld7rZYEquPYDuDcNWgIJKjqGS+7BJdYPuhmOHTRCza1L1N0NdHJRzerIf0XCiJ9mesYclbAMlGJYg914XK1sOUr4It5xEDIMGWW51u0rEYmEt4og= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778618132; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+PL/MH4uw3EOiajsILDQeY6KgmiCKgLUvtYeV1v2eOs=; b=SoaN+Gt4pOb9MKUWYr080OYlg+L51ww/sxDZS32TWqgzJG+3FgXicstHqR1sZXsTg0y20K0ka1TV6WMxFNc5JTvPgXFivVZW5uS2Yik3ZUHNhNsPdR7OZPJeLJ1l0b9WBGqxDjAZTTurucWTaB+IN5vxwm4Y5tFkHTxxugkbl/4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778618132600634.0131615651427; Tue, 12 May 2026 13:35:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wMtoR-0002TQ-Ep; Tue, 12 May 2026 16:34:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wMtoC-0002NX-MD for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:35 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wMto8-0002NW-34 for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:27 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-48a563e4ef7so54148575e9.0 for ; Tue, 12 May 2026 13:34:22 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fc8d69d0bsm16350635e9.13.2026.05.12.13.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2026 13:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1778618062; x=1779222862; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+PL/MH4uw3EOiajsILDQeY6KgmiCKgLUvtYeV1v2eOs=; b=xdcMyVOpErYCApvKo8vB1jw6FgIP1h2OapIU6ZJZW4HPVGdGe1FFB3W2SVzSBBcVZd X9gAUUNiRekJ9HOr4KFxFJEt8QL8djjyIB57VYvR6dcofRxsZEipuUcjVKQk/UHEDcO3 rzQ+JBhBAYZCuhf2iXlJuzVBdTQFJpCN15V2LorxyK0/wMoFTseo5MRSjGHqqwlMwmob BMmEIZiD8C2yM51nr6ZdY3gZ5cG4VOa1/t5OQNH8SqYPi22cyojbN8Di/bZeDHXUoOTV FS3tHSwRhax5xBkCxgLeEfHHSfJwuMOkNTuNZDIGziGXYn9Liv8N/hMryaG+m1wK71Js Pv8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778618062; x=1779222862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+PL/MH4uw3EOiajsILDQeY6KgmiCKgLUvtYeV1v2eOs=; b=gdVhEZgTYqKjLY5AHhLeB82NjePN2CehTQVo+Rt1iA1gAw6X+tzcUIRrjkG5NtaYfd 7TyO21gxP2854FpTPuIIEeNlOploIt8D7Q3+YKXaPvO+vOOi5KxuSZXZjAe5ZFI8tDXv iyGBRgSMiuSbZJGZGBO5a1PNeyVg9mrH5G6+0rPY/8vwEpAp+QYsWbON3RN4vuuqMcx9 cYbxXJp9rDKnanoQY/mxoNg9Po8mEOJJuRgjPOtJedJB0RGHMbuqibQVeiIfCpiKv2Jm Lxm3/gAUHM+Qftlwb/6Mhs7fBcICazqnL4ekFO2Pax9dYEcChN+gk2codhC5GIJlp4K4 l2mg== X-Forwarded-Encrypted: i=1; AFNElJ+JefQ2dYUy/nXxhg1mCNAtgs57jIEhJ4WZznBlKXX2LQzl4mrhQMmCC+xORugCjJCEX3bLOUNJSJoT@nongnu.org X-Gm-Message-State: AOJu0YxLOwNC3CFB6WxtrYfZUTWlnljJXioYEAglaXVWwreJwaOS7uGe SRpKvaxr8t4Cpm8YlRHFqdwn3iIGX1HcGir26geHtleC4iV6sSOs+i85feHUhpzs7KY= X-Gm-Gg: Acq92OF0eYTeJm0TpOgXhsUVSrVZ7ry6QWKxLn8R9hniwdp1IZTrakFj8wM8i6K6B0/ Abavdyu+6W3cPvVWas1tCM9kmyWsMUEK6tST3PeAmEPC9YK8psIxpEPiJUPPWIxwcHslEaoJtLD QKPYe5PemD7O8PQj7drzvmEyY7acbTl95+Wt8AzgUclV+YMzmacKs/qKBo6z/hEPgqA1NjycQC5 eEqbdjzllKibcXm2emz4YlRWdwfvEN/jALmTdTnEQePPigVScoGkfHNpFYvUbuAzH+H5jWDfyJW gcfopUxOWaTmygxo0kOhTEd1LdmHyqaWaNcANPuwfIBhwQ/frhO9q8mBcQOvwy9wi5+BJ0S/P3u iFpsgwnRrJSwuSj+iAQKwDhwfa62zTs2IHV5sToot4ZlP8dC1fvrecefhFABel8H/EGWSck2bTj hmEI1f/vj80ufpbx5hraZeHkuCpgtznOSo6djnIxs6UnmGh0/YgHtRQJHf10RiLM76BCuviVrBA xrQJ97GYuAdYQXDDqtZJKCDzwOzxUU= X-Received: by 2002:a05:600c:83c7:b0:48a:93f8:dd02 with SMTP id 5b1f17b1804b1-48fc9a31d69mr4786575e9.14.1778618061746; Tue, 12 May 2026 13:34:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/12] hw/arm/omap: Remove unused omap1_dma_irq_map[] entries Date: Tue, 12 May 2026 21:34:06 +0100 Message-ID: <20260512203414.3633237-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512203414.3633237-1-peter.maydell@linaro.org> References: <20260512203414.3633237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778618136312154100 Content-Type: text/plain; charset="utf-8" For the one remaining OMAP board, we use only the first 6 entries in the omap1_dma_irq_map[] array; the rest were for OMAP1610. Delete the now-unused elements. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/omap1.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 15087ba03e..40ca8c9890 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -3710,16 +3710,6 @@ static const struct dma_irq_map omap1_dma_irq_map[] = =3D { { 0, OMAP_INT_DMA_CH3 }, { 0, OMAP_INT_DMA_CH4 }, { 0, OMAP_INT_DMA_CH5 }, - { 1, OMAP_INT_1610_DMA_CH6 }, - { 1, OMAP_INT_1610_DMA_CH7 }, - { 1, OMAP_INT_1610_DMA_CH8 }, - { 1, OMAP_INT_1610_DMA_CH9 }, - { 1, OMAP_INT_1610_DMA_CH10 }, - { 1, OMAP_INT_1610_DMA_CH11 }, - { 1, OMAP_INT_1610_DMA_CH12 }, - { 1, OMAP_INT_1610_DMA_CH13 }, - { 1, OMAP_INT_1610_DMA_CH14 }, - { 1, OMAP_INT_1610_DMA_CH15 } }; =20 /* DMA ports for OMAP1 */ --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778618172; cv=none; d=zohomail.com; s=zohoarc; b=mj24hU8b0UwiRbfpgC7YD2WvDKkuwps4n91fK5IBzpeJyTxMiGj86skUcIIu1ZoaCzgJk5y0W225YXqwSkSnkSO1mG+NCyBEUGz1vFnNWEY3XAJ1fghMSVAfC92BrF6jqNszLRPIsfnkudEeG2FXSrei+fXeQgCh066CcAx8jBw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778618172; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=9aaDQ12UBCrB15ahgAwdguXL2xkiRYB5Sw8BTXsTekM=; b=iTf0NXxYsGAABizvqllEn857paKhl8p+zsXQbyYLV0iOtXqxbq9h5bsDSFWDv+8Yh2eBuCQcONJ3uCJBqwzvWvYyqdmkFGmQfP1s8t321rPMu9f+zDnaDcecnASFV1EkjBkfhb3MaHt5y9CN3ew9S076NlJli5+FLRklNmjHyMk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778618172059649.9515398347373; Tue, 12 May 2026 13:36:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wMtoW-0002Xh-CH; Tue, 12 May 2026 16:34:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wMtoF-0002Nv-JS for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:35 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wMtoA-0002P6-QA for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:29 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-488b8bc6bc9so37565275e9.3 for ; Tue, 12 May 2026 13:34:23 -0700 (PDT) Received: from lanath.. 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/omap.h | 185 ------------------------------------------ 1 file changed, 185 deletions(-) diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 96a52d280c..14d6e9d214 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -35,10 +35,7 @@ #define OMAP_LOCALBUS_BASE 0x30000000 #define OMAP_MPUI_BASE 0xe1000000 =20 -#define OMAP730_SRAM_SIZE 0x00032000 #define OMAP15XX_SRAM_SIZE 0x00030000 -#define OMAP16XX_SRAM_SIZE 0x00004000 -#define OMAP1611_SRAM_SIZE 0x0003e800 #define OMAP_CS0_SIZE 0x04000000 #define OMAP_CS1_SIZE 0x04000000 #define OMAP_CS2_SIZE 0x04000000 @@ -130,16 +127,6 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk = clk); * Common OMAP-15xx IRQ numbers for level 1 interrupt handler */ #define OMAP_INT_15XX_IH2_IRQ 0 -#define OMAP_INT_15XX_LB_MMU 17 -#define OMAP_INT_15XX_LOCAL_BUS 29 - -/* - * OMAP-1510 specific IRQ numbers for level 1 interrupt handler - */ -#define OMAP_INT_1510_SPI_TX 4 -#define OMAP_INT_1510_SPI_RX 5 -#define OMAP_INT_1510_DSP_MAILBOX1 10 -#define OMAP_INT_1510_DSP_MAILBOX2 11 =20 /* * OMAP-310 specific IRQ numbers for level 1 interrupt handler @@ -149,42 +136,6 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk = clk); #define OMAP_INT_310_HSB_MAILBOX1 12 #define OMAP_INT_310_HSAB_MMU 18 =20 -/* - * OMAP-1610 specific IRQ numbers for level 1 interrupt handler - */ -#define OMAP_INT_1610_IH2_IRQ 0 -#define OMAP_INT_1610_IH2_FIQ 2 -#define OMAP_INT_1610_McBSP2_TX 4 -#define OMAP_INT_1610_McBSP2_RX 5 -#define OMAP_INT_1610_DSP_MAILBOX1 10 -#define OMAP_INT_1610_DSP_MAILBOX2 11 -#define OMAP_INT_1610_LCD_LINE 12 -#define OMAP_INT_1610_GPTIMER1 17 -#define OMAP_INT_1610_GPTIMER2 18 -#define OMAP_INT_1610_SSR_FIFO_0 29 - -/* - * OMAP-730 specific IRQ numbers for level 1 interrupt handler - */ -#define OMAP_INT_730_IH2_FIQ 0 -#define OMAP_INT_730_IH2_IRQ 1 -#define OMAP_INT_730_USB_NON_ISO 2 -#define OMAP_INT_730_USB_ISO 3 -#define OMAP_INT_730_ICR 4 -#define OMAP_INT_730_EAC 5 -#define OMAP_INT_730_GPIO_BANK1 6 -#define OMAP_INT_730_GPIO_BANK2 7 -#define OMAP_INT_730_GPIO_BANK3 8 -#define OMAP_INT_730_McBSP2TX 10 -#define OMAP_INT_730_McBSP2RX 11 -#define OMAP_INT_730_McBSP2RX_OVF 12 -#define OMAP_INT_730_LCD_LINE 14 -#define OMAP_INT_730_GSM_PROTECT 15 -#define OMAP_INT_730_TIMER3 16 -#define OMAP_INT_730_GPIO_BANK5 17 -#define OMAP_INT_730_GPIO_BANK6 18 -#define OMAP_INT_730_SPGIO_WR 29 - /* * Common IRQ numbers for level 2 interrupt handler */ @@ -209,15 +160,6 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk = clk); #define OMAP_INT_RTC_ALARM 26 #define OMAP_INT_DSP_MMU 28 =20 -/* - * OMAP-1510 specific IRQ numbers for level 2 interrupt handler - */ -#define OMAP_INT_1510_BT_MCSI1TX 16 -#define OMAP_INT_1510_BT_MCSI1RX 17 -#define OMAP_INT_1510_SoSSI_MATCH 19 -#define OMAP_INT_1510_MEM_STICK 27 -#define OMAP_INT_1510_COM_SPI_RO 31 - /* * OMAP-310 specific IRQ numbers for level 2 interrupt handler */ @@ -229,103 +171,6 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk= clk); #define OMAP_INT_310_USB_W2FC_NON_ISO 30 #define OMAP_INT_310_McBSP2RX_OF 31 =20 -/* - * OMAP-1610 specific IRQ numbers for level 2 interrupt handler - */ -#define OMAP_INT_1610_FAC 0 -#define OMAP_INT_1610_USB_HHC_2 7 -#define OMAP_INT_1610_USB_OTG 8 -#define OMAP_INT_1610_SoSSI 9 -#define OMAP_INT_1610_BT_MCSI1TX 16 -#define OMAP_INT_1610_BT_MCSI1RX 17 -#define OMAP_INT_1610_SoSSI_MATCH 19 -#define OMAP_INT_1610_MEM_STICK 27 -#define OMAP_INT_1610_McBSP2RX_OF 31 -#define OMAP_INT_1610_STI 32 -#define OMAP_INT_1610_STI_WAKEUP 33 -#define OMAP_INT_1610_GPTIMER3 34 -#define OMAP_INT_1610_GPTIMER4 35 -#define OMAP_INT_1610_GPTIMER5 36 -#define OMAP_INT_1610_GPTIMER6 37 -#define OMAP_INT_1610_GPTIMER7 38 -#define OMAP_INT_1610_GPTIMER8 39 -#define OMAP_INT_1610_GPIO_BANK2 40 -#define OMAP_INT_1610_GPIO_BANK3 41 -#define OMAP_INT_1610_MMC2 42 -#define OMAP_INT_1610_CF 43 -#define OMAP_INT_1610_WAKE_UP_REQ 46 -#define OMAP_INT_1610_GPIO_BANK4 48 -#define OMAP_INT_1610_SPI 49 -#define OMAP_INT_1610_DMA_CH6 53 -#define OMAP_INT_1610_DMA_CH7 54 -#define OMAP_INT_1610_DMA_CH8 55 -#define OMAP_INT_1610_DMA_CH9 56 -#define OMAP_INT_1610_DMA_CH10 57 -#define OMAP_INT_1610_DMA_CH11 58 -#define OMAP_INT_1610_DMA_CH12 59 -#define OMAP_INT_1610_DMA_CH13 60 -#define OMAP_INT_1610_DMA_CH14 61 -#define OMAP_INT_1610_DMA_CH15 62 -#define OMAP_INT_1610_NAND 63 - -/* - * OMAP-730 specific IRQ numbers for level 2 interrupt handler - */ -#define OMAP_INT_730_HW_ERRORS 0 -#define OMAP_INT_730_NFIQ_PWR_FAIL 1 -#define OMAP_INT_730_CFCD 2 -#define OMAP_INT_730_CFIREQ 3 -#define OMAP_INT_730_I2C 4 -#define OMAP_INT_730_PCC 5 -#define OMAP_INT_730_MPU_EXT_NIRQ 6 -#define OMAP_INT_730_SPI_100K_1 7 -#define OMAP_INT_730_SYREN_SPI 8 -#define OMAP_INT_730_VLYNQ 9 -#define OMAP_INT_730_GPIO_BANK4 10 -#define OMAP_INT_730_McBSP1TX 11 -#define OMAP_INT_730_McBSP1RX 12 -#define OMAP_INT_730_McBSP1RX_OF 13 -#define OMAP_INT_730_UART_MODEM_IRDA_2 14 -#define OMAP_INT_730_UART_MODEM_1 15 -#define OMAP_INT_730_MCSI 16 -#define OMAP_INT_730_uWireTX 17 -#define OMAP_INT_730_uWireRX 18 -#define OMAP_INT_730_SMC_CD 19 -#define OMAP_INT_730_SMC_IREQ 20 -#define OMAP_INT_730_HDQ_1WIRE 21 -#define OMAP_INT_730_TIMER32K 22 -#define OMAP_INT_730_MMC_SDIO 23 -#define OMAP_INT_730_UPLD 24 -#define OMAP_INT_730_USB_HHC_1 27 -#define OMAP_INT_730_USB_HHC_2 28 -#define OMAP_INT_730_USB_GENI 29 -#define OMAP_INT_730_USB_OTG 30 -#define OMAP_INT_730_CAMERA_IF 31 -#define OMAP_INT_730_RNG 32 -#define OMAP_INT_730_DUAL_MODE_TIMER 33 -#define OMAP_INT_730_DBB_RF_EN 34 -#define OMAP_INT_730_MPUIO_KEYPAD 35 -#define OMAP_INT_730_SHA1_MD5 36 -#define OMAP_INT_730_SPI_100K_2 37 -#define OMAP_INT_730_RNG_IDLE 38 -#define OMAP_INT_730_MPUIO 39 -#define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 -#define OMAP_INT_730_LLPC_OE_FALLING 41 -#define OMAP_INT_730_LLPC_OE_RISING 42 -#define OMAP_INT_730_LLPC_VSYNC 43 -#define OMAP_INT_730_WAKE_UP_REQ 46 -#define OMAP_INT_730_DMA_CH6 53 -#define OMAP_INT_730_DMA_CH7 54 -#define OMAP_INT_730_DMA_CH8 55 -#define OMAP_INT_730_DMA_CH9 56 -#define OMAP_INT_730_DMA_CH10 57 -#define OMAP_INT_730_DMA_CH11 58 -#define OMAP_INT_730_DMA_CH12 59 -#define OMAP_INT_730_DMA_CH13 60 -#define OMAP_INT_730_DMA_CH14 61 -#define OMAP_INT_730_DMA_CH15 62 -#define OMAP_INT_730_NAND 63 - /* omap_dma.c */ enum omap_dma_model { omap_dma_3_0, @@ -437,9 +282,6 @@ struct omap_dma_lcd_channel_s { #define OMAP_DMA_CAMERA_IF_RX 20 #define OMAP_DMA_MMC_TX 21 #define OMAP_DMA_MMC_RX 22 -#define OMAP_DMA_NAND 23 /* Not in OMAP310 */ -#define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ -#define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ #define OMAP_DMA_USB_W2FC_RX0 26 #define OMAP_DMA_USB_W2FC_RX1 27 #define OMAP_DMA_USB_W2FC_RX2 28 @@ -447,33 +289,6 @@ struct omap_dma_lcd_channel_s { #define OMAP_DMA_USB_W2FC_TX1 30 #define OMAP_DMA_USB_W2FC_TX2 31 =20 -/* These are only for 1610 */ -#define OMAP_DMA_CRYPTO_DES_IN 32 -#define OMAP_DMA_SPI_TX 33 -#define OMAP_DMA_SPI_RX 34 -#define OMAP_DMA_CRYPTO_HASH 35 -#define OMAP_DMA_CCP_ATTN 36 -#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 -#define OMAP_DMA_CMT_APE_TX_CHAN_0 38 -#define OMAP_DMA_CMT_APE_RV_CHAN_0 39 -#define OMAP_DMA_CMT_APE_TX_CHAN_1 40 -#define OMAP_DMA_CMT_APE_RV_CHAN_1 41 -#define OMAP_DMA_CMT_APE_TX_CHAN_2 42 -#define OMAP_DMA_CMT_APE_RV_CHAN_2 43 -#define OMAP_DMA_CMT_APE_TX_CHAN_3 44 -#define OMAP_DMA_CMT_APE_RV_CHAN_3 45 -#define OMAP_DMA_CMT_APE_TX_CHAN_4 46 -#define OMAP_DMA_CMT_APE_RV_CHAN_4 47 -#define OMAP_DMA_CMT_APE_TX_CHAN_5 48 -#define OMAP_DMA_CMT_APE_RV_CHAN_5 49 -#define OMAP_DMA_CMT_APE_TX_CHAN_6 50 -#define OMAP_DMA_CMT_APE_RV_CHAN_6 51 -#define OMAP_DMA_CMT_APE_TX_CHAN_7 52 -#define OMAP_DMA_CMT_APE_RV_CHAN_7 53 -#define OMAP_DMA_MMC2_TX 54 -#define OMAP_DMA_MMC2_RX 55 -#define OMAP_DMA_CRYPTO_DES_OUT 56 - struct omap_uart_s; struct omap_uart_s *omap_uart_init(hwaddr base, qemu_irq irq, omap_clk fclk, omap_clk iclk, --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778618191; cv=none; d=zohomail.com; s=zohoarc; b=FNpWQv6zLyvQfB/pgTmH1SpkRQdVl7nmZXruJkzdX0GgUshRCewJgrYCLoK8sDBgMJKM+bEtvsFhg7C1r9VoZI1iVuYv65p0ZyPFm4jZCZBkbajm0tVkZKW+N9RMHjrtkaqsY1Rr2Tg50fgv7DlH/Is7cNHKHTQHiyt2akBWKoU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778618191; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=KPoAYypSDNORF0pUxIKtlzts64GOfXtKmSc+PiEhbG8=; b=SeTbHXkWwaFbquLxybYpBo1FJKjh6DsFDpaoPtpgZ72p0jPegaOx9ZTXB09bO3JEEadPJVWosPiL9qnnzaQG2Uu/DVwT4OrBymcHr9mSiTSe+t3etslWxcHlW3LeFv0YvSrFWRPqVSxP+3VLaQa8ukh5OFZyxaZv72/DBS24G3Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778618191004501.0660796864555; Tue, 12 May 2026 13:36:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wMtoQ-0002Sf-Ld; Tue, 12 May 2026 16:34:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wMtoG-0002OU-RL for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:35 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wMtoC-0002Qg-53 for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:31 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4891c00e7aeso51387975e9.2 for ; Tue, 12 May 2026 13:34:24 -0700 (PDT) Received: from lanath.. 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However nothing ever touches that qemu_irq again, so omap_mpu_wakeup() is never called. Remove all this as dead code. This lets us remove a direct call to cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB) from within board/SoC code, which is pretty ugly and might not even do the right thing these days. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/omap1.c | 18 ++---------------- include/hw/arm/omap.h | 2 -- 2 files changed, 2 insertions(+), 18 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 40ca8c9890..80168644ce 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -1846,7 +1846,6 @@ struct omap_mpuio_s { qemu_irq kbd_irq; qemu_irq *in; qemu_irq handler[16]; - qemu_irq wakeup; MemoryRegion iomem; =20 uint16_t inputs; @@ -2074,14 +2073,13 @@ static void omap_mpuio_onoff(void *opaque, int line= , int on) =20 static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, hwaddr base, - qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, + qemu_irq kbd_int, qemu_irq gpio_int, omap_clk clk) { struct omap_mpuio_s *s =3D g_new0(struct omap_mpuio_s, 1); =20 s->irq =3D gpio_int; s->kbd_irq =3D kbd_int; - s->wakeup =3D wakeup; s->in =3D qemu_allocate_irqs(omap_mpuio_set, s, 16); omap_mpuio_reset(s); =20 @@ -3693,16 +3691,6 @@ static void omap_setup_dsp_mapping(MemoryRegion *sys= tem_memory, } } =20 -void omap_mpu_wakeup(void *opaque, int irq, int req) -{ - struct omap_mpu_state_s *mpu =3D opaque; - CPUState *cpu =3D CPU(mpu->cpu); - - if (cpu->halted) { - cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); - } -} - static const struct dma_irq_map omap1_dma_irq_map[] =3D { { 0, OMAP_INT_DMA_CH0_6 }, { 0, OMAP_INT_DMA_CH1_7 }, @@ -3765,8 +3753,6 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegio= n *dram, s->sdram_size =3D memory_region_size(dram); s->sram_size =3D OMAP15XX_SRAM_SIZE; =20 - s->wakeup =3D qemu_allocate_irq(omap_mpu_wakeup, s, 0); - /* Clocks */ omap_clk_init(s); =20 @@ -3912,7 +3898,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegio= n *dram, s->mpuio =3D omap_mpuio_init(system_memory, 0xfffb5000, qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOAR= D), qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), - s->wakeup, omap_findclk(s, "clk32-kHz")); + omap_findclk(s, "clk32-kHz")); =20 s->gpio =3D qdev_new("omap-gpio"); omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 14d6e9d214..ea5c0eff8b 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -463,8 +463,6 @@ struct omap_mpu_state_s { struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, const char *core); =20 -void omap_mpu_wakeup(void *opaque, int irq, int req); - #define OMAP_BAD_REG(paddr) \ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"= \n", \ __func__, paddr) --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778618190; cv=none; d=zohomail.com; s=zohoarc; b=MhUmwnR077hZvT7C1bBDy6+zdXlXk5QalZKIF3TM3/Oli6spqreRGfOCBMfHJmhH+y+ZZUhUtyCMuVFUHQfQX2xkFXYviP2tDRTtzMmHtJjgk2Nsj21v1nIjX1dUWj37lpPgWYIYd9YUwBwOvHrE9BRcGw9q+OyLcFaR82+GAEc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778618190; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kEnLeUmWLWQ40InBmDqKDvsE7iKQP1+4r5LocGruHdE=; b=WxduS/EpyYNNbHLI8zM3tTa7qCFRFzUAmCV5rUTJLVSjJaY3CBljJJm35pfvA3sKKJUwmeOdJ5Dv9wGnHIG+VLq2n3ojNLu/r7F5kQpzymiWID8IF83cONo+O2ZM7xFGlH5UE8n+VdCBfAb9xDi+AGvuavFPbw04gQOlmc/LnR4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778618190651383.20030100444467; Tue, 12 May 2026 13:36:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wMtoU-0002Vd-0e; Tue, 12 May 2026 16:34:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wMtoL-0002Qs-QV for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:40 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wMtoC-0002RH-55 for qemu-devel@nongnu.org; Tue, 12 May 2026 16:34:32 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4891c00e7aeso51388045e9.2 for ; Tue, 12 May 2026 13:34:25 -0700 (PDT) Received: from lanath.. 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However, our one remaining OMAP SoC always passes omap_dma_3_1 into the omap_dma_init() function, so the handling for 3_0 and 3_2 is never used. Remove the support for the other versions; this lets us delete entirely two large functions that were specific to 3.2 DMA to the LCD controller, and all their associated fields in the omap_dma_lcd_channel_s struct. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/dma/omap_dma.c | 348 ++---------------------------------------- include/hw/arm/omap.h | 28 ---- 2 files changed, 15 insertions(+), 361 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index 784a3a4f7f..9a86d90b4e 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -110,7 +110,6 @@ struct omap_dma_s { omap_clk clk; qemu_irq irq[4]; void (*intr_update)(struct omap_dma_s *s); - enum omap_dma_model model; int omap_3_1_mapping_disabled; =20 uint32_t gcr; @@ -752,10 +751,7 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, break; =20 case 0x02: /* SYS_DMA_CCR_CH0 */ - if (s->model <=3D omap_dma_3_1) - *value =3D 0 << 10; /* FIFO_FLUSH reads as 0 */ - else - *value =3D ch->omap_3_1_compatible_disable << 10; + *value =3D 0 << 10; /* FIFO_FLUSH reads as 0 */ *value |=3D (ch->mode[1] << 14) | (ch->mode[0] << 12) | (ch->end_prog << 11) | @@ -892,8 +888,6 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, ch->mode[1] =3D (omap_dma_addressing_t) ((value & 0xc000) >> 14); ch->mode[0] =3D (omap_dma_addressing_t) ((value & 0x3000) >> 12); ch->end_prog =3D (value & 0x0800) >> 11; - if (s->model >=3D omap_dma_3_2) - ch->omap_3_1_compatible_disable =3D (value >> 10) & 0x1; ch->repeat =3D (value & 0x0200) >> 9; ch->auto_init =3D (value & 0x0100) >> 8; ch->priority =3D (value & 0x0040) >> 6; @@ -1002,250 +996,6 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *= s, return 0; } =20 -static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int of= fset, - uint16_t value) -{ - switch (offset) { - case 0xbc0: /* DMA_LCD_CSDP */ - s->brust_f2 =3D (value >> 14) & 0x3; - s->pack_f2 =3D (value >> 13) & 0x1; - s->data_type_f2 =3D (1 << ((value >> 11) & 0x3)); - s->brust_f1 =3D (value >> 7) & 0x3; - s->pack_f1 =3D (value >> 6) & 0x1; - s->data_type_f1 =3D (1 << ((value >> 0) & 0x3)); - break; - - case 0xbc2: /* DMA_LCD_CCR */ - s->mode_f2 =3D (value >> 14) & 0x3; - s->mode_f1 =3D (value >> 12) & 0x3; - s->end_prog =3D (value >> 11) & 0x1; - s->omap_3_1_compatible_disable =3D (value >> 10) & 0x1; - s->repeat =3D (value >> 9) & 0x1; - s->auto_init =3D (value >> 8) & 0x1; - s->running =3D (value >> 7) & 0x1; - s->priority =3D (value >> 6) & 0x1; - s->bs =3D (value >> 4) & 0x1; - break; - - case 0xbc4: /* DMA_LCD_CTRL */ - s->dst =3D (value >> 8) & 0x1; - s->src =3D ((value >> 6) & 0x3) << 1; - s->condition =3D 0; - /* Assume no bus errors and thus no BUS_ERROR irq bits. */ - s->interrupts =3D (value >> 1) & 1; - s->dual =3D value & 1; - break; - - case 0xbc8: /* TOP_B1_L */ - s->src_f1_top &=3D 0xffff0000; - s->src_f1_top |=3D 0x0000ffff & value; - break; - - case 0xbca: /* TOP_B1_U */ - s->src_f1_top &=3D 0x0000ffff; - s->src_f1_top |=3D (uint32_t)value << 16; - break; - - case 0xbcc: /* BOT_B1_L */ - s->src_f1_bottom &=3D 0xffff0000; - s->src_f1_bottom |=3D 0x0000ffff & value; - break; - - case 0xbce: /* BOT_B1_U */ - s->src_f1_bottom &=3D 0x0000ffff; - s->src_f1_bottom |=3D (uint32_t) value << 16; - break; - - case 0xbd0: /* TOP_B2_L */ - s->src_f2_top &=3D 0xffff0000; - s->src_f2_top |=3D 0x0000ffff & value; - break; - - case 0xbd2: /* TOP_B2_U */ - s->src_f2_top &=3D 0x0000ffff; - s->src_f2_top |=3D (uint32_t) value << 16; - break; - - case 0xbd4: /* BOT_B2_L */ - s->src_f2_bottom &=3D 0xffff0000; - s->src_f2_bottom |=3D 0x0000ffff & value; - break; - - case 0xbd6: /* BOT_B2_U */ - s->src_f2_bottom &=3D 0x0000ffff; - s->src_f2_bottom |=3D (uint32_t) value << 16; - break; - - case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ - s->element_index_f1 =3D value; - break; - - case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ - s->frame_index_f1 &=3D 0xffff0000; - s->frame_index_f1 |=3D 0x0000ffff & value; - break; - - case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ - s->frame_index_f1 &=3D 0x0000ffff; - s->frame_index_f1 |=3D (uint32_t) value << 16; - break; - - case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ - s->element_index_f2 =3D value; - break; - - case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ - s->frame_index_f2 &=3D 0xffff0000; - s->frame_index_f2 |=3D 0x0000ffff & value; - break; - - case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ - s->frame_index_f2 &=3D 0x0000ffff; - s->frame_index_f2 |=3D (uint32_t) value << 16; - break; - - case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ - s->elements_f1 =3D value; - break; - - case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ - s->frames_f1 =3D value; - break; - - case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ - s->elements_f2 =3D value; - break; - - case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ - s->frames_f2 =3D value; - break; - - case 0xbea: /* DMA_LCD_LCH_CTRL */ - s->lch_type =3D value & 0xf; - break; - - default: - return 1; - } - return 0; -} - -static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int off= set, - uint16_t *ret) -{ - switch (offset) { - case 0xbc0: /* DMA_LCD_CSDP */ - *ret =3D (s->brust_f2 << 14) | - (s->pack_f2 << 13) | - ((s->data_type_f2 >> 1) << 11) | - (s->brust_f1 << 7) | - (s->pack_f1 << 6) | - ((s->data_type_f1 >> 1) << 0); - break; - - case 0xbc2: /* DMA_LCD_CCR */ - *ret =3D (s->mode_f2 << 14) | - (s->mode_f1 << 12) | - (s->end_prog << 11) | - (s->omap_3_1_compatible_disable << 10) | - (s->repeat << 9) | - (s->auto_init << 8) | - (s->running << 7) | - (s->priority << 6) | - (s->bs << 4); - break; - - case 0xbc4: /* DMA_LCD_CTRL */ - qemu_irq_lower(s->irq); - *ret =3D (s->dst << 8) | - ((s->src & 0x6) << 5) | - (s->condition << 3) | - (s->interrupts << 1) | - s->dual; - break; - - case 0xbc8: /* TOP_B1_L */ - *ret =3D s->src_f1_top & 0xffff; - break; - - case 0xbca: /* TOP_B1_U */ - *ret =3D s->src_f1_top >> 16; - break; - - case 0xbcc: /* BOT_B1_L */ - *ret =3D s->src_f1_bottom & 0xffff; - break; - - case 0xbce: /* BOT_B1_U */ - *ret =3D s->src_f1_bottom >> 16; - break; - - case 0xbd0: /* TOP_B2_L */ - *ret =3D s->src_f2_top & 0xffff; - break; - - case 0xbd2: /* TOP_B2_U */ - *ret =3D s->src_f2_top >> 16; - break; - - case 0xbd4: /* BOT_B2_L */ - *ret =3D s->src_f2_bottom & 0xffff; - break; - - case 0xbd6: /* BOT_B2_U */ - *ret =3D s->src_f2_bottom >> 16; - break; - - case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ - *ret =3D s->element_index_f1; - break; - - case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ - *ret =3D s->frame_index_f1 & 0xffff; - break; - - case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ - *ret =3D s->frame_index_f1 >> 16; - break; - - case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ - *ret =3D s->element_index_f2; - break; - - case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ - *ret =3D s->frame_index_f2 & 0xffff; - break; - - case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ - *ret =3D s->frame_index_f2 >> 16; - break; - - case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ - *ret =3D s->elements_f1; - break; - - case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ - *ret =3D s->frames_f1; - break; - - case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ - *ret =3D s->elements_f2; - break; - - case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ - *ret =3D s->frames_f2; - break; - - case 0xbea: /* DMA_LCD_LCH_CTRL */ - *ret =3D s->lch_type; - break; - - default: - return 1; - } - return 0; -} - static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int of= fset, uint16_t value) { @@ -1462,12 +1212,10 @@ static uint64_t omap_dma_read(void *opaque, hwaddr = addr, unsigned size) =20 switch (addr) { case 0x300 ... 0x3fe: - if (s->model <=3D omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { - if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret)) - break; - return ret; + if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret)) { + break; } - /* Fall through. */ + return ret; case 0x000 ... 0x2fe: reg =3D addr & 0x3f; ch =3D (addr >> 6) & 0x0f; @@ -1476,20 +1224,13 @@ static uint64_t omap_dma_read(void *opaque, hwaddr = addr, unsigned size) return ret; =20 case 0x404 ... 0x4fe: - if (s->model <=3D omap_dma_3_1) - break; - /* Fall through. */ + break; case 0x400: if (omap_dma_sys_read(s, addr, &ret)) break; return ret; =20 case 0xb00 ... 0xbfe: - if (s->model =3D=3D omap_dma_3_2 && s->omap_3_1_mapping_disabled) { - if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret)) - break; - return ret; - } break; } =20 @@ -1511,12 +1252,10 @@ static void omap_dma_write(void *opaque, hwaddr add= r, =20 switch (addr) { case 0x300 ... 0x3fe: - if (s->model <=3D omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { - if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value)) - break; - return; + if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value)) { + break; } - /* Fall through. */ + return; case 0x000 ... 0x2fe: reg =3D addr & 0x3f; ch =3D (addr >> 6) & 0x0f; @@ -1525,20 +1264,13 @@ static void omap_dma_write(void *opaque, hwaddr add= r, return; =20 case 0x404 ... 0x4fe: - if (s->model <=3D omap_dma_3_1) - break; - /* fall through */ + break; case 0x400: if (omap_dma_sys_write(s, addr, value)) break; return; =20 case 0xb00 ... 0xbfe: - if (s->model =3D=3D omap_dma_3_2 && s->omap_3_1_mapping_disabled) { - if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value)) - break; - return; - } break; } =20 @@ -1577,51 +1309,6 @@ static void omap_dma_clk_update(void *opaque, int li= ne, int on) soc_dma_set_request(s->ch[i].dma, on); } =20 -static void omap_dma_setcaps(struct omap_dma_s *s) -{ - switch (s->model) { - default: - case omap_dma_3_1: - break; - case omap_dma_3_2: - /* XXX Only available for sDMA */ - s->caps[0] =3D - (1 << 19) | /* Constant Fill Capability */ - (1 << 18); /* Transparent BLT Capability */ - s->caps[1] =3D - (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) = */ - s->caps[2] =3D - (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ - (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ - (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ - (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ - (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ - (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ - (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ - (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ - (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ - s->caps[3] =3D - (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ - (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ - (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ - (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ - (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ - (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ - (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ - (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ - s->caps[4] =3D - (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ - (1 << 6) | /* SYNC_STATUS_CPBLTY */ - (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ - (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ - (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ - (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ - (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ - (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ - break; - } -} - struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, MemoryRegion *sysmem, qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk c= lk, @@ -1630,20 +1317,16 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_i= rq *irqs, int num_irqs, memsize, i; struct omap_dma_s *s =3D g_new0(struct omap_dma_s, 1); =20 - if (model <=3D omap_dma_3_1) { - num_irqs =3D 6; - memsize =3D 0x800; - } else { - num_irqs =3D 16; - memsize =3D 0xc00; - } - s->model =3D model; + assert(model =3D=3D omap_dma_3_1); + + num_irqs =3D 6; + memsize =3D 0x800; s->mpu =3D mpu; s->clk =3D clk; s->lcd_ch.irq =3D lcd_irq; s->lcd_ch.mpu =3D mpu; =20 - s->dma =3D soc_dma_init((model <=3D omap_dma_3_1) ? 9 : 16); + s->dma =3D soc_dma_init(9); s->dma->freq =3D omap_clk_getrate(clk); s->dma->transfer_fn =3D omap_dma_transfer_generic; s->dma->setup_fn =3D omap_dma_transfer_setup; @@ -1656,12 +1339,11 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_i= rq *irqs, s->ch[i].sibling =3D &s->ch[i + 6]; s->ch[i + 6].sibling =3D &s->ch[i]; } - for (i =3D (model <=3D omap_dma_3_1) ? 8 : 15; i >=3D 0; i --) { + for (i =3D 8; i >=3D 0; i--) { s->ch[i].dma =3D &s->dma->ch[i]; s->dma->ch[i].opaque =3D &s->ch[i]; } =20 - omap_dma_setcaps(s); omap_clk_adduser(s->clk, qemu_allocate_irq(omap_dma_clk_update, s, 0)); omap_dma_reset(s->dma); omap_dma_clk_update(s, 0, 1); diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index ea5c0eff8b..36569815e8 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -216,34 +216,6 @@ struct omap_dma_lcd_channel_s { hwaddr src_f2_top; hwaddr src_f2_bottom; =20 - /* Used in OMAP DMA 3.2 gigacell */ - unsigned char brust_f1; - unsigned char pack_f1; - unsigned char data_type_f1; - unsigned char brust_f2; - unsigned char pack_f2; - unsigned char data_type_f2; - unsigned char end_prog; - unsigned char repeat; - unsigned char auto_init; - unsigned char priority; - unsigned char fs; - unsigned char running; - unsigned char bs; - unsigned char omap_3_1_compatible_disable; - unsigned char dst; - unsigned char lch_type; - int16_t element_index_f1; - int16_t element_index_f2; - int32_t frame_index_f1; - int32_t frame_index_f2; - uint16_t elements_f1; - uint16_t frames_f1; - uint16_t elements_f2; - uint16_t frames_f2; - omap_dma_addressing_t mode_f1; - omap_dma_addressing_t mode_f2; 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The other cases in those functions are DMA 3.2-only and now dead code. Fold the 0x400 register directly into the callers, and remove the rest. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/dma/omap_dma.c | 121 ++-------------------------------------------- 1 file changed, 5 insertions(+), 116 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index 9a86d90b4e..49348f40c5 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -317,16 +317,6 @@ static void omap_dma_interrupts_3_1_update(struct omap= _dma_s *s) qemu_irq_raise(ch[5].irq); } =20 -static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) -{ - struct omap_dma_channel_s *ch =3D s->ch; - int i; - - for (i =3D s->chans; i; ch ++, i --) - if (ch->status) - qemu_irq_raise(ch->irq); -} - static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) { s->omap_3_1_mapping_disabled =3D 0; @@ -334,13 +324,6 @@ static void omap_dma_enable_3_1_mapping(struct omap_dm= a_s *s) s->intr_update =3D omap_dma_interrupts_3_1_update; } =20 -static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) -{ - s->omap_3_1_mapping_disabled =3D 1; - s->chans =3D 16; - s->intr_update =3D omap_dma_interrupts_3_2_update; -} - static void omap_dma_process_request(struct omap_dma_s *s, int request) { int channel; @@ -1106,98 +1089,6 @@ static int omap_dma_3_1_lcd_read(struct omap_dma_lcd= _channel_s *s, int offset, return 0; } =20 -static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t v= alue) -{ - switch (offset) { - case 0x400: /* SYS_DMA_GCR */ - s->gcr =3D value; - break; - - case 0x404: /* DMA_GSCR */ - if (value & 0x8) - omap_dma_disable_3_1_mapping(s); - else - omap_dma_enable_3_1_mapping(s); - break; - - case 0x408: /* DMA_GRST */ - if (value & 0x1) - omap_dma_reset(s->dma); - break; - - default: - return 1; - } - return 0; -} - -static int omap_dma_sys_read(struct omap_dma_s *s, int offset, - uint16_t *ret) -{ - switch (offset) { - case 0x400: /* SYS_DMA_GCR */ - *ret =3D s->gcr; - break; - - case 0x404: /* DMA_GSCR */ - *ret =3D s->omap_3_1_mapping_disabled << 3; - break; - - case 0x408: /* DMA_GRST */ - *ret =3D 0; - break; - - case 0x442: /* DMA_HW_ID */ - case 0x444: /* DMA_PCh2_ID */ - case 0x446: /* DMA_PCh0_ID */ - case 0x448: /* DMA_PCh1_ID */ - case 0x44a: /* DMA_PChG_ID */ - case 0x44c: /* DMA_PChD_ID */ - *ret =3D 1; - break; - - case 0x44e: /* DMA_CAPS_0_U */ - *ret =3D (s->caps[0] >> 16) & 0xffff; - break; - case 0x450: /* DMA_CAPS_0_L */ - *ret =3D (s->caps[0] >> 0) & 0xffff; - break; - - case 0x452: /* DMA_CAPS_1_U */ - *ret =3D (s->caps[1] >> 16) & 0xffff; - break; - case 0x454: /* DMA_CAPS_1_L */ - *ret =3D (s->caps[1] >> 0) & 0xffff; - break; - - case 0x456: /* DMA_CAPS_2 */ - *ret =3D s->caps[2]; - break; - - case 0x458: /* DMA_CAPS_3 */ - *ret =3D s->caps[3]; - break; - - case 0x45a: /* DMA_CAPS_4 */ - *ret =3D s->caps[4]; - break; - - case 0x460: /* DMA_PCh2_SR */ - case 0x480: /* DMA_PCh0_SR */ - case 0x482: /* DMA_PCh1_SR */ - case 0x4c0: /* DMA_PChD_SR_0 */ - qemu_log_mask(LOG_UNIMP, - "%s: Physical Channel Status Registers not implement= ed\n", - __func__); - *ret =3D 0xff; - break; - - default: - return 1; - } - return 0; -} - static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size) { struct omap_dma_s *s =3D opaque; @@ -1225,10 +1116,9 @@ static uint64_t omap_dma_read(void *opaque, hwaddr a= ddr, unsigned size) =20 case 0x404 ... 0x4fe: break; - case 0x400: - if (omap_dma_sys_read(s, addr, &ret)) - break; - return ret; + case 0x400: /* SYS_DMA_GCR */ + return s->gcr; + break; =20 case 0xb00 ... 0xbfe: break; @@ -1265,9 +1155,8 @@ static void omap_dma_write(void *opaque, hwaddr addr, =20 case 0x404 ... 0x4fe: break; - case 0x400: - if (omap_dma_sys_write(s, addr, value)) - break; + case 0x400: /* SYS_DMA_GCR */ + s->gcr =3D value; return; =20 case 0xb00 ... 0xbfe: --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Now we have no 3.2 support, the omap_3_1_compatible_disable flag is set to false and can't be changed, so we can remove it, folding out all the conditions where we were testing it as always-false. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/dma/omap_dma.c | 59 +++++++++++++++-------------------------------- 1 file changed, 19 insertions(+), 40 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index 49348f40c5..fe43fec58d 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -73,9 +73,6 @@ struct omap_dma_channel_s { int fs; int bs; =20 - /* compatibility */ - int omap_3_1_compatible_disable; - qemu_irq irq; struct omap_dma_channel_s *sibling; =20 @@ -144,7 +141,6 @@ static void omap_dma_channel_load(struct omap_dma_chann= el_s *ch) { struct omap_dma_reg_set_s *a =3D &ch->active_set; int i, normal; - int omap_3_1 =3D !ch->omap_3_1_compatible_disable; =20 /* * TODO: verify address ranges and alignment @@ -177,14 +173,14 @@ static void omap_dma_channel_load(struct omap_dma_cha= nnel_s *ch) break; case single_index: a->elem_delta[i] =3D ch->data_type + - ch->element_index[omap_3_1 ? 0 : i] - 1; + ch->element_index[0] - 1; a->frame_delta[i] =3D 0; break; case double_index: a->elem_delta[i] =3D ch->data_type + - ch->element_index[omap_3_1 ? 0 : i] - 1; - a->frame_delta[i] =3D ch->frame_index[omap_3_1 ? 0 : i] - - ch->element_index[omap_3_1 ? 0 : i]; + ch->element_index[0] - 1; + a->frame_delta[i] =3D ch->frame_index[0] - + ch->element_index[0]; break; default: break; @@ -442,20 +438,13 @@ static void omap_dma_transfer_generic(struct soc_dma_= ch_s *dma) /* End of Block */ /* Disable the channel */ =20 - if (ch->omap_3_1_compatible_disable) { + if (!ch->auto_init) omap_dma_disable_channel(s, ch); - if (ch->link_enabled) - omap_dma_enable_channel(s, - &s->ch[ch->link_next_ch]); - } else { - if (!ch->auto_init) - omap_dma_disable_channel(s, ch); - else if (ch->repeat || ch->end_prog) - omap_dma_channel_load(ch); - else { - ch->waiting_end_prog =3D 1; - omap_dma_deactivate_channel(s, ch); - } + else if (ch->repeat || ch->end_prog) + omap_dma_channel_load(ch); + else { + ch->waiting_end_prog =3D 1; + omap_dma_deactivate_channel(s, ch); } =20 if (ch->interrupts & END_BLOCK_INTR) @@ -610,19 +599,13 @@ static void omap_dma_transfer_setup(struct soc_dma_ch= _s *dma) /* End of Block */ /* Disable the channel */ =20 - if (ch->omap_3_1_compatible_disable) { + if (!ch->auto_init) omap_dma_disable_channel(s, ch); - if (ch->link_enabled) - omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); - } else { - if (!ch->auto_init) - omap_dma_disable_channel(s, ch); - else if (ch->repeat || ch->end_prog) - omap_dma_channel_load(ch); - else { - ch->waiting_end_prog =3D 1; - omap_dma_deactivate_channel(s, ch); - } + else if (ch->repeat || ch->end_prog) + omap_dma_channel_load(ch); + else { + ch->waiting_end_prog =3D 1; + omap_dma_deactivate_channel(s, ch); } =20 if (ch->interrupts & END_BLOCK_INTR) @@ -711,7 +694,6 @@ void omap_dma_reset(struct soc_dma_s *dma) s->ch[i].cpc =3D 0x0000; s->ch[i].fs =3D 0; s->ch[i].bs =3D 0; - s->ch[i].omap_3_1_compatible_disable =3D 0; memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); s->ch[i].priority =3D 0; s->ch[i].interleave_disabled =3D 0; @@ -752,7 +734,7 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, case 0x06: /* SYS_DMA_CSR_CH0 */ *value =3D ch->status; ch->status &=3D SYNC; - if (!ch->omap_3_1_compatible_disable && ch->sibling) { + if (ch->sibling) { *value |=3D (ch->sibling->status & 0x3f) << 6; ch->sibling->status &=3D SYNC; } @@ -791,11 +773,8 @@ static int omap_dma_ch_reg_read(struct omap_dma_s *s, *value =3D ch->element_index[0]; break; =20 - case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ - if (ch->omap_3_1_compatible_disable) - *value =3D ch->active_set.src & 0xffff; /* CSAC */ - else - *value =3D ch->cpc; + case 0x18: /* SYS_DMA_CPC_CH0 */ + *value =3D ch->cpc; break; =20 case 0x1a: /* DMA_CDAC */ --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Remove the function and the unused omap_3_1_mapping_disabled struct field, and drop the indirection from omap_dma_interrupts_update() through the intr_update function pointer to omap_dma_interrupts_3_1_update(), instead inlining that last function into omap_dma_interrupts_update(). The only other thing omap_dma_enable_3_1_mapping() was doing was setting s->chans; since this is now never changed at runtime we can move its setting into the init function rather than reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/dma/omap_dma.c | 52 ++++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index fe43fec58d..b05e46724c 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -106,8 +106,6 @@ struct omap_dma_s { struct omap_mpu_state_s *mpu; omap_clk clk; qemu_irq irq[4]; - void (*intr_update)(struct omap_dma_s *s); - int omap_3_1_mapping_disabled; =20 uint32_t gcr; uint32_t ocp; @@ -134,7 +132,27 @@ struct omap_dma_s { =20 static inline void omap_dma_interrupts_update(struct omap_dma_s *s) { - s->intr_update(s); + struct omap_dma_channel_s *ch =3D s->ch; + + /* First three interrupts are shared between two channels each. */ + if (ch[0].status | ch[6].status) { + qemu_irq_raise(ch[0].irq); + } + if (ch[1].status | ch[7].status) { + qemu_irq_raise(ch[1].irq); + } + if (ch[2].status | ch[8].status) { + qemu_irq_raise(ch[2].irq); + } + if (ch[3].status) { + qemu_irq_raise(ch[3].irq); + } + if (ch[4].status) { + qemu_irq_raise(ch[4].irq); + } + if (ch[5].status) { + qemu_irq_raise(ch[5].irq); + } } =20 static void omap_dma_channel_load(struct omap_dma_channel_s *ch) @@ -294,32 +312,6 @@ static void omap_dma_channel_end_prog(struct omap_dma_= s *s, } } =20 -static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) -{ - struct omap_dma_channel_s *ch =3D s->ch; - - /* First three interrupts are shared between two channels each. */ - if (ch[0].status | ch[6].status) - qemu_irq_raise(ch[0].irq); - if (ch[1].status | ch[7].status) - qemu_irq_raise(ch[1].irq); - if (ch[2].status | ch[8].status) - qemu_irq_raise(ch[2].irq); - if (ch[3].status) - qemu_irq_raise(ch[3].irq); - if (ch[4].status) - qemu_irq_raise(ch[4].irq); - if (ch[5].status) - qemu_irq_raise(ch[5].irq); -} - -static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) -{ - s->omap_3_1_mapping_disabled =3D 0; - s->chans =3D 9; - s->intr_update =3D omap_dma_interrupts_3_1_update; -} - static void omap_dma_process_request(struct omap_dma_s *s, int request) { int channel; @@ -660,7 +652,6 @@ void omap_dma_reset(struct soc_dma_s *dma) s->lcd_ch.condition =3D 0; s->lcd_ch.interrupts =3D 0; s->lcd_ch.dual =3D 0; - omap_dma_enable_3_1_mapping(s); for (i =3D 0; i < s->chans; i ++) { s->ch[i].suspend =3D 0; s->ch[i].prefetch =3D 0; @@ -1193,6 +1184,7 @@ struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq= *irqs, s->clk =3D clk; s->lcd_ch.irq =3D lcd_irq; s->lcd_ch.mpu =3D mpu; + s->chans =3D 9; =20 s->dma =3D soc_dma_init(9); s->dma->freq =3D omap_clk_getrate(clk); --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778618181; cv=none; d=zohomail.com; s=zohoarc; b=mFAEyIYek+/+MUKA6qe0Kjq10YZ7K2c/8FlRXZdv4ax+U0yEgYY2L6PArhIVz273gY+4YOnA2nV7tCzbAfebPEpVdN67a/RJekL+1cB9JOcKU+3RcQ/7wL3m4giaJh1cG2NzLNfD0syyZZ2db5lajh0eryaXZnIXSgbEQyjeC/w= ARC-Message-Signature: i=1; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fc8d69d0bsm16350635e9.13.2026.05.12.13.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2026 13:34:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1778618069; x=1779222869; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=t9k4mJ0mJoHclk3+nrD0mbmPSwGXLUxcP1ddS/QHoQQ=; b=nFXISXaY2TLeFTKR77SeexEOUVt14Yu59k4YvSG9s86Cc6VwC69OQG+R7mrUK+NGvP QSY/nePYCACcx58TefECjsdempaglfhgWBkX0erus4l86FFcvfriPVkQULh/f9Ce9CMg FFKYzb8jyTtsp1RGOT++vqVKQkqmiLtlXB1oFOMUZ3byoWg5kE0rk0IooR+NHxY30wyj BRDmMmbPjgrPuQ6XXIt3M3YAo7T++8549l4X6gGwJiqoschjrS5AYBiNoDOO1cy67p6p +SAMVLi3obnTGojpue/N0ceXlRLTC2yDGhA8PJQJXQH0IGapUiB9kUpIXn2Ts0IiyGsr ni1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778618069; x=1779222869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=t9k4mJ0mJoHclk3+nrD0mbmPSwGXLUxcP1ddS/QHoQQ=; b=epFneIK5vviprUNu/VnSfXSz4OkxVlJJltR+l1H8OzwkvPW4Hi7cxUW2L7jj8nOYEK LfvFYsl+uPoVe1tHO7zUnVxYk5DMPWZ4EgwO/qqokUqqX3XIOtLRgZYyU/BNuKbOK4wb NhDiQLGJAN+/ofuajV0AMjmsk5vWTPfKwA/3y3qFBRJvYkHTbuDBdKMlK05W+NNgtP1a gqRpAkFZiebY910iu2g6/FC9ZgJuiYZbXgGpPB/9ybyNaKuflBjQwJsXYrSTHVCf3UNv qWeB4vwflC+aRlUJzGH/MXBCEFnA0Cxt/IzRdYbp62KqSF7xPpFx8JxW6GGBZyAlggnp QFdg== X-Forwarded-Encrypted: i=1; AFNElJ9UhmSAjtTf/gL2k2hdNr4w4OxFvTE/gFkfR2NYgh2ziU4pEe8UMER5CpdM7vAz/+SsXdEUMug71bBb@nongnu.org X-Gm-Message-State: AOJu0YyGUabJIThAVEM1kmEV1cSXeBKH4OBf0KH43LWktRE7O/bCPYNI 3biZD3Y1VewjchZz/xhPI6l/AYClekI63UjM3CnofKoO1ceQyafsUmJNyAhrKeRdqtpl1bxUexB hPS7r X-Gm-Gg: Acq92OH77tG36SyedCjuKgFeTa2wghXJ3b5vXe3OCPZF/Pvg73zfg1sq/2jA1llPknt WpzEBrdjIVFFFIlgjBiXA3P2kwjjTjKumLkUKx7KEKof8LXfFZFUOtXHhGeMnvVkPu8T8X7BAd9 kKPkenUOnBhhCDADi3DFZ1C/JSNET34WcgNfyqkcrWQA36rEJtEext4dGq4K5cltyAyxD84V69J 8VoX2oq56/FiqS2kAwAAmQcP+VBAZQjOe9VW/v94ZYrOP9PMMk0vmQdVkrbVvTKrW7hN/obaYam KW8LnKH77QTaT8m9iTfhBolYxs95dvizgIG/fjr0A085KQ7ODvlYHXRgQcM7AqSqXjNPXJEDJ3y 94s/gcEURFTlLzDcxAbfEUS4mCXBCsZ8w014UvoNINGGIlhnzG+vash0297cDYJCkI8BTvrCLqB 2ezpjjHPiWBw+FggSaH092D7AtIc329UvaBsGc9Hyyof6MjgnahAV2zr+vP+NgBll9lZ6wlIpxv xImjipsYyVhCnYBbjOl16LwkmK9Cz+y1FVveTjv8A== X-Received: by 2002:a05:600c:8b41:b0:488:b187:3c with SMTP id 5b1f17b1804b1-48fc9a3320cmr5563825e9.14.1778618069185; Tue, 12 May 2026 13:34:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/12] hw/dma/omap_dma: Remove unused ifdeffed out code Date: Tue, 12 May 2026 21:34:13 +0100 Message-ID: <20260512203414.3633237-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512203414.3633237-1-peter.maydell@linaro.org> References: <20260512203414.3633237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778618183074154100 Content-Type: text/plain; charset="utf-8" The OMAP DMA device includes a lot of code which has been disabled via ifdefs for over a decade. Whatever this unfinished development work was, all knowledge of it is long gone, and we're unlikely to be doing any serious work on this device model in future. If we did, we'd likely have to start from scratch. Remove all the ifdeffed out code. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/dma/omap_dma.c | 94 ----------------------------------------------- 1 file changed, 94 deletions(-) diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index b05e46724c..dea251afbc 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -343,9 +343,6 @@ static void omap_dma_transfer_generic(struct soc_dma_ch= _s *dma) struct omap_dma_channel_s *ch =3D dma->opaque; struct omap_dma_reg_set_s *a =3D &ch->active_set; int bytes =3D dma->bytes; -#ifdef MULTI_REQ - uint16_t status =3D ch->status; -#endif =20 do { /* Transfer a single element */ @@ -362,7 +359,6 @@ static void omap_dma_transfer_generic(struct soc_dma_ch= _s *dma) a->dest +=3D a->elem_delta[1]; a->element ++; =20 -#ifndef MULTI_REQ if (a->element =3D=3D a->elements) { /* End of Frame */ a->element =3D 0; @@ -375,78 +371,6 @@ static void omap_dma_transfer_generic(struct soc_dma_c= h_s *dma) ch->cpc =3D a->dest & 0xffff; } } while ((bytes -=3D ch->data_type)); -#else - /* If the channel is element synchronized, deactivate it */ - if (ch->sync && !ch->fs && !ch->bs) - omap_dma_deactivate_channel(s, ch); - - /* If it is the last frame, set the LAST_FRAME interrupt */ - if (a->element =3D=3D 1 && a->frame =3D=3D a->frames - 1) - if (ch->interrupts & LAST_FRAME_INTR) - ch->status |=3D LAST_FRAME_INTR; - - /* If the half of the frame was reached, set the HALF_FRAME - interrupt */ - if (a->element =3D=3D (a->elements >> 1)) - if (ch->interrupts & HALF_FRAME_INTR) - ch->status |=3D HALF_FRAME_INTR; - - if (ch->fs && ch->bs) { - a->pck_element ++; - /* Check if a full packet has been transferred. */ - if (a->pck_element =3D=3D a->pck_elements) { - a->pck_element =3D 0; - - /* Set the END_PKT interrupt */ - if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) - ch->status |=3D END_PKT_INTR; - - /* If the channel is packet-synchronized, deactivate it */ - if (ch->sync) - omap_dma_deactivate_channel(s, ch); - } - } - - if (a->element =3D=3D a->elements) { - /* End of Frame */ - a->element =3D 0; - a->src +=3D a->frame_delta[0]; - a->dest +=3D a->frame_delta[1]; - a->frame ++; - - /* If the channel is frame synchronized, deactivate it */ - if (ch->sync && ch->fs && !ch->bs) - omap_dma_deactivate_channel(s, ch); - - /* If the channel is async, update cpc */ - if (!ch->sync) - ch->cpc =3D a->dest & 0xffff; - - /* Set the END_FRAME interrupt */ - if (ch->interrupts & END_FRAME_INTR) - ch->status |=3D END_FRAME_INTR; - - if (a->frame =3D=3D a->frames) { - /* End of Block */ - /* Disable the channel */ - - if (!ch->auto_init) - omap_dma_disable_channel(s, ch); - else if (ch->repeat || ch->end_prog) - omap_dma_channel_load(ch); - else { - ch->waiting_end_prog =3D 1; - omap_dma_deactivate_channel(s, ch); - } - - if (ch->interrupts & END_BLOCK_INTR) - ch->status |=3D END_BLOCK_INTR; - } - } - } while (status =3D=3D ch->status && ch->active); - - omap_dma_interrupts_update(s); -#endif } =20 enum { @@ -475,13 +399,6 @@ static void omap_dma_transfer_setup(struct soc_dma_ch_= s *dma) dest_p =3D &s->mpu->port[ch->port[1]]; if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) || (!dest_p->addr_valid(s->mpu, a->dest))) { -#if 0 - /* Bus time-out */ - if (ch->interrupts & TIMEOUT_INTR) - ch->status |=3D TIMEOUT_INTR; - omap_dma_deactivate_channel(s, ch); - continue; -#endif printf("%s: Bus time-out in DMA%i operation\n", __func__, dma->num); } @@ -552,11 +469,6 @@ static void omap_dma_transfer_setup(struct soc_dma_ch_= s *dma) =20 /* Set appropriate interrupts and/or deactivate channels */ =20 -#ifdef MULTI_REQ - /* TODO: should all of this only be done if dma->update, and otherwise - * inside omap_dma_transfer_generic below - check what's faster. */ - if (dma->update) { -#endif =20 /* If the channel is element synchronized, deactivate it */ if (min_elems =3D=3D elements[omap_dma_intr_element_sync]) @@ -612,9 +524,7 @@ static void omap_dma_transfer_setup(struct soc_dma_ch_s= *dma) =20 /* TODO: check if we really need to update anything here or perhap= s we * can skip part of this. */ -#ifndef MULTI_REQ if (dma->update) { -#endif a->element +=3D min_elems; =20 frames =3D a->element / a->elements; @@ -629,11 +539,7 @@ static void omap_dma_transfer_setup(struct soc_dma_ch_= s *dma) =20 /* TODO: if the destination port is IMIF or EMIFF, set the dir= ty * bits on it. */ -#ifndef MULTI_REQ } -#else - } -#endif =20 omap_dma_interrupts_update(s); } --=20 2.43.0 From nobody Sat May 30 17:44:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778618203; cv=none; d=zohomail.com; s=zohoarc; b=D82aP+Ow4UnJSDXilqilLrTkFKAzBu/WgXPNAhzczP1+muDXZauNITbBAlkeq3pO0Fsd0kJNPIFp0vq+He3DHnFo/4IqSnlUCHm/Cd3QeAAPenCjz16PTReqCErvX8p83u/cxGpEI0sTITpu2bH5+U9Ez4G5uQPEoUVf575PCQw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778618203; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/omap1.c | 2 +- hw/dma/omap_dma.c | 8 +++----- include/hw/arm/omap.h | 12 +++--------- 3 files changed, 7 insertions(+), 15 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 80168644ce..44f9dd67c3 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -3789,7 +3789,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegio= n *dram, } s->dma =3D omap_dma_init(0xfffed800, dma_irqs, system_memory, qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), - s, omap_findclk(s, "dma_ck"), omap_dma_3_1); + s, omap_findclk(s, "dma_ck")); =20 s->port[emiff ].addr_valid =3D omap_validate_emiff_addr; s->port[emifs ].addr_valid =3D omap_validate_emifs_addr; diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index dea251afbc..a93d9ad196 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -1075,15 +1075,13 @@ static void omap_dma_clk_update(void *opaque, int l= ine, int on) } =20 struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, - MemoryRegion *sysmem, - qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk c= lk, - enum omap_dma_model model) + MemoryRegion *sysmem, + qemu_irq lcd_irq, + struct omap_mpu_state_s *mpu, omap_clk clk) { int num_irqs, memsize, i; struct omap_dma_s *s =3D g_new0(struct omap_dma_s, 1); =20 - assert(model =3D=3D omap_dma_3_1); - num_irqs =3D 6; memsize =3D 0x800; s->mpu =3D mpu; diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 36569815e8..2675d064f2 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -172,17 +172,11 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk= clk); #define OMAP_INT_310_McBSP2RX_OF 31 =20 /* omap_dma.c */ -enum omap_dma_model { - omap_dma_3_0, - omap_dma_3_1, - omap_dma_3_2, -}; - struct soc_dma_s; struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, - MemoryRegion *sysmem, - qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk c= lk, - enum omap_dma_model model); + MemoryRegion *sysmem, + qemu_irq lcd_irq, + struct omap_mpu_state_s *mpu, omap_clk clk= ); void omap_dma_reset(struct soc_dma_s *s); =20 struct dma_irq_map { --=20 2.43.0