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Tue, 12 May 2026 04:34:21 -0400 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2026 01:34:16 -0700 Received: from lxy-clx-4s.sh.intel.com ([10.239.48.22]) by orviesa007.jf.intel.com with ESMTP; 12 May 2026 01:34:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778574860; x=1810110860; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7RIfmRFxhE7Bt/J8eFND2kVyc/t5pAosMx3RGwcy/aE=; b=WseB3Z7TOAg/X8Vno6T5T255iN1i0sFiPggK/hphXvTyGIAxzWUkkNAV Gs85rmYddF1/GH4TLoVuiLCEvMfN4qL8qPU5oI2etmRhpZgtuLBPccBt8 sh5Kw0AcFOa06TLqdnu1U2xQFJJCjGoN/Rj0OMttwFEMe2OOTbha4Pol3 s57huAtj7V7I2epDTJTX2jZ5p1WCPwmqez0z+wrnVgsVpzL1L7eqLdsm6 8vGGNONqGnGkGQSnlQKWlX6uospcpO/cDBQfNKNM1H7ClylCsKIrSl3tQ ES/u6l7TBaUor1atYft+zLk7MQpW/EtVJ+xx71SI2dwHKLyBPOo/MjAbk g==; X-CSE-ConnectionGUID: tOJEXnH+TpWwYLnTFn+S7g== X-CSE-MsgGUID: 7gEY+i70TR+vHt+pIkWNJg== X-IronPort-AV: E=McAfee;i="6800,10657,11783"; a="90060001" X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="90060001" X-CSE-ConnectionGUID: RNyc/RtFRHy57Z/Obm7dhg== X-CSE-MsgGUID: JMvop23qQ4CVT13LZ67/aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="237947177" From: Xiaoyao Li To: Paolo Bonzini Cc: qemu-devel@nongnu.org, =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Chenyi Qiang , xiaoyao.li@intel.com Subject: [PATCH 1/3] i386/tdx: Use .has_gpa field to check if the gpa is valid Date: Tue, 12 May 2026 16:21:06 +0800 Message-ID: <20260512082108.621596-2-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512082108.621596-1-xiaoyao.li@intel.com> References: <20260512082108.621596-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=192.198.163.11; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.999, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1778574929822158500 When translating the QAPI type GuestPanicInformationTdx into its C struct, the generated code provides a .has_gpa boolean field to indicate whether the optional gpa field is present. Replace the magic sentinel value -1ULL, previously used to signal "no valid GPA", with the idiomatic .has_gpa field. This removes the implicit sentinel coupling and makes the validity check self-documenting. Signed-off-by: Xiaoyao Li Reviewed-by: Daniel P. Berrang=C3=A9 Reviewed-by: Zhenzhong Duan --- Refine the commit message when re-sending it. --- system/runstate.c | 2 +- target/i386/kvm/tdx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/system/runstate.c b/system/runstate.c index 770253b467b5..2bb36b2a7247 100644 --- a/system/runstate.c +++ b/system/runstate.c @@ -704,7 +704,7 @@ void qemu_system_guest_panicked(GuestPanicInformation *= info) " error code: 0x%" PRIx32 " error message:\"%s\"= \n", info->u.tdx.error_code, message); g_free(message); - if (info->u.tdx.gpa !=3D -1ull) { + if (info->u.tdx.has_gpa) { qemu_log_mask(LOG_GUEST_ERROR, "Additional error informati= on " "can be found at gpa page: 0x%" PRIx64 "\n", info->u.tdx.gpa); diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 4714c9d514ef..6f93997d62db 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -1403,7 +1403,7 @@ int tdx_handle_report_fatal_error(X86CPU *cpu, struct= kvm_run *run) uint64_t reg_mask =3D run->system_event.data[R_ECX]; char *message =3D NULL; uint64_t *tmp; - uint64_t gpa =3D -1ull; + uint64_t gpa =3D 0; bool has_gpa =3D false; =20 if (error_code & 0xffff) { --=20 2.43.0 From nobody Sat May 30 17:44:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1778574915; cv=none; d=zohomail.com; s=zohoarc; b=IV7ckm52xkT+RGHPfT0bI2ivcmuzpSLfa9eKbixQRIyd1oPvXvIhOCVJB2ueLQfx2HM4u+ssqj7+GqpmL47teo6/cIxMGNzeOcO5AaHK4UwZ49axkwV9LMupfG8nD27qjIUEgx8kw2aDtR89edvGeUFg/Ds8OKmZ39L5iUAJLZg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778574915; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: t/d5c5swSQytRGOp0imclg== X-CSE-MsgGUID: ETIzc2uURwuXEqe0yuoE4w== X-IronPort-AV: E=McAfee;i="6800,10657,11783"; a="90060005" X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="90060005" X-CSE-ConnectionGUID: u6DhdmH9QIac95HEJuQq8Q== X-CSE-MsgGUID: axzOspCCQ5KnMRPkC9rBfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="237947186" From: Xiaoyao Li To: Paolo Bonzini Cc: qemu-devel@nongnu.org, =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Chenyi Qiang , xiaoyao.li@intel.com Subject: [PATCH 2/3] i386/tdx: Make AMX alias bits supported Date: Tue, 12 May 2026 16:21:07 +0800 Message-ID: <20260512082108.621596-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512082108.621596-1-xiaoyao.li@intel.com> References: <20260512082108.621596-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=192.198.163.11; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.999, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1778574917957158500 Content-Type: text/plain; charset="utf-8" When booting a TD guest on a platform that supports AMX alias bits, QEMU emits the warning such as: qemu-system-x86_64: warning: TDX forcibly sets the feature: CPUID[eax=3D1= Eh,ecx=3D01h].EAX.amx-int8-alias [bit 0] ... Bit[3:0] of CPUID(0x1e,1).EAX alias the AMX CPUID bits from leaf 7. Their TDX virtualization type is "CPUID_Enabled & Native": the value is determined by the leaf-7 AMX bit they are aliased to and the native hardware value. These bits must be added to the TDX supported bits list so that they can be enabled without triggering the forced-set warning. For simplicity, mark them as supported whenever the corresponding AMX XFAM bit is supported, rather than checking each aliased leaf-7 bit individually. This reduces code complexity. Any platform that supports the AMX XFAM bit but not these alias bits will still be handled correctly, since the TDX module provides the real value via tdx_check_features(). Signed-off-by: Xiaoyao Li Tested-by: Chenyi Qiang --- target/i386/kvm/tdx.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 6f93997d62db..6c80f6e7dcbe 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -560,13 +560,19 @@ typedef struct TdxXFAMDep { } TdxXFAMDep; =20 /* - * Note, only the CPUID bits whose virtualization type are "XFAM & Native"= are - * defiend here. + * Note, usually the CPUID bits whose virtualization type are "XFAM & Nati= ve" + * are defined here while "XFAM & Configured & Native" are not. Because the + * latter are reported as configurable bits by KVM when they are supported. + * And they are not supported when not in the configurable bits list from = KVM + * even if the corresponding XFAM bit is supported. * - * For those whose virtualization type are "XFAM & Configured & Native", t= hey - * are reported as configurable bits. And they are not supported if not in= the - * configureable bits list from KVM even if the corresponding XFAM bit is - * supported. + * Special cases: + * + * - AMX alias bits, their type is "CPUID_Enabled & Native" which means th= eir + * value is determined by the CPUID bit they are aliased to. + * + * For simplicity, relax the dependency to related XFAM bit. + * tdx_check_features() will eventually catch the unsupported configuratio= ns. */ TdxXFAMDep tdx_xfam_deps[] =3D { { XSTATE_YMM_BIT, { FEAT_1_ECX, CPUID_EXT_FMA } }, @@ -580,6 +586,10 @@ TdxXFAMDep tdx_xfam_deps[] =3D { { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_BF16 } }, { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE } }, { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_INT8 } }, + { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_INT8_ALIAS= } }, + { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_BF16_ALIAS= } }, + { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_COMPLEX_AL= IAS } }, + { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_FP16_ALIAS= } }, }; =20 static struct kvm_cpuid_entry2 *find_in_supported_entry(uint32_t function, --=20 2.43.0 From nobody Sat May 30 17:44:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1778574914; cv=none; d=zohomail.com; s=zohoarc; b=M59NGVed3pD37nY7Kt4ELUekUdhfkNi3vWjmT5cpCWewzVA97ImkbM5LRqG25F9r3JRpkhKVXxiVI4FPhILvsc/6WerCMofwOsN7C8glyQlr54QX8p9lvuvoYZ4Y1GUhzFRf/w9J5VFeudDjv/IiwiDQEUIanEUggOlSClRpQnA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778574914; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: C3HalHuXTtSNM0cHqb9OLQ== X-CSE-MsgGUID: fawhNhGQRgGsCMU7tKzi7w== X-IronPort-AV: E=McAfee;i="6800,10657,11783"; a="90060007" X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="90060007" X-CSE-ConnectionGUID: 1GtA795FSLmt63R32VOrVA== X-CSE-MsgGUID: pETO5cfbRKmC3ga1VaFhNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,230,1770624000"; d="scan'208";a="237947190" From: Xiaoyao Li To: Paolo Bonzini Cc: qemu-devel@nongnu.org, =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Chenyi Qiang , xiaoyao.li@intel.com Subject: [PATCH 3/3] i386/tdx: Add CPUID_24_0_EBX_AVX10_VL_MASK as supported Date: Tue, 12 May 2026 16:21:08 +0800 Message-ID: <20260512082108.621596-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260512082108.621596-1-xiaoyao.li@intel.com> References: <20260512082108.621596-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=192.198.163.11; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.999, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1778574917941154100 Content-Type: text/plain; charset="utf-8" AVX10 depends on CPUID_24_0_EBX_AVX10_VL_MASK as defined in feature_dependencies[]. Currently CPUID_24_0_EBX_AVX10_VL_MASK is always not supported for TDX, so AVX10 cannot be exposed to TD guest. The TDX virtualization type of these bits is "XFAM & CPUID_Enabled & Native": their value is determined by XFAM[5:7], the AVX10 CPUID bit, and the native hardware value. For simplicity, add CPUID_24_0_EBX_AVX10_VL_MASK to tdx_xfam_deps[] under the AVX512/XFAM dependency, without separately checking the AVX10 bit. It's safe because any invalid combination supplied by the user will be caught by tdx_check_features(). Signed-off-by: Xiaoyao Li Tested-by: Chenyi Qiang --- target/i386/kvm/tdx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 6c80f6e7dcbe..b1bc4ffd950f 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -571,6 +571,9 @@ typedef struct TdxXFAMDep { * - AMX alias bits, their type is "CPUID_Enabled & Native" which means th= eir * value is determined by the CPUID bit they are aliased to. * + * - AVX10_VL_MASK, their type is "XFAM & CPUID_Enabled & Native" which me= ans + * their value is determined by both the corresponding XFAM bit and CPUID = bit. + * * For simplicity, relax the dependency to related XFAM bit. * tdx_check_features() will eventually catch the unsupported configuratio= ns. */ @@ -579,6 +582,7 @@ TdxXFAMDep tdx_xfam_deps[] =3D { { XSTATE_YMM_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX2 } }, { XSTATE_OPMASK_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_AVX512_VBMI } }, { XSTATE_OPMASK_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AVX512_FP16 } }, + { XSTATE_OPMASK_BIT, { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK = } }, { XSTATE_PT_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT } }, { XSTATE_PKRU_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU } }, { XSTATE_CET_U_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK } }, --=20 2.43.0